Image sensor and method of forming the same

Abstract

Various embodiments of the present disclosure are directed to an image sensor having a semiconductor substrate including a front side surface opposite a backside surface. A plurality of photodetectors are disposed in the semiconductor substrate. An isolation structure extends from the backside surface of the semiconductor substrate into the semiconductor substrate and is disposed between adjacent photodetectors. The isolation structure includes a metallic core, a conductive liner disposed between the semiconductor substrate and the metallic core, and a first dielectric liner disposed between the conductive liner and the semiconductor substrate. The metallic core comprises a first metallic material, and the conductive liner comprises the first metallic material and a second metallic material different from the first metallic material.

Description

Technical Field

[0001] This disclosure relates to an image sensor and a method for forming the same. Background Technology

[0002] Many modern electronic devices (e.g., digital cameras, optical imaging devices, etc.) include image sensors. Image sensors convert optical images into digital data that can be represented as digital images. Image sensors contain an array of pixel sensors, which are unit devices used to convert optical images into digital data. Some types of pixel sensors include charge-coupled device (CCD) image sensors and complementary metal-oxide-semiconductor (CMOS) image sensors. Compared to CCD pixel sensors, CMOS pixel sensors are favored due to their lower power consumption, smaller size, faster data processing, direct data output, and lower manufacturing cost. Attached Figure Description

[0003] When read in conjunction with the accompanying drawings, aspects of this disclosure are best understood in the following detailed description. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased.

[0004] Figure 1 Cross-sectional views of some embodiments of an image sensor are shown, the image sensor including an isolation structure that laterally surrounds a plurality of photodetectors and a bias circuit configured as a bias isolation structure.

[0005] Figure 2 Showing the section along line A-A' Figure 1 Top view of some embodiments of the image sensor.

[0006] Figure 3 Cross-sectional views of some embodiments of an image sensor are shown, the image sensor including an isolation structure that laterally surrounds a plurality of photodetectors, a metal grid structure that contacts the isolation structure, and a bias circuit configured as a bias isolation structure.

[0007] Figure 4 Show Figure 1 Cross-sectional views of some other embodiments of the image sensor.

[0008] Figure 5A and Figure 5B Various views illustrating some embodiments of an image sensor, the image sensor including a substrate having a pixel array region laterally adjacent to a peripheral region.

[0009] Figure 6ACross-sectional views of some embodiments of an image sensor are shown, the image sensor including an isolation structure that laterally surrounds a plurality of photodetectors and a bias circuit configured as a bias isolation structure.

[0010] Figure 6B Show Figure 6A Cross-sectional views of some embodiments of an image sensor.

[0011] Figures 7 to 16 Cross-sectional views of some embodiments of a method for forming an image sensor are shown, the image sensor including an isolation structure that laterally surrounds a plurality of photodetectors and a bias circuit configured to bias the isolation structure.

[0012] Figure 17 A flowchart illustrating some embodiments of a method for forming an image sensor, the image sensor including an isolation structure laterally surrounding a plurality of photodetectors and a bias circuit configured as a bias isolation structure. Detailed Implementation

[0013] This disclosure provides numerous different embodiments or instances for implementing various features of this disclosure. Specific examples of components and arrangements are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features such that the first and second features are not in direct contact. Additionally, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0014] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" are used herein to describe the relationship between one element or feature and another element(s) as shown in the diagrams. In addition to the orientations depicted in the diagrams, the spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein shall be interpreted accordingly.

[0015] Complementary metal-oxide-semiconductor (CIS) image sensors comprise multiple photodetectors disposed in a device region on a semiconductor substrate. In improving CIS, the device geometry can be miniaturized to achieve lower manufacturing costs and increased device density. Due to device miniaturization, the size of each photodetector decreases and the photodetectors are placed closer together. Electrical and optical isolation can be implemented between adjacent photodetectors to reduce blooming in the CIS and increase quantum efficiency (QE). Trench isolation structures are disposed in / above the back surface of the semiconductor substrate and laterally positioned between adjacent photodetectors. Furthermore, deep implantation wells extending to the depth of the photodetectors can be formed. The trench isolation structures and deep implantation wells are configured to increase isolation between photodetectors, thereby increasing the overall performance of the CIS and facilitating device feature miniaturization.

[0016] The challenges of the aforementioned CIS include crosstalk between adjacent photodetectors and increased manufacturing costs. For example, trench isolation structures may include one or more dielectric materials disposed within trenches in a semiconductor substrate. The dielectric materials of the trench isolation structure have relatively low reflectivity (e.g., about 29% or less), allowing incident light incident on a first photodetector to pass through a section of the trench isolation structure to reach a second photodetector laterally adjacent to the first photodetector. This partially increases crosstalk between laterally adjacent photodetectors, thereby degrading the performance of the CIS. Furthermore, dopants in deep implanted wells can diffuse outwards from the deep implanted well into other areas of the semiconductor substrate (e.g., into areas of the photodetectors), thereby increasing the size of the deep implanted well and decreasing the size of the photodetector. The outward diffusion of dopants reduces the full-well capacity of the photodetector (e.g., the amount of charge the photodetector can accumulate before saturation) because the photodetector size has been reduced. Additionally, forming deep implanted wells can increase the complexity, time, and cost associated with manufacturing the CIS.

[0017] Therefore, various embodiments of this disclosure relate to an image sensor including a trench isolation structure that increases optical and electrical isolation between photodetectors. The image sensor includes a plurality of photodetectors disposed within a substrate. The trench isolation structure extends into the surface of the substrate to a position below the surface of the substrate and is laterally disposed between each photodetector. The trench isolation structure includes a conductive liner (e.g., comprising titanium, aluminum, another suitable conductive material, or any combination thereof) and a metal core (e.g., comprising aluminum). In various embodiments, the conductive liner may act as a seed layer and / or diffusion barrier layer for the metal core. One or more dielectric liners are disposed between the substrate and the conductive liner. By means of the trench isolation structure including the conductive liner and the metal core, crosstalk between adjacent photodetectors can be reduced. For example, the metallic material of the metal core and / or the conductive liner has a relatively high reflectivity (e.g., greater than or equal to about 80%), such that incident light disposed on a first photodetector is blocked from passing through a section of the trench isolation structure to reach a second photodetector laterally adjacent to the first photodetector.

[0018] Additionally, the image sensor includes a bias circuit electrically coupled to the trench isolation structure and configured to apply a bias voltage (e.g., a negative bias) to the metal core. In some embodiments, applying a negative bias (e.g., about -3 volts) to the metal core further reduces leakage current and crosstalk between adjacent photodetectors. Furthermore, by including the bias circuit and applying a bias voltage (e.g., about -3 volts) to the trench isolation structure, the fabrication of a deep-well implant can be omitted, thereby reducing manufacturing costs and increasing the full-well capacity of the photodetector.

[0019] Figure 1 A cross-sectional view of some embodiments of an image sensor 100 is shown, the image sensor 100 including an isolation structure 120 that laterally surrounds a plurality of photodetectors 118 and a bias circuit 130 configured to bias the isolation structure 120.

[0020] Image sensor 100 includes an interconnect structure 102 disposed along the front surface 104f of substrate 104. In some embodiments, substrate 104 includes any semiconductor body (e.g., bulk silicon) and / or has a first doping type (e.g., p-type doping). Interconnect structure 102 includes interconnect dielectric structure 106, a plurality of conductive lines 108, and a plurality of vias 110. A plurality of pixel devices 112 are disposed along the front surface 104f of substrate 104, and pixel devices 112 are electrically coupled to each other and / or electrically coupled to other semiconductor devices (not shown) by means of the plurality of conductive lines 108 and the plurality of vias 110. The plurality of pixel devices 112 may include a gate electrode 114 and a gate dielectric layer 116 disposed between the gate electrode 114 and the front surface 104f of substrate 104.

[0021] Multiple photodetectors 118 are disposed within the pixel array region of substrate 104 and may include a second doping type (e.g., n-type) opposite to a first doping type (e.g., p-type doping). In various embodiments, the first doping type is p-type and the second doping type is n-type, or vice versa. The multiple photodetectors 118 are configured to absorb incident light (e.g., photons) and generate corresponding electrical signals corresponding to the incident light. In such embodiments, the photodetectors 118 may generate electron-hole pairs from the incident light. Multiple pixel devices 112 may be configured to read out the generated electrical signals from the multiple photodetectors 118 by means of interconnect structure 102.

[0022] An isolation structure 120 extends into the back surface 104b of the substrate 104, reaching a position below the back surface 104b, and laterally surrounds each of the plurality of photodetectors 118. An upper dielectric layer 132 covers the back surface 104b of the substrate 104 and the isolation structure 120. A metal grid structure 134 covers the back surface 104b of the substrate 104, and a dielectric grid structure 136 covers the metal grid structure 134. In various embodiments, the metal grid structure 134 and the dielectric grid structure 136 include sidewalls defining a plurality of openings that directly cover corresponding photodetectors among the plurality of photodetectors 118. The metal grid structure 134 includes one or more metal layers configured to reduce crosstalk between adjacent photodetectors 118. Furthermore, the dielectric grating structure 136 can be configured to guide incident light to the corresponding photodetector 118 via total internal reflection (TIR), thereby further reducing crosstalk and increasing the quantum efficiency (QE) of the photodetector 118. In yet another embodiment, a color filter 138 is disposed within the openings of the metal grating structure 134 and the dielectric grating structure 136. The color filter 138 is configured to transmit a specific wavelength of incident light while blocking other wavelengths of incident light. Additionally, a plurality of microlenses 140 are overlaid with the color filter 138 and configured to focus incident light toward the photodetector 118.

[0023] An isolation structure 120 is disposed between adjacent photodetectors 118. The isolation structure 120 is configured to electrically isolate the photodetectors 118 from each other and to reduce crosstalk between adjacent photodetectors 118. In various embodiments, the isolation structure 120 includes a first dielectric liner 122, a second dielectric liner 124, a conductive liner 126, and a metal core 128. The first dielectric liner 122 is lined within the sidewalls of one or more trenches extending into the back surface 104b of the substrate 104, and the second dielectric liner 124 is disposed along the first dielectric liner 122. In various embodiments, the first dielectric liner 122 includes a first dielectric material (e.g., a high-k dielectric material), and the second dielectric liner 124 includes a second dielectric material (e.g., an oxide, such as silicon dioxide), which is different from the first dielectric material.

[0024] A conductive liner 126 extends into one or more trenches and is disposed along a second dielectric liner 124. Furthermore, a metal core 128 is disposed within one or more trenches, and the conductive liner 126 is disposed between the metal core 128 and the second dielectric liner 124. In some embodiments, the conductive liner 126 is configured as a seed layer and / or a diffusion barrier layer for the metal core 128. Additionally, the metal core 128 comprises a metallic material (e.g., aluminum) having a relatively high reflectivity (e.g., greater than or equal to about 80%), which helps reduce crosstalk between adjacent photodetectors. For example, incident light may be angled relative to the back surface 104b, and the metal core 128 is configured to prevent incident light positioned directly above a corresponding photodetector from passing through a section of the isolation structure 120 to reach an adjacent photodetector. This is partly because the metal core 128 comprises a metallic material that helps reflect angled incident light away from the adjacent photodetector and back to the corresponding photodetector. Therefore, by reducing crosstalk and increasing the QE of the photodetector 118, the performance of the image sensor 100 is improved.

[0025] Furthermore, bias circuit 130 is electrically coupled to metal core 128 and substrate 104. Bias circuit 130 is configured to apply a bias voltage (e.g., a negative bias voltage) to metal core 128. In various embodiments, bias circuit 130 may be implemented via a substrate via (TSV) (not shown) and / or interconnect structure 102 (e.g., see [link]). Figure 5A and Figure 5B Electrically coupled to the metal core 128. In various embodiments, the bias voltage is about -3 volts (in the range of about -20 volts to +20 volts) or another suitable value. During operation of the image sensor 100, the bias circuit 130 applies a bias voltage (e.g., a negative bias of about -3 volts) that generates electron-hole accumulation along the sidewalls of the isolation structure 120 (i.e., along the sidewalls of the first dielectric liner 122) and prevents electrons from being trapped in the vicinity of the isolation structure 120, thereby reducing leakage current and further reducing crosstalk between adjacent photodetectors 118. Additionally, by generating electron-hole accumulation along the sidewalls of the isolation structure 120, the full-well capacity of each of the plurality of photodetectors 118 is increased.

[0026] Furthermore, because the bias circuit 130 increases the full-well capacity of the photodetector 118 by applying a negative bias voltage, the fabrication of deep implanted wells (not shown) surrounding each of the photodetectors 118 can be omitted. This slows down the diffusion of dopants outward from the deep implanted wells and reduces the cost associated with fabricating the image sensor 100, thereby increasing the overall performance of the photodetector 118. Additionally, the conductive liner 126 comprises a conductive material (e.g., titanium, aluminum, copper, another conductive material, or any combination thereof) and is configured to act as a seed layer for the metal core 128. Therefore, the conductive liner 126 promotes the growth or deposition of the metal core 128 within one or more trenches, thereby reducing the formation of voids within the metal core 128. This partially prevents the metal core 128 from being delaminated from the conductive liner 126, the second dielectric liner 124, and / or the first dielectric liner 122 and increases the structural integrity of the metal core 128, thereby ensuring that a negative bias voltage can be properly applied to the metal core 128 via the bias circuit 130. Therefore, the performance and durability of the image sensor 100 are increased.

[0027] In some embodiments, the isolation structure 120 may be referred to as a deep trench isolation (DTI) structure or a back-side DTI structure. Additionally, the first dielectric liner 122 and the second dielectric liner 124 may be referred to as the dielectric isolation structure of the isolation structure 120.

[0028] Figure 2 Show along Figure 1 A top view of some embodiments of the image sensor 100, captured by line A-A'. In various embodiments, Figure 1 Show along Figure 2 Some embodiments of the image sensor 100 cross-sectional view taken by line A-A'.

[0029] In some embodiments, the isolation structure 120 is arranged in an isolation grid such that the metal core 128 laterally surrounds each photodetector 118. The photodetectors 118 are respectively disposed between opposite sidewalls of the metal core 128. In other embodiments, the metal grid structure ( Figure 1 134) and dielectric lattice structure ( Figure 1 136) directly covers the insulating structure 120 and, when viewed from above, each has the same shape and / or layout as the metal core 128. Therefore, when viewed from above, the metal grid structure ( Figure 1 134) and dielectric lattice structure ( Figure 1 Each of the 136) has a grid shape corresponding to the shape and / or layout of the metal core 128.

[0030] Figure 3 Showing the corresponding Figure 1Cross-sectional views of some embodiments of image sensor 100 and some embodiments of image sensor 300, wherein the metal grid structure 134 directly contacts the metal core 128 of the isolation structure 120.

[0031] In some embodiments, the metal grid structure 134 is electrically coupled to the metal core 128 of the isolation structure 120, and the bias circuit 130 is electrically coupled to the metal core 128 via the metal grid structure 134. Therefore, the bias circuit 130 can apply a negative bias voltage to the isolation structure 120 via the metal grid structure 134. In various embodiments, the substrate 104 may be, for example, or include single-crystal silicon, epitaxial silicon, silicon-germanium (SiGe), silicon-on-insulator (SOI) substrate, another semiconductor material, etc. The isolation structure 120 includes a first dielectric liner 122, a second dielectric liner 124, a conductive liner 126, and a metal core 128. In some embodiments, the first dielectric liner 122 may be or include a high-k dielectric material, hafnium oxide, titanium oxide, aluminum oxide, strontium titanium oxide, zirconium oxide, hafnium silicate (e.g., HfSiO4), lanthanum oxide, yttrium oxide, another dielectric material, or any combination thereof. As used herein, a high-k dielectric material is a dielectric material with a dielectric constant greater than 3.9. In other embodiments, the second dielectric liner 124 may include an oxide, such as silicon dioxide. In yet another embodiment, the first dielectric liner 122 includes a first dielectric material (e.g., a high-k dielectric material) and the second dielectric liner 124 includes a second dielectric material (e.g., silicon dioxide), wherein the first dielectric material has a larger dielectric constant than the second dielectric material.

[0032] The conductive liner 126 may be, for example, titanium, aluminum, carbon, titanium, titanium aluminum carbide, titanium aluminum, another conductive material, or any combination thereof. The metal core 128 may be, for example, copper, silver, gold, tungsten, aluminum, etc. In various embodiments, the metal core 128 may be substantially composed of aluminum. In other embodiments, the metal core 128 includes a first metallic material (e.g., aluminum), and the conductive liner 126 may include the first metallic material and a second metallic material different from the first metallic material. For example, the conductive liner 126 may be, for example, titanium aluminum carbide. Additionally, the upper dielectric layer 132 may be, for example, an oxide, such as silicon dioxide. In various embodiments, the upper dielectric layer 132 may include a second dielectric material (e.g., silicon dioxide) and may be part of the second dielectric liner 124. In yet another embodiment, the sidewalls of the metal core 128 are aligned with the sidewalls of the metal grid structure 134 and / or with the sidewalls of the dielectric grid structure 136.

[0033] Figure 4 Showing the corresponding Figure 1Cross-sectional views of some embodiments of image sensor 100 and some embodiments of image sensor 400, wherein a metal core 128 has a plurality of metal segments 128a to 128c, each having a hexagonal shape. It should be understood that the metal segments 128a to 128c can each have any polygonal shape, such as a rectangle, rhombus, pentagon, hexagon, etc. Furthermore, the top surfaces of the metal core 128 and the conductive liner 126 are disposed above the back surface 104b of the substrate 104. In other embodiments, the width of each metal segment 128a to 128c of the metal core 128 continuously increases from the top surface of the metal core 128 to a first depth below the back surface 104b of the substrate 104, and the width of each metal segment 128a to 128c continuously decreases from the first depth to the bottom surface of the metal core 128. In various embodiments, the first width of the top surface of each metal segment 128a to metal segment 128c is smaller than the second width of the bottom surface of each metal segment 128a to metal segment 128c.

[0034] Furthermore, the first dielectric liner 122 includes a first dielectric layer 402 and a second dielectric layer 404 covering the first dielectric layer 402. The first dielectric layer 402 liner the opposing sidewalls and lower surface of one or more trenches defined by the substrate 104. In yet another embodiment, the top surface of the first dielectric layer 402 is aligned with the back surface 104b of the substrate 104. The second dielectric layer 404 extends from the back surface 104b of the substrate 104 to the inner sidewall of the first dielectric layer 402. In various embodiments, the first dielectric layer 402 and the second dielectric layer 404 each comprise the same dielectric material (e.g., a high-k dielectric material). In yet another embodiment, the top surface of the second dielectric layer 404 is disposed vertically above the top surface of the metal core 128 and the conductive liner 126.

[0035] Figure 5A and Figure 5B Various views of some embodiments of an image sensor 500 are shown, the image sensor 500 including an isolation structure 120 that laterally surrounds a plurality of photodetectors 118 and a bias circuit 130 configured to bias the isolation structure 120. Figure 5A and Figure 5B The image sensor 500 can correspond to Figure 4 Some embodiments of the image sensor 400. Figure 5A As shown by Figure 5B Some embodiments of the cross-sectional view of the image sensor 500 indicated by lines A-A' and B-B'. Figure 5B As shown by Figure 5A Some embodiments of the top view of the image sensor 500 indicated by lines A-A' and B-B'.

[0036] Multiple photodetectors 118 are disposed within a pixel array region 502 of substrate 104, the pixel array region 502 being laterally adjacent to a peripheral region 504 of substrate 104. In various embodiments, a metal core 128 of an isolation structure 120 extends laterally continuously from the pixel array region 502 to the peripheral region 504. A substrate through-hole (TSV) 506 is disposed within the peripheral region 504 and electrically coupled to the metal core 128. In various embodiments, the metal core 128 may directly contact the TSV 506 (not shown). Furthermore, an upper conductive structure 510 extends laterally within the peripheral region 504 and directly covers the TSV 506. In various embodiments, the upper conductive structure 510 may be configured as a bonding pad and may electrically couple the image sensor 500 to another integrated circuit (not shown) or other semiconductor device (not shown). The upper conductive structure 510 is configured to electrically couple the metal core 128 of the isolation structure 120 to the TSV 506, and the TSV 506 is electrically coupled to the bottom conductive line 108 within the interconnect structure 102. Therefore, in various embodiments, the metal core 128 can be electrically coupled to the bias circuit 130 by means of the upper conductive structure 510, the TSV 506, and / or the interconnect structure 102. Furthermore, a third dielectric liner 508 is disposed within the peripheral region 504 and laterally surrounds the TSV 506. The third dielectric liner 508 is configured to electrically isolate the TSV 506 from other devices and / or structures disposed within and / or on the substrate 104. In yet another embodiment, the third dielectric liner 508 laterally separates the metal core 128 from the TSV 506. In various embodiments, the TSV 506 may be referred to as a negative bias terminal, and the upper conductive structure 510 may be referred to as a negative bias pad or a negative bias contact.

[0037] Figure 6A Showing the corresponding Figure 1A cross-sectional view of some embodiments of image sensor 100 and image sensor 600, wherein a metal core 128 has a plurality of metal segments 128a to 128c disposed within a substrate 104. In various embodiments, the width of each metal segment 128a to 128c decreases continuously from the bottom surface of the metal grid structure 134 to the back surface 104b of the substrate 104. In other embodiments, the curved sidewalls of each metal segment 128a to 128c are directly covered by a conductive liner 126. A first distance 602 is defined between opposing sidewalls of the first dielectric liner 122 and above a segment of a trench in which an intermediate metal segment 128b of the metal core 128 is disposed. In various embodiments, the first distance 602 is about 60 nanometers (nm) (in the range of about 50 nanometers to 70 nanometers) or another suitable value. Furthermore, the height 604 of the metal segments 128a to 128c disposed within the substrate 104 is approximately 2 micrometers (µm) (in the range of approximately 1.9 micrometers to approximately 2.1 micrometers) or another suitable value. In yet another embodiment, the outer metal segment 128c includes sidewalls defining a gap 606 disposed within a trench in the substrate 104.

[0038] Figure 6B Show Figure 6A A cross-sectional view of some embodiments of an image sensor 600, wherein an upper portion of a metal core 128 is disposed above the top surface of a first dielectric liner 122 and includes opposing sidewalls directly overlying a second dielectric liner 124. The metal core 128 extends continuously from a first position aligned with the top surface of the second dielectric liner 124 to a second position below the back surface 104b of the substrate 104.

[0039] Figures 7 to 16 Cross-sectional views 700 to 1600 illustrate some embodiments of a method for forming an image sensor according to the present disclosure, the image sensor including an isolation structure laterally surrounding a plurality of photodetectors and a bias circuit configured to bias the isolation structure. Although described with reference to the method... Figures 7 to 16 The cross-sectional views 700 to 1600 are shown in the figure, but it should be understood that... Figures 7 to 16 The structures illustrated herein are not limited to the method described, but can be used independently of the method. Furthermore, although... Figures 7 to 16 The description is a series of actions, but it should be understood that these actions are not limited to other embodiments where the order of the actions may be changed, and the disclosed methods are also applicable to other structures. In other embodiments, some actions shown and / or described may be omitted entirely or partially.

[0040] like Figure 7As shown in cross-sectional view 700, a plurality of photodetectors 118 are formed within pixel array region 502 of substrate 104. In some embodiments, substrate 104 may be, for example, or include a bulk silicon substrate, single-crystal silicon, epitaxial silicon, silicon-germanium (SiGe), or another suitable semiconductor material and / or include a first doping type (e.g., p-type). Substrate 104 includes a front surface 104f opposite to back surface 104b. In various embodiments, the process for forming the plurality of photodetectors 118 includes: selectively forming a mask layer (not shown) over the front surface 104f of the substrate; performing a selective ion implantation process based on the mask layer, thereby implanting one or more dopants into substrate 104 and forming photodetectors 118; and performing a removal process to remove the mask layer (not shown). The one or more dopants may be, for example, or include phosphorus, arsenic, antimony, another suitable n-type dopant, or any combination thereof having a second doping type (e.g., n-type). Therefore, photodetectors 118 include a second doping type (e.g., n-type). In various embodiments, the first doping type is p-type and the second doping type is n-type, or vice versa.

[0041] like Figure 8 As shown in cross-sectional view 800, a plurality of pixel devices 112 and interconnect structures 102 are formed along the front surface 104f of substrate 104. In some embodiments, each pixel device 112 includes a gate electrode 114 and a gate dielectric layer 116 disposed between the gate electrode 114 and the substrate 104. The interconnect structure 102 includes an interconnect dielectric structure 106, a plurality of conductive lines 108, and a plurality of vias 110. In various embodiments, the interconnect dielectric structure 106 may be formed by one or more deposition processes, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), another suitable growth or deposition process, or any combination thereof. In other embodiments, the plurality of pixel devices 112, the plurality of conductive lines 108 and / or the plurality of vias 110 may be formed by one or more deposition processes, one or more patterning processes, one or more planarization processes, one or more ion implantation processes or some other suitable processes.

[0042] like Figure 9As shown in cross-sectional view 900, a patterning process is performed on the back surface 104b of substrate 104 to define an isolation structure opening 902 extending from the back surface 104b to a location below the back surface 104b. In various embodiments, the isolation structure opening 902 may be referred to as a trench, and substrate 104 includes opposing sidewalls and a lower surface defining the isolation structure opening 902. In some embodiments, the patterning process includes: forming a mask layer (not shown) over the back surface 104b of substrate 104; etching substrate 104 according to the mask layer, thereby defining the isolation structure opening 902; and performing a removal process to remove the mask layer (not shown). In such embodiments, the etching process may include performing a wet etching process, a dry etching process, another suitable etching process, or any combination thereof.

[0043] like Figure 10 As shown in cross-sectional view 1000, a first dielectric liner 122 is formed over the substrate 104 such that the first dielectric liner 122 liners the isolation structure opening 902. The first dielectric liner 122 may be formed over the substrate 104 by one or more deposition processes (such as PVD, CVD, ALD, or another suitable growth or deposition process). Furthermore, the first dielectric liner 122 includes a first dielectric layer 402 and a second dielectric layer 404, wherein the first dielectric layer 402 liners the sidewall of the substrate 104 defining the isolation structure opening 902, and the second dielectric layer 404 is disposed along the back surface 104b of the substrate 104. In yet another embodiment, the process for forming the first dielectric liner 122 includes: depositing a first dielectric layer 402 over the substrate 104 and within the isolation structure opening 902 by a first deposition process; performing a planarization process on the first dielectric layer 402; and depositing a second dielectric layer 404 over the substrate 104 and the first dielectric layer 402 by a second deposition process. In various embodiments, the first deposition process and the second deposition process differ. For example, the first deposition process may include performing an ALD process, a plasma-enhanced ALD (PEALD) process, a CVD process, a metal-organic CVD (MOCVD) process, etc., and the second deposition process may include performing a PVD process, a plasma-enhanced CVD (PECVD) process, etc. In yet another embodiment, the planarization process may include an etching process, a chemical mechanical planarization (CMP) process, etc., and the planarization process may be performed such that the top surface of the first dielectric layer 402 is coplanar with the back surface 104b of the substrate 104. In other embodiments, after depositing the second dielectric layer 404 over the substrate and the first dielectric layer 402, an etch-back process can be performed to remove the second dielectric layer 404 from the region of the isolation structure opening 902.

[0044] The first dielectric layer 402 may be, for example, or include a high-k dielectric material, hafnium oxide, titanium oxide, aluminum oxide, strontium titanium oxide, zirconium oxide, hafnium silicate (e.g., HfSiO4), lanthanum oxide, yttrium oxide, another dielectric material, or any combination thereof. The second dielectric layer 404 may be, for example, or include a high-k dielectric material, hafnium oxide, titanium oxide, tantalum oxide, aluminum oxide, strontium titanium oxide, zirconium oxide, hafnium silicate (e.g., HfSiO4), lanthanum oxide, yttrium oxide, another dielectric material, or any combination thereof.

[0045] like Figure 11 As shown in cross-sectional view 1100, a second dielectric liner 124 is formed over the first dielectric liner 122 such that the second dielectric liner 124 liners the opening 902 of the isolation structure. In various embodiments, the second dielectric liner 124 is formed by a PECVD process, a PEALD process, an ALD process, a PVD process, or another suitable growth or deposition process. Furthermore, the second dielectric liner 124 may be, for example, an oxide, such as silicon dioxide, and has a dielectric constant that is smaller than that of the first dielectric layer 402 and the second dielectric layer 404, respectively.

[0046] like Figure 12 As shown in cross-sectional view 1200, a conductive liner 126 is formed above the back surface 104b of the substrate 104, and a metal core 128 is formed above the conductive liner 126. The conductive liner 126 is lined within the opening of the isolation structure ( Figure 11 The isolation structure opening 902), and the metal core 128 fills the isolation structure opening ( Figure 11 The isolation structure opening 902). In various embodiments, the conductive liner 126 is formed by a third deposition process, and the metal core 128 is formed by a fourth deposition process different from the third deposition process. For example, the third deposition process may include performing an ALD process, and the fourth deposition process may include performing a CVD process. It should be understood that the conductive liner 126 and the metal core 128 can be formed by other deposition processes (such as PVD, CVD, sputtering, electroplating, electrodeless plating, or another suitable deposition or growth process). In yet another embodiment, the conductive liner 126 may be configured as a seed layer that promotes the metal core 128 in the isolation structure opening ( Figure 11 Appropriate growth or deposition within the 902) reduces the presence of voids within the metal core 128. This partially increases the structural integrity of the metal core 128, promotes the reduction of crosstalk between the photodetectors 118, and ensures that a bias voltage (e.g., a negative bias) can be properly applied to the metal core 128. Furthermore, the conductive liner 126 can also be configured as a diffusion barrier layer that slows the diffusion of conductive material from the metal core 128 to the first dielectric liner 122, the second dielectric liner 124, and the substrate 104.

[0047] The conductive liner 126 may be, for example, or comprise titanium, aluminum, carbon, titanium, titanium aluminum carbide, titanium aluminum, another conductive material, or any combination thereof. The metal core 128 may be, for example, or comprise copper, silver, gold, tungsten, aluminum, etc. In various embodiments, the metal core 128 may be substantially composed of aluminum. In other embodiments, the metal core 128 comprises a first metallic material (e.g., aluminum), and the conductive liner 126 may comprise the first metallic material and a second metallic material different from the first metallic material. For example, the conductive liner 126 may be, for example, titanium aluminum carbide.

[0048] like Figure 13 As shown in cross-sectional view 1300, a planarization process is performed on the metal core 128 and the conductive substrate 126, thereby defining the isolation structure 120. In various embodiments, the planarization process may include performing a CMP process on the metal core 128 and the conductive substrate 126 until the top surface of the second dielectric substrate 124 is reached. In various embodiments, the process for forming the isolation structure 120 may include... Figures 9 to 13 The processing steps shown and described are as follows.

[0049] like Figure 14 As shown in cross-sectional view 1400, a substrate through-hole (TSV) 506 is formed above the conductive line 108 within the peripheral region 504. Furthermore, a third dielectric liner 508 is formed within the substrate 104 and laterally surrounds the TSV 506, and an upper conductive structure 510 is formed within the peripheral region 504, located above the TSV 506 and the metal core 128. The upper conductive structure 510 electrically couples the metal core 128 to the TSV 506.

[0050] like Figure 15As shown in cross-sectional view 1500, an upper dielectric layer 132 is formed within the pixel array region 502 and above the isolation structure 120. Additionally, a metal grid structure 134 and a dielectric grid structure 136 are formed above the upper dielectric layer 132, such that a metal core 128 is overlaid on the metal grid structure 134 and the dielectric grid structure 136. In some embodiments, the upper dielectric layer 132 is formed using a PECVD process, a PEALD process, an ALD process, a PVD process, or another suitable growth or deposition process. In other embodiments, the upper dielectric layer 132 can be formed using the same deposition process as the second dielectric substrate 124. The upper dielectric layer 132 may be, for example, an oxide, such as silicon dioxide, and has a dielectric constant that is smaller than that of the first dielectric layer 402 and the second dielectric layer 404, respectively. The process for forming the metal grid structure 134 and the dielectric grid structure 136 includes: depositing a metal grid layer over an upper dielectric layer 132 (e.g., by PVD, CVD, ALD, etc.); depositing a dielectric grid layer over the metal grid layer (e.g., by PVD, CVD, ALD, etc.); forming a mask layer (not shown) over the dielectric grid layer; patterning the metal grid layer and the dielectric grid layer according to the mask layer, thereby defining the metal grid structure 134 and the dielectric grid structure 136; and performing a removal process to remove the mask layer.

[0051] like Figure 16 As shown in cross-sectional view 1600, a plurality of color filters 138 are formed above a plurality of photodetectors 118, and a plurality of microlenses 140 are formed above the plurality of color filters 138. In some embodiments, the color filters 138 and microlenses 140 may be deposited by, for example, CVD, PVD, ALD, or another suitable deposition or growth process. Additionally, a bias circuit 130 is formed to be electrically coupled to the metal core 128 and the substrate 104, wherein the bias circuit 130 is configured to apply a bias voltage (e.g., a negative bias voltage) to the metal core 128 by means of an interconnect structure, a TSV 506, and an upper conductive structure 510. In various embodiments, the bias voltage may be about -3 volts (in the range of about -20 volts to about +20 volts) or another suitable value. Applying a bias voltage to the metal core 128 by means of the bias circuit 130 eliminates the need for the formation of a deep implanted well (not shown) around the photodetector 118 and increases the full-well capacity of the photodetector 118. This can partially reduce the number of people who are in contact with the virus. Figures 7 to 16 The method reduces the number of processing steps performed and improves the performance of the photodetector 118.

[0052] Figure 17Some embodiments of a method 1700 for forming an image sensor according to this disclosure are shown, the image sensor including an isolation structure laterally surrounding a plurality of photodetectors and a bias circuit configured to bias the isolation structure. Although method 1700 is shown and / or described as a series of actions or events, it should be understood that the method is not limited to the shown order or actions. Therefore, in some embodiments, actions may be performed and / or may be performed simultaneously with different sequences shown. Additionally, in some embodiments, the shown actions or events may be subdivided into multiple actions or events that may be performed at different times or simultaneously with other actions or sub-actions. In some embodiments, some shown actions or events may be omitted, and other actions or events not shown may be included.

[0053] At action 1702, multiple photodetectors are formed within the pixel array region of the substrate. Figure 7 A cross-sectional view 700 is shown, corresponding to some embodiments of action 1702.

[0054] At action 1704, the back surface of the substrate is patterned to define trenches extending into the back surface of the substrate. Figure 9 A cross-sectional view 900 is shown, corresponding to some embodiments of action 1704.

[0055] At action 1706, a first dielectric liner is formed above the back surface of the substrate and within the trench. Figure 10 Cross-sectional view 1000 is shown for some embodiments corresponding to action 1706.

[0056] At action 1708, a second dielectric substrate is formed over the first dielectric substrate. Figure 11 Cross-sectional view 1100 shows some embodiments corresponding to action 1708.

[0057] At action 1710, a conductive substrate is formed over the second dielectric substrate. Figure 12 A cross-sectional view 1200 is shown, corresponding to some embodiments of action 1710.

[0058] At action 1712, a metal core is formed above the conductive liner and within the trench, such that the metal core laterally surrounds each of the plurality of photodetectors. Figure 12 A cross-sectional view 1200 is shown, corresponding to some embodiments of action 1712.

[0059] At step 1714, a planarization process is performed on the metal core and conductive liner. Figure 13 Cross-sectional view 1300 is shown for some embodiments corresponding to action 1714.

[0060] At action 1716, a substrate through-hole (TSV) is formed in the peripheral region of the substrate, and an upper conductive structure is formed above the back surface of the substrate. The upper conductive structure electrically couples the TSV to the metal core. Figure 14 Cross-sectional view 1400 is shown for some embodiments corresponding to action 1716.

[0061] At action 1718, a metal grid structure is formed above the metal core, and a dielectric grid structure is formed above the metal grid structure. Figure 15 Cross-sectional view 1500 is shown for some embodiments corresponding to action 1718.

[0062] At action 1720, multiple color filters are formed above the photodetector, and multiple microlenses are formed above the color filters. Figure 16 Cross-sectional view 1600 shows some embodiments corresponding to action 1720.

[0063] At action 1722, a bias circuit is formed that is electrically coupled to the metal core and the substrate. Figure 16 Cross-sectional view 1600 shows some embodiments corresponding to action 1722.

[0064] Therefore, in some embodiments, this disclosure relates to an image sensor including an isolation structure laterally surrounding a photodetector, wherein the isolation structure includes a conductive liner and a metal core. A bias circuit is electrically coupled to the metal core and configured to apply a bias voltage to the metal core.

[0065] In some embodiments, this disclosure provides an image sensor comprising: a semiconductor substrate including a front surface opposite to a back surface; a plurality of photodetectors disposed in the semiconductor substrate; and an isolation structure extending from the back surface of the semiconductor substrate into the semiconductor substrate and disposed between adjacent photodetectors, wherein the isolation structure includes a metal core, a conductive liner disposed between the semiconductor substrate and the metal core, and a first dielectric liner disposed between the conductive liner and the semiconductor substrate, wherein the metal core includes a first metal material, and the conductive liner includes the first metal material and a second metal material different from the first metal material.

[0066] In some embodiments, the width of the metal core continuously increases from the back surface to a first position disposed below the back surface, and the width of the metal core continuously decreases from the first position to a second position disposed below the first position. In some embodiments, the first metal material comprises aluminum, and the second metal material comprises titanium and carbon. In some embodiments, the image sensor further comprises: a second dielectric substrate disposed between the first dielectric substrate and the conductive substrate, wherein the first dielectric substrate has a first dielectric constant greater than the second dielectric constant of the second dielectric substrate. In some embodiments, the image sensor further comprises: a conductive grid structure covering the back surface of the semiconductor substrate, wherein the conductive grid structure directly covers and is aligned with the metal core. In some embodiments, the image sensor further comprises: a bias circuit electrically coupled to the isolation structure and configured to apply a negative bias voltage to the metal core. In some embodiments, the bias circuit is configured to apply the negative bias voltage to the metal core by means of the conductive grid structure. In some embodiments, the metal core includes sidewalls defining gaps, wherein the gaps are located between and laterally spaced from the opposite sidewalls of the conductive substrate.

[0067] In some embodiments, this disclosure provides an image sensor comprising: a semiconductor substrate including sidewalls defining a trench; a plurality of photodetectors laterally arranged within a pixel array region of the semiconductor substrate; an isolation structure disposed within the trench of the semiconductor substrate, wherein the isolation structure laterally surrounds the plurality of photodetectors, wherein the isolation structure includes a metal core and a conductive liner disposed between the sidewalls of the defining trench of the semiconductor substrate and the metal core; a metal grid structure overlying the isolation structure; and a bias circuit electrically coupled to the metal core and configured to apply a bias voltage to the metal core.

[0068] In some embodiments, the image sensor further includes: a substrate via disposed within a peripheral region of the semiconductor substrate, wherein the peripheral region is laterally offset from the pixel array region, and wherein the metal core is electrically coupled to the substrate via. In some embodiments, the image sensor further includes: an upper conductive structure extending laterally within the peripheral region, wherein the bias circuitry is electrically coupled to the metal core via the substrate via and the upper conductive structure. In some embodiments, the metal core extends laterally continuously from the pixel array region to the peripheral region and directly contacts the upper conductive structure. In some embodiments, the top surface of the metal core and the top surface of the conductive liner directly contact the bottom surface of the metal grid structure. In some embodiments, the metal core is substantially composed of aluminum, and the conductive liner comprises aluminum titanium carbide. In some embodiments, the image sensor further includes: a first dielectric liner disposed between the conductive liner and the semiconductor substrate, wherein the first dielectric liner comprises a first dielectric layer and a second dielectric layer, wherein the first dielectric layer liners the sidewalls of the semiconductor substrate defining the trench, and wherein the second dielectric layer extends continuously from the back surface of the semiconductor substrate to the inner sidewall of the first dielectric layer. In some embodiments, the top surface of the first dielectric layer is vertically aligned with the back surface of the semiconductor substrate.

[0069] In some embodiments, this disclosure provides a method for forming an image sensor, the method comprising: forming a plurality of photodetectors within a semiconductor substrate; patterning a back surface of the semiconductor substrate to define trenches extending from the back surface of the semiconductor substrate into the semiconductor substrate; depositing a first dielectric liner over the semiconductor substrate such that the first dielectric liner liner is within the trenches; forming an isolation structure in the trenches, wherein forming the isolation structure includes depositing a conductive liner over the first dielectric liner and depositing a metal core over the conductive liner, wherein the metal core comprises a first metal material, and wherein the conductive liner comprises the first metal material and a second conductive material different from the first metal material; and performing a planarization process on the metal core and the conductive liner.

[0070] In some embodiments, the method for forming an image sensor further includes: forming a conductive grid structure above the back surface of the semiconductor substrate, such that the conductive grid structure directly covers and aligns with the metal core of the isolation structure. In some embodiments, the conductive substrate is deposited using an atomic layer deposition process, and the metal core is deposited using a chemical vapor deposition process. In some embodiments, a first distance between the metal core and the first dielectric substrate at a first position vertically aligned with the back surface of the semiconductor substrate is greater than a second distance between the metal core and the first dielectric substrate at a second position vertically aligned with the bottom surface of the metal core.

[0071] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of this disclosure. Those skilled in the art will understand that this disclosure can be readily used as a basis for designing or modifying other processes and structures for carrying out the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

Claims

1. An image sensor, comprising: A semiconductor substrate, including a front surface opposite to a back surface; Multiple photodetectors are disposed in the semiconductor substrate; as well as An isolation structure extends from the back surface of the semiconductor substrate into the semiconductor substrate and is disposed between adjacent photodetectors. The isolation structure includes a metal core, a conductive liner disposed between the semiconductor substrate and the metal core, and a first dielectric liner disposed between the conductive liner and the semiconductor substrate. The metal core comprises a first metal material, and the conductive liner comprises the first metal material and a second metal material different from the first metal material. The width of the metal core continuously increases from the back surface to a first position below the back surface, and the width of the metal core continuously decreases from the first position to a second position below the first position.

2. The image sensor according to claim 1, wherein the first metal material comprises aluminum, and the second metal material comprises titanium and carbon.

3. The image sensor according to claim 1, further comprising: A second dielectric substrate is disposed between the first dielectric substrate and the conductive substrate, wherein the first dielectric substrate has a first dielectric constant that is greater than the second dielectric constant of the second dielectric substrate.

4. The image sensor according to claim 1, further comprising: A conductive grid structure is overlaid on the back surface of the semiconductor substrate, wherein the conductive grid structure is directly overlaid on and aligned with the metal core.

5. The image sensor according to claim 4, further comprising: A bias circuit is electrically coupled to the isolation structure and configured to apply a negative bias voltage to the metal core.

6. The image sensor of claim 5, wherein the bias circuit is configured to apply the negative bias voltage to the metal core by means of the conductive grid structure.

7. The image sensor of claim 1, wherein the metal core includes sidewalls defining a gap, wherein the gap is located between and laterally spaced from the opposite sidewalls of the conductive liner.

8. An image sensor, comprising: A semiconductor substrate, including sidewalls defining a trench, a back surface, and a front surface opposite the back surface; Multiple photodetectors are arranged laterally within the pixel array region of the semiconductor substrate; An isolation structure is disposed within the trench of the semiconductor substrate, wherein the isolation structure laterally surrounds the plurality of photodetectors, wherein the isolation structure includes a metal core and a conductive liner, the conductive liner being disposed between the sidewall defining the trench of the semiconductor substrate and the metal core; A metal grid structure, covered by the aforementioned isolation structure; as well as A bias circuit, electrically coupled to the metal core and configured to apply a bias voltage to the metal core. The isolation structure extends from the back surface of the semiconductor substrate, wherein the width of the metal core continuously increases from the top surface of the metal core to a first depth below the back surface of the semiconductor substrate, and the width of the metal core continuously decreases from the first depth to the bottom surface of the metal core.

9. The image sensor according to claim 8, further comprising: A substrate via is disposed in a peripheral region of the semiconductor substrate, wherein the peripheral region is laterally offset from the pixel array region, and wherein the metal core is electrically coupled to the substrate via.

10. The image sensor according to claim 9, further comprising: An upper conductive structure extends laterally within the peripheral region, wherein the bias circuitry is electrically coupled to the metal core via the substrate vias and the upper conductive structure.

11. The image sensor of claim 10, wherein the metal core extends laterally from the pixel array region to the peripheral region and directly contacts the upper conductive structure.

12. The image sensor of claim 8, wherein the top surface of the metal core and the top surface of the conductive liner are in direct contact with the bottom surface of the metal grid structure.

13. The image sensor of claim 8, wherein the metal core is composed of aluminum, and the conductive liner comprises aluminum titanium carbide.

14. The image sensor according to claim 8, further comprising: A first dielectric liner is disposed between the conductive liner and the semiconductor substrate, wherein the first dielectric liner includes a first dielectric layer and a second dielectric layer, wherein the first dielectric layer is lined within the sidewall of the semiconductor substrate defining the trench, and wherein the second dielectric layer extends continuously from the back surface of the semiconductor substrate to the inner sidewall of the first dielectric layer.

15. The image sensor of claim 14, wherein the top surface of the first dielectric layer is vertically aligned with the back surface of the semiconductor substrate.

16. A method for forming an image sensor, comprising: Multiple photodetectors are formed within a semiconductor substrate, wherein the semiconductor substrate has a front surface and a back surface opposite to the front surface; The back surface of the semiconductor substrate is patterned to define trenches extending from the back surface of the semiconductor substrate into the semiconductor substrate. A first dielectric liner is deposited over the semiconductor substrate such that the first dielectric liner is lining the trench; An isolation structure is formed in the trench, wherein forming the isolation structure includes depositing a conductive liner over the first dielectric liner and depositing a metal core over the conductive liner, wherein the metal core comprises a first metal material, and wherein the conductive liner comprises the first metal material and a second conductive material different from the first metal material; as well as A planarization process is performed on the metal core and the conductive liner. The isolation structure extends from the back surface of the semiconductor substrate, wherein the width of the metal core increases continuously from the top surface of the metal core to a first depth below the back surface of the semiconductor substrate, and the width of the metal core decreases continuously from the first depth to the bottom surface of the metal core.

17. The method for forming an image sensor according to claim 16, further comprising: A conductive grid structure is formed above the back surface of the semiconductor substrate, such that the conductive grid structure directly covers the metal core of the isolation structure and is aligned with the metal core of the isolation structure.

18. The method for forming an image sensor according to claim 16, wherein the conductive substrate is deposited by atomic layer deposition and the metal core is deposited by chemical vapor deposition.

19. The method for forming an image sensor according to claim 16, wherein a first distance between the metal core and the first dielectric substrate at a first position vertically aligned with the back surface of the semiconductor substrate is greater than a second distance between the metal core and the first dielectric substrate at a second position vertically aligned with the bottom surface of the metal core.

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