Vertical transistor and its manufacturing method

Abstract

The various embodiments disclosed in this invention relate to a vertical transistor and a method for manufacturing the same, wherein the vertical transistor has different doping distributions in its upper and lower channel layers to reduce leakage current while increasing contact resistance. According to one embodiment of the invention, a semiconductor device includes: a lower contact, a vertical channel layer on the lower contact, and an upper contact on the vertical channel layer, wherein the vertical channel layer comprises a metal component and an oxygen component. The vertical channel layer has a gradient doping distribution, wherein the doping concentration of the metal component is lowest in the middle region and gradually increases from the middle region upwards to the upper contact.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0003864, filed on January 12, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Exemplary embodiments of the present invention relate to a vertical transistor and a method for manufacturing the same, and more specifically, to a vertical transistor using an oxide semiconductor as a channel layer and a method for manufacturing the same. Background Technology

[0004] With the increasing integration of memory devices, techniques for using vertical transistors have been proposed to increase transistor density. Techniques have also been proposed to use oxide semiconductors with excellent electrical properties as channel materials for vertical transistors. Summary of the Invention

[0005] The various embodiments disclosed in this invention relate to a vertical transistor and a method for manufacturing the same, wherein the vertical transistor has different doping distributions in its upper and lower channel layers to reduce leakage current and improve contact resistance.

[0006] According to one embodiment of the present invention, a semiconductor device includes: a lower contact portion, a vertical channel layer on the lower contact portion, and an upper contact portion on the vertical channel layer, wherein the vertical channel layer comprises a metal component and an oxygen component. The vertical channel layer has a gradient doping distribution, wherein the doping concentration of the metal component is lowest in an intermediate region and gradually increases from the intermediate region to the upper contact portion.

[0007] According to one embodiment of the present invention, a vertical transistor includes: a lower contact portion on a substrate; a channel layer including a lower channel layer, an intermediate channel layer, and an upper channel layer sequentially formed on the lower contact portion, the channel layer comprising a metal component and an oxygen component; and an upper contact portion on the upper channel layer. The channel layers have a gradient doping distribution, wherein the doping concentration of the metal component is lowest in the intermediate channel layer and gradually increases towards the upper contact portion in the upper channel layer.

[0008] According to one embodiment of the present invention, a method for manufacturing a vertical transistor includes: forming a lower contact material on a substrate, forming a lower channel material comprising a metal component and an oxygen component on the lower contact material, forming a channel material comprising a metal component and an oxygen component on the lower channel material, and performing a process on the channel material to divide the channel material into an intermediate channel material and an upper channel material on the intermediate channel material.

[0009] According to one embodiment of the present invention, leakage current can be reduced by forming different doping distributions in the upper channel layer and the lower channel layer.

[0010] According to one embodiment of the present invention, contact resistance can be improved by forming an upper insertion layer between the channel layer and the upper contact portion and a lower insertion layer between the channel layer and the lower contact portion. Attached Figure Description

[0011] Figure 1 This is a perspective view showing a vertical transistor according to one embodiment.

[0012] Figure 2 This is a perspective view showing the upper contact, lower contact, and channel layer of a vertical transistor according to one embodiment.

[0013] Figure 3A , Figure 3B , Figure 3C , Figure 3D , Figure 3E , Figure 3F , Figure 3G , Figure 3H and Figure 3I This is a diagram illustrating an example method of manufacturing a vertical transistor according to one embodiment; Figure 4A , Figure 4B , Figure 4C and Figure 4D This is a perspective view showing the upper contact portion, lower contact portion, and channel layer of a vertical transistor according to one embodiment; Figure 5 This is a perspective view showing a vertical transistor according to one embodiment.

[0014] Figure 6 This is a perspective view showing the upper contact, lower contact, and channel layer of a vertical transistor according to one embodiment.

[0015] Figure 7A and Figure 7B This is a perspective view showing the upper contact, lower contact, and channel layer of a vertical transistor according to one embodiment; and Figure 8 This is a perspective view showing a vertical transistor according to one embodiment. Detailed Implementation

[0016] In this document, exemplary cross-sectional views, plan views, and block diagrams may be used to describe various embodiments of the present disclosure and may be modified according to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the present disclosure are not limited to the specific types shown and described herein, but may include changes or modifications caused by manufacturing processes. For example, areas or regions shown in the drawings may be schematically illustrated, and the shapes shown are provided only as examples and are not intended to limit the type or scope of the invention. For illustrative purposes, elements shown in the drawings may be exaggerated in terms of their thickness and spacing. Well-known components or elements unrelated to the subject matter of the present disclosure may be omitted from the description. Throughout the specification and drawings, the same or substantially the same reference numerals are used to refer to the same or substantially the same elements. Embodiments of the present disclosure are described in detail below in conjunction with the accompanying drawings.

[0017] Figure 1 This is a perspective view showing a vertical transistor according to one embodiment.

[0018] like Figure 1 As shown, the vertical transistor 100 may include a stacked structure comprising a lower contact 110, a channel layer 120, and an upper contact 130. The vertical transistor 100 may also include a dielectric layer 140 and a gate 150 formed on the side surface of the channel layer 120. That is, the lower contact 110, the channel layer 120, and the upper contact 130 may have a stacked structure in a direction perpendicular to the substrate (not shown), while the dielectric layer 140 and the gate 150 may have a stacked structure in a direction parallel to the substrate (not shown).

[0019] The lower contact portion 110 and the channel layer 120 may be square columnar; however, their shapes are not limited to this and may include various other shapes (e.g., rectangular columnar or cylindrical) as needed. The lower contact portion 110 and the channel layer 120 may have the same width. The upper contact portion 130 may be cylindrical; however, its shape is not limited to this and may include various other shapes (e.g., square columnar or rectangular columnar) as needed.

[0020] The diameter of the upper contact 130 (or the width when the upper contact 130 has a square column shape) can be smaller than the diameter (or width) of the channel layer 120. A dielectric layer 140 can be formed on the side surface of the channel layer 120. The dielectric layer 140 can cover all sidewalls of the channel layer 120. That is, the dielectric layer 140 can be formed to surround the entire side surface of the channel layer 120. The channel layer 120 and the dielectric layer 140 can have the same height. Height refers to the dimension of the channel layer 120 and the dielectric layer 140 in their stacking direction. A gate 150 can be formed to surround the dielectric layer 140. The thickness of the gate 150 can be greater than the thickness of the dielectric layer 140. The gate 150 can cover all sidewalls of the dielectric layer 140. That is, the gate 150 can be formed to surround the entire side surface of the dielectric layer 140. Therefore, the dielectric layer 140 can be located between the gate 150 and the channel layer 120.

[0021] The lower contact 110 may be disposed on a substrate, such as a semiconductor substrate (not shown). The lower contact 110 may include a metallic material. The lower contact 110 may include a metal or a metal compound. The lower contact 110 may include a tungsten-containing material. Alternatively, the lower contact 110 may include a semiconductor material. The lower contact 110 may include a silicon-containing material. The lower contact 110 may be doped with impurities.

[0022] Channel layer 120 may be located on lower contact 110. Channel layer 120 may be referred to as a "vertical channel layer". Channel layer 120 may include an oxide. Channel layer 120 may include a metal component and an oxygen component. Channel layer 120 may include an oxide semiconductor. For example, channel layer 120 may include at least one of indium (In), gallium (Ga), or zinc (Zn). Channel layer 120 may include InSn, InGaZnO, InSnZnO, InGASnO, InSnO, InZnO, InGaO, or combinations thereof. Channel layer 120 may be doped with impurities. Channel layer 120 may be doped with silicon (Si) or germanium (Ge). The doping distribution of the metal material may be non-uniform depending on the height of channel layer 120. An example of doping distribution is described below.

[0023] The upper contact 130 may be located on the channel layer 120. The upper contact 130 may include the same material as the lower contact 110. In another embodiment, the upper contact 130 may include a material different from the lower contact 110. The upper contact 130 may include a metallic material. The upper contact 130 may include a metal or a metal compound. The upper contact 130 may include a tungsten-containing material. Alternatively, the upper contact 130 may include a semiconductor material. The upper contact 130 may include a silicon-containing material. The upper contact 130 may be doped with impurities. Any suitable impurities may be used.

[0024] The vertical transistor 100 may include a gate 150 that surrounds the sidewalls of the channel layer 120 and shares the same axis. A dielectric layer 140 may be located between the gate 150 and the channel layer 120. The gate 150 may be spaced apart from the channel layer 120 by the dielectric layer 140. The gate 150 may include a metal or a metal compound. The dielectric layer 140 may be any suitable dielectric layer known in the art. According to an embodiment, the dielectric layer 140 may include a high-k material, such as HfO2, ZrO2, or other metal oxides.

[0025] Figure 2 This is a perspective view showing the upper contact, lower contact, and channel layer of a vertical transistor according to one embodiment. Figure 2 It is an omission Figure 1 Described by dielectric layer 140 and gate 150 Figure 1 A schematic diagram of the channel layer 120.

[0026] like Figure 2 As shown in Figure 2, the channel layer 120 may include: a lower channel layer 121 formed on the lower contact portion 110, an intermediate channel layer 122 formed on the lower channel layer 121, and an upper channel layer 123 formed on the intermediate channel layer 122. That is, the channel layer 120 may include a stack of the lower channel layer 121, the intermediate channel layer 122, and the upper channel layer 123. The height LBO of the lower channel layer 121, the height LG of the intermediate channel layer 122, and the height LTO of the upper channel layer 123 may be the same or different.

[0027] The channel layer 120 may include an oxide. The channel layer 120 may include a metallic material and an oxygen material. The channel layer 120 may include an oxide semiconductor. The channel layer 120 may be doped with impurities. The impurity doping distribution in the channel layer 120 may be non-uniform depending on the height. The impurity doping distribution may differ in the lower channel layer 121, the middle channel layer 122, and the upper channel layer 123.

[0028] Figure 2 The schematic diagram illustrates the doping concentration of the metal composition at corresponding height positions. As the doping concentration increases, the metallicity increases. As the metallicity of the upper surface of the channel layer 120 increases, the contact resistance with the upper contact portion 130 can decrease. As the metallicity of the lower surface of the channel layer 120 increases, the contact resistance with the lower contact portion 110 can decrease.

[0029] The channel layer 120 may have a gradual doping distribution, wherein the doping concentration of the metal component gradually increases in a region closer to the upper contact 130 (e.g., closer to the upper contact 130 from the boundary between the intermediate channel layer 122 and the upper channel layer 123). The channel layer 120 may also have an abrupt doping distribution, wherein the doping concentration of the metal component changes abruptly in a region closer to the lower contact 110 (e.g., at the boundary between the intermediate channel layer 122 and the lower channel layer 121). That is, at the boundary between the intermediate channel layer 122 and the lower channel layer 121, the doping concentration of the metal component may increase rapidly. For example, an abrupt doping distribution may include a stepped distribution.

[0030] The doping concentration can be divided into: a first doped region P1 corresponding to the height LB of the lower contact layer, a second doped region P2 corresponding to the height LBO of the lower channel layer, a third doped region P3 corresponding to the height LG of the intermediate channel layer, a fourth doped region P4 corresponding to the height LTO of the upper channel layer, and a fifth doped region P5 corresponding to the height LT of the upper contact layer. The doping concentration of the first doped region P1 to the fifth doped region P5 can be continuous. In this embodiment, the doping concentration refers to the doping concentration of the metal component.

[0031] First, the doping concentrations of the first doped region P1, the second doped region P2, and the third doped region P3 can each include constant values. That is, the doping concentration of the metal component in the film can be uniformly maintained in the lower contact 110, the lower channel layer 121, and the intermediate channel layer 122. The doping distribution of the first doped region P1, the second doped region P2, and the third doped region P3 can include a stepped distribution. The doping concentration of the first doped region P1 can be greater than the doping concentrations of the second doped region P2 and the third doped region P3. The doping concentration of the second doped region P2 can be greater than the doping concentration of the third doped region P3. The third doped region P3 can include the lowest doping concentration among the first doped region P1 to the fifth doped region P5. The doping concentration difference between the second doped region P2 and the third doped region P3 can be greater than the doping concentration difference between the first doped region P1 and the second doped region P2. The doping concentration difference between the second doped region P2 and the third doped region P3 can be at least twice the doping concentration difference between the first doped region P1 and the second doped region P2. That is, a sudden doping distribution can be provided, wherein at the boundary between the third doped region P3 and the second doped region P2, the doping concentration of the metal component increases rapidly from the third doped region P3 to the second doped region P2. As the doping concentration difference between the third doped region P3 and the second doped region P2 increases, the doping concentration difference between the second doped region P2 and the first doped region P1 can decrease. As the doping concentration difference between the second doped region P2 and the first doped region P1 decreases, the contact resistance with the lower contact portion 110 can decrease.

[0032] The doping concentration of the fourth doped region P4 can increase at a constant slope in the direction from the fourth doped region P4 to the fifth doped region P5. The doping concentration of the fourth doped region P4 can increase from a doping concentration equal to that of the third doped region P3 to a doping concentration equal to that of the fifth doped region P5. The doping concentration of the fourth doped region P4 can also increase from a doping concentration equal to that of the third doped region P3 to a doping concentration equal to that of the second doped region P2. That is, the fourth doped region P4 can include a gradient doping distribution, wherein the doping concentration of the metal component gradually increases as it approaches the upper surface of the upper channel layer 123.

[0033] In another embodiment, the doping distribution of the fourth doped region P4 may have a doping concentration slope that increases with height. In another embodiment, the doping distribution of the fourth doped region P4 may have a decreasing slope. Because the fourth doped region P4 has a gradually changing doping distribution, leakage current can be reduced. As the doping concentration difference between the fourth doped region P4 and the fifth doped region P5 decreases, the contact resistance with the upper contact portion 130 can be reduced.

[0034] The doping concentration of the fifth doped region P5 can be constant. The doping concentration of the fifth doped region P5 can be lower than or equal to the doping concentration of the first doped region P1. The doping concentration of the fifth doped region P5 can be continuous with the doping concentration of the fourth doped region P4.

[0035] According to this embodiment, the leakage current of the vertical transistor 100 can be reduced by changing the doping distribution of impurities according to the height. According to this embodiment, the contact resistance with the lower contact portion 110 and the upper contact portion 130 can be reduced by forming a higher doping concentration on the upper and lower surfaces of the channel layer 120.

[0036] Figures 3A to 3I This is a schematic diagram illustrating a method for manufacturing a vertical transistor according to one embodiment.

[0037] See Figure 3A Substrate 11 can be fabricated. Substrate 11 may include a semiconductor substrate. Substrate 11 may be formed of a silicon-containing material. Substrate 11 may include other semiconductor materials, such as germanium. Substrate 11 may include a III-V group semiconductor substrate. Substrate 11 may include a compound semiconductor substrate, such as GaAs. Substrate 11 may include a silicon-on-insulator (SOI) substrate.

[0038] The lower contact material 12A may be formed on the substrate 11. The lower contact material 12A may include a metallic material. The lower contact material 12A may include a metal or a metal compound. The lower contact material 12A may include a tungsten-containing material. The lower contact material 12A may be doped with impurities. In another embodiment, the lower contact material 12A may include a silicon-containing material. The lower contact material 12A may include polycrystalline silicon. The lower contact material 12A may include impurity-doped polycrystalline silicon.

[0039] The lower channel material 13A may be formed on the lower contact material 12A. The thickness of the lower channel material 13A may be less than the thickness of the lower contact material 12A. The lower channel material 13A may include an oxide. The lower channel material 13A may include a metal component and an oxygen component. The lower channel material 13A may include an oxide semiconductor. For example, the lower channel material 13A may include at least one of indium (In), gallium (Ga), or zinc (Zn). The lower channel material 13A may include InSn, InGaZnO, InSnZnO, InGASnO, InSnO, InZnO, InGaO, or combinations thereof. The lower channel material 13A may be doped with impurities. For example, the lower channel material 13A may be doped with silicon (Si) or germanium (Ge).

[0040] The lower channel material 13A can be deposited in an oxygen atmosphere. Alternatively, it can be deposited in a low-concentration oxygen atmosphere (O2 environment). This increases oxygen vacancies, resulting in a film with a high doping concentration of the metal component. The lower channel material 13A can include a doping distribution with a constant doping concentration. The doping concentration of the lower channel material 13A can be the same as or different from (e.g., lower than) the doping concentration of the lower contact material 12A.

[0041] The lower channel material 13A can be formed using methods such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plasma-enhanced CVD (PECVD), or plasma-enhanced ALD (PEALD). The lower channel material 13A can be deposited at room temperature. Deposition at room temperature prevents oxygen diffusion.

[0042] The channel material 14 can be formed on the lower channel material 13A. The thickness of the channel material 14 can be greater than the thickness of the lower channel material 13A.

[0043] The channel material 14 may include the same material as the lower channel material 13A. The channel material 14 may include an oxide. The channel material 14 may contain a metal component and an oxygen component. The channel material 14 may include an oxide semiconductor. For example, the channel material 14 may include at least one of indium (In), gallium (Ga), or zinc (Zn). The channel material 14 may include InSn, InGaZnO, InSnZnO, InGASnO, InSnO, InZnO, InGaO, or combinations thereof. The channel material 14 may be doped with impurities. For example, the channel layer 120 may be doped with silicon (Si) or germanium (Ge).

[0044] Channel material 14 can be deposited in an oxygen atmosphere. Channel material 14 can also be deposited in a high-concentration oxygen atmosphere (O2 environment). Therefore, oxygen vacancies are reduced, resulting in a film with a low metal composition doping concentration. Channel material 14 can include a doping distribution with a constant doping concentration. The metal composition doping concentration of channel material 14 can be lower than the doping concentration of the lower channel material 13A. At the boundary between the lower channel material 13A and channel material 14, the metal composition doping concentration changes abruptly. Therefore, an abrupt doping distribution can be formed, wherein the metal composition doping concentration changes rapidly at the boundary between the lower channel material 13A and channel material 14.

[0045] The channel material 14 can be formed using methods such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plasma-enhanced CVD (PECVD), or plasma-enhanced ALD (PEALD). The channel material 14 can be deposited at room temperature. Deposition at room temperature prevents oxygen diffusion.

[0046] The lower channel material 13A and the channel material 14 can be formed in situ in their respective devices, or they can be formed in situ in a device.

[0047] like Figure 3B As shown, the channel material 14 can be divided into an intermediate channel material 15A and an upper channel material 16A. The intermediate channel material 15A and the upper channel material 16A can be divided according to the doping distribution. The step of dividing the channel material 14 into the intermediate channel material 15A and the upper channel material 16A can be performed in situ together with the step of forming the channel material 14.

[0048] To divide the channel material 14 into an intermediate channel material 15A and an upper channel material 16A, processing can be performed. During processing, the doping distribution can be adjusted according to the height of the channel material 14. During processing, oxygen vacancies can be formed in the channel material 14. Oxygen vacancies can be formed by increasing horizontally towards the upper surface of the channel material. Therefore, the channel material 14 can be divided into an intermediate channel material 15A with a constant metal doping concentration and an upper channel material 16A with a metal doping concentration that gradually increases towards the upper surface of the channel material 14. The doping concentration of the intermediate channel material 15A can be the same as the doping concentration during the deposition of the channel material 14. The intermediate channel material 15A can include a constant doping distribution. The upper channel material 16A can include a doping distribution that increases from the doping concentration of the intermediate channel material 15A at a constant slope. In another embodiment, the doping distribution of the upper channel material 16A can include a non-constant slope. The upper channel material 16A may include a gradient doping distribution, wherein the doping concentration of the metal component gradually increases as it approaches the upper surface.

[0049] The treatment may include the use of plasma. For example, the plasma treatment energy can be adjusted to create oxygen vacancies. The plasma treatment energy can be increased from a higher level to a lower level for the upper channel material 16A.

[0050] The process may include the use of ions. For example, the ions may include inert gases that can be used to perform the process, such as He, Ne, Ar, Kr, Xe, or combinations thereof. Plasma and ions can be used to form oxygen vacancies. The process utilizing plasma and ions can be referred to as "multi-plasma processing". When performing "multi-plasma processing", a higher doping concentration can be formed on the upper surface of the upper channel material 16A.

[0051] Therefore, according to Figure 3B The doping distribution of highly metallic materials can be compared with... Figure 2 The doping distributions of the first doped region P1 to the fourth doped region P4 shown are the same.

[0052] like Figure 3C As shown, the upper channel material 16A, the middle channel material 15A, the lower channel material 13A, and the lower contact material 12A can be etched to form the upper channel layer 16, the middle channel layer 15, the lower channel layer 13, and the lower contact layer 12, respectively. The upper channel layer 16, the middle channel layer 15, and the lower channel layer 13 can constitute the channel layer CH.

[0053] A first mask (not shown) can be used as an etching mask to etch the upper channel material 16A, the middle channel material 15A, the lower channel material 13A, and the lower contact material 12A. Therefore, the upper channel layer 16, the middle channel layer 15, the lower channel layer 13, and the lower contact 12 can have the same width. The channel layer CH and the lower contact 12 can be rectangular columnar. In another embodiment, the channel layer CH and the lower contact 12 can have different shapes (e.g., cylindrical).

[0054] like Figure 3D As shown, an upper contact material 17A can be formed to cover the channel layer CH and the lower contact portion 12. The upper contact material 17A can also cover the surface of the substrate 11.

[0055] The upper contact material 17A may include the same material as the lower contact material 12. The upper contact material 17A may include a metallic material. The upper contact material 17A may include a metal or a metal compound. The upper contact material 17A may include a tungsten-containing material. The upper contact material 17A may be doped with impurities. In another embodiment, the upper contact material 17A may include a silicon-containing material. The upper contact material 17A may include polycrystalline silicon. The upper contact material 17A may include polycrystalline silicon doped with impurities.

[0056] like Figure 3E As shown, an upper contact portion 17 can be formed on the channel layer CH.

[0057] A second mask (not shown) can be used as an etching mask to etch the upper contact material 17A to form the upper contact 17. The upper contact 17 can be cylindrical. The diameter (or width) of the upper contact 17 can be smaller than the diameter (or width) of the channel layer CH. The height of the upper contact 17 can be the same as or different from the height of the lower contact 12.

[0058] In another embodiment, when forming the upper contact portion 17, the channel layer CH and the lower contact portion 12 can be formed together. In this case, the upper contact portion 17, the channel layer CH, and the lower contact portion 12 can have the same width. The upper contact portion 17, the channel layer CH, and the lower contact portion 12 can be cylindrical. In another embodiment, the upper contact portion 17, the channel layer CH, and the lower contact portion 12 can all be rectangular columnar.

[0059] like Figure 3F As shown, an insulating layer 18 can be formed to cover the sidewall of the lower contact portion 12.

[0060] To form the insulating layer 18, after forming an insulating material 18A covering all surfaces of the upper contacts 17, the channel layer CH, the lower contacts 12, and the substrate 11, the insulating material 18A can be removed to have the same height as the lower contacts 12. To remove the insulating material 18A, a process such as etch-back can be performed. Therefore, the height of the insulating layer 18 can be the same as the height of the lower contacts 12. The insulating layer 12 may include oxides, nitrides, or combinations thereof.

[0061] like Figure 3G As shown, a dielectric material 19A can be formed to cover the exposed surfaces of the insulating layer 18, the channel layer CH, and the upper contact 17. The dielectric material 19A can be conformally formed along the exposed surfaces of the insulating layer 18, the channel layer CH, and the upper contact 17. The dielectric material 19A can be any dielectric material known in the art. According to one embodiment, the dielectric material 19A may include a high-k material, such as HfO2, ZrO2, or other metal oxides.

[0062] like Figure 3H As shown, the dielectric material 19A can be partially removed so that it remains only on the sidewalls of the channel layer CH. Therefore, the dielectric layer 19 can be formed.

[0063] The dielectric layer 19 may cover all exposed sidewalls of the channel layer CH, i.e., the sidewalls of the channel layer CH not covered by the insulating layer 18. The height of the dielectric layer 19 may be the same as the height of the channel layer CH. The dielectric layer 19 may be conformally formed on the channel layer CH. In another embodiment, the dielectric layer 19 may cover only a portion of the exposed sidewalls of the channel layer CH; for example, a pair of parallel dielectric layers 19 may be formed on two opposite exposed sidewalls of the channel layer CH.

[0064] like Figure 3I As shown, a gate 20 covering the exposed surface of the dielectric layer 19 can be formed on the insulating layer 18. To form the gate 20, a gate material 20A can be formed first, and then the gate material 20A can be partially removed to form a gate 20 having the same height as the dielectric layer 19. Therefore, the height of the gate 20 can be the same as the height of the channel layer CH. The dielectric layer 19 can be located between the gate 20 and the channel layer CH. The gate 20 can cover the upper surface of the insulating layer 18. The gate 20 can include a metal or a metal compound.

[0065] The vertical transistor formed according to this manufacturing method can reduce leakage current by having different metal component doping concentrations depending on the height position in the channel layer CH.

[0066] In the vertical transistor formed according to this manufacturing method, the doping concentration on the upper surface of the channel layer CH is close to the doping concentration of the upper contact portion 17, and the doping concentration on the lower surface of the channel layer CH is close to the doping concentration of the lower contact portion 12, thereby improving the contact resistance.

[0067] Figures 4A to 4D This is a 3D diagram showing an example of a vertical transistor. Figures 4A to 4D It was omitted. Figure 1 The dielectric layer 140 and gate 150 are shown in the schematic diagram illustrating the lower contact 110, channel layer 120, and upper contact 130 according to various embodiments. Therefore, Figures 4A to 4D The vertical transistors 101, 102, 103 and 104 can be similar to each other. Figures 4A to 4D The vertical transistors 101, 102, 103, and 104 can be similar to Figure 2 The vertical transistor 100. Therefore, Figures 4A to 4D The attached figure labels are related to Figure 2 The same reference numerals in the figures may refer to the same components. Descriptions or brief descriptions of repeated components may be omitted.

[0068] First, such as Figure 4A As shown, a vertical transistor 101 can be formed. The vertical transistor 101 may include an upper insertion layer 124 on the upper channel layer 123.

[0069] The upper insertion layer 124 may be cylindrical. The upper insertion layer 124 may have the same diameter (or width) as the upper contact portion 130. The upper insertion layer 124 may overlap with the bottom surface of the upper contact portion 130. The upper insertion layer 124 may partially cover the upper surface of the upper channel layer 123.

[0070] The upper insertion layer 124 can be formed of an indium (In) or indium tin (InSn) compound. The upper insertion layer 124 can be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD). The upper insertion layer 124 can prevent oxidation of the upper layer by trapping the external diffusion of oxygen within the channel layer 120 during subsequent heat treatment processes, thereby preventing electrical resistance degradation due to metal oxidation. The upper insertion layer 124 can be formed after the formation of the channel layer 120.

[0071] An upper barrier layer 125 may be formed on the upper insertion layer 124. The upper barrier layer 125 may be located between the upper contact portion 130 and the upper insertion layer 124. The upper barrier layer 125 may have a cylindrical shape. The diameter (or width) of the upper barrier layer 125 may be the same as the diameter (or width) of the upper contact portion 130. The thickness of the upper barrier layer 125 may be the same as or different from the thickness of the upper insertion layer 124.

[0072] The upper barrier layer 125 may include a material capable of scavenging oxygen. The upper barrier layer 125 may include a metal or a metal compound. The upper barrier layer 125 may include titanium (Ti), titanium nitride (TiN), or a combination thereof. The upper barrier layer 125 may be formed by methods such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plasma-enhanced CVD (PECVD), and plasma-enhanced ALD (PEALD).

[0073] In one embodiment, an oxygen-removing upper barrier layer 125 is formed between the channel layer 120 and the upper contact portion 130, thereby reducing the contact resistance with the upper and lower metal materials. Furthermore, an oxygen-capturing upper insertion layer 124 is formed beneath the upper barrier layer 125, thereby accumulating oxygen ions absorbed through the removal by the upper barrier layer 125, and thus preventing oxidation of the upper barrier layer 125 and an increase in interface resistance, while simultaneously reducing contact resistance.

[0074] Figure 4A The schematic diagram illustrates the doping concentration of the metal composition according to the height position. As the doping concentration increases, the metallicity can increase. As the metallicity of the upper surface of the channel layer 120 increases, the contact resistance with the upper contact portion 130 can decrease. As the metallicity of the lower surface of the channel layer 120 increases, the contact resistance with the lower contact portion 110 can decrease. Figure 4A The diagram can be compared with Figure 2 Similar to the schematic diagram. Therefore, with Figure 2 In the accompanying drawings, the same reference numerals can refer to the same components.

[0075] The doping concentration can be divided into: a first doped region P1 corresponding to the height LB of the lower contact layer, a second doped region P2 corresponding to the height LBO of the lower channel layer, a third doped region P3 corresponding to the height LG of the middle channel layer, a fourth doped region P4 corresponding to the height LTO of the upper channel layer, and a fifth doped region P5 corresponding to the height LT of the upper contact layer. Figure 2 The schematic diagram may differ, and may also include a region corresponding to the height LM1 of the insertion layer 124. The doping concentration can be continuous depending on the height.

[0076] The doping distribution between the third doped region P3 and the second doped region P2 can include abrupt changes, such as a step change. As the doping concentration difference between the third doped region P3 and the second doped region P2 increases, the doping concentration difference between the second doped region P2 and the first doped region P1 can decrease. As the doping concentration difference between the second doped region P2 and the first doped region P1 decreases, the contact resistance with the lower contact portion 110 can decrease.

[0077] The doping concentration of the fourth doped region P4 can increase at a constant slope. For example, the doping concentration of the fourth doped region P4 can increase from a doping concentration equal to that of the third doped region P3 to a doping concentration equal to that of the second doped region P2. The fourth doped region P4 can include a gradient doping distribution. Because the fourth doped region P4 has a gradient doping distribution, leakage current can be reduced.

[0078] The region corresponding to the height LM1 of the upper insertion layer 124 may include a portion with varying doping concentration. That is, the region corresponding to the height LM1 of the upper insertion layer 124 may include both the highest doping concentration of the fourth doping region P4 and the doping concentration of the fifth doping region P5. The region corresponding to the height LM1 of the upper insertion layer 124 may include both a gradually varying doping distribution and a constant doping distribution. As the doping concentration variation in the region corresponding to the height LM1 of the upper insertion layer 124 decreases, the contact resistance with the upper contact portion 130 can decrease.

[0079] The fifth doped region P5 may be a region including the upper barrier layer 125 and the upper contact portion 130. The doping concentration of the fifth doped region P5 may have a constant value. The doping concentration of the fifth doped region P5 may be lower than or equal to the doping concentration of the first doped region P1. The doping concentration of the fifth doped region P5 may be continuous with the doping concentration of the fourth doped region P4.

[0080] According to this embodiment, the contact resistance with the upper contact portion 130 can be reduced by forming a high doping concentration on the upper and lower surfaces of the channel layer 120. According to this embodiment, the leakage current of the vertical transistor 101 can be reduced by forming a doping distribution of the metal composition that varies with height.

[0081] like Figure 4B As shown, a vertical transistor 102 can be formed. The vertical transistor 102 may include an upper insertion layer 126 formed on the upper channel layer 123. The vertical transistor 102 may include an upper barrier layer 125 formed on the upper insertion layer 126. The upper insertion layer 126 may have a rectangular column shape. The upper insertion layer 126 may have the same width as the upper channel layer 123. The upper barrier layer 125 may cover the bottom surface of the upper contact portion 130. The upper insertion layer 126 may cover the upper surface of the upper channel layer 123.

[0082] Figure 4B The diagram can be compared with Figure 4A Similar to the schematic diagram. Therefore, with Figure 4A In the accompanying drawings, the same reference numerals can refer to the same components.

[0083] like Figure 4C As shown, a vertical transistor 103 can be formed. The vertical transistor 103 may include an upper insertion layer 124 and an upper barrier layer 125, and... Figure 4A Similar to the vertical transistor 101. Unlike... Figure 4A The vertical transistor 103 may further include a lower barrier layer 127 formed between the lower contact 110 and the lower channel layer 121 and a lower insertion layer 128 formed on the lower barrier layer 127.

[0084] The lower barrier layer 127 may have a rectangular columnar shape. The width of the lower barrier layer 127 may be the same as the width of the lower contact portion 110. The lower barrier layer 127 may include the same material as the upper barrier layer 125. Therefore, the lower barrier layer 127 may include a material capable of scavenging oxygen. The lower barrier layer 127 may include a metal or a metal compound. The lower barrier layer 127 may include titanium (Ti), titanium nitride (TiN), or a combination thereof. The lower barrier layer 127 may be formed by methods such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plasma-enhanced CVD (PECVD), and plasma-enhanced ALD (PEALD).

[0085] The lower insertion layer 128 can be formed on the lower barrier layer 127. The lower insertion layer 128 can be rectangular columnar. The lower insertion layer 128 can have the same width as the lower contact portion 110. The lower insertion layer 128 can overlap the upper surface of the lower contact portion 110. The lower insertion layer 128 can cover the lower surface of the lower channel layer 121. The thickness of the lower insertion layer 128 can be the same as or different from the thickness of the lower barrier layer 127.

[0086] The lower insertion layer 128 may comprise the same material as the upper insertion layer 124. The lower insertion layer 128 may be formed from an indium (In) or indium tin (InSn) compound. The lower insertion layer 128 may be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD). The lower insertion layer 128 can prevent oxidation of the underlying layer by trapping external diffusion of oxygen within the channel layer 120 during subsequent heat treatment processes, thus preventing resistivity degradation due to metal oxidation.

[0087] In one embodiment, an upper barrier layer 125 and a lower barrier layer 127 capable of removing oxygen are formed between the channel layer 120 and the upper contact portion 130, and between the channel layer 120 and the lower contact portion 110, respectively, thereby reducing the contact resistance with the upper and lower metal materials. Furthermore, an upper insertion layer 124 and a lower insertion layer 128 capable of capturing oxygen are formed below the upper barrier layer 125 and on the lower barrier layer 127, respectively, thereby accumulating oxygen ions absorbed through the removal by the upper barrier layer 125 and the lower barrier layer 127. This prevents oxidation of the upper barrier layer 125 and the lower barrier layer 127 and an increase in interface resistance, while simultaneously reducing contact resistance.

[0088] Figure 4C The schematic diagram illustrates the doping concentration of the metal composition based on the height. As the doping concentration increases, the metallicity increases. As the metallicity of the upper surface of the channel layer 120 increases, the contact resistance with the upper contact portion 130 can decrease. As the metallicity of the lower surface of the channel layer 120 increases, the contact resistance with the lower contact portion 110 can decrease. Figure 4C The diagram can be compared with Figure 4A Similar to the schematic diagram. Therefore, with Figure 4A In the accompanying drawings, the same reference numerals can refer to the same components.

[0089] The doping concentration can be divided into: a first doped region P1 corresponding to the height LB of the lower contact layer; a second doped region P2 corresponding to the height LBO of the lower channel layer; a third doped region P3 corresponding to the height LG of the middle channel layer; a fourth doped region P4 corresponding to the height LTO of the upper channel layer; and a fifth doped region P5 corresponding to the height LT of the upper contact layer. This is different from... Figure 4A The schematic diagram shows that the doping concentration may also include the region corresponding to the height LM2 of the lower insertion layer 128. The doping concentration can be continuous depending on the height.

[0090] The first doped region P1 may be a region including the lower contact portion 110 and the lower barrier layer 127. The doping concentration of the first doped region P1 may have a constant value.

[0091] The region corresponding to the height LM2 of the lower insertion layer 128 can be located between the first doped region P1 and the second doped region P2. The region corresponding to the height LM2 of the lower insertion layer 128 can include both the doping concentration of the first doped region P1 and the doping concentration of the second doped region P2. The region corresponding to the height LM2 of the lower insertion layer 128 can include a portion where the doping concentration changes from the doping concentration of the first doped region P1 to the doping concentration of the second doped region P2. As the doping concentration change in the region corresponding to the height LM2 of the lower insertion layer 128 decreases, the contact resistance with the lower contact portion 110 can decrease.

[0092] The doping distribution between the third doped region P3 and the second doped region P2 can include abrupt changes, such as a step change. As the doping concentration difference between the third doped region P3 and the second doped region P2 increases, the doping concentration variation in the region corresponding to the height LM2 of the lower insertion layer 128 can decrease.

[0093] The fourth doped region P4 can include a gradient doping distribution. Because the fourth doped region P4 has a gradient doping distribution, leakage current can be reduced.

[0094] The region corresponding to the height LM1 of the upper insertion layer 124 may include a portion with varying doping concentration. That is, the region corresponding to the height LM1 of the upper insertion layer 124 may connect the highest doping concentration in the fourth doping region P4 and the doping concentration in the fifth doping region P5. The region corresponding to the height LM1 of the upper insertion layer 124 may include both a gradually varying doping distribution and a constant doping distribution. As the doping concentration variation in the region corresponding to the height LM1 of the upper insertion layer 124 decreases, the contact resistance with the upper contact portion 130 can decrease.

[0095] The fifth doped region P5 can be a region including the upper barrier layer 125 and the upper contact portion 130. The doping concentration of the fifth doped region P5 can have a constant value.

[0096] According to this embodiment, the contact resistance with the lower contact portion 110 and the upper contact portion 130 can be reduced by forming a higher doping concentration on the upper and lower surfaces of the channel layer 120. According to this embodiment, the leakage current of the vertical transistor 103 can be reduced by changing the doping distribution of impurities according to the height.

[0097] like Figure 4D As shown, a vertical transistor 104 can be formed. Similar to... Figure 4B The vertical transistor 102, vertical transistor 104 may include an upper insertion layer 126 and an upper blocking layer 125. Unlike... Figure 4B The vertical transistor 102 and the vertical transistor 104 have a lower barrier layer 127 between the lower contact 110 and the lower channel layer 121 and a lower insertion layer 128 on the lower barrier layer 127. The lower barrier layer 127 and the lower insertion layer 128 of the vertical transistor 104 can be coupled to... Figure 4C The vertical transistor 103 is the same.

[0098] Figure 4D The diagram can be compared with Figure 4C Similar to the schematic diagram. Therefore, with Figure 4C In the accompanying drawings, the same reference numerals can refer to the same components.

[0099] Figure 5 This is a schematic diagram illustrating a vertical transistor 200 according to another embodiment. The vertical transistor 200 can be coupled with... Figure 1 The vertical transistor 200 is similar to the vertical transistor 100. Except for the shape of the component, the vertical transistor 200 can be similar to... Figure 1 The vertical transistor 100 is similar to that of the vertical transistor 200. Therefore, the materials included in the components of the vertical transistor 200 can be similar to those included in the vertical transistor 200. Figure 1 The materials in the components of the vertical transistor 100 are the same or similar.

[0100] The vertical transistor 200 may include: a cylindrical lower contact 210, a channel layer 220 formed on the lower contact 210, and an upper contact 230 formed on the channel layer 220. The lower contact 210, channel layer 220, and upper contact 230 may all be cylindrical. The lower contact 210, channel layer 220, and upper contact 230 may have the same diameter (also referred to as width). A dielectric layer 240 may be formed on the channel layer 220. The dielectric layer 240 may cover the channel layer 220. A gate 250 may be formed surrounding the dielectric layer 240. The thickness of the gate 250 may be greater than the thickness of the dielectric layer 240. The gate 250 may cover the channel layer 220. Therefore, the dielectric layer 240 may be located between the gate 250 and the channel layer 220.

[0101] Figure 6 It was omitted. Figure 5 The dielectric layer 240 and gate 250 are described Figure 5 A schematic diagram of the channel layer 220.

[0102] like Figure 6 As shown, the channel layer 220 may include: a lower channel layer 221 on the lower contact portion 120, an intermediate channel layer 222 on the lower channel layer 221, and an upper channel layer 223 on the intermediate channel layer 222. That is, the channel layer 220 may include a stack of the lower channel layer 221, the intermediate channel layer 222, and the upper channel layer 223. The height LBO of the lower channel layer 221, the height LG of the intermediate channel layer 222, and the height LTO of the upper channel layer 223 may be the same or different.

[0103] Channel layer 220 may include an oxide. Channel layer 220 may include a metallic material and an oxygen material. Channel layer 220 may be doped with impurities. Channel layer 220 may include an oxide semiconductor. Channel layer 220 may have a non-uniform doping distribution according to its height. The impurity doping distribution may be different in the lower channel layer 221, the middle channel layer 222, and the upper channel layer 223.

[0104] Figure 6 The schematic diagram illustrates the doping concentration of the metal composition based on the height. As the doping concentration increases, the metallicity increases. As the metallicity of the upper surface of the channel layer 220 increases, the contact resistance with the upper contact portion 230 can decrease. As the metallicity of the lower surface of the channel layer 220 increases, the contact resistance with the lower contact portion 210 can decrease.

[0105] The doping concentration can be divided into: a first doped region P1 corresponding to the height LB of the lower contact layer, a second doped region P2 corresponding to the height LBO of the lower channel layer, a third doped region P3 corresponding to the height LG of the middle channel layer, a fourth doped region P4 corresponding to the height LTO of the upper channel layer, and a fifth doped region P5 corresponding to the height LT of the upper contact layer. The doping concentration of the first doped region P1 to the fifth doped region P5 can be continuous.

[0106] First, the doping concentrations of the first doped region P1, the second doped region P2, and the third doped region P3 can each include constant values. The doping distribution of the first doped region P1, the second doped region P2, and the third doped region P3 can include a step distribution. The doping concentration of the first doped region P1 can be greater than the doping concentrations of the second doped region P2 and the third doped region P3. The doping concentration of the second doped region P2 can be greater than the doping concentration of the third doped region P3. The third doped region P3 can include the lowest doping concentration among the first doped region P1 to the fifth doped region P5. The doping concentration difference between the second doped region P2 and the third doped region P3 can be greater than the doping concentration difference between the first doped region P1 and the second doped region P2. The doping concentration difference between the second doped region P2 and the third doped region P3 can be at least twice the doping concentration difference between the first doped region P1 and the second doped region P2. That is, the doping distribution between the third doped region P3 and the second doped region P2 can include an abrupt distribution, such as a step change. As the doping concentration difference between the third doped region P3 and the second doped region P2 increases, the doping concentration difference between the second doped region P2 and the first doped region P1 can decrease. As the doping concentration difference between the second doped region P2 and the first doped region P1 decreases, the contact resistance of the lower contact portion 210 can decrease.

[0107] The doping concentration of the fourth doped region P4 can increase at a constant slope. The doping concentration of the fourth doped region P4 can increase from a doping concentration equal to that of the third doped region P3 to a doping concentration equal to that of the fifth doped region P5. The doping concentration of the fourth doped region P4 can increase from a doping concentration equal to that of the third doped region P3 to a doping concentration equal to that of the second doped region P2. That is, the fourth doped region P4 can include a gradually changing doping distribution. In another embodiment, the doping distribution of the fourth doped region P4 can increase with a slope that increases according to the height of the doping concentration. In another embodiment, the doping distribution of the fourth doped region P4 can increase with a decreasing slope. Because the fourth doped region P4 has a gradually changing doping distribution, leakage current can be reduced. As the doping concentration difference between the fourth doped region P4 and the fifth doped region P5 decreases, the contact resistance with the upper contact portion 230 can be reduced.

[0108] The doping concentration of the fifth doped region P5 can be constant. The doping concentration of the fifth doped region P5 can be lower than or equal to the doping concentration of the first doped region P1. The doping concentration of the fifth doped region P5 can be continuous with the doping concentration of the fourth doped region P4.

[0109] According to this embodiment, the leakage current of the vertical transistor 200 can be reduced by changing the doping distribution of impurities according to height.

[0110] According to this embodiment, by forming a higher doping concentration on the upper and lower surfaces of the channel layer 220, the contact resistance with the lower contact portion 210 and the upper contact portion 230 can be reduced.

[0111] Figures 7A to 7B This is a three-dimensional view showing an exemplary vertical transistor. Figures 7A to 7B It was omitted. Figure 5 The dielectric layer 240 and gate 250 are shown in the schematic diagram illustrating the lower contact 210, channel layer 220, and upper contact 230 according to various embodiments. Therefore, Figures 7A to 7B The vertical transistors 201 and 202 can be similar to each other. Figures 7A to 7B The vertical transistors 201 and 202 can be with Figure 6 Similar to the vertical transistor 200. Therefore, Figures 7A to 7B The attached figure labels are related to Figure 6 In the accompanying drawings, the same reference numerals can refer to the same components.

[0112] First, such as Figure 7A As shown, a vertical transistor 201 can be formed. The vertical transistor 201 may include an upper insertion layer 224 formed on the upper channel layer 223.

[0113] The upper insertion layer 224 may be cylindrical. The upper insertion layer 224 may have the same diameter (or width) as the upper contact portion 230. The upper insertion layer 224 may overlap with the lower surface of the upper contact portion 230. The upper insertion layer 224 may partially cover the upper surface of the upper channel layer 223.

[0114] The upper insertion layer 224 can be formed of indium (In) or indium tin (InSn) compounds. The upper insertion layer 224 can be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD). The upper insertion layer 224 can prevent oxidation of the upper layer by trapping the external diffusion of oxygen within the channel layer 220 during subsequent heat treatment processes, thus preventing electrical resistance degradation due to metal oxidation. The upper insertion layer 224 can be formed after the channel layer 220 is formed.

[0115] An upper barrier layer 225 may be formed on the upper insertion layer 224. The upper barrier layer 225 may be located between the upper contact portion 230 and the upper insertion layer 224. The upper barrier layer 225 may be cylindrical. The width of the upper barrier layer 225 may be the same as the width of the upper contact portion 230. The thickness of the upper barrier layer 225 may be the same as or different from the thickness of the upper insertion layer 224.

[0116] The upper barrier layer 225 may include a material capable of scavenging oxygen. The upper barrier layer 225 may include a metal or a metal compound. The upper barrier layer 225 may include titanium (Ti), titanium nitride (TiN), or a combination thereof. The upper barrier layer 225 may be formed by methods such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plasma-enhanced CVD (PECVD), and plasma-enhanced ALD (PEALD).

[0117] In one embodiment, an oxygen-removing upper barrier layer 225 is formed between the channel layer 220 and the upper contact portion 230, thereby reducing the contact resistance with the upper and lower metal materials. Furthermore, an oxygen-capturing upper insertion layer 224 is formed beneath the upper barrier layer 225, thereby accumulating oxygen ions absorbed through the removal by the upper barrier layer 225, thus preventing oxidation of the upper barrier layer 224 and an increase in interface resistance, while simultaneously reducing contact resistance.

[0118] Figure 7A The schematic diagram illustrates the doping concentration of the metal composition based on the height. As the doping concentration increases, the metallicity can increase. As the metallicity of the upper surface of the channel layer 220 increases, the contact resistance with the upper contact portion 230 can decrease. As the metallicity of the lower surface of the channel layer 220 increases, the contact resistance with the lower contact portion 210 can decrease. Figure 7A The diagram can be compared with Figure 6 Similar to the schematic diagram. Therefore, with Figure 6 In the accompanying drawings, the same reference numerals can refer to the same components. Descriptions of duplicate components will be omitted.

[0119] The doping concentration can be divided into: a first doped region P1 corresponding to the height LB of the lower contact layer, a second doped region P2 corresponding to the height LBO of the lower channel layer, a third doped region P3 corresponding to the height LG of the middle channel layer, a fourth doped region P4 corresponding to the height LTO of the upper channel layer, and a fifth doped region P5 corresponding to the height LT of the upper contact layer. (This is not used for...) Figure 6 The schematic diagram shows that the doping concentration may also include a region corresponding to the height LM1 of the insertion layer 224. The doping concentration can be continuous depending on the height.

[0120] The doping distribution between the third doped region P3 and the second doped region P2 can include abrupt changes, such as a step change. As the doping concentration difference between the third doped region P3 and the second doped region P2 increases, the doping concentration difference between the second doped region P2 and the first doped region P1 can decrease. As the doping concentration difference between the second doped region P2 and the first doped region P1 decreases, the contact resistance of the lower contact portion 210 can decrease.

[0121] The doping concentration of the fourth doped region P4 can increase at a constant slope. For example, the doping concentration of the fourth doped region P4 can increase from a doping concentration equal to that of the third doped region P3 to a doping concentration equal to that of the second doped region P2. The fourth doped region P4 can include a gradient doping distribution. Because the fourth doped region P4 has a gradient doping distribution, leakage current can be reduced.

[0122] The region corresponding to the height LM1 of the upper insertion layer 224 can include a portion with varying doping concentration. That is, the region corresponding to the height LM1 of the upper insertion layer 224 can connect the highest doping concentration in the fourth doping region P4 and the doping concentration in the fifth doping region P5. The region corresponding to the height LM1 of the upper insertion layer 224 can include both a gradually varying doping distribution and a constant doping distribution. As the doping concentration in the region decreases with decreasing height LM1 of the upper insertion layer 224, the contact resistance of the upper contact portion 230 can decrease.

[0123] The fifth doped region P5 may be a region including the upper barrier layer 225 and the upper contact portion 230. The doping concentration of the fifth doped region P5 may have a constant value. The doping concentration of the fifth doped region P5 may be lower than or equal to the doping concentration of the first doped region P1. The doping concentration of the fifth doped region P5 may be continuous with the doping concentration of the fourth doped region P4.

[0124] According to this embodiment, the contact resistance with the upper contact portion 230 can be reduced by increasing the doping concentration on the upper surface of the channel layer 220. According to this embodiment, the leakage current of the vertical transistor 201 can be reduced by forming a doping distribution of impurities that varies with height.

[0125] like Figure 7B As shown, a vertical transistor 202 can be formed. (And...) Figure 7A Similar to the vertical transistor 201, the vertical transistor 202 may include an upper insertion layer 224 and an upper blocking layer 225. Unlike... Figure 7A The vertical transistor 201 and the vertical transistor 202 may further include a lower barrier layer 226 between the lower contact 210 and the lower channel layer 221 and a lower insertion layer 227 on the lower barrier layer 226.

[0126] The lower barrier layer 226 may be cylindrical. The diameter of the lower barrier layer 226 may be the same as the diameter of the lower contact portion 210. The lower barrier layer 226 may include the same material as the upper barrier layer 225. Therefore, the lower barrier layer 226 may include a material capable of scavenging oxygen. The lower barrier layer 226 may include a metal or a metal compound. The lower barrier layer 226 may include titanium (Ti), titanium nitride (TiN), or a combination thereof. The lower barrier layer 226 may be formed by methods such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plasma-enhanced CVD (PECVD), and plasma-enhanced ALD (PEALD).

[0127] The lower insertion layer 227 can be formed on the lower barrier layer 226. The lower insertion layer 227 can be cylindrical. The lower insertion layer 227 can have the same diameter (or width) as the lower contact portion 210. The lower barrier layer 226 can cover the upper surface of the lower contact portion 210. The lower insertion layer 227 can cover the lower surface of the lower channel layer 221. The thickness of the lower insertion layer 227 can be the same as or different from the thickness of the lower barrier layer 226.

[0128] The lower insertion layer 227 may comprise the same material as the upper insertion layer 224. The lower insertion layer 227 may be formed from an indium (In) or indium tin (InSn) compound. The lower insertion layer 227 may be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD). The lower insertion layer 227 can prevent oxidation of the underlying layer by trapping external diffusion of oxygen within the channel layer 220 during subsequent heat treatment processes, thereby preventing resistivity degradation due to metal oxidation.

[0129] In one embodiment, an upper barrier layer 225 and a lower barrier layer 226 capable of removing oxygen are formed between the channel layer 220 and the upper contact portion 230, and between the channel layer 220 and the lower contact portion 210, respectively, to reduce the contact resistance with the upper and lower metal materials. Furthermore, an upper insertion layer 224 and a lower insertion layer 227 capable of capturing oxygen are formed below the upper barrier layer 225 and above the lower barrier layer 226, respectively, thereby accumulating oxygen ions absorbed through the removal by the upper barrier layer 225 and the lower barrier layer 226, thus preventing oxidation of the upper barrier layer 225 and the lower barrier layer 226 and an increase in interface resistance, while simultaneously reducing the contact resistance.

[0130] Figure 7B The schematic diagram illustrates the doping concentration of the metal composition based on the height. As the doping concentration increases, the metallicity increases. As the metallicity of the upper surface of the channel layer 220 increases, the contact resistance with the upper contact portion 230 decreases. As the metallicity of the lower surface of the channel layer 220 increases, the contact resistance with the lower contact portion 210 decreases. Figure 7B The diagram can be compared with Figure 7A Similar to the schematic diagram. Therefore, with Figure 7A In the accompanying drawings, the same reference numerals can refer to the same components. Descriptions of duplicate components will be omitted.

[0131] The doping concentration can be divided into: a first doped region P1 corresponding to the height LB of the lower contact, a second doped region P2 corresponding to the height LBO of the lower channel layer, a third doped region P3 corresponding to the height LBO of the middle channel layer, a fourth doped region P4 corresponding to the height LTO of the upper channel layer, and a fifth doped region P5 corresponding to the height LT of the upper contact. This is different from... Figure 7A The schematic diagram shows that the doping concentration may also include the region corresponding to the height LM2 of the lower insertion layer 227. The doping concentration can be continuous depending on the height.

[0132] The first doped region P1 may be a region including the lower contact 210 and the lower barrier layer 226. The doping concentration of the first doped region P1 may have a constant value.

[0133] The region corresponding to the height LM2 of the lower insertion layer 227 can be located between the first doped region P1 and the second doped region P2. The region corresponding to the height LM2 of the lower insertion layer 227 can include both the doping concentration of the first doped region P1 and the doping concentration of the second doped region P2. The region corresponding to the height LM2 of the lower insertion layer 227 can include a portion where the doping concentration changes from the doping concentration of the first doped region P1 to the doping concentration of the second doped region P2. As the doping concentration change in the region corresponding to the height LM2 of the lower insertion layer 227 decreases, the contact resistance with the lower contact portion 210 can decrease.

[0134] The doping distribution between the third doped region P3 and the second doped region P2 can include abrupt changes, such as a step change. As the doping concentration difference between the third doped region P3 and the second doped region P2 increases, the doping concentration variation in the region corresponding to the height LM2 of the lower insertion layer 227 can decrease.

[0135] The fourth doped region P4 can include a gradient doping distribution. Because the fourth doped region P4 has a gradient doping distribution, leakage current can be reduced.

[0136] The region corresponding to the height LM1 of the upper insertion layer 224 can include a portion with varying doping concentration. That is, the region corresponding to the height LM1 of the upper insertion layer 224 can connect the highest doping concentration in the fourth doping region P4 and the doping concentration in the fifth doping region P5. The region corresponding to the height LM1 of the upper insertion layer 224 can include both a gradually varying doping distribution and a constant doping distribution. As the doping concentration variation in the region corresponding to the height LM1 of the upper insertion layer 224 decreases, the contact resistance with the upper contact portion 230 can decrease.

[0137] The fifth doped region P5 can be a region including the upper barrier layer 225 and the upper contact portion 230. The doping concentration of the fifth doped region P5 can have a constant value.

[0138] According to this embodiment, the contact resistance with the lower contact portion 210 and the upper contact portion 230 can be reduced by forming a higher doping concentration on the upper and lower surfaces of the channel layer 220. According to this embodiment, the leakage current of the vertical transistor 202 can be reduced by forming a doping distribution of impurities that varies with height.

[0139] Figure 8 This is an explanation Figure 1 A three-dimensional diagram of a variant of a vertical transistor. Figure 8 The vertical transistor 300 can be similar to Figure 1 Vertical transistor 100. Therefore, with Figure 1 The same reference numerals in the figures can refer to the same components. Except for dielectric layer 141 and gate 151. Figure 8 The vertical transistor 300 can have the same characteristics as... Figure 1 The structure is similar to that of the vertical transistor 100. Therefore, to avoid redundancy, the description of the components already described above will be omitted in this document.

[0140] like Figure 8 As shown, gate 151 may cover a pair of opposing sidewalls of channel layer 120. A pair of parallel gates 151 may be formed. Dielectric layer 141 may be formed between gate 151 and channel layer 120. Therefore, a pair of parallel dielectric layers 141 may be formed on a pair of opposing sidewalls of channel layer 120. Dielectric layer 141 and gate 151 may include [missing information - likely related to dielectric properties]. Figure 1 The dielectric layer 140 and the gate 150 are made of the same material.

[0141] Although not shown, Figure 8 The vertical transistor 300 may include, for example, Figures 4A to 4C The diagram shows the lower blocking layer, lower insert layer, upper insert layer, and upper blocking layer. Figure 8 The vertical transistor 300 may include, for example, Figure 5 The cylindrical lower electrode and channel layer shown may include, for example, Figures 7A to 7BThe diagram shows the lower blocking layer, lower insert layer, upper insert layer, and upper blocking layer.

[0142] Although this disclosure has been shown and described in conjunction with embodiments thereof, it will be readily understood by those skilled in the art that various changes or modifications may be made thereto without departing from the spirit of the disclosure.

Claims

1. A vertical transistor, comprising: The lower contact portion is located on the substrate; The channel layer includes a lower channel layer, an intermediate channel layer and an upper channel layer sequentially formed on the lower contact portion, the channel layer comprising a metal component and an oxygen component; as well as Upper contact portion, which is on the upper channel layer, wherein The doping concentration of the metal component is lowest in the intermediate channel layer and gradually increases towards the upper contact portion in the upper channel layer. The doping concentration of the metal component increases sharply at the boundary between the intermediate channel layer and the lower channel layer. The doping concentration of the metal component is kept constant in the intermediate channel layer and the lower channel layer.

2. The vertical transistor according to claim 1, wherein The trench layer includes at least: Any one of oxygen, indium, gallium, or zinc.

3. The vertical transistor according to claim 1, wherein The channel layer is doped with impurities.

4. The vertical transistor according to claim 3, wherein The impurities include silicon or germanium.

5. The vertical transistor according to claim 1, wherein The lower channel layer is formed in a low-concentration oxygen atmosphere, while the intermediate channel layer and the upper channel layer are formed in a high-concentration oxygen atmosphere.

6. The vertical transistor of claim 1, wherein... The upper channel layer has a constant doping concentration of the metal component on its surface, and wherein... The doping concentration of the metal component on the surface of the upper channel layer is the same as the doping concentration of the upper contact portion.

7. The vertical transistor of claim 1, further comprising: An upper insertion layer is placed on the upper channel layer; as well as An upper barrier layer is located between the upper insertion layer and the upper contact portion.

8. The vertical transistor of claim 7, wherein... The upper insertion layer comprises indium or an indium-tin compound, and wherein... The upper barrier layer comprises titanium or a titanium nitride compound.

9. The vertical transistor of claim 7, further comprising: A lower barrier layer is located on the lower contact portion; as well as A lower insertion layer is located between the lower barrier layer and the lower channel layer.

10. The vertical transistor of claim 9, wherein... The lower insert layer comprises the same material as the upper insert layer, and wherein... The lower barrier layer comprises the same material as the upper barrier layer.

11. A method for manufacturing a vertical transistor, the method comprising: The lower contact material is formed on the substrate; A lower channel material comprising a metal component and an oxygen component is formed on the lower contact material; A channel material comprising a metal component and an oxygen component is formed on the lower channel material; as well as The channel material is processed to divide it into intermediate channel material and upper channel material on the intermediate channel material. The boundary between the intermediate channel material and the lower channel material exhibits an abrupt doping distribution, wherein the doping concentration of the metal component increases sharply, while the upper channel material exhibits a gradual doping distribution, wherein the doping concentration of the metal component gradually increases towards the upper surface of the upper channel material. The doping concentration of the metal component is kept constant in both the intermediate channel material and the lower channel material.

12. The method of claim 11, wherein The lower channel material is formed in a low-concentration oxygen atmosphere, and the channel material is formed in a high-concentration oxygen atmosphere.

13. The method of claim 11, wherein The lower channel material and the channel material are formed in situ or ex-situ.

14. The method of claim 11, wherein The process utilizes plasma.

15. The method of claim 11, wherein The process utilizes an inert gas.

16. The method of claim 11, wherein The lower channel material and the channel material include at least one of oxygen, indium, gallium or zinc.

17. The method of claim 11, wherein The lower channel material and the channel material are mixed with impurities.

18. The method of claim 17, wherein The impurities include silicon or germanium.

19. The method of claim 11, further comprising: After performing the aforementioned process The lower contact, lower channel layer, intermediate channel layer and upper channel layer are formed by etching the lower contact material, the lower channel material, the intermediate channel material and the upper channel material; An upper insertion layer is formed on the upper channel layer; as well as An upper barrier layer is formed on the upper insertion layer, wherein The upper insertion layer comprises indium or an indium-tin compound.

20. The method of claim 11, further comprising: After performing the aforementioned process The lower contact, lower channel layer, intermediate channel layer and upper channel layer are formed by etching the lower contact material, the lower channel material, the intermediate channel material and the upper channel material; An upper barrier layer is formed on the upper channel layer; An upper contact portion is formed on the upper barrier layer; as well as An upper insertion layer is formed between the upper channel layer and the upper barrier layer, wherein The upper insertion layer comprises indium or an indium-tin compound.

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