High gain detector techniques for low bandwidth low noise phase locked loops

Abstract

This application relates to high-gain detector techniques for low-bandwidth low-noise phase-locked loops. In the described examples, a feedback loop has phase detection (PD) circuitry (2412) with a reference input for receiving a reference frequency signal, a feedback input for receiving a feedback signal, and a phase difference output. A phase-to-digital converter (P2DC) (FIG. 24) includes a first phase-to-charge converter (PCC) (2425) with a gain polarity and a first phase error output, a second PCC (2426) with an opposite gain polarity and a second phase error output. A differential loop filter (2401) has an amplifier (2420) with an inverting input (2421) coupled to the first phase error output and a non-inverting input (2422) coupled to the second phase error output. An analog-to-digital converter (ADC) (2431) has an input coupled to an output of the differential loop filter. A feedback path is coupled to an output of the P2DC, and an output of the feedback path provides the feedback signal to the PD feedback input.

Description

[0001] Cross-reference to related applications This application claims priority to U.S. Provisional Patent Application No. 63 / 136,245, filed January 12, 2021, the entirety of which is incorporated herein by reference. Technical Field

[0002] This application relates to high-gain phase detector technology for low-noise feedback loops. Background Technology

[0003] High-gain phase detector (PD) technology enables low-phase-noise operation of phase-locked loops (PLLs) or correlated feedback structures. High-gain PDs allow for low detector noise, which is often a key bottleneck in achieving low phase noise at low-frequency offsets.

[0004] Several techniques exist for achieving high-gain PD functionality. An example is the slope-based sampling PD structure, for instance, see: “A 28-nm 75-fsrms Analog Fractional-N Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock DutyCycle Correction,” Wanghua Wu et al, 2019. Another example is an up / down resistor-capacitor (RC) charging circuit utilizing a finite-time range of the up / dn timing window, for instance, see: “A Low Area, Switched-Resistor Based Fractional-N Synthesizer Applied to a MEMS-Based Programmable Oscillator Phase detector,” Michael H. Perrott, et al, 2010. Slope-based sampling PD structures offer high gain, but suffer from process and temperature (PT) sensitivity to this gain because the slope will typically be affected by PT variations. Up / Dn RC charging circuits offer gain that is generally robust to PT variations, but are typically more limited by the supply voltage than slope-based structures. Both methods are sensitive to power supply noise. Summary of the Invention

[0005] In the described example, the feedback loop includes a fully differential loop filter structure whose gain is fed by a high-gain phase detector with opposite gain polarity for power supply suppression. In some examples, the differential output is fed into a differential or pseudo-differential ADC. In some examples, the feedback loop is reinforced with a bang-bang detector with a dead time to extend the phase error range for faster phase locking.

[0006] In the example described for low-bandwidth applications, an enhanced delta-sigma modulator is used to reduce quantization noise at low frequencies without significantly affecting shaping noise at high frequencies. Attached Figure Description

[0007] Figure 1 This is a block diagram of an example phase-locked loop (PLL).

[0008] Figure 2 yes Figure 1 Example noise model of PLL.

[0009] Figures 3-5 yes Figure 2 The graph shows the phase noise level (dBc / Hz) of the noise model relative to the offset frequency (f).

[0010] Figure 6A is a schematic diagram of a phase detector and loop filter in the prior art. Figure 6B This is its timing diagram.

[0011] Figure 7A is a schematic diagram of another prior art phase detector and Figure 7B This is its timing diagram.

[0012] Figure 8A is a schematic diagram of another prior art phase detector and Figure 8B This is its timing diagram.

[0013] Figure 9A This is a schematic diagram of an example high-gain phase detector and Figure 9B This is its timing diagram.

[0014] Figure 10 yes Figure 9A A schematic diagram of the equivalent circuit of the phase detector.

[0015] Figure 11A This is a schematic diagram of an example phase-to-charge converter without a charge pump boost. Figure 11B This is its timing diagram.

[0016] Figure 12 It is shown in Figure 9A Timing diagram of the effect of the charge pump structure provided in the phase detector.

[0017] Figure 13AThis is a schematic diagram of another example of a high-gain phase detector and Figure 13B This is its timing diagram.

[0018] Figure 14 This is a schematic diagram of an example differential high-gain phase detector and a loop filter.

[0019] Figure 15 This is a schematic diagram of a simple XOR phase detector.

[0020] Figure 16 This is a schematic diagram of an example XOR differential high-gain phase detector and a loop filter.

[0021] Figure 17 This is a schematic diagram of an example phase detector and frequency detector circuit.

[0022] Figure 18 It is shown Figure 17 The timing diagram for the operation of the example circuit.

[0023] Figure 19 This is a graph showing the phase noise in an example PLL.

[0024] Figure 20 This is a block diagram of an example voltage source for a PLL.

[0025] Figure 21 yes Figure 20 The power supply noise versus frequency curve.

[0026] Figure 22 This is a block diagram of an example feedback loop with a high-gain phase detector.

[0027] Figure 23 It is shown Figure 22 Timing diagram of the operation of the high-gain phase detector within the feedback loop.

[0028] Figure 24 This is a schematic diagram of an example phase-to-digital converter with a low BW feedback loop.

[0029] Figure 25 yes Figure 24 Simulation model of the resistor switching section.

[0030] Figure 26 This is a schematic diagram of an example fully differential phase-to-digital converter with a low BW feedback loop.

[0031] Figure 27 This is another example of a low-BW feedback loop, a schematic diagram of a fully differential phase-to-digital converter.

[0032] Figure 28 This is a schematic diagram illustrating an example of an alternative switch-resistor phase-to-charge converter.

[0033] Figure 29 This is a schematic diagram of an example alternative switch scheme.

[0034] Figure 30 This is a schematic diagram illustrating example configurability options for an example phase-to-digital converter.

[0035] Figure 31 This is a block diagram of an example circuit for generating early / late pulses. Figure 32 This is its timing diagram.

[0036] Figures 33-36 This is a schematic diagram and timing diagram of an example linear phase detector.

[0037] Figures 37A-37E This is a timing diagram showing an example bang-bang timing with linear phase detector timing.

[0038] Figure 38 This is a schematic diagram of an example circuit used to generate bang-bang signals.

[0039] Figure 39 This is a block diagram of an example second-order MASH delta-sigma modulator.

[0040] Figure 40 This is a block diagram of an example enhanced second-order MASH delta-sigma modulator.

[0041] Figure 41 yes Figure 40 Example noise model of the enhanced delta-sigma.

[0042] Figure 42 It is shown Figure 40 The graph shows the simulation results of the enhanced delta-sigma.

[0043] Figure 43 It is by Figure 22 A block diagram of an example simulated phase-locked loop for feedback loop control.

[0044] Figure 44 It is enhanced by a digital PLL. Figure 43 Here is a block diagram simulating a phase-locked loop.

[0045] Figure 45 It is shown Figure 2 The example noise model is shown as a graph of the phase noise level (dBc / Hz) versus the offset frequency during simulation.

[0046] Figure 46 It is shown Figure 43The example frequency generation system 4300 is shown in the simulation operation of the phase noise level (dBc / Hz) versus the offset frequency.

[0047] Figure 47A , Figure 47B This is a graph illustrating the operation of the example bang-bang circuit. Detailed Implementation

[0048] In the accompanying drawings, for consistency, similar elements are indicated by similar reference numerals.

[0049] In the example described in this paper, high-gain phase detector (PD) technology enables low phase noise at low offset frequencies for phase-locked loops or correlated feedback structures. Specifically, high-gain PD allows for reduction of detector noise, which is often a key bottleneck in achieving low phase noise at low frequency offsets.

[0050] In other examples described herein, achieving a wide bandwidth (BW) of the PLL to suppress voltage-controlled oscillator (VCO) noise greatly contributes to low-noise PLLs or associated feedback structures. However, wide-BW PLLs are significantly affected by phase detector noise, and therefore low phase detector noise must be achieved to achieve low jitter. High-gain phase detector techniques allow for achieving low detector noise impact.

[0051] While high-gain PD techniques exist, they are typically sensitive to process and temperature (PT) variations, voltage source noise, and / or limited supply voltage (typically <1.2V for core devices in advanced CMOS). PD gain variations can degrade PLL jitter performance across PT variations due to corresponding changes in PLL bandwidth.

[0052] Voltage source noise can degrade low-frequency phase noise performance. While this power supply noise can be reduced with passive low-pass filtering, such filters require a large area and may even need to include undesirable off-chip components such as discrete capacitors. Lower supply voltages are desirable to reduce power consumption and allow the use of core devices in advanced CMOS, but this can degrade PLL performance due to reduced PD gain.

[0053] Several techniques exist for achieving high-gain power PD functionality. One example is a slope-based sampling PD structure. Another example is an up / down resistor-capacitor (RC) charging circuit utilizing a finite-time range of an up / down timing window. Slope-based sampling PD structures offer high gain, but suffer from PT sensitivity to this gain because the slope will typically be affected by PT variations. Up / Dn RC charging circuits offer gain that is generally robust to PT variations, but are typically more limited by the supply voltage than slope-based structures. Both approaches are sensitive to supply noise.

[0054] In the examples described herein, high-gain PD techniques reduce sensitivity to power supply noise by utilizing a differential structure. In another example, a technique for enhancing a delta-sigma modulator to reduce its low-frequency quantization noise without significantly increasing high-frequency quantization noise is described. This helps improve low-frequency phase noise performance without additional noise folding due to the nonlinearity of the phase detector. In yet another example, a digital-to-time converter is used as an alternative for reducing quantization noise, offering the benefit of wider bandwidth, but at the cost of higher complexity, power consumption, and area.

[0055] The example described in this paper is based on an improvement to the Up / Dn RC charging circuit method to achieve higher PD gain and reduced sensitivity to power supply noise. Higher PD gain is achieved by utilizing charge pump technology to increase the effective power supply voltage witnessed by the PD during the Up / Dn charging / discharging time.

[0056] Lower sensitivity to power supply noise is achieved through loop filter topologies that can be combined with various phase detector techniques. This paper describes single-ended and differential versions of example loop filter topologies. Some examples described utilize differential structures to reduce sensitivity to power supply noise while maintaining high gain of the PD. In some described examples, an ADC is included to digitize the differential signal.

[0057] Achieving low noise through brute-force methods, such as increased power / area, typically encounters practical limitations due to product power / area constraints. In the examples described herein, techniques for increasing PD gain utilize circuit topologies that can be implemented with modest power / area requirements and enable compliance with current jitter levels. Insensitivity to low-frequency power supply noise can typically be achieved using external capacitors, but this is undesirable due to increased cost of the final system and the difficulty in avoiding noise injection into the routing traces and pins associated with external capacitors during board design. The examples described herein employ techniques for reducing power supply sensitivity that avoid the need for such external capacitors.

[0058] Figure 1 This is a block diagram of an example phase-locked loop (PLL) 100. A voltage-controlled oscillator (VCO) 108 outputs a variable-frequency signal tuned according to a control voltage 107 at oscillator output 122. Feedback is used to lock the VCO output frequency to a multiple of the reference frequency input signal 120 using a multi-modulus frequency divider (MMD) 110, a phase detector (PD) 102, and a loop filter 106. In this example, the phase detector 102 also includes frequency detection (FD) logic 104. The phase detector 102 includes pulse generation (PG) logic 103 that generates up pulses and down pulses (Dn) whose pulse widths vary with the phase difference between the reference frequency input signal 120 (Ref) and the frequency-divided feedback signal 121 output by the divider (Div). A phase-to-charge converter (PCC) 105 converts the uplink PD signal and the downlink PD signal into pulses, which are then filtered by a loop filter 106 to form a control voltage 107. The PCC 105 is configured to provide high gain for the PD 102.

[0059] A digital-to-time converter (DTC) 112 is used to reduce the quantization error (dithering of divider 110) from the delta-sigma modulator 114 in order to avoid noise folding due to the nonlinearity of the high-gain PD 102. In some examples, the DTC 112 allows phase adjustment. The DTC 112 produces a variable delay determined by the digital input values ​​provided by the delta-sigma modulator 114 and the MMD 110. The division value of the MMD 112 is controlled by the delta-sigma modulator 114. The output of the MMD 110 is used as the clock input of the delta-sigma modulator 114 and the input of the DTC 112.

[0060] In some examples, the divisor value of the multimodal divider 110 can be dynamically changed.

[0061] Figure 2 yes Figure 1 Example noise model 200 for PLL. Figure 3 yes Figure 2 The graph shows the original phase noise level (dBc / Hz) of the noise model relative to the offset frequency (f). Figure 3 It is in PLL 100 ( Figure 1 The graph shows the phase noise level before filtering within the filter. Figure 4 It is in PLL 100 ( Figure 1The graph shows the phase noise level after filtering within the circuit. This example model includes a phase detector 202, a loop filter 206, a VCO 208, and a divider 210. D 202 is the gain of phase detector 102. H(s) 206 is the transfer function of loop filter 106. (2πKv) / s 208 is the transfer function of VCO 108. N is the divider value of divider 110.

[0062] Various noise sources degrade loop performance, such as: phase detector (DET) noise 221, quantization noise from the divider, DTC thermal noise and delta-sigma jitter noise 223, some residual noise that is not eliminated, power supply noise, etc. Power supply noise affects all blocks, but is particularly problematic for the phase detector and loop filter. The delta-sigma modulator 114 causes noise 223 to rise to a higher frequency that can be filtered by the loop filter 206. VCO noise 222 is high-pass filtered through the loop, but some low-frequency noise passes through. The phase detector 202 is low-pass filtered by the loop filter 206, but some high-frequency noise passes through.

[0063] like Figure 4 As shown, after filtering by PLL 100, detector noise 421 is mainly characterized by a low-frequency shift relative to the PLL bandwidth shown in 301. VCO noise 422 is mainly characterized by a high-frequency shift. DTC and DS noise 422 are reduced due to filtering by the PLL.

[0064] Reference Figure 2 Expression (1) quantifies the transfer function relationship from detector noise to the output signal on output 122. For cases where s is much smaller than the PLL bandwidth (BW), expression (1) can be simplified to expression (2). Therefore, the detector noise 421 is approximately equal to N / K. D Therefore, maximizing the detector gain K D This minimizes the impact of detector noise on output 122.

[0065] Figure 5 This shows what happens if DTC 112 is not included in PLL 100 (see...). Figure 1 Noise folding may occur. Without DTC 112, nonlinearity in phase detector 102 causes noise folding in delta-sigma noise 423, as indicated at 523. This noise folding is avoided by using DTC 112, which reduces the noise of delta-sigma modulator 114 (see...). Figure 1 The effect of jitter on phase error.

[0066] Figure 6A is a schematic diagram of a prior art phase detector 601 and loop filter 602 used in a feedback structure such as a phase-locked loop. The phase detector 601 generates an uplink pulse signal 624 and a downlink pulse signal 625, the width of which is a function of the phase difference between a reference frequency signal 620 and a feedback frequency divider signal 621, such as... Figure 6B As shown.

[0067] Charge pump 626 turns on in response to uplink pulse signal 624, and charge pump 627 turns on in response to downlink pulse signal 625. Charge pumps 626 and 627 are added to allow uplink or downlink control of the VCO tuning voltage formed on node 628. Expression (3) represents the loop filter transfer function H(s) from the output of the charge pump to the VCO tuning voltage on node 628. Typically, a larger charge pump current (which is beneficial for improved detector noise) must be accompanied by an increase in the loop filter capacitor to obtain a given PLL bandwidth. This typically leads to the requirement for large physical capacitors, which must usually be located off-chip, which is undesirable for integrated single-chip solutions. Figure 7A is a schematic diagram of a prior art phase detector 701 and loop filter for a feedback structure such as a phase-locked loop, which does not use a current source to increase the phase detector gain. Instead, the ratio of the reference signal period (Tref) to the frequency-divided feedback signal period (Tdiv) is increased. In this example, the divisor is chosen such that the frequency of the feedback frequency-divided signal 721 is four times the frequency of the reference frequency signal 720. The phase detector 701 sees a phase error range over a smaller phase window, and the corresponding phase detector gain increases due to the smaller phase error range. In this example, there is a 4-fold improvement due to the 4-fold frequency ratio. This provides a relatively stable phase detector gain because the Tref / Tdiv ratio is PVT insensitive. However, this phase detector and loop filter method is very sensitive to supply voltage (Vdd) noise, and there are some effects of noise folding for fractional N implementations due to the nonlinearity of the RC charging behavior within the loop filter.

[0068] Phase detector 701 generates an uplink pulse signal 724 and a downlink pulse signal 725, the width of which is a function of the phase difference between the reference frequency signal 720 and the feedback frequency divider signal 721, such as... Figure 7B As shown.

[0069] Phase detector 701 is based on an RC charging mechanism with resistor R1 and capacitor C1. When the uplink pulse signal 724 is active, capacitor C1 is charged via resistor R1. When the downlink pulse signal 725 is active, C1 is discharged. When neither uplink nor downlink is active, capacitor C1 maintains its voltage.

[0070] Figure 8A is a schematic diagram of another prior art switch-type phase detector 801 and loop filter 802. Figure 8B This is its timing diagram. In this example, for simplicity, only the phase-to-charge converter 805 of the phase detector is shown in detail. The pulse generation module 803 generates... Figure 8B The pulse signal is shown in the figure. In this example, separate uplink charge resistor Rup and downlink charge resistor Rdn are connected to charging node 828 and charging capacitor Cdet. In this example, the phase detector includes pulse generation module 803 to generate uplink pulse signal 824, downlink pulse signal 825, and gate signal 826.

[0071] In this example, the divider is configured to provide a frequency-divided feedback signal 821 with a frequency lower than that of the reference signal 820. As in the example of Figure 7A, the gain of the phase detector increases due to the ratio of Fref / Fdiv.

[0072] Switch 830 is controlled by gate signal 826 to transfer charge from RC node 828 to loop filter 802 only for a limited time period. The resulting increase in phase detector gain reduces the impact of noise transferred from phase-to-charge converter 805 to loop filter 802.

[0073] Phase detectors 701 (Figure 7A) and 802 are described in more detail in “A Low Area, Switched-Resistor Based Fractional-N Synthesizer Applied to a MEMS-Based Programmable Oscillator Phase detector,” Michael H. Perrott, et al, 2010.

[0074] Example of a high-bandwidth, high-gain phase detector Figure 9AThis is a schematic diagram of a switched resistor phase detector 901 and a loop filter 902. In this example, the gain of the phase detector 901 is improved by changing the structure of the RC charging circuit. The phase detector gain is limited by the supply voltage. The gain can be increased by using a larger supply voltage. However, due to overvoltage issues, the process limits the magnitude of the supply voltage in the absence of equipment problems. In this example, the "effective" supply voltage on the RC charging circuit is increased by using a voltage boost structure (also known as a "charge pump") to enhance the phase detector. For this purpose, capacitors Cup2 and Cdn2 are added along with inverters 927 and 929 to inject additional charge into capacitors Cup1 and Cdn1, respectively, during the assertions of the Up and Dn signals. This injection of additional charge has a similar effect on the RC charging as it would be with a higher supply voltage. An additional switch 932 allows the sharing of the Up and Dn network charge states after the Up and Dn charging events occur. Switches 933 and 934 pass the combined Up and Dn charge states to capacitor C1, enabling the realization of a phase error voltage signal (Vfilt), which can be further filtered before affecting the VCO control voltage Vctrl.

[0075] In the described example, inverters 927 and 929 boost the charging voltages on boost capacitors Cup2 and Cdn2, respectively, to increase the gain of the phase detector. In another example, a charge pump structure that pushes current into suitable components, such as inductors, can be used to increase the effective supply voltage to increase the gain of the phase detector.

[0076] Figure 9B This is a timing diagram showing the uplink pulse signal 924, downlink pulse signal 925, and gate signal 926 generated by the pulse generator module 903 in response to the reference signal 920 (Ref_xN) and the frequency division feedback signal 921 (Div). The duration of the uplink pulse signal 924 is proportional to the time between the edges of the reference signal 920 and the frequency division feedback signal 921. The duration of the downlink pulse signal 925 is also proportional to the time between the edges of the reference signal 920 and the frequency division feedback signal 921. The total length of the uplink pulse signal 924 and the downlink pulse signal 925 is constrained to the period Tspan of the reference signal.

[0077] For example, when the downlink pulse signal 925 is asserted and switch 931 is closed, the output of inverter 927 will switch to a high voltage state, thereby charging capacitor Cdn2 through resistor Rdn to ground via Vdn RC node 937, and also sharing charge with capacitor Cdn1. Then, when the uplink pulse signal 924 is asserted and switch 930 is closed, the output of inverter 929 will go low, thereby charging capacitor Cup2 through resistor Rup via Vup RC node 936 from Vreg, and also sharing charge with capacitor Cup1. Then, when the uplink pulse signal 924 and the downlink pulse signal 925 are de-asserted and switches 930 and 931 are open, gate signal 926 is activated to close switches 932, 933 and 934, thereby coupling RC nodes 936 and 937 to filter capacitor C1 at phase error output node 928.

[0078] In this example, for simplicity, only the phase-to-charge converter 905 of the phase detector 901 is shown in detail. The pulse generation module 903 generates... Figure 9B The pulse signals are shown in the diagram. The pulse generation module 903 generates an uplink pulse signal 924, a downlink pulse signal 925, and a gate signal 926. In this example, the downlink pulse signal 925 is enabled only from the rising edge of the reference signal 920 to the rising edge of the frequency divider feedback signal 921, and the uplink pulse signal 924 is enabled only from the rising edge of the frequency divider feedback signal 921 to the rising edge of the reference signal 920. In this way, the uplink pulse signal 924 and the downlink pulse signal 925 do not overlap and have a total effective time equivalent to the period (Tspan) of the reference signal 920.

[0079] In this example, the divider is configured to provide a frequency-divided feedback signal 921 with a frequency lower than that of the reference signal 920. The gain of the phase detector increases due to the ratio of Fref / Fdiv.

[0080] Switches 933 and 934 are controlled by gate signal 926 to transfer charge from RC nodes 936 and 937 to output node 928 for a limited period of time when gate signal 926 is active. This prevents the phase error voltage Vfilt and the VCO control voltage Vctrl from being disturbed by RC charging activity during the activation of uplink and downlink pulses.

[0081] When switches 932, 933, and 934 are open, uplink pulse signal 924 and downlink pulse signal 925 are enabled. The phase detector gain is improved by an alpha factor, which is the ratio of the capacitors given by equation (4). Equation (5) represents the total gain factor of phase detector 901 assuming that the values ​​of capacitors Cup1 and Cdn1 are equal and the values ​​of capacitors Cup2 and Cdn2 are also equal. In some examples, multiple capacitors can be provided, which can be selectively turned off using switches, multiplexers, or other known or later-developed techniques to dynamically change the system gain by varying the capacitor ratio alpha in order to optimize the gain. If only minimizing the effect of detector noise is considered, the alpha should be chosen to be as high as possible. However, other considerations such as the implementation region, the achievable switching speed of the inverters 927 and 929 with capacitive loads, and the impact on the power supply can influence the optimal setting of the alpha.

[0082] Figure 10 yes Figure 9A A schematic diagram of the equivalent circuit 1005 of the phase detector 901 and the phase-to-charge converter 905. (See diagram below.) Figure 9A The charge pump structure and Cup2, Cdn2 produce an effect equivalent to increasing the power supply voltage. In this example, the result is the same as the following: the power supply voltage increase is equal to α. det Multiply by half the supply voltage and the ground voltage drop equal to α det This is the amount multiplied by half the supply voltage. In this example, the supply voltage for phase detector 901 is the regulated voltage Vreg. In other examples, the supply voltage for the phase detector can be the chip-width supply voltage Vdd or another different voltage source. In this example, the use of the charge pump structure and Cup2, Cdn2 allows for an effective increase in the phase detector gain, as determined by the capacitor ratio α. det It's confirmed.

[0083] Figure 11A This is a schematic diagram of an example phase-to-charge converter (PCC) 1105 and Figure 11B This is its timing diagram, showing the phase-to-charge converter compared to the PCC 905 without a charge pump structure. Figure 9A Similarly, in this example without a gain-boosting charge pump, for both the uplink and downlink paths, the discharge at node 1136 during the uplink pulse signal 924 and at node 1137 during the downlink pulse signal 925 begins at approximately Vreg / 2. The resulting Vfilt signal is formed at output node 1128.

[0084] Figure 12 This is a timing diagram for the example PCC 905, illustrating the effect of the charge pump structure and Cup2, Cdn2. In this example, the gain boost is achieved by increasing the initial voltages across resistors Rup and Rdn during the enable times of the uplink pulse signal 924 and the downlink pulse signal 925, as indicated by Vup 936 and Vdn 937 at 1242 and 1243, respectively. For a given change in phase error, this results in a significant change in the amplitude of Vfilt 928. Therefore, the PCC 905 with the charge pump structure and Cup2, Cdn2 has a higher gain than the PCC 1105 without the charge pump structure.

[0085] Figure 13A It is similar to PCC 905 ( Figure 9A Another example is a schematic diagram of a high-gain phase-to-charge converter (PCC) 1305. In this example, switch 932 is controlled by gate0 signal 13260, while switches 933 and 934 are controlled by offset gate1 signal 13261.

[0086] Figure 13B This illustrates a module similar to pulse generation module 903 ( Figure 9A The timing diagram shows the uplink pulse signal 924, downlink pulse signal 925, gate0 signal 13260, and gate1 signal 13261 generated by the pulse generator module in response to the reference signal 920 (Ref_xN) and the frequency division feedback signal 921 (Div). The gate0 signal 13260 is offset slightly from the gate1 signal 13261, causing switch 932 to close slightly before switches 933 and 934. This allows the ripple on nodes 1336 and 1337 to stabilize before switches 933 and 934 are closed, thereby reducing the ripple sent to filter 1302 and the output. In this example, the offset time is approximately 5%–10% of Tspan, but the optimal offset time will vary depending on the stable behavior when the switches are on and other constraints. It should be noted that the gate0 signal is shown as being deasserted before the gate1 signal, but other implementations may deasserte the gate0 signal simultaneously with or after the gate1 signal.

[0087] Figure 14 It can be used Figure 1A schematic diagram of an example differential high-gain phase detector and loop filter 1400 in example PLL 100. In this example, the wideband feedforward (FF) path 1401 includes a high-gain PCC unit 1410 coupled to the FF filter 1412. The lossy integration path 1402 includes an operational amplifier 1420 having an inverting input 1421 coupled to receive the filtered output from PCC unit 1425 and a non-inverting input 1422 coupled to receive the filtered output from PCC unit 1426.

[0088] The lossy integration path 1402 also includes a frequency detection path 1424, wherein a switch 1411 is configured to detect the output signal (such as the output signal at output 122) at the output signal ( Figure 1 When the frequency of the output signal is too low, the inverting input 1421 is coupled to ground via resistor Rfd_lo when the signal FDlo asserts, and the switch 1411 is configured to couple the inverting input 1421 to Vreg via resistor Rfd_hi when the frequency of the output signal is too high.

[0089] FF filter 1412 combines the output 1407 of PCC unit 1410 with integration path 1402 to generate control voltage Vctrl at output node 1414. Control voltage Vctrl is used to control the generation of an output signal at output 122. Figure 1 A variable frequency oscillator. In another example, additional filtering can be provided to the control voltage Vctrl before it is output at node 1414.

[0090] PCC units 1410, 1425, and 1426 are compatible with PCC 905 ( Figure 9A ), PCC 1005 ( Figure 10 ), PCC 1105 ( Figure 11B ), PCC 1305 ( Figure 13A This is the same as other known or later developed PCC units. However, it should be noted that the uplink pulse signal 924 and the downlink pulse signal 925 are reversed between PCC units 1425 and 1426. This allows for the elimination of low-frequency power supply noise by utilizing both the inverting input 1421 and the non-inverting input 1422 of operational amplifier 1420. In this way, by utilizing both the inverting and non-inverting gain paths, the noise effect of operational amplifier 1420 is reduced to approximately half of its original value.

[0091] The DC gain of the operational amplifier's inverting path corresponds to the ratio of the resistance across the feedback to the input resistor - (r13 / (r10+r11)), while the DC gain of the non-inverting path is (1+r13 / (r10+r11)). When the magnitude of the DC gain of the inverting path is significantly greater than 1, the magnitude of the DC gain of the non-inverting path will have a similar magnitude. Therefore, any common-mode signals (such as power supply noise in the high-gain PCC units 1425 and 1426) will be largely eliminated. For example, if the magnitude of the DC gain of the inverting path is 10, then the magnitude of the DC gain of the non-inverting path is 1+10=11. In this case, assuming the power supply noise has the same effect on both high-gain PCC units 1425 and 1426, the power supply noise will be attenuated by approximately 90%. Therefore, good power supply noise cancellation is provided in a single-ended system (as opposed to a differential dual-output system), which facilitates analog control of the VCO, as the VCO typically has a single-ended control input.

[0092] This example demonstrates the benefits of low-frequency power supply noise cancellation and effectively gains more from the operational amplifier. If only the inverting terminal is used, the gain is 10 (in this example); however, in this case, the gain of the inverting input is -10 and the gain of the non-inverting input is 11, effectively doubling the total gain of the lossy integration path compared to a value of 21. Therefore, the operational amplifier output provides twice the phase error signal compared to using only the inverting or non-inverting path. This is significant because the noise from the operational amplifier is amplified by the gain of the non-inverting path, so doubling the gain of the phase error signal relative to the non-inverting path results in approximately a 2x improvement in the signal-to-noise ratio at the operational amplifier output. In effect, the operational amplifier noise effect is reduced to approximately half of its original value. Therefore, this example demonstrates the benefits of eliminating low-frequency power supply noise through the integration path, as well as the benefit of reducing the impact of operational amplifier noise in the system.

[0093] In this example, each PCC unit 1410, 1425, 1426 operates on a regulated voltage Vreg of 1.1V. In another example, a different supply voltage can be used. Each PCC unit 1410, 1425, 1426 and its associated filter network can be optimized individually.

[0094] In this example, integration path 1402 is described as a "lossy" integrator. To avoid saturation issues, feedback capacitor C13 is shunt by feedback resistor R13. The parallel combination of C13 and R13 operates like a real capacitor dissipating power, rather than an ideal capacitor. For this reason, the actual integrator is called a lossy integrator. In another example, the amount of loss contributed by R13 can be selected based on other parameters to control saturation.

[0095] Figure 15 This is a schematic diagram of a simple XOR phase detector unit 1500. In this example, a reference signal 1520 and a frequency-divided feedback signal 1521 are connected to the input of the XOR gate 1501. The feedback signal 1521 is similar to that of a PLL 100 (…). Figure 1 The frequency division feedback signal 121 () Figure 1 Inverting buffer 1504 provides a buffered phase detection signal Vpdb 1507. Inverting buffer 1505 provides an inverse phase detection signal Vpd 1506.

[0096] Figure 16 Is using Figure 15 A schematic diagram of an example XOR differential high-gain phase detector 1600, where a simple XOR PD unit replaces a PCC unit. This configuration is useful when a high-frequency reference signal (such as Ref 1520) is available. One way to increase PD gain is to reduce the time range required to obtain a given voltage error signal from the PD after filtering, which is the case when the PD's operating frequency increases. Typical reference frequencies are less than a few hundred MHz; however, in this example, the reference oscillator operates at 2.5 GHz, while the VCO operates at several GHz. Because the reference frequency is very high, a PCC configuration where the reference frequency and the feedback divider signal are multiples of each other is not required, and a simple XOR type PD (such as PD 1500) can be used instead. Figure 15 In this example, there is no need to increase the PD gain; instead, a simple implementation is desired to allow robust operation at very high frequencies. Because narrow output pulses are avoided during steady-state operation, the XOR PD provides very linear behavior in systems incorporating delta-sigma modulation in the feedback loop, provided the instantaneous phase error deviation is not large enough to create a very small pulse at the PD output.

[0097] In this example, the wideband feedforward (FF) path 1601 includes a PD unit 1610 coupled to the FF filter 1412. The lossy integration path 1602 includes an operational amplifier 1420 having an inverting input 1421 coupled to receive the filtered output from the PD unit 1625 and a non-inverting input 1422 coupled to receive the filtered output from the PD unit 1626.

[0098] The lossy integration path 1602 also includes a frequency detection path 1424, wherein a switch 1411 is configured to detect the output signal (such as the output signal at output 122) at the output signal ( Figure 1When the frequency of the output signal is too low, the inverting input 1421 is coupled to ground via resistor Rfd_lo when the signal FDlo asserts, and the switch 1411 is configured to couple the inverting input 1421 to Vreg via resistor Rfd_hi when the frequency of the output signal is too high.

[0099] FF filter 1412 combines the output 1507 of PD unit 1610 with integration path 1602 to generate a control voltage Vctrl at output node 1614. The control voltage Vctrl is used to control the variable-frequency oscillator that generates the output signal at output 122. In another example, additional filtering may be applied to the control voltage Vctrl before it is output at node 1414.

[0100] In this example, PD units 1610, 1625, and 1626 are related to PD unit 1500 ( Figure 15 This is the same as another known or later-developed PD unit. However, it should be noted that the output signal Vpd 1506 is coupled to the inverting input 1421 of the operational amplifier 1420, while the opposite polarity output signal Vpdb 1507 is coupled to the non-inverting input 1422. This allows for the elimination of low-frequency power supply noise by utilizing both the inverting input 1421 and the non-inverting input 1422 of the operational amplifier 1420. In this way, by utilizing both the inverting and non-inverting gain paths, the noise effect of the operational amplifier 1420 is reduced to approximately half of its original value.

[0101] The DC gain of the operational amplifier's inverting path corresponds to the ratio of the resistance across the feedback to the input resistor - (r13 / (r10+r11)), while the DC gain of the non-inverting path is (1+r13 / (r10+r11)). When the magnitude of the DC gain of the inverting path is significantly greater than 1, the magnitude of the DC gain of the non-inverting path will have a similar magnitude. Therefore, any common-mode signals (such as power supply noise in the high-gain PD units 1625 and 1626) will be largely eliminated. For example, if the magnitude of the DC gain of the inverting path is 10, then the magnitude of the DC gain of the non-inverting path is 1+10=11. In this case, assuming the power supply noise has the same effect on both the high-gain PD units 1625 and 1626, the power supply noise will be attenuated by approximately 90%. Therefore, good power supply noise cancellation is provided in a single-ended system (as opposed to a differential dual-output system), which facilitates analog control of the VCO, as the VCO typically has a single-ended control input.

[0102] This example demonstrates the benefits of low-frequency power supply noise cancellation and effectively gains more from the operational amplifier. If only the inverting terminal is used, the gain is 10 (in this example); however, in this case, the gain of the inverting input is -10 and the gain of the non-inverting input is 11, effectively doubling the total gain of the lossy integration path compared to a value of 21. Therefore, the operational amplifier output provides twice the phase error signal compared to using only the inverting or non-inverting path. This is significant because the noise from the operational amplifier is amplified by the gain of the non-inverting path, so doubling the gain of the phase error signal relative to the non-inverting path results in approximately a 2x improvement in the signal-to-noise ratio at the operational amplifier output. In effect, the operational amplifier noise effect is reduced to approximately half of its original value. Therefore, this example demonstrates the benefits of eliminating low-frequency power supply noise through the integration path, as well as the benefit of reducing the impact of operational amplifier noise in the system.

[0103] In this example, each PD unit 1610, 1625, 1626 operates on a regulated voltage Vreg of 1.1V. In another example, a different supply voltage can be used. Each PD unit 1610, 1625, 1626 and its associated filter network can be optimized individually.

[0104] Figure 17 This is a schematic diagram of an example phase detector pulse generation (PG) circuit 1701, a frequency detector circuit 1702, and a bang-bang phase detector circuit 1703. A reference frequency input signal 120 and a frequency division feedback signal 121 are provided as inputs to these circuits. The PG circuit 1701 generates an uplink pulse signal 924, a downlink pulse signal 925, and a gate signal 926, which are used in the PCC unit described in more detail above. When the frequency of the oscillator output is outside the selected range, the frequency detector circuit 1702 generates the FDhi and FDlo signals, described in more detail above, to achieve initial locking of the PLL. The bang-bang PD circuit 1703 is used for DTC calibration and will be described in more detail below.

[0105] Figure 18 It is shown Figure 17The following is a timing diagram of the operation of the PG circuit 1701 in the example circuit. In this example, the frequency of the reference frequency input signal 120 is 1.25 GHz. The frequency of the frequency-divided feedback signal 121 is 625 MHz, such that the reference frequency input signal 120 has twice the frequency of the frequency-divided feedback signal 121. In another example, a larger multiple and a higher reference frequency can be used. The double frequency difference between the reference frequency input signal 120 and the frequency-divided feedback signal 121 provides an equivalent of double the gain in the PD / PCC unit. Alternatively, in another example, the frequency of the frequency-divided feedback signal 121 can be configured as a multiple of the frequency of the reference frequency input signal 120.

[0106] As a function of phase error, the uplink pulse signal 924 and the downlink pulse signal 925 change their widths in opposite ways. This relationship provides high linearity even in the event of a mismatch between the Up / Dn loop filter paths. This contrasts with existing techniques where the width of the uplink or downlink pulses changes independently.

[0107] Figure 19 The graph, expressed in dBc / Hz, is a curve showing the noise relative to the offset frequency (Hz) in an example PLL. In this example, PLL 100 ( Figure 1 It is equipped with a PG circuit 1701 and a frequency detector circuit 1702. Figure 17 ) PCC block and loop filter circuit 1400 ( Figure 14 In this example, the reference frequency is 1.25 GHz and the feedback frequency is 625 MHz. As indicated by graph 1902, low-frequency noise from the regulated supply voltage (Vreg) is well suppressed. The overall noise is indicated by graph 1901. The overall jitter integrating from 12 kHz to 20 MHz is 46.0 fs (rms).

[0108] The described example illustrates a method for operating a phase-locked loop (PLL). This is achieved using a first PCC unit 1425 with gain polarity. Figure 14 A first phase error signal is generated based on the phase difference between the reference signal and the feedback signal. A second phase error signal is generated using a second PCC unit 1426 with opposite gain polarity based on the phase difference between the reference signal and the feedback signal. The first and second phase error signals are generated by operational amplifier 1420 (…). Figure 14 The results are amplified and combined to form an integral phase error signal. This is achieved using a third phase detector unit 1410. Figure 14A third phase error signal is generated based on the phase difference between the reference signal and the feedback signal to form the feedforward phase error signal. The feedforward phase error signal is combined with the integral phase error signal to form the control voltage Vctrl 1414. Figure 14 ).

[0109] In the described example, the voltage-controlled oscillator (VCO) 108 operates in response to the control voltage Vctrl. Figure 1 To generate the output signal Out at output 122. Figure 1 The frequency of the output signal is continuously monitored to determine if it is outside the target frequency range. When the frequency of the output signal is outside the target frequency range, the magnitude (value and / or sign) of the integrated phase error signal is adjusted.

[0110] In the described example, the divider 110 is coupled to the VCO ( Figure 1 The output of the signal is modulated using a delta-sigma modulator. The feedback signal is transmitted through a DTC 112 ( Figure 1 The amount of change is delayed in response to the modulated output of the divider.

[0111] In the described example, a first voltage is applied to the upward charge resistor Rup and capacitor Cup1 within a time period proportional to the first phase difference. Figure 9A ) to generate a first phase error signal by forming a first RC node voltage, wherein the magnitude of the voltage is determined by a first charge pump ( Figure 9A Strengthening. A second voltage is applied to the downward charge resistor Rdn and capacitor Cdn1 within a time amount proportional to the second phase difference. Figure 9A ) to form the second RC node voltage, wherein the magnitude of the voltage is determined by the second charge pump ( Figure 9A Strengthened by closing switch 932 ( Figure 9A The first RC node voltage and the second RC node voltage are combined to form a combined RC node voltage. This is achieved through switches 933 and 934. Figure 9A The combined RC node voltages are passed to the filter. In some examples, this is done through gate signals 13260 and 13261. Figure 13B This delays the propagation of the combined RC node voltage to the filter for a certain period of time, allowing the combined RC node voltage to stabilize.

[0112] Example of a low-bandwidth, high-gain phase detector In the following example, a differential switching RC front end is used to eliminate low-frequency noise from the voltage regulator. The differential front end is combined with partially and fully differential loop filters and an ADC (analog-to-digital converter). The gain of the loop filter is set high enough that the effect of ADC noise is sufficiently reduced.

[0113] In some examples, linear PDs utilize bang-bang detectors and frequency detectors to reinforce and achieve reasonable lock-in times.

[0114] In some examples, digital delta-sigma modulators are enhanced to reduce quantization noise at low frequencies without significantly increasing noise folding by avoiding a significant increase in the quantization noise spectral magnitude at high frequencies.

[0115] Figure 20 This is a block diagram of an example voltage source for an example PLL. In a typical PLL system, the power supply voltage 2001 is provided by circuitry such as a bandgap circuit, which creates an accurate reference voltage Vref. While Vref provides a reasonably consistent and accurate voltage value across the PVT, it is often accompanied by high noise and cannot provide sufficient output current to power the various circuits within the integrated circuit, including the PLL. Therefore, a voltage source regulator Vreg 2003 is used to provide sufficient output current to the PLL and other blocks, and Vref 2001 is used as the reference voltage for Vreg to achieve an accurate voltage across the PVT. The noise present in Vref is filtered 2002 before being supplied to Vreg. Therefore, due to the effect of the low-pass filtered bandgap noise, the output noise spectral density of a typical power supply regulator used for a PLL is highest at low frequencies.

[0116] Figure 21 yes Figure 20 An example graph of the noise spectral density (V / rHz) of a voltage source regulator versus frequency (Hz) shows the effect of Vref noise at lower frequencies.

[0117] Figure 22 This is a block diagram of an example feedback loop 2200 that provides a digital frequency ratio signal “OutN” at the output node, derived from a comparison of the phase / frequency of a high-frequency bulk acoustic wave (BAW) oscillator 2201 with a reference frequency Ftcxo. Specifically, the output signal OutN at node 2215 is an estimated instantaneous ratio of the frequency of the BAW output signal 2202 to the frequency of the reference signal 2204, which in this example is provided by a temperature-controlled crystal oscillator (TCXO) 2203. BAW resonators, characterized by high operating frequencies (up to several GHz) and small size, have been used for many years in mobile applications, such as filters in the RF front end of wireless transceivers. A BAW resonator is a piezoelectric thin-film resonator (which operates similarly to a quartz crystal) used by a BAW oscillator circuit to create a periodic oscillating signal. In this example, the BAW oscillator 2201 operates at 2.5 GHz.

[0118] The multimode divider (MMD) 2206 divides the frequency of the BAW output signal 2202 by the ratio N of the feedback signal 2217 provided by the digital delta-sigma modulator 2216. For example... Figure 23 As shown, the Div_early and div_late pulses are generated by the MMD 2206. In this example, the delta-sigma modulator 2216 is clocked by the div_late output pulse signal 2219.

[0119] In response to the timing relationship between the reference signal 2204 and the div_early and div_late pulses, the phase detector 2208 uses the reference signal 2204 and the div_early and div_late pulses to generate a phase difference signal including an uplink pulse signal 2209 and a downlink pulse signal 2210.

[0120] A phase-to-digital converter (P2DC) 2212 generates a digital output value 2213 in response to an uplink pulse signal 2209 and a downlink pulse signal 2210. A digital loop filter 2214 filters the digital output value 2213 to generate an output signal OutN at node 2215.

[0121] In this example, the initial lock-in time is improved by using "bang-bang" (BB) loops 2220 and 2221, which will be described in more detail below. The BB loops enhance the system during initial stabilization using an additional phase detector. The BB loops provide an error signal to drive the system. Once the system locks in, the BB loops disengage during operation without affecting noise, etc.

[0122] In this example, the delta-sigma modulator 2216 is designed to reduce the effects of delta-sigma noise without exacerbating noise folding, as will be described in more detail below.

[0123] Figure 23 This shows the MMD 2206 ( Figure 22 ) and PD 2208 ( Figure 22 The timing diagram of the generated timing signal.

[0124] Figure 24 It is used for applications such as feedback loop 2200 ( Figure 22 A schematic diagram of an example P2DC 2412 with a low BW feedback loop.

[0125] The P2DC 2412 includes differentially configured switched-resistor phase-to-charge converters (PCCs) 2425 and 2426. Each PCC 2425 and 2426 includes two switches, such as switches 2451 and 2452, controlled by an uplink pulse signal 2209 and a downlink pulse signal 2210, respectively. In this example, switches 2451 and 2452 are each implemented as FET transistors.

[0126] The differential loop filter 2401 includes an operational amplifier 2420. The output of PCC 2425 is coupled to the inverting input 2421 of operational amplifier 2420, and the output of PCC 2426 is coupled to the non-inverting input 2422 of operational amplifier 2420. It should be noted that from PD 2208 ( Figure 22 The received uplink pulse signal 2209 and downlink pulse signal 2210 are reversed between PCC 2425 and 2426.

[0127] The anti-aliasing filter 2430 attenuates frequencies above the Nyquist sampling rate of the analog-to-digital converter (ADC) 2431 to eliminate aliasing.

[0128] The ADC 2431 converts the amplified output from the operational amplifier 2420 into a digital value output at node 2215. This digital value is useful for digital phase-locked loops (DPLLs).

[0129] In this example, the differential configuration suppresses low-frequency noise on the regulated supply voltage Vreg and reduces the impact of noise generated by operational amplifier 2420, as is the case for operational amplifier 1420. Figure 14 (A more detailed description follows.)

[0130] Figure 25 yes Figure 24 A simulation model of the resistor switching section (such as PCC 2426). The value of the equivalent resistor Rdet2501 is given by expression (6), but this expression is approximate because Rdet can be obtained through... Figure 24 The effect of parasitic capacitance in PCC 2425 and 2426 is reduced. Block 2508, corresponding to the DC gain from phase error to Verror, indicates the DC gain of phase detector 2208 to reference signal 2204 ( Figure 22 The ratio of the period of Div_early to the time span Tspan between the rising edges of Div_early and Div_late increases.

[0131] The DC gain of the loop filter circuit fed by Verror changes as a function of the reference (TCXO) frequency based on expression (7), where Rdet is given by expression (6). The lower frequency of the reference signal 2204 results in an increase in R... det And consequently, lower DC gain. The higher frequency of the reference signal 2204 results in reduced R... det And therefore, higher DC gain.

[0132] The DC gain of the loop filter = 1 + 2 R fb / (R det + R neg (7) ADC 2431 ( Figure 24 The input of the ADC and the output of the operational amplifier 2420 each have limited voltage ranges. This results in a trade-off between effective phase error resolution and effective phase error range. The effective phase error range must be wide enough to accommodate jitter (including delta-sigma jitter). The effective phase error range is affected by the voltage range of the ADC operational amplifier, the PD gain, and the loop filter gain (expression (7)).

[0133] Figure 26 It is used for applications such as feedback loop 2200 ( Figure 22 A schematic diagram of an example fully differential P2DC 2600 with a low BW feedback loop. In this example, phase-to-charge converters (PCCs) 2425, 2426 are configured differentially and coupled to two separate operational amplifiers 2420, 2620.

[0134] The differential loop filter 2601 includes operational amplifiers 2420 and 2620. The output of PCC 2425 is coupled to the inverting input 2421 of operational amplifier 2420, and the output of PCC 2426 is coupled to the non-inverting input 2422 of operational amplifier 2420. Similarly, the output of PCC 2425 is coupled to the non-inverting input 2622 of operational amplifier 2620, and the output of PCC 2426 is coupled to the inverting input 2621 of operational amplifier 2620. It should be noted that from PD 2208 ( Figure 22 The received uplink pulse signal 2209 and downlink pulse signal 2210 are reversed between PCC 2425 and 2426.

[0135] The outputs 2423 of operational amplifier 2420 and 2623 of operational amplifier 2620 are coupled to the input of differential ADC 2631. ADC 2631 quantizes the voltage difference between outputs 2423 and 2623 and converts it into a digital output. The output of ADC 2631 is then provided at output node 2215. ADC 2631 can be fully differential or pseudo-differential.

[0136] Figure 27 It is used for applications such as feedback loop 2200 ( Figure 22 This is a schematic diagram of an example fully differential P2DC 2700 with a low BW feedback loop. In this example, phase-to-charge converters (PCCs) 2425 and 2426 are configured differentially, utilizing a differential loop filter 2701 including a single differential operational amplifier 2720. The output of PCC 2425 is coupled to the inverting input 2721 of operational amplifier 2720, and the output of PCC 2426 is coupled to the non-inverting input 2722 of operational amplifier 2720. Operational amplifier 2720 provides differential outputs 2723 and 2724 coupled to a differential ADC 2631. ADC 2631 quantizes the voltage difference between differential outputs 2723 and 2724 and converts it into a digital output. The output of ADC 2631 is then provided at output node 2215. ADC 2631 can be fully differential or pseudo-differential.

[0137] Figure 28 This is a schematic diagram illustrating an example of an alternative to a switched-resistor phase-to-charge converter. In this example, a switched-resistor PCC 2825 with a single resistor Rdet1 can replace a PCC 2425 with two resistors Rup1 and Rdn1. Similarly, a switched-resistor PCC 2826 with a single resistor Rdet0 can replace a PCC2426 with two resistors Rup0 and Rdn0. This alternative configuration can be used with any of the P2DC 2412, 2600, or 2700 described earlier.

[0138] Figure 29 This is a schematic diagram of an example alternative switching scheme for the PCC 2426 (see 24). In the PCC 2425 ( Figure 24A similar configuration can be used. In this example, buffer 2902 is inserted between switching transistor 2901 (e.g., FET) and Vreg and tracks the uplink pulse signal 2209. In this configuration, the supply voltage to switching transistor 2901 is provided by the output of buffer 2902. Therefore, when the uplink pulse signal 2209 is invalid, a voltage approximately at ground potential is supplied to switching transistor 2901. Similarly, buffer 2904 is inserted between switching transistor 2903 (e.g., FET) and ground and inverts the downlink pulse signal 2210. In this configuration, the supply voltage to switching transistor 2903 is provided by the output of buffer 2904. Therefore, when the downlink pulse signal 2210 is invalid, a voltage approximately at Vreg potential is supplied to switching transistor 2903. In this way, the turn-off resistance of switching circuits 2951, 2952 is significantly increased. The on-resistance is only slightly increased due to the resistance of buffers 2902, 2904.

[0139] Figure 30 This is a schematic diagram illustrating example configurability options for example PCC 3012, which has the same features as examples PCC2425 and 2426 ( Figure 24 The same overall schematic diagram applies. It is beneficial to maintain a sufficiently high loop filter gain so that the ADC 2413 quantization noise is well scrambled (i.e., at least some ADC codes are executed through noise or other signals). Referring to expressions (6) and (7), the loop filter gain varies with the period Tref of the reference frequency. Therefore, it is beneficial to maintain sufficient loop filter gain by appropriately adjusting or trimming the values ​​of the various resistors and capacitors in the PCC 3012 as Tref changes.

[0140] In this example, Rup0, Rup1, Rdn0, Rdn1, Rop_p, Rneg, Rfb, Cdet0, Cdet1, and Cfb are individually adjusted using trimming switches and additional resistors and capacitors (such as trimming components connected in series or parallel) in an appropriate configuration. In this example, the trimming switches are controlled by a configuration register (not shown), which is set by the system's control processor (not shown). In another example, trimming can be controlled using known or later developed techniques, such as fusible links, erasable programmable read-only memory (EPROM) bits, etc.

[0141] Figure 31 It is used in Figure 22 The block diagram of the example circuit 3100 for generating Div_early output pulse signal 2218 and Div_late output pulse signal 2219 in the multimode divider 2206 shown is as follows. Figure 32This is its timing diagram. The multi-stage divider topology 3102 provides feedback signal 2217 from Div_In (see...). Figure 22 The Div_early output pulse signal 2218 is retimed. In this example, a configurable shift register 3104 is used to accurately delay the Div_late output pulse signal 2219 by a selected number of Div_in 2217 pulses. In this way, the time length Tspan between the rising edge of the Div_early output pulse signal 2218 and the rising edge of the Div_late output pulse signal 2219 is accurately set. In some examples, the configurable shift register 3104 may be configured to allow Tspan to be adjusted by half a cycle of the Div_In feedback signal 2217. Known or later developed techniques can be used with multiplexers and registers to control the configuration of the configurable shift register 3104 and thereby select the value of Tspan.

[0142] Figure 33 It is included in PD 2208 (see Figure 22 A schematic diagram of an example linear phase detector 3300 is shown in the diagram. Figure 34 This is its timing diagram. In this example, flip-flop 3302 receives the Div_early output pulse signal 2218 on the clock input and the Div_late output pulse signal 2219 on the reset input. A pure "1" logic level is applied to the D input. Flip-flop 3302 generates the pd_pulse signal 3303, which is coupled to the inputs of gates 3304 and 3306. Reference signal 2204 is coupled to the second input of gate 3304, and an inverted version of reference signal 2204 is coupled to the second input of gate 3306. AND gate 3304 generates a downlink pulse signal 2210, while AND gate 3306 generates an uplink pulse signal 2209. In this example, an optional delay module 3308 is included to delay the downlink pulse signal 2210 by a small amount, so that the uplink and downlink pulses do not overlap. In this example, Tdelay is implemented using an inverter. In another example, other types of known or later-developed techniques or circuit elements can be used to generate the delay. In some examples, delay module 3308 can be omitted if overlapping uplink / downlink pulses are acceptable.

[0143] Figure 35 It is included in PD 2208 (see Figure 22 A schematic diagram of an example linear phase detector 3500 is shown within the diagram. Figure 36This is its timing diagram. In this example, flip-flop 3502 receives reference signal 2204 on the clock input, a pure 1 logic level on the D input, and div_early on the reset input. Flip-flop 3502 generates a downlink pulse signal 2210. Flip-flop 3504 receives reference signal 2204 on the clock input, a pure 1 logic level on the D input, and div_late on the reset input. Flip-flop 3504 generates an uplink pulse signal 2209. In this example, an optional delay module 3508 is included to delay the downlink pulse signal 2210 by a small amount, so that the uplink and downlink pulses do not overlap. In this example, Tdelay is implemented using an inverter. In another example, other types of known or later-developed techniques or circuit elements can be used to generate the delay. In some examples, delay module 3308 can be omitted if overlapping uplink / downlink pulses are acceptable.

[0144] Figures 37A-37E This shows the PD 2208 ( Figure 22 The timing diagram shows an example bang-bang (BB) timing signal generated by the timing circuit system within the system, along with the timing diagrams of the linear phase detector signals Up and Dn. Figure 37B , Figure 37C and Figure 37D As shown, as long as the rising edge of the reference signal 2204 falls within the Tspan window 3701, the BB late output signal 2223 and the BB early output signal 2222 are invalid. The Tspan window 3701 is defined by the time between the rising edge of the Div_early output pulse signal 2218 and the subsequent rising edge of the Div_late output pulse signal 2219. Figure 37A An example case is shown where the rising edge of reference signal 2204 occurs before Tspan window 3701. In this case, BB early output signal 2222 is activated. Figure 37E An example is shown where the rising edge of reference signal 2204 occurs after Tspan window 3701. In this case, BB late output signal 2223 is activated. Therefore, in this example, as long as uplink pulse signal 2209 and downlink pulse signal 2210 are both valid, thus indicating feedback loop 2200 ( Figure 22 If BB_early and BB_late are locked, then BB_early and BB_late are invalid. It should be noted that there are cases, such as with a PD circuit of 35, where Up and Dn can be active outside the Tspan window without interfering with the relationship that BB_early and BB_late become invalid outside the Tspan window.

[0145] Figure 38 It is included in PD 2208 ( Figure 22 A schematic diagram of an example circuit for generating a bang-bang signal within ) . This is provided as long as the rising edge of reference signal 2204 falls within Tspan window 3701 ( Figure 37A Within this window, the BB_early output signal 2223 and the BB_early output signal 2222 are invalid. The Tspan window 3701 is defined by the time between the rising edge of the Div_early output pulse signal 2218 and the subsequent rising edge of the Div_late output pulse signal 2219.

[0146] Assuming the Sigma-Delta module is clocked by the div_late output pulse signal 2219, the timing of triggers 3801 and 3802 is re-tied to synchronize the timing of BB_early and BB_late to the div_late output pulse signal 2219. Assuming the ADC 2431 ( Figure 24 ) or ADC 2631 ( Figure 26 or Figure 27 The module is clocked by the ADC clock signal 2226, and the triggers 3803 and 3804 are re-timed to synchronize the timing of BB_early and BB_late to the ADC clock signal 2226.

[0147] Enhanced digital delta-sigma modulator As mentioned above, regarding Figures 1-5 As described, if DTC 112 (see...) Figure 1 If the noise is not included in PLL 100, noise folding may occur. Without DTC 112, the nonlinearity in phase detector 102 causes noise folding of delta-sigma noise 223, such as 523 ( Figure 5 This is indicated at the location. This noise folding is avoided by using DTC 112, which reduces the delta-sigma modulator 114 (see [reference]). Figure 1 The effect of DTC 112 on phase error by the jitter of the phase detector 102. Figure 1 The phase change of the circuit allows for wide bandwidth operation. However, DTC adds complexity, power consumption, and area to the integrated circuit.

[0148] Delta-sigma (ΔΣ; or sigma-delta, ΣΔ) modulation is a method for encoding analog signals into digital signals, as found in analog-to-digital converters (ADCs). It is also used to convert high-bit-count digital signals with relatively low-frequency content into lower-bit-count, higher-frequency digital signals in which the relatively low-frequency content is preserved. For example, the conversion of digital signals to analog signals can utilize delta-sigma modulation as part of digital-to-analog converters (DACs) and fractional-N frequency synthesizers. Delta-sigma modulation techniques are known, for example, see: "Delta-sigma modulation," Wikipedia, August 9, 2021 or later.

[0149] Figure 39 This is a block diagram of a 2nd-order MASH digital delta-sigma modulator 3901. Multistage noise-shaping (MASH) digital structures have noise-shaping properties and are commonly used in digital audio and fractional-N frequency synthesizers. It comprises two or more cascaded overflow accumulators, each of which corresponds to a first-order sigma-delta modulator. The carry outputs are combined through summation and delay to produce a binary output whose width depends on the number of stages (orders) of the MASH.

[0150] Such as PCC 2212 ( Figure 22 The RC charging of the high-gain PCC has a nonlinearity, which leads to the behavior of the delta-sigma modulator 2216 ( Figure 22 The noise folding of the generated delta-sigma noise. The second-order MASH delta-sigma modulator 3901 typically produces acceptable low noise folding, but without sufficient noise shaping. However, the third-order delta-sigma typically produces unacceptably high noise folding.

[0151] Figure 40 This is a block diagram of an example enhanced 2nd-order MASH delta-sigma modulator 4001. In this example, the 2nd-order MASH delta-sigma modulator 3901 is enhanced using a feedback loop with design parameters "K" and "a". In this example, feedback block 4009 acts as a digital low-pass filter that extracts low-frequency quantization noise so that the low-frequency quantization noise is suppressed by the feedback. The resulting feedback causes a change in the DC gain of the closed-loop system, which is compensated by cascaded gain block 4007.

[0152] Figure 41 yes Figure 40Example noise model of the example enhanced delta-sigma modulator 4001. In this example, expression (8) represents the transfer function from the delta-sigma quantization noise 4010 to the output 4005. The overall delta-sigma noise spectrum is represented by expression (9), where “n” is the MASH order of the delta-sigma. The signal transfer function from the input 4003 to the output 4005 is represented by expression (10). Figure 42 This demonstrates a comparison with conventional second-order and third-order MASH structures. Figure 40 The simulation results (in dB / Hz) of the enhanced delta-sigma modulator are plotted against frequency (MHz). Line 4201 in the graph represents the second-order MASH delta-sigma modulator 3901 ( Figure 39 The curve 4202 represents the enhanced second-order MASH delta-sigma 4001 (). Figure 40 The curve 4203 represents the 3rd order MASH delta-sigma (not shown).

[0153] In this example, K is chosen as 3 and is set in feedback loop 4009 ( Figure 40 In this example, a low-pass bandwidth of approximately 1 / 100th of the clock frequency is achieved. High-frequency noise remains roughly the same, but an improvement of approximately 9 dB is observed at lower frequencies.

[0154] Phase-locked loop example Figure 43 It includes by Figure 22 A block diagram of an example frequency generation system 4300 controlled by a low-bandwidth feedback loop 2200 and a high-bandwidth analog phase-locked loop 4301. The high-BW PLL 4301 is similar to the high-BW PLL 100 (…). Figure 1 In this example, the high BWPLL 4301 is locked to a reference frequency Fbaw provided by the BAW oscillator 2201, which offers high frequency and low jitter. In this example, for simplicity, the divider 4302 divides the reference frequency Fbaw by 4, but the high-gain PD technique discussed in the discussion can be applied, thus leading to a change in the optimal choice of this division value. In another example, the reference frequency can be provided by another known or later-developed technique, such as a crystal-based reference oscillator.

[0155] In this example, the low BW feedback loop 2200 is also locked to the reference frequency Fbaw and the Ftcxo reference frequency signal 2204 provided by a temperature-controlled crystal oscillator. In another example, the reference frequency may be provided by another known or later-developed technique, such as a crystal-based reference oscillator.

[0156] In this example, the high-gain PLL 4301 may include a high-gain phase detector 102 as described in more detail above. In this example, the low-gain feedback loop 2200 may include a high-gain PD 2208 as described in more detail above.

[0157] In this example, digital processing logic 4310 receives the OutN signal from feedback loop 2200. The OutN signal provides the value of the ratio between the frequencies of the BAW output signal 2202 and the Ftcxo reference signal 2204. Processing logic 4310 converts this ratio into a fractional value Nfrac 4311 provided to the delta-sigma modulator 114. This allows the ppm accuracy of Fvco1 to be set according to Ftcxo, and enables the suppression of low-frequency phase noise in the BAW.

[0158] In this example, APLL 4301 is described. In another example, a digital PLL can be used instead of APLL 4301.

[0159] Figure 44 It includes enhancements by the Digital PLL (DPLL) 4401. Figure 43 The example frequency generation system 4300 is shown in the block diagram. In this example, open-loop cancellation of BAW low-offset phase noise is provided by TCXO feedback loop 2200 and analog PLL 4301, as described in more detail above.

[0160] In this example, the DPLL 4401 provides closed-loop tracking to the Fref 4406 to provide PPM accuracy and very low offset phase noise suppression. The DPLL 4401 includes a time-to-digital converter (TDC) 4402, a digital loop filter 4403, a multimode divider 4404, and a delta-sigma converter 4405.

[0161] In this example, APLL 4301 is described. In another example, a digital PLL can be used instead of APLL 4301. Similarly, a digital PLL 4401 is described in this example. In another example, an analog PLL can be used instead of digital PLL 4401.

[0162] simulation Figure 45 yes Figure 2 The plot of the phase noise level (dBc / Hz) versus offset frequency for the simulation operation of the example noise model shows the noise folding effect of delta-sigma noise (see [link]). Figure 5 In this example, curve 4510 represents an output of 122. Figure 1The overall phase noise at ( ). In this example, the carrier frequency is 312.5 MHz, and the reference frequency is the input signal frequency of 120 ( ). Figure 2 The frequency is 40.0 MHz, and the divider 210 ( Figure 2 The input is 2.5 GHz and the BW is 14.7 kHz. Due to noise folding of the delta-sigma quantization noise, significant degradation occurs at low frequencies, but the total noise remains below the noise targets of the two example systems, as indicated at 4501 and 4502.

[0163] Figure 46 It is shown Figure 43 The example frequency generation system 4300 is shown as a graph of the phase noise level (dBc / Hz) versus the offset frequency during simulation operation. In this example, the carrier frequency is 312.5 MHz, and the reference frequency of the BAW output signal 2202 is ( Figure 43 The frequency is 40.0 MHz, and the divider 110 ( Figure 43 The input is 2.5 GHz, and the BW is 14.7 kHz. In this example, curve 4610 shows the output at 122 ( Figure 43 The overall phase noise on the TCXO loop 2200 is shown in graph 4611. Figure 43 The folded delta-sigma noise in the simulated parallel BAW oscillator 2201 is shown in graph 4612. Figure 43 BAW noise of TXCO loop 2200. Plot 4613 shows the BAW noise of TXCO loop 2200. Figure 43 The quantization noise of the 10-bit 4.0 MHz ADC quantizer is within the range. The total noise remains below the noise targets of the two example systems, as indicated at 4501 and 4502.

[0164] Figure 47A , Figure 47B This shows the PD 2208 ( Figure 22 The timing circuit system within the circuit generates a graph of the operation of an example bang-bang circuit. In this example, graph line 4701 shows the operation of the feed into the delta-sigma modulator 114 ( Figure 43 The fractional ratio value is 4311 ( Figure 43 The simulated step response of BB early and BBlate is shown. Before the step, the output signals BB early and BBlate are 2222 and 2223 respectively. Figure 22The BB early output signal 2222 and BB late output signal 2223 are stationary, as indicated at 4702. After a step input, the BB early output signal 2222 and BB late output signal 2223 are active for a short time (ms), as indicated at 4703, to stabilize the ratio value more quickly. After a short period of time, once the ratio value stabilizes, the BB early output signal 2222 and BB late output signal 2223 become stationary again, as indicated at 4704.

[0165] Other embodiments In the described examples, high-gain high-BW phase detectors and high-gain low-BW phase detectors are proposed. In these examples, they are combined in various ways to provide a variable-frequency system that generates a stable frequency signal with low noise. In another example, these components can be configured in various topologies to provide enhanced low-noise system performance.

[0166] In this specification, the term "phase detector" is used to refer to circuitry that detects the phase difference between a reference signal and a feedback signal. In some examples, the phase detector may include pulse generator timing circuitry, such as the PG circuit 1701 (…). Figure 17 In other examples, the phase detector can be such as... Figure 15 The simple XOR gate is shown. In some examples, the phase detector may include a phase-to-charge converter (PCC), such as the PCC 905 (Figure 9). In some examples, the phase detector may include a phase-to-digital converter, such as the phase-to-digital converter 2212 (Figure 9). Figure 22 ).

[0167] In the described example, an operational amplifier is used in the PCC. In another example, a known or later-developed amplifier configuration with inverting and non-inverting inputs may be used.

[0168] In this specification, the term "coupled" and its derivatives mean indirect, direct, optical, and / or wireless electrical connections. Therefore, if a first device is coupled to a second device, the connection can be a direct electrical connection, an indirect electrical connection via other devices and connections, an optoelectronic connection, and / or a radio connection.

[0169] Within the scope of the claims, modifications to the described embodiments are possible, and other embodiments are also possible.

Claims

1. A feedback loop, or FBL, comprising: The phase detection circuit system, also known as the PD circuit system, has a reference input for receiving a reference frequency signal, a feedback input for receiving a feedback signal, and a phase difference output. A phase-to-digital converter, or P2DC, has an input coupled to the phase difference output and an output; the P2DC includes: The first phase-to-charge converter, i.e., the first PCC, has a gain polarity and a first phase error output. The second PCC has opposite gain polarity and a second phase error output; A differential loop filter having a filter output, the loop filter having an amplifier having an inverting input coupled to a first phase error output and a non-inverting input coupled to a second phase error output, the amplifier having an output; An analog-to-digital converter, i.e., an ADC, has an input coupled to the output of the differential loop filter, and an output for providing the output of the P2DC; and A feedback path, the feedback path being coupled to the output of the P2DC, wherein the output of the feedback path is coupled to the feedback input of the PD.

2. The FBL according to claim 1, wherein the amplifier is a first operational amplifier, and further comprises a second operational amplifier having an inverting input coupled to the second phase error output and a non-inverting input coupled to the first phase error output, and the second operational amplifier having an output; and The ADC is a differential ADC, which has a first input coupled to the output of the first operational amplifier and a second input coupled to the output of the second operational amplifier.

3. The FBL of claim 1, wherein the output of the amplifier is a differential inverting and non-inverting output, and wherein the ADC has a differential input coupled to the differential output of the amplifier.

4. The FBL according to claim 1 further includes an anti-aliasing filter, the anti-aliasing filter being coupled between the input of the ADC and the output of the differential loop filter.

5. The FBL of claim 1, wherein the phase detection circuit system further comprises a bang-bang detector configured to be effective when the phase difference between the reference frequency signal and the feedback signal is outside a defined range.

6. The FBL according to claim 1, wherein the first PCC includes a resistor-capacitor node, i.e., an RC node, wherein a first resistor is coupled from the RC node to a first voltage source via a first switch, a second resistor is coupled from the RC node to a second voltage source via a second switch, and a capacitor is coupled from the RC node to the second voltage source, wherein the first switch is controlled by a first phase difference output of the PD and the second switch is controlled by a second phase difference output of the PD.

7. The FBL according to claim 1, wherein the first PCC includes a resistor-capacitor node, i.e., an RC node, wherein the RC node is coupled to a first voltage source via a first switch, the RC node is coupled to a second voltage source via a second switch, and a resistor and a capacitor are connected in series from the RC node to the second voltage source, wherein the first switch and the second switch are controlled by the corresponding phase difference output of the PD.

8. The FBL of claim 6, wherein the first switch is a field-effect transistor (FET), and further comprises a first buffer having an input coupled to the first phase difference output of the PD, wherein the output of the first buffer couples the first voltage source to the FET; and The second switch is a FET, and the device also includes a second buffer having an input coupled to a second phase difference output of the PD, wherein the output of the second buffer couples the second voltage source to the FET.

9. The FBL according to claim 6, further comprising a first trimming resistor coupled to the first resistor, a second trimming resistor coupled to the second resistor, and a trimming capacitor coupled to the capacitor.

10. The FBL of claim 1, further comprising a delta-sigma modulator having an input coupled to the output of the P2DC and an output coupled to the feedback input of the PD.

11. The FBL of claim 10, wherein the delta-sigma modulator is a second-order multi-stage noise shaping structure, i.e., a second-order MASH structure, and further comprises a feedback loop filter coupled from the output of the delta-sigma modulator to the input of the delta-sigma modulator.

12. A delta-sigma modulator, comprising a second-order multistage noise shaping structure, i.e., a second-order MASH structure, having an input and an output; and a feedback loop filter coupled from the output of the delta-sigma modulator to the input of the delta-sigma modulator.

13. The delta-sigma modulator of claim 12, further comprising a gain block coupled to the input of the delta-sigma modulator.

14. A frequency generation system, comprising: A first reference oscillator, the first reference oscillator having a first reference signal output; A second oscillator, the second oscillator having a second reference signal output; A feedback loop having a first input coupled to the first reference signal output and a second input coupled to the second reference signal output, the feedback loop having a ratio output, wherein the feedback loop is configured to provide on the ratio output a signal representing the ratio of the frequency of the first reference signal at the first reference signal output to the frequency of the second reference signal at the second reference signal output; as well as A phase-locked loop (PLL) has a first input coupled to the first reference signal output and a second input coupled to the ratio output of the feedback loop. The PLL also has an output for a variable frequency signal.

15. The frequency generation system according to claim 14, wherein the feedback loop comprises: The phase detection circuit system, also known as the PD circuit system, has a first reference input for receiving the first reference signal, a second reference input for receiving the second reference signal, a feedback input for receiving the feedback signal, and a phase difference output. A phase-to-digital converter, or P2DC, has an input coupled to the phase difference output and an output; the P2DC includes: The first phase-to-charge converter, i.e., the first PCC, has a gain polarity and a first phase error output. The second PCC has opposite gain polarity and a second phase error output; A differential loop filter having a filter output, the loop filter having an amplifier having an inverting input coupled to a first phase error output and a non-inverting input coupled to a second phase error output, the amplifier having an output; An analog-to-digital converter (ADC) having an input coupled to the output of the differential loop filter and an output coupled to the output of the P2DC; and A feedback path, the feedback path being coupled to the output of the P2DC, wherein the output of the feedback path is coupled to the feedback input of the PD.

16. The system of claim 15, wherein the amplifier is a first operational amplifier, and further comprises a second operational amplifier having an inverting input coupled to the second phase error output and a non-inverting input coupled to the first phase error output, the second operational amplifier having an output; and The ADC is a differential ADC, which has a first input coupled to the output of the first operational amplifier and a second input coupled to the output of the second operational amplifier.

17. The system of claim 15, wherein the output of the amplifier is a differential inverting and non-inverting output, and wherein the ADC has a differential input coupled to the differential output of the amplifier.

18. The system of claim 15 further includes an anti-aliasing filter coupled between the input of the ADC and the output of the differential loop filter.

19. The system of claim 15, wherein the phase detection circuitry further comprises a bang-bang detector configured to be effective when the phase difference between the reference signal and the feedback signal is outside a defined range.

20. The system of claim 14, wherein the PLL comprises: The first phase detector unit, also known as the first PD unit, has a gain polarity and includes a reference input coupled to the first reference signal output, a feedback input coupled to the ratio output, and a phase error output. The second PD unit has opposite gain polarity, and has a reference input coupled to the first reference signal output, a feedback input coupled to the ratio output, and a phase error output. as well as A loop filter has a filter output and an integration path and a feedforward path coupled to the filter output. The feedforward path has a third PD unit with a reference input coupled to the reference signal output, a feedback input coupled to the ratio output, and a phase error output AC coupled to the filter output. The integration path includes an operational amplifier with an inverting input coupled to the phase error output of the first PD unit and a non-inverting input coupled to the phase error output of the second PD unit. The operational amplifier also has an output coupled to the filter output.

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