Image sensing device

Abstract

The present disclosure provides an image sensing device, including: a pixel array, which is configured to include a first pixel belonging to the first row and the first column and a second pixel belonging to the second row and the second column, each of the first pixel and the second pixel includes one or more photoelectric conversion elements configured to generate photocharges in response to incident light; and a DCG capacitor connected between the first pixel and the second pixel. The first pixel includes: a first floating diffusion area, which is configured to store the photocharges generated by the photoelectric conversion element of the first pixel; and a first DCG transistor, which is used to selectively connect the DCG capacitor to the first floating diffusion area or disconnect it from the first floating diffusion area. The second pixel includes: a second floating diffusion area, which is configured to store the photocharges generated by the photoelectric conversion element of the second pixel; and a second DCG transistor, which is used to selectively connect the DCG capacitor to the second floating diffusion area or disconnect it from the second floating diffusion area.

Description

Technical Field

[0001] Techniques and implementations disclosed in this disclosure generally relate to image sensing devices including pixels capable of adjusting sensitivity. Background Art

[0002] Image sensing devices are devices for capturing optical images by converting light into electrical signals using photosensitive semiconductor materials that react to light. With the development of the automotive, medical, computer, and communication industries, there is an increasing demand for high-performance image sensing devices in various fields such as smartphones, digital cameras, game consoles, IoT (Internet of Things), robots, security cameras, and medical micro cameras.

[0003] Image sensing devices can be roughly divided into CCD (Charge Coupled Device) image sensing devices and CMOS (Complementary Metal Oxide Semiconductor) image sensing devices. CCD image sensing devices provide better image quality, but they tend to consume more power and are larger in size than CMOS image sensing devices. CMOS image sensing devices are smaller in size and consume less power than CCD image sensing devices. In addition, CMOS sensors are manufactured using CMOS manufacturing technology, so photosensors and other signal processing circuits can be integrated into a single chip, enabling miniaturized image sensing devices to be produced at a lower cost. For these reasons, CMOS image sensing devices are being developed for many applications, including mobile devices. Summary of the invention

[0004] Various embodiments of the disclosed technology relate to an image sensing device in which pixels capable of adjusting sensitivity are efficiently arranged.

[0005] According to an embodiment of the disclosed technology, an image sensing device may include: a pixel array, which is configured to include a first pixel belonging to a first row and a first column, and a second pixel belonging to a second row and a second column, the second row is adjacent to the first row and the second column is adjacent to the first column, each of the first pixel and the second pixel includes one or more photoelectric conversion elements configured to generate photocharges in response to incident light; and a dual conversion gain (DCG) capacitor connected between the first pixel and the second pixel. The first pixel includes: a first floating diffusion area, which is configured to store the photocharges generated by the one or more photoelectric conversion elements of the first pixel; and a first dual conversion gain (DCG) transistor, which is used to selectively connect the DCG capacitor to the first floating diffusion area of ​​the first pixel or disconnect the DCG capacitor from the first floating diffusion area of ​​the first pixel. The second pixel includes: a second floating diffusion area, which is configured to store the photocharges generated by the one or more photoelectric conversion elements of the second pixel; and a second dual conversion gain (DCG) transistor, which is used to selectively connect the DCG capacitor to the second floating diffusion area of ​​the second pixel or disconnect the DCG capacitor from the second floating diffusion area of ​​the second pixel.

[0006] According to another embodiment of the disclosed technology, an image sensing device may include: a pixel array configured to include a first pixel at a first position and a second pixel arranged at a second position diagonally to the first position, each of the first pixel and the second pixel including one or more photoelectric conversion elements configured to generate photocharges in response to incident light. The first pixel includes a first dual conversion gain (DCG) gate configured to control the capacitance of a first floating diffusion region, the first floating diffusion region configured to store the photocharges generated by the first pixel. The second pixel includes a second dual conversion gain (DCG) gate configured to control the capacitance of a second floating diffusion region, the second floating diffusion region configured to store the photocharges generated by the second pixel. The common area is disposed at a contact surface between the first pixel and the second pixel and overlaps with each of the first DCG gate and the second DCG gate.

[0007] It is to be understood that both the foregoing general description and the following detailed description of the disclosed technology are exemplary and explanatory and are intended to provide further explanation of the disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other features and advantageous aspects of the disclosed technology will become more apparent with reference to the following detailed description when considered in conjunction with the accompanying drawings.

[0009] Figure 1 is a block diagram illustrating an example of an image sensing device based on some implementations of the disclosed technology.

[0010] Figure 2 Some implementations based on the disclosed technology are illustrated. Figure 1 Schematic diagram of an example of a pixel array shown in .

[0011] Figure 3 Some implementations based on the disclosed technology are illustrated. Figure 2 A circuit diagram of an example of a first pixel and a second pixel is shown.

[0012] Figure 4 Some implementations based on the disclosed technology are illustrated. Figure 2 A plan view of an example of a first pixel to a fourth pixel is shown.

[0013] Figure 5 is an example of some implementations based on the disclosed technology. Figure 4 A cross-sectional view of the layout structure taken along line AA′ shown in FIG.

[0014] Figure 6 Some implementations based on the disclosed technology are illustrated. Figure 2 A plan view of another example of the first to fourth pixels shown.

[0015] Figure 7 is an example of some implementations based on the disclosed technology. Figure 6 A cross-sectional view of the layout structure taken along line BB′ shown in FIG. DETAILED DESCRIPTION

[0016] The present disclosure provides implementations and examples of image sensing device designs that can be used in configurations to substantially solve one or more technical or engineering problems and mitigate limitations or disadvantages encountered in some other image sensing devices. Some implementations of the disclosed technology relate to image sensing devices in which pixels capable of adjusting sensitivity are effectively arranged. The disclosed technology provides various implementations of image sensing devices that can obtain the capacitance required for a low sensitivity mode by changing the layout structure of pixels without increasing the size of each pixel or using capacitors that may cause noise to appear.

[0017] The disclosed technology will now be described in detail with reference to embodiments thereof, examples of which are shown in the accompanying drawings. Wherever possible, the same reference numerals will be used throughout the accompanying drawings to refer to the same or similar parts. Although the disclosure is susceptible to various modifications and alternative forms, specific embodiments thereof are shown by way of example in the accompanying drawings. However, the disclosure should not be construed as being limited to the embodiments set forth herein.

[0018] Figure 1 is a block diagram illustrating an image sensing device 100 according to an embodiment of the disclosed technology.

[0019] Reference Figure 1 , the image sensing device 100 may include a pixel array 110, a row driver 120, a correlated double sampler (CDS) 130, an analog-to-digital converter (ADC) 140, an output buffer 150, a column driver 160, and a timing controller 170. The discussion is by way of example only. Figure 1 The components of image sensing device 100 are shown, and the present disclosure encompasses numerous other variations, substitutions, variations, alterations, and modifications.

[0020] The pixel array 110 may include a plurality of unit imaging pixels arranged in rows and columns. In one example, the plurality of unit imaging pixels may be arranged in a two-dimensional pixel array including rows and columns. In another example, the plurality of unit imaging pixels may be arranged in a three-dimensional pixel array. The plurality of unit imaging pixels may convert optical signals into electrical signals on a unit pixel basis or on a pixel group basis, wherein the unit pixels in the pixel group share at least some internal circuits. The pixel array 110 may receive a drive signal including a row selection signal, a pixel reset signal, and a transmission signal from the row driver 120. Upon receiving the drive signal, the corresponding unit imaging pixel in the pixel array 110 may be activated to perform operations corresponding to the row selection signal, the pixel reset signal, and the transmission signal.

[0021] The row driver 120 may activate the pixel array 110 to perform certain operations on the imaging pixels in the corresponding row based on commands and control signals provided by a controller circuit such as the timing controller 170. In some implementations, the row driver 120 may select one or more imaging pixels arranged in one or more rows of the pixel array 110. The row driver 120 may generate a row selection signal to select one or more rows among the plurality of rows. The row driver 120 may sequentially enable a pixel reset signal for resetting the imaging pixels corresponding to at least one selected row and a transmission signal for the pixels corresponding to the at least one selected row. Therefore, a reference signal and an image signal, which are analog signals generated by each imaging pixel of the selected row, may be sequentially transmitted to the CDS 130. The reference signal may be an electrical signal provided to the CDS 130 when a sensing node (e.g., a floating diffusion node) of the imaging pixel is reset, and the image signal may be an electrical signal provided to the CDS 130 when a photocharge generated by the imaging pixel is accumulated in the sensing node. The reference signal indicating the unique reset noise of each pixel and the image signal indicating the intensity of the incident light may be collectively referred to as a pixel signal as needed.

[0022] CMOS image sensors can use correlated double sampling (CDS) to remove undesired pixel offset values, known as fixed pattern noise, by sampling the pixel signal twice to eliminate the difference between the two samples. In one example, correlated double sampling (CDS) can remove undesired pixel offset values ​​by comparing the pixel output voltages obtained before and after the photocharges generated by the incident light are accumulated in the sensing node, so that only the pixel output voltage based on the incident light can be measured. In some embodiments of the disclosed technology, CDS130 can sequentially sample and hold the voltage levels of the reference signal and the image signal, which are provided from the pixel array 110 to each of the plurality of column lines. That is, CDS130 can sample and hold the voltage levels of the reference signal and the image signal corresponding to each column of the pixel array 110.

[0023] In some implementations, the CDS 130 may transmit the reference signal and the image signal for each column to the ADC 140 as a correlated double sampling signal based on a control signal from the timing controller 170 .

[0024] ADC 140 is used to convert the analog CDS signal into a digital signal. In some implementations, ADC 140 can be implemented as a ramp comparison ADC. The ramp comparison ADC may include a comparator circuit for comparing the analog pixel signal with a reference signal such as a ramp signal that ramps up or down, and a timer counts until the voltage of the ramp signal matches the analog pixel signal. In some embodiments of the disclosed technology, ADC 140 may convert the correlated double sampling signal generated by CDS 130 for each column into a digital signal and output the digital signal. ADC 140 may perform counting operations and calculation operations based on the correlated double sampling signal for each column and the ramp signal provided from the timing controller 170. In this way, ADC 140 may eliminate or reduce noise such as reset noise that occurs from imaging pixels when generating digital image data.

[0025] ADC 140 may include a plurality of column counters. Each column of pixel array 110 is connected to a column counter, and image data may be generated by converting a correlated double sampling signal received from each column into a digital signal using the column counter. In another embodiment of the disclosed technology, ADC 140 may include a global counter to convert a correlated double sampling signal corresponding to the column into a digital signal using a global code provided from the global counter.

[0026] The output buffer 150 may temporarily hold the column-based image data provided from the ADC 140 to output the image data. In one example, the output buffer 150 outputs the image data provided from the ADC 140 and stored in the output buffer 150 based on a control signal of the timing controller 170. The output buffer 150 may provide an interface to compensate for a data rate difference or a transmission rate difference between the image sensing device 100 and other devices.

[0027] The column driver 160 may select a column of the output buffer upon receiving a control signal from the timing controller 170, and sequentially output the image data temporarily stored in the selected column of the output buffer 150. In some implementations, upon receiving an address signal from the timing controller 170, the column driver 160 may generate a column selection signal based on the address signal and select a column of the output buffer 150, and the output buffer 150 outputs the image data from the selected column of the output buffer 150 as an output signal.

[0028] The timing controller 170 may control operations of the row driver 120 , the ADC 140 , the output buffer 150 , and the column driver 160 .

[0029] The timing controller 170 may provide the row driver 120, the CDS 130, the ADC 140, the output buffer 150, and the column driver 160 with clock signals required for the operation of the components of the image sensing device 100, control signals for timing control, and address signals for selecting rows or columns. In an embodiment of the disclosed technology, the timing controller 170 may include a logic control circuit, a phase-locked loop (PLL) circuit, a timing control circuit, a communication interface circuit, and the like.

[0030] Figure 2 Some implementations based on the disclosed technology are illustrated. Figure 1 Schematic diagram of an example of a pixel array shown in .

[0031] Reference Figure 2 , the pixel array 200 may be Figure 1 The pixel array 110 is shown as an example of some parts, and may include first to fourth pixels PX1 to PX4 arranged in a (2×2) matrix array. Figure 2 The pixel array 200 is shown to include only four pixels PX1 to PX4, but other implementations are also possible. For example, the pixel array 200 may correspond to an (M×N) matrix array including a plurality of pixels (wherein M and N are both integers of 2 or greater), the plurality of pixels including the first pixel PX1 to the fourth pixel PX4 repeatedly arranged in the row direction (ROW) and the column direction (COL).

[0032] Each of the first pixel PX1 to the fourth pixel PX4 can convert the intensity of the incident light into an electrical signal, and then the electrical signal can be output. To this end, each of the first pixel PX1 to the fourth pixel PX4 may include at least one photoelectric conversion element, a floating diffusion (FD) area, and a plurality of transistors. In this case, at least one photoelectric conversion element in each pixel can convert the intensity of the incident light into a photocharge, the photocharge can be accumulated in the floating diffusion (FD) area, and the plurality of transistors in each pixel can convert the photocharge into an electrical signal as the output of the pixel. Specifically, the plurality of transistors may include a transfer transistor for moving the photocharge from the photoelectric conversion element to the floating diffusion (FD) area, a reset transistor for resetting the floating diffusion (FD) area, a dual conversion gain (DCG) transistor for selectively providing additional capacitance to the floating diffusion (FD) area, a source follower transistor for converting the voltage level of the floating diffusion (FD) area into an electrical signal, and a selection transistor for outputting the electrical signal to the output signal line.

[0033] The row driver 120 may send control signals for controlling a plurality of transistors to each of the pixels PX1 to PX4. The control signals may include a transfer control signal for controlling a transfer transistor, a reset control signal for controlling a reset transistor, a DCG control signal for controlling a DCG transistor, and a selection control signal for controlling a selection transistor.

[0034] The row driver 120 may provide a control signal through a control signal line extending in a row direction (ROW). Therefore, the pixels PX1 to PX4 included in the pixel array 200 may be driven on a row basis.

[0035] In more detail, the first pixel PX1 and the third pixel PX3 belonging to the first row may receive the first transmission control signal TC1, the first reset control signal RC1, the first DCG control signal DCG1, and the first selection control signal SEL1 through the same control signal line. Figure 2 Only one control signal line for the first pixel PX1 and the third pixel PX3 is illustrated, but other implementations are possible. For example, there may be control signal lines for providing the first transmission control signal TC1, the first reset control signal RC1, the first DCG control signal DCG1, and the first selection control signal SEL1, respectively.

[0036] The second pixel PX2 and the fourth pixel PX4 belonging to the second row can receive the second transmission control signal TC2, the second reset control signal RC2, the second DCG control signal DCG2 and the second selection control signal SEL2 through the same control signal line. In some implementations, the second transmission control signal TC2, the second reset control signal RC2, the second DCG control signal DCG2 and the second selection control signal SEL2 can be provided through respective control signal lines.

[0037] Each of the pixels PX1 to PX4 included in the pixel array 200 can output an electrical signal (i.e., a pixel signal) through an output signal line extending in a column direction (COL). Each of the first pixel PX1 and the fourth pixel PX4 belonging to the first column can output a pixel signal through a first output signal line (Vout1). Each of the second pixel PX2 and the third pixel PX3 belonging to the second column can output a pixel signal through a second output signal line (Vout2).

[0038] Generally, four adjacent pixels PX1, PX2, PX3, and PX4 in two adjacent rows and columns are arranged so that pixels PX1 and PX2 are diagonally opposite to each other, and pixels PX3 and PX4 are diagonally opposite to each other. Figure 2 , the four adjacent pixels PX1, PX2, PX3 and PX4 of two adjacent rows and columns are not aligned in rows and columns, and are specially designed to have a small spatial offset in the column direction between two adjacent columns, so that although the first pixel PX1 and the third pixel PX3 belong to the first row, the third pixel PX3 belonging to the second column can be spatially offset (for example, upward as shown in this example) by a predetermined width in the column direction (COL) compared with the first pixel PX1 belonging to the first column. Similarly, although the second pixel PX2 and the fourth pixel PX4 belong to the second row, the second pixel PX2 belonging to the second column can be spatially offset by a predetermined width upward in the column direction (COL) compared with the fourth pixel PX4 belonging to the first column.

[0039] Therefore, due to this spatial offset, the first pixel PX1 in the first column and the second pixel PX2 in the second adjacent column may contact each other through the contact surface CS corresponding to the predetermined width.

[0040] This arrangement is different from various other pixel layouts in the following imaging sensors: in which four adjacent pixels PX1, PX2, PX3 and PX4 in two adjacent rows and columns are aligned without any offset in the rows and columns, so that pixels PX1 and PX2 are diagonally opposite each other without any spatial overlap, and pixels PX3 and PX4 are diagonally opposite each other without any spatial overlap.

[0041] exist Figure 2In this spatially offset pixel layout, the first pixel PX1 and the second pixel PX2 can be located in two different rows adjacent to each other and in two different columns adjacent to each other. Therefore, the first pixel PX1 and the second pixel PX2 can be arranged in a diagonal direction relative to the row direction (ROW) or the column direction (COL). Therefore, the first pixel PX1 and the second pixel PX2 can receive control signals through different control signal lines and can output pixel signals through different output lines. The first pixel PX1 and the second pixel PX2 can be connected to each other through the contact surface CS, and thus can share at least one element.

[0042] In some implementations, the first pixel PX1 and the second pixel PX2 may be coupled to each other through a contact surface CS so that at least some portions of the DCG transistors of the first pixel PX1 and the second pixel PX2 may be shared with each other.

[0043] Figure 3 Some implementations based on the disclosed technology are illustrated. Figure 2 An exemplary circuit diagram 300 of a first pixel PX1 and a second pixel PX2 is shown.

[0044] Figure 3 Examples include Figure 2 A circuit diagram 300 of a first pixel PX1 and a second pixel PX2 is shown.

[0045] The first pixel PX1 may include a plurality of first photoelectric conversion elements PD1_1 to PD1_n (where "n" is an integer of 2 or more), a plurality of first transfer transistors TX1_1 to TX1_n, a first reset transistor RX1, a first DCG transistor DX1, a first floating diffusion (FD) region FD1, a first source follower transistor SF1, and a first selection transistor SX1. The first pixel PX1 may refer to a shared pixel configured to include a plurality of first photoelectric conversion elements PD1_1 to PD1_n. The first pixel PX1 includes first transfer transistors TX1_1 to TX1_n arranged to correspond to the first photoelectric conversion elements PD1_1 to PD1_n, respectively. The remaining elements in the first pixel PX1 except the first transfer transistors TX1_1 to TX1_n may be shared by the first photoelectric conversion elements PD1_1 to PD1_n.

[0046] Each of the first photoelectric conversion elements PD1_1 to PD1_n may generate and accumulate photocharges corresponding to the intensity of incident light. For example, each of the first photoelectric conversion elements PD1_1 to PD1_n may be implemented as a photodiode, a phototransistor, a photogate, or a pinned photodiode, or a combination thereof.

[0047] If each of the first photoelectric conversion elements PD1_1 to PD1_n is implemented as a photodiode, each of the first photoelectric conversion elements PD1_1 to PD1_n may be a region doped with a second conductive impurity (e.g., an N-type impurity) in a substrate including a first conductive impurity (e.g., a P-type impurity). As an example, the substrate will hereinafter be referred to as a first conductive substrate, such as a P-type substrate.

[0048] Each of the first transfer transistors TX1_1 to TX1_n may be connected in series between the first floating diffusion (FD) region FD1 and a corresponding one of the first photoelectric conversion elements PD1_1 to PD1_n. The first transfer transistors TX1_1 to TX1_n may be turned on or off in response to first transfer control signals TC1_1 to TC1_n, respectively. If the first transfer transistor TX1_1 is turned on, the first transfer transistor TX1_1 may transfer photocharges accumulated in the corresponding photoelectric conversion element to the first floating diffusion (FD) region FD1.

[0049] In some implementations, the first transmission transistors TX1_1 to TX1_n may be turned on sequentially. In some other implementations, at least two first transmission transistors may be turned on simultaneously.

[0050] The first reset transistor RX1 may be coupled between a power supply voltage (VDD) and a first floating diffusion (FD) region FD1 and may reset a voltage of the first floating diffusion (FD) region FD1 to the power supply voltage (VDD) in response to a first reset control signal RC1.

[0051] The other pixels are constructed similarly to the first pixel PX1 and are in a similar circuit sharing configuration. For example, the pixel PX2 may include a plurality of second photoelectric conversion elements PD2_1 to PD2_n (wherein "n" is an integer of 2 or greater), a plurality of second transfer transistors TX2_1 to TX2_n, a second reset transistor RX2, a second DCG transistor DX2, a second floating diffusion (FD) region FD2, a second source follower transistor SF2, and a second selection transistor SX2.

[0052] It is worth noting that in Figure 3 In the example, the DCG capacitor (C DCG ) may be coupled between the first DCG transistor DX1 and the second DCG transistor DX2 to provide a common DCG capacitor (C DCG ) is shared by two diagonal pixels PX1 and PX2 with overlapping contact surface CS, such as Figure 2 Specifically, Figure 3As shown, the first DCG transistor DX1 may be coupled between the second DCG transistor DX2 of the second pixel PX2 and the first floating diffusion (FD) region FD1, and may allow the DCG capacitor (C DCG ) is coupled between the first DCG transistor DX1 and the second DCG transistor DX2 to be selectively coupled to the first floating diffusion (FD) region FD1 in response to the first DCG control signal DCG1. The DCG capacitor (C DCG ) can be a region in which second conductive impurities (e.g., N-type impurities) are doped in a substrate (e.g., a first conductive substrate or a P-type substrate) including first conductive impurities (e.g., a P-type substrate), and can be modeled as a single junction capacitor.

[0053] The first pixel PX1 may operate in two operation modes including a high-sensitivity mode and a low-sensitivity mode.

[0054] The high sensitivity mode may refer to a mode having a relatively large increase in response due to an increase in the intensity of incident light. The "response" may refer to a pixel signal generated by the first pixel PX1 that has detected the intensity of the incident light. Therefore, the high sensitivity mode may refer to a mode having a relatively high sensitivity to the incident light.

[0055] The low sensitivity mode may refer to a mode having a relatively small increase in response due to an increase in incident light intensity. Thus, the low sensitivity mode may refer to a mode having a relatively low sensitivity to incident light.

[0056] The sensitivity of the first pixel PX1 or the second pixel PX2 can be determined by connecting to the DCG capacitor (C DCG ) or with a DCG capacitor (C DCG ) is turned off. This is described in detail below using the first pixel PX1 as an example.

[0057] In the high sensitivity mode, the photocharge storage capacity of the first floating diffusion (FD) area FD1 may be set to a relatively low level. In the case where the photocharge storage capacity of the first floating diffusion (FD) area FD1 is at a relatively low level, if a predetermined photocharge is accumulated (or stored) in the first floating diffusion (FD) area FD1, the voltage change of the first floating diffusion (FD) area FD1 may be relatively large, so that the voltage change of the electrical signal generated by the first source follower transistor SF1 may be relatively large, resulting in an increase in the sensitivity of the first pixel PX1. In order to reduce the photocharge storage capacity of the first floating diffusion (FD) area FD1 in the high sensitivity mode, the first DCG transistor DX1 may be turned off so that the DCG capacitor (C DCG) may not be provided to the first floating diffusion (FD) region FD1.

[0058] On the other hand, in the low sensitivity mode, the photocharge storage capacity of the first floating diffusion (FD) area FD1 may be set to a relatively high level. In the case where the photocharge storage capacity of the first floating diffusion (FD) area FD1 is at a relatively high level, if a predetermined photocharge is accumulated (or stored) in the first floating diffusion (FD) area FD1, the voltage change of the first floating diffusion (FD) area FD1 may be relatively small, so that the voltage change of the electrical signal generated by the first source follower transistor SF1 may be relatively small, resulting in a reduction in the sensitivity of the first pixel PX1. In order to reduce the photocharge storage capacity of the first floating diffusion (FD) area FD1 in the low sensitivity mode, the first DCG transistor DX1 may be turned on so that the DCG capacitor (C DCG ) can be provided to the first floating diffusion region (FD) region FD1.

[0059] A high dynamic range (HDR) can be achieved using both a response of a high sensitivity mode applicable to a low illumination range and a response of a low sensitivity mode applicable to a high illumination range. The above-mentioned case of using both the high sensitivity mode and the low sensitivity mode can enable the first pixel PX1 to have a high dynamic range (HDR) corresponding to a specific range from a minimum value of the high sensitivity mode dynamic range to a maximum value of the low sensitivity mode dynamic range, compared to other cases where any one of the high sensitivity mode and the low sensitivity mode is used. In this case, the dynamic range of the pixel can refer to a range of incident light intensities for which the first pixel PX1 can have an effective response indicating the incident light intensity.

[0060] In some other implementations, the first pixel PX1 may have not only a high sensitivity mode and a low sensitivity mode, but also an ultra-low sensitivity mode having a lower sensitivity than the low sensitivity mode.

[0061] The first floating diffusion (FD) region FD1 in the ultra-low sensitivity mode can have a larger photocharge storage capacity than the first floating diffusion (FD) region FD1 in the low sensitivity mode. In order to further improve the photocharge storage capacity of the first floating diffusion (FD) region FD1 in the ultra-low sensitivity mode, the first DCG transistor DX1 and the second DCG transistor DX2 are turned on, so that the DCG capacitor (C DCG ) and the capacitance of the second floating diffusion (FD) region FD2 may be provided to the first floating diffusion (FD) region FD1.

[0062] A high dynamic range (HDR) can be achieved using not only a response of a high sensitivity mode suitable for a low illumination range and a response of a low sensitivity mode suitable for a high illumination range, but also a response of an ultra-low sensitivity mode suitable for an ultra-high illumination range. As a result, the first pixel PX1 can have a more extended dynamic range compared to other cases where both the high sensitivity mode and the low sensitivity mode are used.

[0063] In the low sensitivity mode, when the first DCG transistor DX1 is turned on, the DCG capacitor (C DCG ) and the parasitic capacitance of the first DCG transistor DX1 may be provided to the first floating diffusion (FD) region FD1.

[0064] Similarly, in the ultra-low sensitivity mode, when the first DCG transistor DX1 and the second DCG transistor DX2 are turned on, not only the DCG capacitor (C DCG ) and the capacitance of the second floating diffusion (FD) region FD2, and the parasitic capacitance of the first DCG transistor DX1 and the second DCG transistor DX2 can also be provided to the first floating diffusion (FD) region FD1.

[0065] The first floating diffusion (FD) region FD1 may accumulate and store photocharges received from each of the first transfer transistors TX1_1 to TX1_n. The first floating diffusion (FD) region FD1 may refer to a region doped with second conductive impurities (e.g., N-type impurities) in a substrate (i.e., a first conductive substrate or a P-type substrate) including first conductive impurities (e.g., P-type impurities), and may be modeled as a single junction capacitor.

[0066] The first source follower transistor SF1 can be connected between the power supply voltage (VDD) and the first selection transistor SX1, can amplify the potential change of the first floating diffusion (FD) region FD1 that has received the photocharges accumulated in each of the first photoelectric conversion elements PD1_1 to PD1_n, and can transmit the amplified potential to the first selection transistor SX1.

[0067] The first selection transistor SX1 may be coupled between the first source follower transistor SF1 and the first output signal line ( Vout1 ), and may be turned on in response to a first selection control signal SEL1 so that an electrical signal received from the first source follower transistor SF1 may be output to the first output signal line ( Vout1 ).

[0068] As follows Figure 4 and Figure 5 As further explained in Figure 2 The useful DCG capacitor (CDCG ).

[0069] Figure 4 Some implementations based on the disclosed technology are illustrated. Figure 2 FIG. 1 is a plan view of an example of first to fourth pixels PX1 to PX4 .

[0070] Figure 4 It is an example Figure 2 1 is a schematic diagram of an example of a first pixel PX1 to a fourth pixel PX4, and illustrates a layout structure 400 including a first pixel 410 to a fourth pixel 440. Each of the first pixel 410 to the fourth pixel 440 may be a 4-shared pixel structure including four photoelectric conversion elements. Therefore, Figure 4 An exemplary structure may correspond to Figure 3 Shown is a case where "n" is set to 4 (ie, n=4).

[0071] The first pixel 410 may include a plurality of first transfer gates TG1_1 to TG1_4 , a first selection gate SG1 , a first source follower gate FG1 , a first reset gate RG1 , and a first DCG gate DG1 .

[0072] The first transfer gates TG1_1 to TG1_4 may correspond to Figure 3 . The first transfer gates TG1_1 to TG1_4 may be arranged in a (2×2) matrix array. Although not shown in the figure, at least a portion of the impurity region corresponding to the first floating diffusion (FD) region FD1 may overlap with each of the first transfer gates TG1_1 to TG1_4 at the central portion of the first transfer gates TG1_1 to TG1_4. In addition, at least a portion of the impurity region corresponding to each of the first photoelectric conversion elements PD1_1 to PD1_4 may overlap with each of the first transfer gates TG1_1 to TG1_4. The impurity regions corresponding to the first photoelectric conversion elements PD1_1 to PD1_4 may be arranged in a (2×2) matrix array while being spaced apart from each other, and may also be spaced apart from the impurity region corresponding to the first floating diffusion (FD) region FD1.

[0073] In the first pixel 410, the first selection gate SG1, the first source follower gate FG1, the first reset gate RG1 and the first DCG gate DG1 may be sequentially arranged at the lower side of the region where the first transfer gates TG1_1 to TG1_4 are arranged. Accordingly, the photoelectric conversion element in the first pixel 410 may be disposed at the upper side of the first DCG gate DG1.

[0074] The first select gate SG1, the first source follower gate FG1, the first reset gate RG1, and the first DCG gate DG1 may correspond to Figure 3 Shown are the gate of the first select transistor SX1, the gate of the first source follower transistor SF1, the gate of the first reset transistor RX1, and the gate of the first DCG transistor DX1.

[0075] The second pixel 420 may include a plurality of second transmission gates TG2_1 to TG2_4, a second selection gate SG2, a second source follower gate FG2, a second reset gate RG2, and a second DCG gate DG2. The second transmission gates TG2_1 to TG2_4, the second selection gate SG2, the second source follower gate FG2, the second reset gate RG2, and the second DCG gate DG2 may correspond to the gates of the second transmission transistors TX2_1 to TX2_4, the gate of the second selection transistor SX2, the gate of the second source follower transistor SF2, the gate of the second reset transistor RX2, and the gate of the second DCG transistor DX2, respectively.

[0076] As described above, although the second pixel 420 is different from the first pixel 410 in terms of relative arrangement of the transfer gate and other gates, the second pixel 420 may be substantially the same in terms of the structure of elements as those of the first pixel 410. Therefore, a detailed description of each element included in the second pixel 420 will be omitted.

[0077] In the second pixel 420, the second DCG gate DG2, the second reset gate RG2, the second source follower gate FG2 and the second selection gate SG2 may be sequentially arranged on the upper side of the region in which the second transfer gates TG2_1 to TG2_4 are arranged. Accordingly, the photoelectric conversion element in the second pixel 420 may be disposed on the lower side of the second DCG gate DG2.

[0078] The first selection gate SG1, the first source follower gate FG1, the first reset gate RG1, and the first DCG gate DG1 of the first pixel 410 may be arranged symmetrically with respect to the contact surface CS between the first pixel 410 and the second pixel 420 and the second selection gate SG2, the second source follower gate FG2, the second reset gate RG2, and the second DCG gate DG2 of the second pixel 420. In addition, the first selection gate SG1, the first source follower gate FG1, the first reset gate RG1, the first DCG gate DG1, the second DCG gate DG2, the second reset gate RG2, the second source follower gate FG2, and the second selection gate SG2 may be sequentially arranged in a row.

[0079] The common area CA may be disposed across the first pixel 410 and the second pixel 420 while overlapping the contact surface CS. At least a portion of the common area CA may overlap each of the first DCG gate DG1 and the second gate DG2, so that the common area CA may be formed to include at least some portions of the first DCG gate DG1 and the second gate DG2.

[0080] The common area CA may include a straight line intersecting the contact surface CS, the center point of which will be defined as the rotation center (RC) hereinafter. The gate of the first pixel 410 may correspond to a structure formed by rotating the gate of the second pixel 420 relative to the rotation center (RC), and the gate of the first pixel 410 may correspond to a structure formed by rotating the gate of the second pixel 420 relative to the rotation center (RC). Therefore, the gate of the first pixel 410 and the gate of the second pixel 420 may have rotational symmetry relative to the rotation center (RC).

[0081] The fourth pixel 440 disposed below the first pixel 410 may be substantially identical in structure to the first pixel 410, and the third pixel 430 disposed above the second pixel 420 may be substantially identical in structure to the second pixel 420. Therefore, a detailed description of elements of the third pixel 430 and the fourth pixel 440 will be omitted herein.

[0082] The transistors DG3, RG3, FG3 and SG3 of the third pixel 430 can be arranged in a row together with the transistor 450 of the adjacent pixel arranged in the upward direction of the first pixel 410, and the above description of the first pixel 410 and the second pixel 420 described above can also be basically equally applied not only to the adjacent pixels arranged in the upward direction of the first pixel 410, but also to the third pixel 430.

[0083] The transistors DG4, RG4, FG4 and SG4 of the fourth pixel 440 can be arranged in a row together with the transistor 460 of the adjacent pixel arranged in the downward direction of the second pixel 420, and the detailed description of the first pixel 410 and the second pixel 420 described above can also be basically equally applied not only to the fourth pixel 440, but also to the adjacent pixels arranged in the downward direction of the second pixel 420.

[0084] Figure 5 The following are some examples of implementations based on the disclosed technology. Figure 4 FIG. 5 is a cross-sectional view 500 of the layout structure 400 taken along line AA′ shown in FIG.

[0085] from Figure 5 It can be seen from the cross-sectional view 500 that the Figure 4 The layout structure 400 of the first pixel 410 to the fourth pixel 440 is shown along Figure 4 The first cutting line AA′ shown is taken.

[0086] Reference Figure 5In the layout structure 400 , the first selection gate SG1 , the first source follower gate FG1 , the first reset gate RG1 , the first DCG gate DG1 , the second DCG gate DG2 , the second reset gate RG2 , the second source follower gate FG2 , and the second selection gate SG2 may be sequentially arranged along the first cutting line AA′.

[0087] The first selection gate SG1 may include a gate electrode 501 for receiving a corresponding control signal or photocharge, and a gate insulating layer 502 disposed between the corresponding gate electrode and the substrate 590 to electrically insulate the corresponding gate electrode from the substrate 590. The first source follower gate FG1 may include a gate electrode 511 for receiving a corresponding control signal or photocharge, and a gate insulating layer 512 disposed between the corresponding gate electrode and the substrate 590 to electrically insulate the corresponding gate electrode from the substrate 590. The first reset gate RG1 may include a gate electrode 521 for receiving a corresponding control signal or photocharge, and a gate insulating layer 522 disposed between the corresponding gate electrode and the substrate 590 to electrically insulate the corresponding gate electrode from the substrate 590. The first DCG gate DG1 may include a gate electrode 531 for receiving a corresponding control signal or photocharge, and a gate insulating layer 532 disposed between the corresponding gate electrode and the substrate 590 to electrically insulate the corresponding gate electrode from the substrate 590. The second DCG gate DG2 may include a gate electrode 541 for receiving a corresponding control signal or photocharge, and a gate insulating layer 542 disposed between the corresponding gate electrode and the substrate 590 to electrically insulate the corresponding gate electrode from the substrate 590. The second reset gate RG2 may include a gate electrode 551 for receiving a corresponding control signal or photocharge, and a gate insulating layer 552 disposed between the corresponding gate electrode and the substrate 590 to electrically insulate the corresponding gate electrode from the substrate 590. The second source follower gate FG2 may include a gate electrode 561 for receiving a corresponding control signal or photocharge, and a gate insulating layer 562 disposed between the corresponding gate electrode and the substrate 590 to electrically insulate the corresponding gate electrode from the substrate 590. The second select gate SG2 may include a gate electrode 571 for receiving a corresponding control signal or photocharge, and a gate insulating layer 572 disposed between the corresponding gate electrode and the substrate 590 to electrically insulate the corresponding gate electrode from the substrate 590.

[0088] The substrate 590 may be a semiconductor substrate formed by growing an epitaxial layer on a base substrate. Although the substrate 590 may include a first conductive impurity (e.g., a P-type impurity) or a second conductive impurity (e.g., an N-type impurity), other implementations are possible. In some examples, it is assumed that the substrate 590 includes a first conductive impurity (e.g., a P-type impurity).

[0089] and Figure 4Each impurity region corresponding to the first photoelectric conversion elements PD1_1 to PD1_4 shown in FIG. 5 may be a region doped with second conductive impurities (e.g., N-type impurities) in the substrate 590. In addition, the impurity region corresponding to the first floating diffusion (FD) region FD1 may be a region doped with second conductive impurities (e.g., N-type impurities) in the substrate 590.

[0090] For example, each gate electrode 501, 511, 521, 531, 541, 551, 561, and 571 may include a conductive material such as metal or polysilicon. Each gate insulating layer 502, 512, 522, 532, 542, 552, 562, and 572 may include a silicon nitride oxide film (Si x O y N z , where each of "x", "y" and "z" is a natural number), silicon oxide film (Si x O y , where each of "x" and "y" is a natural number) and a silicon nitride film (Si x N y , where each of "x" and "y" is a natural number). In this case, the silicon oxynitride film (Si x O y N z ), silicon oxide film (Si x O y ) and silicon nitride film (Si x N y ) can be formed from an electrically insulating material.

[0091] Impurity regions may be disposed at both sides of each of the first select gate SG1 , the first source follower gate FG1 , the first reset gate RG1 , the first DCG gate DG1 , the second DCG gate DG2 , the second reset gate RG2 , the second source follower gate FG2 , and the second select gate SG2 .

[0092] In more detail, the first impurity region 503 and the second impurity region 505 may be disposed on both sides of the first selection gate SG1. The second impurity region 505 and the third impurity region 515 may be disposed on both sides of the first source follower gate FG1. The third impurity region 515 and the fourth impurity region 525 may be disposed on both sides of the first reset gate RG1. The fourth impurity region 525 and the common region 535 may be disposed on both sides of the first DCG gate DG1. The common region 535 and the fifth impurity region 545 may be disposed on both sides of the second DCG gate DG2. The fifth impurity region 545 and the sixth impurity region 555 may be disposed on both sides of the second reset gate RG2. The sixth impurity region 555 and the seventh impurity region 565 may be disposed on both sides of the second source follower gate FG2. The seventh impurity region 565 and the eighth impurity region 575 may be disposed on both sides of the second selection gate SG2.

[0093] The common region 535 and each impurity region 503, 505, 515, 525, 545, 555, 565, and 575 may refer to a region in which a second conductive impurity (e.g., N-type impurity) is doped in a substrate 590 including a first conductive impurity (e.g., P-type impurity). The common region 535 and each impurity region 503, 505, 515, 525, 545, 555, 565, and 575 may correspond to a source or a drain of each of the first selection transistor SX1, the first source follower transistor SF1, the first reset transistor RX1, the first DCG transistor DX1, the second DCG transistor DX2, the second reset transistor RX2, the second source follower transistor SF2, and the second selection transistor SX2.

[0094] and Figure 3 Compared to the circuit diagram of , the first impurity region 503 can be connected to the first output signal line (Vout1), the third impurity region 515 can be connected to the power supply voltage (VDD), the fourth impurity region 525 can be connected to the first floating diffusion (FD) region FD1, the fifth impurity region 545 can be connected to the second floating diffusion (FD) region FD2, the sixth impurity region 555 can be connected to the power supply voltage (VDD), and the eighth impurity region 575 can be connected to the second output signal line (Vout2).

[0095] On the other hand, since the common region 535 may refer to a region in which the second conductive impurities (e.g., N-type impurities) are doped in the substrate 590 (i.e., the first conductive substrate, such as the P-type substrate) including the first conductive impurities (e.g., P-type impurities), a junction capacitor may be formed between the common region 535 and the substrate 590. In this case, the junction capacitor may correspond to Figure 3 The DCG capacitor (C DCGAs the size of the contact area between the common area 535 and the substrate 590 increases, the capacitance of the junction capacitor also increases. As a result, as the volume of the common area 535 increases, the DCG capacitor (C DCG ) can also be increased. Since the common region 535 can be formed across the first pixel 410 and the second pixel 420 that are diagonally opposite to each other and have a contact surface between them due to the spatial offset in the column direction, the common region 535 can be advantageously used to provide a DCG capacitor (C DCG ) to connect to or disconnect the DCG capacitor (C DCG ) to modulate the effective capacitance of FD1 or FD2.

[0096] In the case where one impurity region for a DCG capacitor (hereinafter referred to as a first impurity region) is formed at one side of the first DCG gate DG1 in the first pixel 410 and another impurity region for a DCG capacitor (hereinafter referred to as a second impurity region) is formed at one side of the second DCG gate DG2 in the second pixel 420, the capacitance of the DCG capacitor provided by the first impurity region and the capacitance of the DCG capacitor provided by the second impurity region may be smaller than the capacitance of the DCG capacitor (C DCG ) capacitor.

[0097] As the size of the DCG capacitor increases, the sensitivity of the corresponding pixel in the low sensitivity mode may decrease, so that the dynamic range can be expanded in the low sensitivity mode. For example, if the ratio of the dynamic range of the high sensitivity mode to the dynamic range of the low sensitivity mode needs to be set to 1:2, a DCG capacitor with a relatively large capacitance (C DCG ) can more easily achieve the dynamic range required for low-sensitivity modes.

[0098] As before Figure 3 As described in the low sensitivity mode or the ultra low sensitivity mode, a specific floating diffusion (FD) region (eg, FD1) may receive not only a DCG capacitor (C DCG ) and the capacitance of another floating diffusion (FD) region (e.g., FD2), and also receives the parasitic capacitance of the first DCG transistor DX1 and the second DCG transistor DX2, so that the dynamic range required for the low sensitivity mode or the ultra-low sensitivity mode can be more easily achieved. In this case, the parasitic capacitance may refer to the capacitance of a parasitic capacitor formed between a gate electrode and an impurity region (e.g., a parasitic capacitor formed between the first DCG gate DG1 and the common region 535).

[0099] In order to increase the capacitance to be provided to the floating diffusion (FD) region in the low sensitivity mode, a method for increasing the size of the DCG capacitor (i.e., a method for increasing the parasitic capacitance) may be used. However, as the size of the area that can be allocated to a pixel gradually decreases, there is a limit to increasing the size of the DCG transistor within a pixel.

[0100] In addition, in order to increase the capacitance to be provided to the floating diffusion (FD) region in the low sensitivity mode, a method for forming a metal-insulator-metal (MIM) capacitor using a control signal line for applying a DCG control signal may be used, but the method for forming the MIM capacitor has a disadvantage in that stripe noise (e.g., black sun stripe noise) inevitably increases.

[0101] More specifically, pixels belonging to a particular row can be connected to a single control signal line to which a DCG control signal is applied, and a voltage change in the floating diffusion (FD) region of any one pixel can affect the voltage level of the floating diffusion (FD) region of at least one pixel connected to the same control signal line. This is because capacitive coupling occurs between floating diffusion (FD) regions. In addition, the MIM capacitors connected to each floating diffusion (FD) region are only connected to one control signal line, and each MIM capacitor can have a relatively large capacitance, so that capacitive coupling between floating diffusion (FD) regions can occur more significantly through the control signal line.

[0102] In contrast, in some implementations of the disclosed technology, the DCG capacitor (C DCG ) is not used as a capacitor coupled to the control signal line, so that an increase in stripe noise can be advantageously prevented.

[0103] Since the first pixel 410 and the second pixel 420 belong to different rows, the first pixel 410 and the second pixel 420 can be controlled by different control signal lines, and the first pixel 410 and the second pixel 420 can be read out at different times as needed. Therefore, when the first pixel PX1 is read out, the DCG capacitor (C DCG When the second pixel PX2 is read out, the DCG capacitor (C DCG ).

[0104] In other words, the first pixel 410 and the second pixel 420 may be controlled by different control signals, and the first pixel 410 and the second pixel 420 may output pixel signals through different output signal lines. As a result, the first pixel 410 and the second pixel 420 may share the DCG capacitor (C DCG) without causing conflicts or noise.

[0105] An image sensing device based on some implementations of the disclosed technology can obtain the capacitance required for the low-sensitivity mode by changing the layout structure of the pixels without increasing the size of each pixel or using capacitors that may cause noise.

[0106] Figure 6 Some implementations based on the disclosed technology are illustrated. Figure 2 FIG. 1 is a plan view of another example of first to fourth pixels PX1 to PX4 .

[0107] Figure 6 It is an example Figure 2 1 is a schematic diagram of another example of the first pixel PX1 to the fourth pixel PX4, and illustrates a layout structure 600 including the first pixel 610 to the fourth pixel 640. Each of the first pixel 610 to the fourth pixel 640 can be an 8-shared pixel structure including eight photoelectric conversion elements. Therefore, Figure 6 An exemplary structure may correspond to Figure 3 The case where "n" shown in FIG. 8 is set to 8 (ie, n=8).

[0108] The first pixel 610 may include a plurality of first transfer gates TG1_1 to TG1_8, a first source follower gate FG1, a first selection gate SG1, a first reset gate RG1, and a first DCG gate DG1. Figure 4 The structure of the first pixel 410 shown is different from some structures of the first pixel 610. The remaining components of the first pixel 610 can be the same as Figure 4 Those components of the first pixel 410 shown are substantially identical in structure, and as such, detailed descriptions thereof will be omitted herein for the sake of brevity. Figure 4 The first pixel 410 shown has different features as the center. Figure 6 A first pixel 610 is shown.

[0109] The plurality of first transmission gates TG1_1 to TG1_8 may be arranged in a (4×2) matrix array. In other words, the first transmission gates TG1_1 to TG1_4 arranged in a (2×2) matrix array may be vertically spaced apart by a predetermined distance from the first transmission gates TG1_5 to TG1_8 arranged in a (2×2) matrix array. Figure 6, but an impurity region corresponding to the first floating diffusion (FD) region FD1 may be disposed at a central portion of the first transmission gates TG1_1 to TG1_4, and another impurity region corresponding to the first floating diffusion (FD) region FD1 may be disposed at a central portion of the first transmission gates TG1_5 to TG1_8. In this case, the two impurity regions may be electrically coupled to each other, thereby forming a single node. In addition, at least a portion of the impurity region corresponding to each of the first photoelectric conversion elements PD1_1 to PD1_8 may overlap with each of the first transmission gates TG1_1 to TG1_8. The impurity regions corresponding to the first photoelectric conversion elements PD1_1 to PD1_8, respectively, may be spaced apart from each other so that the impurity regions may be arranged in a (4×2) matrix array. In addition, the impurity region may also be spaced apart from other impurity regions corresponding to the first floating diffusion (FD) region FD1.

[0110] In the first pixel 610, the first source follower gate FG1 and the first selection gate SG1 may be disposed between the first transfer gates TG1_1 to TG1_4 and the other first transfer gates TG1_5 to TG1_8, and the first reset gate RG1 and the first DCG gate DG1 may be disposed at the lower side of the region where the first transfer gates TG1_5 to TG1_8 are disposed. Accordingly, the photoelectric conversion element of the first pixel 610 may be disposed to be separated from each other at the upper and lower sides of the first source follower gate FG1 and the first selection gate SG1.

[0111] Subsequently, the second pixel 620 may include a plurality of second transfer gates TG2_1 to TG2_8, a second selection gate SG2, a second source follower gate FG2, a second reset gate RG2, and a second DCG gate DG2. In the second pixel 620, the rest of the second pixel 620 except for the arrangement form may be substantially the same in structure as the constituent elements of the first pixel 610, and thus a detailed description thereof will be omitted herein for the sake of brevity.

[0112] In the second pixel 620, the second reset gate RG2 and the second DCG gate DG2 may be disposed on the upper side of the region where the second transfer gates TG2_5 to TG2_8 are disposed, and the second source follower gate FG2 and the second selection gate SG2 may be disposed between the second transfer gates TG2_1 to TG2_4 and the second transfer gates TG2_5 to TG2_8. Accordingly, the photoelectric conversion element of the second pixel 620 may be disposed to be separated from each other at the upper and lower sides of the second source follower gate FG2 and the second selection gate SG2.

[0113] The first reset gate RG1 and the first DCG gate DG1 of the first pixel 610 may be arranged symmetrically with the second reset gate RG2 and the second DCG gate DG2 of the second pixel 620 relative to the contact surface CS between the first pixel 610 and the second pixel 620. In addition, the first reset gate RG1, the first DCG gate DG1, the second DCG gate DG2, and the second reset gate RG2 may be sequentially arranged in a row.

[0114] The common area CA may be disposed across the first pixel 610 and the second pixel 620 while overlapping the contact surface CS. At least a portion of the common area CA may overlap each of the first DCG gate DG1 and the second gate DG2, so that the common area CA may be integrally formed with the first DCG gate DG1 and the second gate DG2.

[0115] The common area CA may include a straight line formed to overlap the contact surface CS, and for ease of description, the center point of the straight line is defined as the rotation center (RC) below. The gate of the first pixel 610 may correspond to a structure formed by rotating the gate of the second pixel 620 relative to the rotation center (RC), and the gate of the second pixel 620 may correspond to a structure formed by rotating the gate of the first pixel 610 relative to the rotation center (RC). That is, the gate of the first pixel 610 and the gate of the second pixel 620 may have rotational symmetry relative to the rotation center (RC).

[0116] The fourth pixel 640 disposed at the lower side of the first pixel 610 may be substantially identical in structure to the first pixel 610, and the third pixel 630 disposed at the upper side of the second pixel 620 may be substantially identical in structure to the second pixel 620, and as such, a detailed description thereof will be omitted herein for the sake of brevity.

[0117] The transistors DG3 and RG3 of the third pixel 630 can be arranged in a row together with the transistor 650 of the adjacent pixel arranged in the upward direction of the first pixel 610, and the above description of the first pixel 610 and the second pixel 620 described above can be basically and equally applied not only to the adjacent pixels arranged in the upward direction of the first pixel 610, but also to the third pixel 630.

[0118] The transistors DG4 and RG4 of the fourth pixel 640 can be arranged in a row together with the transistors 660 of the adjacent pixels arranged in the downward direction of the second pixel 620, and the detailed description of the first pixel 610 and the second pixel 620 described above can also be basically and equally applied not only to the fourth pixel 640, but also to the adjacent pixels arranged in the downward direction of the second pixel 620.

[0119] Figure 7 is an example of some implementations based on the disclosed technology. Figure 6 FIG. 7 is a cross-sectional view 700 of the layout structure 600 taken along line BB′.

[0120] Reference Figure 6 and Figure 7 ,include Figure 6 The layout structure 600 of the first pixel 610 to the fourth pixel 640 is shown along Figure 6 The second cutting line BB′ shown in FIG.

[0121] In the layout structure 600 , the first reset gate RG1 , the first DCG gate DG1 , the second DCG gate DG2 , and the second reset gate RG2 may be sequentially arranged along the second cutting line BB′.

[0122] The first reset gate RG1 may include a gate electrode 701 for receiving a corresponding control signal, and a gate insulating layer 702 disposed between the corresponding gate electrode and the substrate 790 to electrically insulate the corresponding gate electrode from the substrate 790. The first DCG gate DG1 may include a gate electrode 711 for receiving a corresponding control signal, and a gate insulating layer 712 disposed between the corresponding gate electrode and the substrate 790 to electrically insulate the corresponding gate electrode from the substrate 790. The second DCG gate DG2 may include a gate electrode 721 for receiving a corresponding control signal, and a gate insulating layer 722 disposed between the corresponding gate electrode and the substrate 790 to electrically insulate the corresponding gate electrode from the substrate 790. The second reset gate RG2 may include a gate electrode 731 for receiving a corresponding control signal, and a gate insulating layer 732 disposed between the corresponding gate electrode and the substrate 790 to electrically insulate the corresponding gate electrode from the substrate 790.

[0123] Figure 7 The first reset gate RG1, the first DCG gate DG1, the second DCG gate DG2 and the second reset gate RG2 shown can be structurally and functionally similar to Figure 5 The first reset gate RG1 , the first DCG gate DG1 , the second DCG gate DG2 , and the second reset gate RG2 shown are substantially the same, and thus a detailed description thereof will be omitted herein for the sake of brevity.

[0124] Impurity regions may be disposed at both sides of the first reset gate RG1 , the first DCG gate DG1 , the second DCG gate DG2 , and the second reset gate RG2 .

[0125] In more detail, the ninth impurity region 703 and the tenth impurity region 705 may be disposed on both sides of the first reset gate RG1. The tenth impurity region 705 and the common region 715 may be disposed on both sides of the first DCG gate DG1. The common region 715 and the eleventh impurity region 725 may be disposed on both sides of the second DCG gate DG2. The eleventh impurity region 725 and the twelfth impurity region 735 may be disposed on both sides of the second reset gate RG2.

[0126] Figure 7 The common region 715 and each of the impurity regions 703, 705, 725, and 735 shown in FIG. 7 can be structurally and functionally identical to the common region 715 and each of the impurity regions 703, 705, 725, and 735. Figure 5 The common region 535 and each of the impurity regions 515 , 525 , 545 , and 555 are substantially the same, and thus a detailed description thereof will be omitted herein for the sake of brevity.

[0127] With Figure 5 In the same manner, the common area 715 formed across the first pixel 610 and the second pixel 620 may be associated with the substrate 790 to form a Figure 3 The DCG capacitor (C DCG ) corresponds to the junction capacitor. Figure 7 The DCG capacitor (C DCG ) can be compared with Figure 5 The DCG capacitor (C DCG ) are the same, so for the sake of brevity, its detailed description will be omitted in this article.

[0128] That is, even in an 8-shared pixel structure such as the first pixel 610 or the second pixel 620, an image sensing device based on some implementations of the disclosed technology can obtain the capacitance required for the low-sensitivity mode by changing the layout structure of the pixels without increasing the size of each pixel or using capacitors that may generate noise.

[0129] Although some implementations of the disclosed technology have disclosed 4-shared pixel structures and 8-shared pixel structures, other implementations are possible. For example, a pixel may have only one photoelectric conversion element, or may have other shared pixel structures other than 4-shared or 8-shared pixel structures.

[0130] Although some implementations of the disclosed technology have disclosed exemplary cases where a specific pixel is formed to share a common area with another pixel arranged at the lower right or upper left side of the specific pixel, other implementations are possible. For example, a specific pixel may also share a common area with another pixel arranged at the upper right or lower left side of the specific pixel. Figure 4 As shown, the left pixels 410 and 440 may be arranged horizontally symmetrically with the right pixels 420 and 430 with respect to a boundary line between the left pixels 410 and 440 and the right pixels 420 and 430 .

[0131] It is apparent from the above description that image sensing devices based on some implementations of the disclosed technology can obtain the capacitance required for low-sensitivity mode by changing the layout structure of pixels without increasing the size of each pixel or using capacitors that may cause noise.

[0132] The embodiments of the disclosed technology can provide various effects that can be directly or indirectly recognized through the above disclosure.

[0133] Although a number of exemplary embodiments have been described, it will be appreciated that modifications and enhancements of the disclosed embodiments, as well as other embodiments, may be devised based on what is described and / or illustrated in this disclosure.

[0134] CROSS-REFERENCE TO RELATED APPLICATIONS

[0135] The present disclosure claims priority to and the benefit of Korean Patent Application No. 10-2021-0005686, filed on January 15, 2021, the disclosure of which is incorporated herein by reference in its entirety as a part of the disclosure of the present disclosure.

Claims

1. An image sensing device, comprising: a pixel array including a first pixel belonging to a first row and a first column, and a second pixel belonging to a second row and a second column, the second row being adjacent to the first row and the second column being adjacent to the first column, each of the first pixel and the second pixel including one or more photoelectric conversion elements generating photocharges in response to incident light; a dual conversion gain DCG capacitor coupled between the first pixel and the second pixel; as well as a common area, the common area being arranged at a contact surface between the first pixel and the second pixel, in: The first pixel includes: a first floating diffusion region storing photocharges generated by the one or more photoelectric conversion elements of the first pixel; and a first DCG transistor for selectively connecting the DCG capacitor to the first floating diffusion region of the first pixel or disconnecting the DCG capacitor from the first floating diffusion region of the first pixel; The second pixel includes: a second floating diffusion region storing photocharges generated by the one or more photoelectric conversion elements of the second pixel; and a second DCG transistor for selectively connecting the DCG capacitor to the second floating diffusion region of the second pixel or disconnecting the DCG capacitor from the second floating diffusion region of the second pixel; The second pixel is shifted upward in the column direction of the pixel array to form the contact surface; and The DCG capacitor is a junction capacitor formed between the common region and a substrate in contact with the common region.

2. The image sensing device according to claim 1, wherein: At least a portion of the common region overlaps each of a first DCG gate of the first DCG transistor and a second DCG gate of the second DCG transistor.

3. The image sensing device according to claim 2, wherein: The first pixel and the second pixel have rotational symmetry with respect to a center point of a straight line where the contact surface intersects the common area.

4. The image sensing device according to claim 2, wherein: The first DCG gate and the second DCG gate are arranged in a row along a first direction of the pixel array.

5. The image sensing device according to claim 2, wherein: A first reset gate for resetting the first floating diffusion area and the first DCG gate is arranged symmetrically with respect to the contact surface and a second reset gate for resetting the second floating diffusion area and the second DCG gate.

6. The image sensing device according to claim 2, wherein: Each of the first pixel and the second pixel has a 4-shared pixel structure including four photoelectric conversion elements that generate photocharges corresponding to the incident light.

7. The image sensing device according to claim 2, wherein: Each of the first pixel and the second pixel has an eight-shared pixel structure including eight photoelectric conversion elements that generate photocharges corresponding to the incident light.

8. The image sensing device according to claim 1, wherein: Each of the first pixel and the second pixel stores the photo charges in a first operation mode or a second operation mode based on capacitance of the first floating diffusion region and capacitance of the second floating diffusion region, respectively.

9. An image sensing device, comprising: a pixel array including a first pixel belonging to a first row and a first column, and a second pixel belonging to a second row and a second column, the second row being adjacent to the first row and the second column being adjacent to the first column, each of the first pixel and the second pixel including one or more photoelectric conversion elements generating photocharges in response to incident light; a dual conversion gain DCG capacitor coupled between the first pixel and the second pixel; as well as a common area, the common area being arranged at a contact surface between the first pixel and the second pixel, in: The first pixel includes: a first floating diffusion region storing photocharges generated by the one or more photoelectric conversion elements of the first pixel; and a first DCG transistor for selectively connecting the DCG capacitor to the first floating diffusion region of the first pixel or disconnecting the DCG capacitor from the first floating diffusion region of the first pixel; The second pixel includes: a second floating diffusion region storing photocharges generated by the one or more photoelectric conversion elements of the second pixel; and a second DCG transistor for selectively connecting the DCG capacitor to the second floating diffusion region of the second pixel or disconnecting the DCG capacitor from the second floating diffusion region of the second pixel; At least a portion of the common region overlaps each of a first DCG gate of the first DCG transistor and a second DCG gate of the second DCG transistor; Each of the first pixel and the second pixel has a 4-shared pixel structure including four photoelectric conversion elements that generate photocharges corresponding to the incident light; The first DCG gate, a first reset gate for resetting the first floating diffusion area, a first source follower gate for generating an electrical signal corresponding to a voltage level of the first floating diffusion area, and a first select gate for outputting an electrical signal of the first source follower gate are arranged in a row along a first direction of the pixel array; and The second DCG gate, the second reset gate for resetting the second floating diffusion area, the second source follower gate for generating an electrical signal corresponding to the voltage level of the second floating diffusion area, and the second selection gate for outputting the electrical signal of the second source follower gate are arranged in a row along the first direction of the pixel array.

10. The image sensing device according to claim 9, wherein: The first DCG gate, the first reset gate, the first source follower gate and the first select gate are arranged symmetrically with the second DCG gate, the second reset gate, the second source follower gate and the second select gate relative to the contact surface.

11. An image sensing device, comprising: a pixel array including a first pixel belonging to a first row and a first column, and a second pixel belonging to a second row and a second column, the second row being adjacent to the first row and the second column being adjacent to the first column, each of the first pixel and the second pixel including one or more photoelectric conversion elements generating photocharges in response to incident light; a dual conversion gain DCG capacitor coupled between the first pixel and the second pixel; as well as a common area, the common area being arranged at a contact surface between the first pixel and the second pixel, in: The first pixel includes: a first floating diffusion region storing photocharges generated by the one or more photoelectric conversion elements of the first pixel; and a first DCG transistor for selectively connecting the DCG capacitor to the first floating diffusion region of the first pixel or disconnecting the DCG capacitor from the first floating diffusion region of the first pixel; and The second pixel includes: a second floating diffusion region storing photocharges generated by the one or more photoelectric conversion elements of the second pixel; and a second DCG transistor for selectively connecting the DCG capacitor to the second floating diffusion region of the second pixel or disconnecting the DCG capacitor from the second floating diffusion region of the second pixel; At least a portion of the common region overlaps each of a first DCG gate of the first DCG transistor and a second DCG gate of the second DCG transistor; The one or more photoelectric conversion elements in the first pixel are disposed on an upper side of the first DCG gate; and The one or more photoelectric conversion elements in the second pixel are disposed on a lower side of the second DCG gate.

12. An image sensing device, comprising: a pixel array including a first pixel belonging to a first row and a first column, and a second pixel belonging to a second row and a second column, the second row being adjacent to the first row and the second column being adjacent to the first column, each of the first pixel and the second pixel including one or more photoelectric conversion elements generating photocharges in response to incident light; a dual conversion gain DCG capacitor coupled between the first pixel and the second pixel; as well as a common area, the common area being arranged at a contact surface between the first pixel and the second pixel, in: The first pixel includes: a first floating diffusion region storing photocharges generated by the one or more photoelectric conversion elements of the first pixel; and a first DCG transistor for selectively connecting the DCG capacitor to the first floating diffusion region of the first pixel or disconnecting the DCG capacitor from the first floating diffusion region of the first pixel; and The second pixel includes: a second floating diffusion region storing photocharges generated by the one or more photoelectric conversion elements of the second pixel; and a second DCG transistor for selectively connecting the DCG capacitor to the second floating diffusion region of the second pixel or disconnecting the DCG capacitor from the second floating diffusion region of the second pixel; At least a portion of the common region overlaps each of a first DCG gate of the first DCG transistor and a second DCG gate of the second DCG transistor; Each of the first pixel and the second pixel has an eight-shared pixel structure including eight photoelectric conversion elements that generate photocharges corresponding to the incident light; The first DCG gate and the first reset gate for resetting the first floating diffusion area are spaced apart by a predetermined distance from the first source follower gate for generating an electrical signal corresponding to a voltage level of the first floating diffusion area and the first select gate for outputting the electrical signal of the first source follower gate in a second direction of the pixel array; The second DCG gate and the second reset gate for resetting the second floating diffusion area are spaced apart by a predetermined distance from the second source follower gate for generating an electrical signal corresponding to a voltage level of the second floating diffusion area and the second select gate for outputting the electrical signal of the second source follower gate in a second direction of the pixel array; and The second direction is the same as the column direction.

13. The image sensing device according to claim 12, wherein: The first DCG gate and the first reset gate are arranged symmetrically with respect to the contact surface and the second DCG gate and the second reset gate.

14. The image sensing device according to claim 12, wherein: the one or more photoelectric conversion elements of the first pixel are arranged to be separated from each other on upper and lower sides of the first source follower gate and the first select gate; as well as The one or more photoelectric conversion elements of the second pixel are arranged to be separated from each other at upper and lower sides of the second source follower gate and the second select gate.

15. An image sensing device, comprising: a pixel array including a first pixel at a first position and a second pixel arranged at a second position diagonally opposite to the first position, each of the first pixel and the second pixel including one or more photoelectric conversion elements generating photocharges in response to incident light; a dual conversion gain DCG capacitor coupled between the first pixel and the second pixel; as well as a common area, the common area being arranged at a contact surface between the first pixel and the second pixel, in: The first pixel includes a first dual conversion gain DCG gate, the first DCG gate controls the capacitance of a first floating diffusion region, the first floating diffusion region stores photocharges generated by the first pixel; The second pixel includes a second DCG gate, the second DCG gate controls the capacitance of a second floating diffusion region, the second floating diffusion region stores photocharges generated by the second pixel; and The common region overlaps each of the first DCG gate and the second DCG gate; The second pixel is shifted upward in the column direction of the pixel array to form the contact surface; and The DCG capacitor is a junction capacitor formed between the common region and a substrate in contact with the common region.

16. The image sensing device according to claim 15, wherein: The first DCG gate in the first pixel and the second DCG gate in the second pixel respectively connect the DCG capacitor to the first floating diffusion area or the second floating diffusion area or disconnect the DCG capacitor from the first floating diffusion area or the second floating diffusion area to respectively control the capacitance of the first floating diffusion area or the second floating diffusion area.

17. The image sensing device according to claim 15, wherein: The first pixels and the second pixels are arranged in different adjacent rows and different adjacent columns.

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