Storage device and method for operating a storage device

Abstract

Storage devices and methods for operating storage devices are provided. The storage device includes a non-volatile memory configured to store data written in size units of a mapping size, and a storage controller configured to send commands to the non-volatile memory. The storage controller includes a host interface configured to receive a write command from a host device, the write command including a command to write first data to a first address, the first data having a first size that is less than the mapping size. The storage controller includes processing circuitry configured to, in response to determining that the first size is less than the mapping size and prior to the first data being received at the storage controller by the host interface, send a read command to the non-volatile memory to cause the non-volatile memory to read second data addressed based on the first address that is stored in the non-volatile memory.

Description

[0001] This application claims priority to Korean Patent Application No. 10-2021-0009087, filed on January 22, 2021, with the Korean Intellectual Property Office, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] The present invention relates to a storage device and a method for operating the storage device. Background Technology

[0003] NAND flash memory, as a type of storage device, may not be able to perform in-place writes when the stored data is changed. Summary of the Invention

[0004] The present invention provides a storage device with improved operational performance. The storage device (e.g., a device including NAND flash memory) can be configured to modify data having a size smaller than a mapped size, the mapped size being the data storage unit of the NAND flash memory, and can perform read-modify-write operations that read existing stored data, merge the existing stored data with the new data, and transcribe it to another page with reduced or minimized execution time.

[0005] Aspects of the present invention (e.g., exemplary embodiments) also provide a method for operating a storage device with improved operational performance.

[0006] However, the exemplary embodiments of the inventive concept are not limited to those described herein. These and other aspects of the inventive concept will become more apparent to those skilled in the art by referring to the detailed embodiments of the inventive concept given below.

[0007] Some example embodiments provide a storage device. The storage device may include: a non-volatile memory configured to store data written in units of a mapped size; and a storage controller configured to send commands to the non-volatile memory. The storage controller may include a host interface configured to receive write commands from a host device, the write commands including a command to write first data to a first address, the first data having a first size smaller than the mapped size. The storage controller may include processing circuitry configured to: in response to determining that the first size is smaller than the mapped size and before the first data is received at the storage controller via the host interface, send a read command to the non-volatile memory to cause the non-volatile memory to read second data stored in the non-volatile memory, addressed to the first address.

[0008] Some example embodiments provide a storage device. The storage device may include: a non-volatile memory configured to store data written in units of a mapped size; and a storage controller configured to send commands to the non-volatile memory, wherein the storage controller includes: a host interface configured to receive a write command from a host device, the write command including a command to write first data to a first address, the first data having a first size smaller than the mapped size; a memory interface configured to send a memory command corresponding to the write command to the non-volatile memory; and a processing circuitry configured to: in response to determining that the first size is smaller than the mapped size and before the first data is received through the host interface, send a read command to the non-volatile memory to cause the non-volatile memory to read second data stored in the non-volatile memory, addressed to the first address, through the memory interface.

[0009] Some example embodiments provide a method for operating a storage device. The method may include: providing a non-volatile memory and a storage controller, wherein data is written to the non-volatile memory in units of a mapped size, and the storage controller is configured to send a memory command to the non-volatile memory. The method may include: receiving a write command at the storage controller, the write command including a command for writing first data of a first size to a first address. The method may include: before the first data is received at the storage controller, in response to determining that the first size is less than the mapped size, sending a read command to the non-volatile memory to cause the non-volatile memory to read second data stored in the non-volatile memory, addressed to the first address. Attached Figure Description

[0010] These and other aspects and features of the inventive concept will become clearer from a detailed description of exemplary embodiments of the inventive concept with reference to the accompanying drawings, in which:

[0011] Figure 1 This is a block diagram illustrating a memory system according to some example embodiments;

[0012] Figure 2 Based on some example embodiments Figure 1 A diagram illustrating the reconfiguration of the storage controller and non-volatile memory of the storage device;

[0013] Figure 3 Based on some example embodiments Figure 1 A diagram showing the reconfiguration of the storage controller, memory interface, and non-volatile memory;

[0014] Figure 4 It is shown Figure 3 Example block diagram of non-volatile memory;

[0015] Figure 5 This is a diagram illustrating a 3DV-NAND structure that can be applied to non-volatile memory according to some example embodiments;

[0016] Figure 6 Based on some example embodiments Figure 1 A block diagram of the processor;

[0017] Figure 7 Based on some example embodiments Figure 1 A block diagram of the partial write-to-reader;

[0018] Figure 8 and Figure 9 This is for illustrating some example embodiments. Figure 7 A diagram illustrating the functionality of the command distributor;

[0019] Figure 10 and Figure 11 This is a diagram illustrating the operation of a storage device according to some example embodiments;

[0020] Figure 12 These are diagrams illustrating the effects of a storage device according to some example embodiments;

[0021] Figure 13 This is a diagram illustrating the operation of a storage device according to some example embodiments;

[0022] Figure 14 and Figure 15 These are diagrams illustrating the operation of a storage device according to some example embodiments; and

[0023] Figure 16 This is a diagram illustrating the operation of a storage device according to some example embodiments. Detailed Implementation

[0024] In the following description, some exemplary embodiments based on the technical concept of the present invention will be described with reference to the accompanying drawings.

[0025] Figure 1 This is a block diagram illustrating a memory system according to some example embodiments.

[0026] The memory system 10 may include a host (e.g., a host device) 100 and a storage device 200. Furthermore, the storage device 200 may include a storage controller 210 and non-volatile memory (NVM) 220. Additionally, in some example embodiments, the host device 100 may include a host controller 110 and host memory 120. The host memory 120 may be used as a buffer for temporarily storing data to be sent to or from the storage device 200.

[0027] Storage device 200 may include a storage medium (e.g., a non-transitory computer-readable storage medium) for storing data in response to a request from host device 100. For example, storage device 200 may include at least one of an SSD (Solid State Drive), embedded memory, and removable external memory. When storage device 200 is an SSD, storage device 200 may be a device compliant with the NVMe (Non-Volatile Memory Fast) standard.

[0028] If the storage device 200 is embedded memory or external memory, it can be a device conforming to the UFS (Universal Flash Memory) standard or the eMMC (Embedded Multimedia Card) standard. The host device 100 and the storage device 200 can each generate and send packets according to the standard protocols they employ.

[0029] When the non-volatile memory 220 of storage device 200 includes flash memory, the flash memory may include a 2D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array. As another example, storage device 200 may also include various other types of non-volatile memory. For example, MRAM (magnetic RAM), spin-torque MRAM, conductive bridged RAM (CBRAM), FeRAM (ferroelectric RAM), PRAM (phase RAM), resistive memory (resistive RAM), and various other types of memory may be used as storage device 200.

[0030] In some example embodiments, the host controller 110 and the host memory 120 may be implemented as separate semiconductor chips. Alternatively, in some example embodiments, the host controller 110 and the host memory 120 may be integrated on the same semiconductor chip. As an example, the host controller 110 may be one of multiple modules disposed in an application processor, and such an application processor may be implemented as a system-on-a-chip (SoC). Furthermore, the host memory 120 may be an embedded memory disposed within the application processor, or a non-volatile memory or memory module disposed outside the application processor.

[0031] As described herein, some or all of the host device 100 and / or any part of the host device 100 (including, but not limited to, any one of the host controller 110, host memory 120, and any combination thereof) may include one or more products of a processing circuitry system (e.g., units, instances, etc.), may be included in, and / or may be implemented by, one or more products of a processing circuitry system (e.g., units, instances, etc.), such as hardware including logic circuitry, hardware / software combinations (e.g., processors executing software), or combinations thereof. For example, the processing circuitry system may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a graphics processing unit (GPU), an application processor (AP), a digital signal processor (DSP), a microcomputer, a field-programmable gate array (FPGA), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), a neural network processor (NPU), an electronic control unit (ECU), an image signal processor (ISP), etc. The processing circuitry may also include various types of non-volatile memory (e.g., MRAM (magnetic RAM), spin-torque MRAM, conductive bridged RAM (CBRAM), FeRAM (ferroelectric RAM), PRAM (phase RAM), resistive memory (resistive RAM)) that can implement any part of the host device 100 (e.g., host memory 120). In some example embodiments, the processing circuitry may include a non-transitory computer-readable storage device (e.g., memory) (e.g., a solid-state drive (SSD)) and a processor (e.g., a CPU), the non-transitory computer-readable storage device storing a program of instructions, the processor being configured to execute the program of instructions to implement functions and / or methods performed by some or all of the host device 100 and / or any part of the host device 100, including functions and / or methods performed by some or all of the host controller 110, host memory 120, and any combination thereof.

[0032] The host controller 110 can manage operations that store data in the buffer area (e.g., write data) in the non-volatile memory 220 or store data in the non-volatile memory 220 (e.g., read data) in the buffer area.

[0033] Storage controller 210 may include host interface 211, memory interface 212, and processor 213. In addition, storage controller 210 may also include flash translation layer (FTL) 214, packet manager 215, buffer memory 216, ECC (Error Correction Code, 217) engine, and AES (Advanced Encryption Standard, 218) engine.

[0034] As described herein, some or all of the storage device 200, storage controller 210, and / or non-volatile memory 220, and / or any part thereof (including, but not limited to, any one of host interface 211, memory interface 212, processor 213, FTL 214, packet manager 215, buffer memory 216, ECC 217, AES 218, partial write reader 219, control logic circuitry 510, memory cell array 520, page buffer cell 550, voltage generator 530, line decoder 540, and any combination thereof) may include one or more products of a processing circuitry system (e.g., cells, instances, etc.), may be included in one or more products of a processing circuitry system (e.g., cells, instances, etc.), and / or may be implemented by one or more products of a processing circuitry system (e.g., cells, instances, etc.), such as hardware including logic circuitry, hardware / software combinations (e.g., processors executing software), or combinations thereof. For example, the processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a graphics processing unit (GPU), an application processor (AP), a digital signal processor (DSP), a microcomputer, a field-programmable gate array (FPGA), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), a neural network processor (NPU), an electronic control unit (ECU), an image signal processor (ISP), etc. The processing circuitry may also include various types of non-volatile memory (e.g., MRAM (magnetic RAM), spin-torque MRAM, bridged-conductor RAM (CBRAM), FeRAM (ferroelectric RAM), PRAM (phase RAM), resistive memory (resistive RAM)), which can implement at least a portion of the storage device 200 (including, but not limited to, non-volatile memory 220, memory controller 210, FTL 214, buffer memory 216, ECC 217, AES 218, memory cell array 520, page buffer unit 550, and any combination thereof).In some example embodiments, the processing circuitry may include a non-transitory computer-readable storage device (e.g., memory) (e.g., a solid-state drive (SSD)) and a processor (e.g., a CPU). The non-transitory computer-readable storage device stores a program of instructions, and the processor is configured to execute the program of instructions to implement functions and / or methods performed by some or all of the storage device 200 and / or any part of the storage device 200. The functions and / or methods performed by some or all of the storage device 200 and / or any part of the storage device 200 include functions and / or methods performed by some or all of the non-volatile memory 220 and / or the storage controller 210 (including, but not limited to, those performed by the host interface 211, memory interface 212, processor 213, FTL 214, packet manager 215, buffer memory 216, ECC 217, AES). 218. Partial write reader; 219. Control logic circuit; 510. Memory cell array; 520. Page buffer unit; 550. Voltage generator; 530. Line decoder; 540. And any one of any combination thereof performs functions and / or methods.

[0035] The storage controller 210 may also include working memory (not shown), a flash translation layer (FTL) 214 is loaded into the working memory, and data write and read operations of the non-volatile memory 220 can be controlled when the processor 213 executes the flash translation layer FTL 214.

[0036] The host interface 211, which can serve as a wireless or wired communication interface and / or transceiver (e.g., a wireless network communication transceiver), can send packets (e.g., data packets containing data) to and receive packets (e.g., data packets containing data) from the host device 100. Packets sent from the host device 100 to the host interface 211 may include commands, data to be written to non-volatile memory 220, etc. Packets sent from the host interface 211 to the host device 100 may include responses to commands, data read from non-volatile memory 220, etc. For example, the host interface 211 may be configured to receive write commands from the host device 100, wherein the write command includes a command for writing first data to a first address. As described herein, the "first data" may have a first size (e.g., a specific first size in bytes).

[0037] The memory interface 212 can send data to be written to the non-volatile memory 220, or receive data read from the non-volatile memory 220. Such a memory interface 212 can be implemented in accordance with standard protocols (such as Toggle or ONFI).

[0038] The flash translation layer FTL 214 performs various functions, such as address mapping, wear-leveling, and garbage collection. Address mapping is the process of changing a logical address received from the host to a physical address used to actually store data in the non-volatile memory 220. Wear-leveling is a technique used to ensure that blocks in the non-volatile memory 220 are used evenly to prevent excessive degradation of specific blocks, and can be implemented, for example, through firmware techniques used to balance the erase counts of physical blocks. Garbage collection is a technique used to ensure available capacity in the non-volatile memory 220 by copying valid data from blocks to new blocks and subsequently erasing the existing blocks.

[0039] Packet manager 215 can generate packets according to the protocol of the interface discussed with host device 100, or parse various types of information from packets received from host device 100. Furthermore, buffer memory 216 can temporarily store data to be recorded in non-volatile memory 220 or data to be read from non-volatile memory 220. Buffer memory 216 can be configured to be located inside storage controller 210, but can also be placed outside storage controller 210.

[0040] The ECC engine (ECC 217) performs error detection and correction functions on read data from non-volatile memory 220. More specifically, the ECC engine (ECC 217) generates parity bits for the write data to be written to non-volatile memory 220, and the generated parity bits are stored in non-volatile memory 220 along with the write data. When reading data from non-volatile memory 220, the ECC engine (ECC 217) uses the parity bits read from non-volatile memory 220 along with the read data to correct errors in the read data and outputs the corrected read data.

[0041] The AES engine (AES 218) can use a symmetric key algorithm to perform at least one of the encryption and decryption operations on data input to the storage controller 210.

[0042] Partial write reader 219 can determine whether a write command received from host device 100 is a partial write command (e.g., as described herein, a write command is a command to write first data to a first address of non-volatile memory 220, wherein the first data has a first size smaller than the mapped size of data stored in non-volatile memory 220). If the write command received from host device 100 is a partial write command (e.g., in response to determining that the first size of the first data to be written, as commanded by the write command, is smaller than the mapped size), partial write reader 219 can apply a read command to non-volatile memory 220 to perform a partial write. Partial write reader 219 may, in response to processing a write command and determining that the first size of the first data to be written, as commanded by the write command, is less than the mapped size, apply a read command to non-volatile memory 220. Partial write reader 219 may apply the read command to non-volatile memory 220 before the commanded first data is actually received from host device 100 at storage controller 210 (e.g., before storage controller 21 requests the commanded first data from host device 100). Conversely, if the write command received from host device 100 is not a partial write command, partial write reader 219 does not apply a read command to non-volatile memory 220 and may allow processor 213 to execute the write command.

[0043] In some example embodiments, the partial write reader 219 may be implemented in hardware and included in the storage controller 210. However, the example embodiments are not limited thereto, and the partial write reader 219 may also be implemented in software and executed by the processor 213.

[0044] The following will describe the concept of the partial write command and the specific operation of the partial write reader 219.

[0045] Figure 2 yes Figure 1 A diagram illustrating the reconfiguration of the storage controller and non-volatile memory of the storage device.

[0046] Reference Figure 2 The storage device 200 may include non-volatile memory 220 and a storage controller 210. The storage device 200 may support multiple channels CH1 to CHm, and the non-volatile memory 220 and the storage controller 210 may be connected via multiple channels CH1 to CHm. For example, the storage device 200 may be implemented as a storage device such as an SSD (Solid State Drive).

[0047] Non-volatile memory 220 may include a plurality of non-volatile memory devices NVM11 to NVMmn, where "m" and "n" may each be any positive integer. Each of the non-volatile memory devices NVM11 to NVMmn may be connected to one of a plurality of channels CH1 to CHm via a corresponding conduit (e.g., wire, conductive path, etc.). For example, non-volatile memory devices NVM11 to NVM1n may be connected to a first channel CH1 via way W11 to W1n, and non-volatile memory devices NVM21 to NVM2n may be connected to a second channel CH2 via way W21 to W2n. In some example embodiments, each of the non-volatile memory devices NVM11 to NVMmn may be implemented as an arbitrary memory cell operable according to individual instructions from memory controller 210. For example, although each of the non-volatile memory devices NVM11 to NVMmn may be implemented as a chip or a die, the inventive concept is not limited thereto.

[0048] The storage controller 210 can send signals to and receive signals from the non-volatile memory 220 via multiple channels CH1 to CHm. For example, the storage controller 210 can send commands CMDa to CMDm, addresses ADDRa to ADDRm, and data DATAa to DATAm to the non-volatile memory 220 via channels CH1 to CHm, or it can receive data DATAa to DATAm from the non-volatile memory 220.

[0049] The storage controller 210 can select one of the non-volatile memory devices connected to each channel via each channel, and can send signals to and receive signals from the selected non-volatile memory device. For example, the storage controller 210 can select non-volatile memory device NVM11 from the non-volatile memory devices NVM11 to NVM1n connected to the first channel CH1. The storage controller 210 can send command CMDa, address ADDRa, and data DATAa to the selected non-volatile memory device NVM11 via the first channel CH1, or can receive data DATAa from the selected non-volatile memory device NVM11.

[0050] The storage controller 210 can send signals to and receive signals from the non-volatile memory 220 in parallel through different channels. For example, the storage controller 210 can send command CMDb to the non-volatile memory 220 through the second channel CH2, while simultaneously sending command CMDa to the non-volatile memory 220 through the first channel CH1. For example, the storage controller 210 can receive data DATAb from the non-volatile memory 220 through the second channel CH2, while simultaneously receiving data DATAa from the non-volatile memory 220 through the first channel CH1.

[0051] The memory controller 210 controls the overall operation of the non-volatile memory 220. The memory controller 210 can send signals to channels CH1 to CHm to control each of the non-volatile memory devices NVM11 to NVM1n connected to channels CH1 to CHm. For example, the memory controller 210 can send command CMDa and address ADDRa to the first channel CH1 to control a selected non-volatile memory device among NVM11 to NVM1n.

[0052] Each of the non-volatile memory devices NVM11 to NVMmn can operate under the control of the memory controller 210. For example, non-volatile memory device NVM11 can program data DATAa according to the command CMDa, address ADDRa, and data DATAa provided to the first channel CH1. For example, non-volatile memory device NVM21 can read data DATAb according to the command CMDb and address ADDRb provided to the second channel CH2, and send the read data DATAb to the memory controller 210.

[0053] although Figure 2 The non-volatile memory 220 is shown to communicate with the memory controller 210 through m channels, and the non-volatile memory 220 includes n non-volatile memory devices corresponding to each channel, but the number of channels and the number of non-volatile memory devices connected to a channel can be changed differently.

[0054] Figure 3 yes Figure 1 A diagram showing the reconfiguration of the storage controller, memory interface, and non-volatile memory. Figure 1 The memory interface 212 may include Figure 3 The controller interface (e.g., controller interface circuit) 212a.

[0055] The non-volatile memory 220 may include first pins P11 to eighth pins P18, a memory interface (e.g., memory interface circuitry) 212b, control logic (e.g., control logic circuitry) 510, and a memory cell array 520.

[0056] The memory interface circuit 212b can receive the chip enable signal nCE from the memory controller 210 via the first pin P11. The memory interface circuit 212b can send signals to and receive signals from the memory controller 210 via the second pin P12 to the eighth pin P18 based on the chip enable signal nCE. For example, when the chip enable signal nCE is in an enabled state (e.g., low level), the memory interface circuit 212b can send signals to and receive signals from the memory controller 210 via the second pin P12 to the eighth pin P18.

[0057] The memory interface circuit 212b can receive the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal nWE from the memory controller 210 via pins P12 to P14. The memory interface circuit 212b can receive or send the data signal DQ from the memory controller 210 via pin P17. Command CMD, address ADDR, and data DATA can be transmitted via the data signal DQ. For example, the data signal DQ can be transmitted via multiple data signal lines. In this case, pin P17 may include multiple pins corresponding to the multiple data signals.

[0058] The memory interface circuit 212b can acquire the command CMD from the data signal DQ received in the enable portion (e.g., high state) of the command latch enable signal CLE based on the switching timing of the write enable signal nWE. The memory interface circuit 212b can also acquire the address ADDR from the data signal DQ received in the enable portion (e.g., high state) of the address latch enable signal ALE based on the switching timing of the write enable signal nWE.

[0059] In some example embodiments, the write enable signal nWE remains static (e.g., high or low) and can subsequently toggle between high and low. For example, the write enable signal nWE may be toggled at the portion where command CMD or address ADDR is sent. Therefore, the memory interface circuitry 212b can acquire command CMD or address ADDR based on the toggling timing of the write enable signal nWE.

[0060] The memory interface circuit 212b can receive the read enable signal nRE from the memory controller 210 via pin 5 P15. The memory interface circuit 212b can receive the data strobe signal DQS from the memory controller 210 via pin 6 P16, or it can send the data strobe signal DQS to the memory controller 210.

[0061] In the data DATA output operation of the non-volatile memory 220, the memory interface circuit 212b can receive a switched read enable signal nRE via pin 5 P15 before outputting the data DATA. The memory interface circuit 212b can generate a switched data strobe signal DQS based on the switching of the read enable signal nRE. For example, the memory interface circuit 212b can generate a data strobe signal DQS that starts switching after a predetermined delay (e.g., tDQSRE) based on the switching start time of the read enable signal nRE. The memory interface circuit 212b can send a data signal DQ including the data DATA based on the switching timing of the data strobe signal DQS. Therefore, the data DATA can be arranged and sent to the memory controller 210 at the switching timing of the data strobe signal DQS.

[0062] In the data input operation of the non-volatile memory 220, when the data signal DQ including the data DATA is received from the memory controller 210, the memory interface circuit 212b can receive the switched data strobe signal DQS and the data DATA together from the memory controller 210. The memory interface circuit 212b can obtain the data DATA from the data signal DQ based on the switching timing of the data strobe signal DQS. For example, the memory interface circuit 212b can obtain the data DATA by sampling the data signal DQ at the rising and falling edges of the data strobe signal DQS.

[0063] The memory interface circuit 212b can send a ready / busy output signal nR / B to the memory controller 210 via pin 8 P18. The memory interface circuit 212b can also send the status information of the non-volatile memory 220 to the memory controller 210 via the ready / busy output signal nR / B. When the non-volatile memory 220 is in a busy state (i.e., when internal operations of the non-volatile memory 220 are being executed), the memory interface circuit 212b can send the ready / busy output signal nR / B indicating the busy state to the memory controller 210. When the non-volatile memory 220 is in a ready state (i.e., when internal operations of the non-volatile memory 220 have been completed or not executed), the memory interface circuit 212b can send the ready / busy output signal nR / B indicating the ready state to the memory controller 210.

[0064] For example, when the non-volatile memory 220 reads data DATA from the memory cell array 520 in response to a page read command, the memory interface circuit 212b can send a ready / busy output signal nR / B indicating a busy state (e.g., low level) to the memory controller 210. Similarly, when the non-volatile memory 220 programs data DATA into the memory cell array 520 in response to a programming instruction, the memory interface circuit 212b can send a ready / busy output signal nR / B indicating a busy state to the memory controller 210.

[0065] Control logic circuit 510 typically controls various operations of non-volatile memory 220. Control logic circuit 510 can receive commands / addresses (CMD / ADDR) obtained from memory interface circuit 212b. Control logic circuit 510 can generate control signals for controlling other components of non-volatile memory 220 based on the received commands / addresses (CMD / ADDR). For example, control logic circuit 510 can generate various control signals for programming data DATA into or reading data DATA from memory cell array 520.

[0066] The memory cell array 520 can store data DATA obtained from the memory interface circuit 212b under the control of the control logic circuit 510. The memory cell array 520 can also output the stored data DATA to the memory interface circuit 212b under the control of the control logic circuit 510.

[0067] The memory cell array 520 may include a plurality of memory cells. For example, the plurality of memory cells may be flash memory cells. However, the inventive concept is not limited thereto, and the memory cells may be RRAM (resistive random access memory) cells, FRAM (ferroelectric random access memory) cells, PRAM (phase-change random access memory) cells, TRAM (thyristor random access memory) cells, and MRAM (magnetic random access memory) cells. Hereinafter, embodiments of the inventive concept will be described focusing on some exemplary embodiments in which the memory cells are NAND flash memory cells.

[0068] The storage controller 210 may include first pins P21 to eighth pins P28 and controller interface circuitry 212a. First pins P21 to eighth pins P28 may correspond to first pins P11 to eighth pins P18 of the non-volatile memory 220.

[0069] The controller interface circuit 212a can send the chip enable signal nCE to the non-volatile memory 220 via the first pin P21. The controller interface circuit 212a can send signals to and receive signals from the non-volatile memory 220 via the second pin P22 to the eighth pin P28, which is selected by the chip enable signal nCE.

[0070] The controller interface circuit 212a can send the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal nWE to the non-volatile memory 220 via pins P22 to P24. The controller interface circuit 212a can send the data signal DQ to the non-volatile memory 220 or receive the data signal DQ from the non-volatile memory 220 via pin P27.

[0071] The controller interface circuit 212a can send the data signal DQ, including the command CMD or address ADDR, together with the switching write enable signal nWE to the non-volatile memory 220. The controller interface circuit 212a can send the data signal DQ, including the command CMD, to the non-volatile memory 220 by sending the command latch enable signal CLE with an enabled state, and can send the data signal DQ, including the address ADDR, to the non-volatile memory 220 by sending the address latch enable signal ALE with an enabled state.

[0072] The controller interface circuit 212a can send the read enable signal nRE to the non-volatile memory 220 via the fifth pin P25. The controller interface circuit 212a can receive the data strobe signal DQS from the non-volatile memory 220 via the sixth pin P26, or it can send the data strobe signal DQS to the non-volatile memory 220.

[0073] In the data DATA output operation of the non-volatile memory 220, the controller interface circuit 212a can generate a switching read enable signal nRE and send the read enable signal nRE to the non-volatile memory 220. For example, the controller interface circuit 212a can generate a read enable signal nRE that changes from a quiescent state (e.g., high or low level) to a switching state before the data DATA is output. Therefore, the switching data strobe signal DQS can be generated based on the read enable signal nRE in the non-volatile memory 220. The controller interface circuit 212a can receive a data signal DQ including the data DATA and the switching data strobe signal DQS from the non-volatile memory 220. The controller interface circuit 212a can obtain the data DATA from the data signal DQ based on the switching timing of the data strobe signal DQS.

[0074] During the data input operation of the non-volatile memory 220, the controller interface circuit 212a can generate a switching data strobe signal DQS. For example, the controller interface circuit 212a can generate a data strobe signal DQS that changes from a quiescent state (e.g., high or low level) to a switching state before transmitting the data DATA. The controller interface circuit 212a can send a data signal DQ including the data DATA to the non-volatile memory 220 based on the switching timing of the data strobe signal DQS.

[0075] The controller interface circuit 212a can receive the ready / busy output signal nR / B from the non-volatile memory 220 via pin 8 P28. The controller interface circuit 212a can identify the status information of the non-volatile memory 220 based on the ready / busy output signal nR / B.

[0076] Figure 4 It is shown Figure 3 Example block diagram of non-volatile memory.

[0077] Reference Figure 4 The non-volatile memory 220 may include control logic circuitry 510, a memory cell array 520, a page buffer unit 550, a voltage generator 530, and a line decoder 540. Although not explicitly stated... Figure 4 As shown, but the non-volatile memory 220 may also include Figure 3 The memory interface circuit 212b shown herein may also include column logic, a pre-decoder, a temperature sensor, a command decoder, an address decoder, etc., any one or all of which may be included in, included in, or implemented by one or more products of the processing circuit system described herein.

[0078] The control logic circuit 510 typically controls various operations within the non-volatile memory 220. The control logic circuit 510 can respond to inputs from the memory interface circuitry (…). Figure 3 The control logic circuit 510 can output various control signals by responding to the commands CMD and / or address ADDR of 212b). For example, the control logic circuit 510 can output the voltage control signal CTRL_vol, the row address X-ADDR, and the column address Y-ADDR.

[0079] The memory cell array 520 may include multiple memory blocks BLK1 to BLKz (z is a positive integer), and each of the multiple memory blocks BLK1 to BLKz may include multiple memory cells. The memory cell array 520 can be connected to the page buffer unit 550 via bit line BL, and can be connected to the line decoder 540 via word line WL, serial select line SSL, and ground select line GSL.

[0080] In some example embodiments, the memory cell array 520 may include a three-dimensional memory cell array, and the three-dimensional memory cell array may include a plurality of NAND strings. Each NAND string may include memory cells connected to word lines vertically stacked on a substrate. U.S. Patent Nos. 7,679,133, 8,553,466, 8,654,587, 8,559,235, and 2011 / 0233648 are incorporated herein by reference. In some example embodiments, the memory cell array 520 may include a two-dimensional memory cell array, and the two-dimensional memory cell array may include a plurality of NAND strings arranged along row and column directions.

[0081] Page buffer unit 550 may include multiple page buffers PB1 to PBn (n is an integer of three or greater), and each of the multiple page buffers PB1 to PBn may be connected to a memory cell via multiple bit lines BL. Page buffer unit 550 may select at least one bit line among the bit lines BL in response to column address Y-ADDR. Depending on the operating mode, page buffer unit 550 may operate as an entry driver or a sense amplifier. For example, during a programming operation, page buffer unit 550 may apply a bit line voltage corresponding to the data to be programmed to the selected bit line. During a read operation, page buffer unit 550 may detect the current or voltage of the selected bit line and detect the data stored in the memory cell.

[0082] Voltage generator 530 can generate various types of voltages for performing programming, reading, and erasing operations based on the voltage control signal CTRL_vol. For example, voltage generator 530 can generate programming voltage, reading voltage, programming verification voltage, erasing voltage, etc., as word line voltage VWL.

[0083] The row decoder 540 can select one of multiple word lines WL and one of multiple string select lines SSL in response to the row address X-ADDR. For example, the row decoder 540 can apply a programming voltage and a programming verification voltage to the selected word line during a programming operation, and can apply a read voltage to the selected word line during a read operation.

[0084] Figure 5This is a diagram illustrating a 3D V-NAND structure applicable to non-volatile memory according to some example embodiments. When the memory module of the storage device is implemented as a 3D V-NAND type flash memory, each of the plurality of memory blocks constituting the memory module can be configured as follows: Figure 5 The equivalent circuit representation is shown in the figure.

[0085] Figure 5 The memory block BLKi shown illustrates a three-dimensional memory block formed in a three-dimensional structure on a substrate. For example, multiple NAND strings included in the memory block BLKi may be formed in a direction perpendicular to the substrate (e.g., the Z-axis direction). In some example embodiments, the X-axis and Y-axis directions are parallel to the substrate and perpendicular to each other.

[0086] Reference Figure 5 The memory block BLKi may include multiple memory NAND strings NS11 to NS33 connected between bit lines BL1, BL2, and BL3 and the common-source line CSL. Each of the multiple memory NAND strings NS11 to NS33 may each include a string select transistor SST, multiple memory cells MC1, MC2, ..., and MC8, and a ground select transistor GST. Although Figure 7 Each of the multiple memory NAND strings NS11 to NS33 is shown to include eight memory cells MC1, MC2, ..., MC8, but the example embodiment is not necessarily limited thereto.

[0087] The string select transistor SST can be connected to the corresponding string select lines SSL1, SSL2, and SSL3. Multiple memory cells MC1, MC2, ..., MC8 can each be connected to their corresponding gate lines GTL1, GTL2, ..., and GTL8. Gate lines GTL1, GTL2, ..., GTL8 can correspond to word lines, and some of these gate lines can correspond to dummy word lines. The ground select transistor GST can be connected to the corresponding ground select lines GSL1, GSL2, and GSL3. The string select transistor SST can be connected to the corresponding bit lines BL1, BL2, and BL3, and the ground select transistor GST can be connected to the common-source line CSL.

[0088] Word lines of the same height (e.g., WL1) are connected together, and ground select lines GSL1, GSL2, and GSL3 can be separated from string select lines SSL1, SSL2, and SSL3. Although Figure 9 The example shows that the memory block BLK is connected to eight gate lines GTL1, GTL2, ..., and GTL8, and three bit lines BL1, BL2, and BL3, but the example embodiment is not limited to this.

[0089] Figure 6 yes Figure 1 A block diagram of the processor.

[0090] Reference Figure 1 and Figure 6 The processor 213 (e.g., a product of at least a processing circuit system implementing the processor 213) may include a first processor (e.g., processor 1) 213a and a second processor (e.g., processor 2) 213b. The first processor 213a and the second processor 213b may be implemented by a separate product of the processing circuit system (e.g., a separate CPU), or may be implemented by a single product of the processing circuit system.

[0091] In response to a write command being provided (e.g., sent) from host device 100 and received from host device 100 at storage controller 210, first processor 213a may request and receive data (e.g., first data as described herein) from host device 100 to perform a write operation. Furthermore, first processor 213a may store the data received from host device 100 (e.g., first data as described herein) in buffer memory 216 (e.g., in response to receiving first data from host device 100). In some example embodiments, first processor 213a may include, but is not limited to, a host core.

[0092] The second processor 213b can write data stored in buffer memory 216 (e.g., the first data and the third data as described herein) to non-volatile memory 220 to execute write commands received from host device 100. In some example embodiments, the second processor 213b may include, but is not limited to, a flash memory core.

[0093] Figure 7 Based on some example embodiments Figure 1 A block diagram of the partial write to the reader. Figure 8 and Figure 9 This is for illustrating some example embodiments. Figure 7 A diagram illustrating the functionality of the command allocator.

[0094] Reference Figure 1 and Figure 7 Partial write reader 219 may include command allocator 219a and unloading engine 219b.

[0095] Command allocator 219a can determine whether a write command received from host device 100 is a partial write command. Here, a partial write command refers to a write command for data smaller than a storage unit (mapped size unit, also referred to as the mapped size) of non-volatile memory 220. As described herein, non-volatile memory 220 can be configured to store data written in units of size, which have a size corresponding to a specific mapped size unit (e.g., four write units WU and a mapped size unit of 4096 bytes) (e.g., a size that is a specific mapped size unit or an integer multiple of a specific mapped size unit). For example, non-volatile memory 220 can be configured to store data written in units of the mapped size (e.g., written in a size that is the mapped size or an integer multiple of the mapped size). As described herein, the host interface 211 of the storage controller 210 receives a write command from the host device 100, wherein the write command includes a command for writing first data to a first address, and the first data has a first size smaller than the mapped size when data stored in the non-volatile memory 220 is written, and the write command may be referred to as a partial write command.

[0096] For example, refer to Figure 8 When the non-volatile memory 220 stores data in four write units WU (where a write unit WU is a specific unit of data size or quantity), the mapped size of the data stored by the non-volatile memory 220 can be equal to four write units WU. If a write command with a size of four write units WU (e.g., a write command for writing data with a size of four write units WU) is applied from the host device 100, this is not a partial write command.

[0097] For example, when a write unit WU is 1024 bytes, the non-volatile memory 220 stores data in units of 4096 bytes (mapped size), e.g., size units, and if a write command is applied from the host device 100 to write data with a size of 4096 bytes (e.g., data size) (e.g., the data to be written has a size of 4096 bytes), this is not a partial write command. Here, although the mapped size of the non-volatile memory 220 is shown as 4096 bytes as an example, this is only an example, and the example embodiment is not limited to this. The mapped size of the non-volatile memory 220 can be modified to 1024 bytes, 2048 bytes, 8192 bytes, etc.

[0098] In this manner, when a write command to write data of the same size as the mapped size of the non-volatile memory 220 is received from the host device 100, the storage controller 210 may write the data provided (e.g., sent) from the host device 100 to the non-volatile memory 220 as is (e.g., not divided into two separate data entries, not combined with other data, etc.). It will be understood that the storage controller 210 is therefore configured to provide (e.g., send) commands to the non-volatile memory 220. It will be understood that, as described herein, providing commands, data, etc., to the device can be interchangeably referred to as sending commands, data, etc., to the device.

[0099] Incidentally, refer to Figure 9 When a write command having a size of one, two, or three write units WU (e.g., a write command for writing data having a size of one, two, or three write units WU) is applied from the host device 100, this is a partial write command.

[0100] In other words, when a write command of size 1024 bytes (e.g., a write command to write data of size 1024 bytes) is applied from host device 100, a write command of size 2048 bytes (e.g., a write command to write data of size 2048 bytes) is applied, or a write command of size 3072 bytes (e.g., a write command to write data of size 3072 bytes) is applied, this is a partial write command.

[0101] Reference Figure 1 , Figure 6 and Figure 7 Command allocator 219a determines whether a write command received from host device 100 is a partial write command that requires writing data with a size smaller than the mapped size of non-volatile memory 220. For example, command allocator 219a may determine whether the first size of first data being written to a first address of non-volatile memory 220 by the write command is smaller than the mapped size, where the data is stored at the mapped size in non-volatile memory 220.

[0102] If the write command is not a partial write command, then the command allocator 219a will only issue a command for requesting data from the host device 100 to the first processor 213a to receive data from the host device 100.

[0103] In some example embodiments, if the write command is a partial write command (e.g., the first data to be written, as commanded by the write command, has a first size smaller than the mapped size), then command allocator 219a issues a command to request data from host device 100 to first processor 213a to receive data from host device 100, and issues a command to read data required for partial write to offload engine 219b. Therefore, command allocator 219a can be understood as determining whether the "first size" of the first data to be written, as commanded by the write command, is smaller than the mapped size of non-volatile memory 220, and offload engine 219b can be understood as being configured to selectively provide (e.g., send) read commands to non-volatile memory 220 based on the determined output of whether the first size is smaller than the mapped size. A more specific description thereof will be provided below.

[0104] Reference Figure 1 and Figure 7 The unloading engine 219b may include an address converter 219c and a flash manager 219d.

[0105] Address translator 219c can, for example, search for the physical address of non-volatile memory 220 corresponding to a logical address received from host device 100 by referring to a mapping table stored in FTL 214. FTL can be configured to store a mapping table in which the physical address of non-volatile memory 220 (e.g., a second address) is stored, where the second address corresponds to a logical address (e.g., a first address, to which first data to be written is commanded to be written by a write command from host device 100). Address translator 219c can search for the "second address" based on the mapping table stored in FTL 214.

[0106] The flash memory manager 219d can apply a read command to the non-volatile memory 220, which reads data addressed to a physical address searched from the address converter 219c. The flash memory manager 219d can provide (e.g., send) a read command to the non-volatile memory 220 using a second address that has already been searched (e.g., send a read command provided by the partial write reader 219 in response to determining that a first size of the first data to be written, as ordered by the write command, is smaller than the mapped size of the non-volatile memory 220).

[0107] In some example embodiments, such a flash memory manager 219d is implemented separately from the processor 213, and read commands can be applied to the non-volatile memory 220 without using the processor 213. That is, in some example embodiments, the flash memory manager 219d and the processor 213 can apply read commands to the non-volatile memory 220 independently of each other.

[0108] In the following text, reference will be made to Figure 10 and Figure 11 The operation of storage device 200 will be described in more detail. It will be understood that any operation as described herein (including, but not limited to, any operation according to any of the accompanying drawings) may be performed by any part of memory system 10 according to any example embodiment, any part of memory system 10 according to any example embodiment including any part of memory controller 210 according to any example embodiment (and including any processing circuitry system that implements any part of memory controller 210).

[0109] Figure 10 and Figure 11 This is a diagram illustrating the operation of a storage device according to some example embodiments.

[0110] Reference Figure 1 , Figure 10 and Figure 11 The storage controller 210 receives a write command from the host device 100 (S100). The write command may be a command to write first data of a first size to a first address (e.g., a logical address) of the non-volatile memory 220.

[0111] Write commands provided (e.g., sent) from host device 100 may be provided (e.g., sent) to command distributor 219a of storage controller 210.

[0112] The command distributor 219a of the storage controller 210 determines whether the write command received from the host device 100 is a partial write command (S110) (for example, determining whether the first size of the first data to be written as commanded by the write command is less than the mapped size of the non-volatile memory 220).

[0113] In some example embodiments, in response to determining that the first size of the first data to be written, as commanded by the write command, is the same size as the mapped size of the non-volatile memory 220 (e.g., having a size equal to the mapped size of the non-volatile memory 220), as further described below, the storage controller 210 may selectively refrain from providing (e.g., sending) read commands to the non-volatile memory 220. For example, if the write command received from the host device 100 is not a partial write command, the command allocator 219a issues a command requesting data from the host device 100 for the write operation to the non-volatile memory 220 to the first processor 213a, and in this case, the offloading engine 219b does not operate.

[0114] In the following text, an example will be described where the mapped size of the non-volatile memory 220 is four write units WU, but a write command received from the host device 100 is issued to write "a" corresponding to one write unit WU (and thus has a first size smaller than the mapped size).

[0115] If the write command received from the host device 100 is a partial write command (e.g., in response to determining at the storage controller 210 that the first data to be written, as ordered by the write command, has a first size smaller than the mapped size of the non-volatile memory 220), then the command allocator 219a issues a command for reading data required for partial writing to the unloading engine 219b (S112). If the write command is not a partial write command, then the command allocator 219a selectively restricts issuing such commands to the unloading engine 219b.

[0116] The address converter 219c of the unloading engine 219b searches for the physical address (e.g., the second address) of the non-volatile memory 220 based on (e.g., according to) the logical address (e.g., the first address) received by the write command (S114).

[0117] For example, when a write command (e.g., a first address) received from host device 100 issues a command for writing data a (e.g., first data) to logical address L1, the address converter 219c of unloading engine 219b searches for the physical address P1 (e.g., a second address) of non-volatile memory 220 corresponding to logical address L1 based on reference mapping table (e.g., L2P) 214a.

[0118] In some example embodiments, the read command of S120 may include a command to read second data addressed to a second address stored in non-volatile memory 220. The second data may have a size equal to the mapping size. The read command may be provided (e.g., sent) to non-volatile memory 220 via memory interface 212 of memory controller 210. In some example embodiments, although mapping table 214a may be included in FTL 214, the example embodiments are not limited thereto.

[0119] The flash memory manager 219d of the unloading engine 219b applies a read command to the non-volatile memory 220 (S120), which is a command to read data (e.g., second data) addressed to physical address P1.

[0120] As described above, in some example embodiments, the flash memory manager 219d applies read commands to the non-volatile memory 220 without using a second processor 213b that performs the function of applying commands to the non-volatile memory 220 in the processor 213.

[0121] In some example embodiments, if the write command received from the host device 100 is a partial write command, the command allocator 219a issues a command to the first processor 213a for requesting data from the host device 100 for the write operation to the non-volatile memory 220 (S122).

[0122] Storage controller 210 may provide (e.g., send) a read command to non-volatile memory 220 in S120, and subsequently, after the read command is provided (e.g., sent) to non-volatile memory in S120, send a request signal to host device in S130 to request first data. In S130, storage controller 210 may send the request signal to host device 100 to request first data (e.g., data a) from host device 100, wherein the request signal can be sent via host interface 211. For example, in some example embodiments, in response to providing (e.g., sending) a read command, first processor 213a requests data (e.g., first data) from host device 100 (S130) and receives data a (e.g., first data) from host device 100 (S140). The first processor 213a, having received data a, stores data a (e.g., first data) in data buffer 216a (which may be included in buffer memory 216). In addition, the first processor 213a notifies the second processor 213b that data a has been received.

[0123] Therefore, as Figures 10 to 11 As shown, when a write command, including a command to write data of a first size to a logical address (e.g., a first address) of the non-volatile memory 220, is received from the host device 100 at the storage controller 210 in S100, in S120, the storage controller 210 may, in response to determining in S110 that the first size of the first data is less than the mapped size of the non-volatile memory 220, provide (e.g., send) a read command to the non-volatile memory 220 (e.g., send to the non-volatile memory 220) to cause the non-volatile memory 220 to read the second data stored in the non-volatile memory 220 based on the first address. Figure 10 As further shown, a read command can be provided (e.g., sent) to the non-volatile memory 220 in S120 before the first data is actually received at the memory controller 210 in S140.

[0124] In some example embodiments, although the data buffer 216a may be included in the buffer memory 216, the example embodiments are not limited thereto, and the data buffer 216a may also be placed outside the storage controller 210.

[0125] In response to a read command applied from flash memory manager 219d, data d, e, f, and g (e.g., second data) are read from non-volatile memory 220 (S150). The data d, e, f, and g read from non-volatile memory 220 and thus received at memory controller 210 can be stored in buffer memory 216. Here, as described above, the existence of four data items is due to the fact that the mapped size of non-volatile memory 220 is four write units WU. Therefore, in S120, in response to the read command, the second data being read can have a second size equal to the mapped size of non-volatile memory 220. In some example embodiments, non-volatile memory 220 can be accessed via the above reference... Figure 3 The described data input / output operations provide (e.g., send) data d, e, f, and g to storage controller 210.

[0126] Data d, e, f, and g are read and stored in data buffer 216a via flash memory manager 219d. At this time, by referring to the sector bitmap, flash memory manager 219d does not store all read data d, e, f, and g in data buffer 216a, but only data e, f, and g in data buffer 216a.

[0127] In some example embodiments, only a limited portion of the received second data (e.g., data e, f, g) may be stored in data buffer 216a (which may be included in buffer memory 216). The limited portion of the received second data stored in data buffer 216a may be selected to have a size equal to the difference between the mapping size and a first size of the first data (e.g., data a), such that the sum of the first size and the size of the limited portion of the second data stored in data buffer 216a is equal to the mapping size. Data e, f, and g can be third data stored in data buffer 216a, wherein the third data (data e, f, g) is a finite portion of the second data (data d, e, f, g), the finite portion of the second data (data d, e, f, g) excluding the separate portion of the second data read having a size equal to the first size (e.g., excluding data d having the same size as data a), such that the third data (e.g., data e, f, g) has a third size (e.g., three write units WU), the third size being equal to the difference between the mapped size (e.g., four write units WU) and the first size (e.g., one write unit WU).

[0128] For example, in some example embodiments, the flash memory manager 219d identifies one of the four write units WU of the data buffer 216a as an area where data a received from the host device 100 is stored via a sector bitmap, and stores data e, f, and g only in the remaining three write units WU.

[0129] Through this processing, data used to execute partial write commands received from host device 100 without overwrite or data copying is stored in data buffer 216a. For example, at least... Figure 11 As shown, data buffer 216a (which may be included in buffer memory 216) may be configured to store data in units of the mapped size (e.g., four write units WU), and only some of the second data and the first data (e.g., data a and a finite portion of data d, e, f and g including data e, f and g but excluding data d) may be stored in data buffer 216a to correspond to the mapped size (e.g., the stored data a, e, f and g have a combined size of four write units WU equal to the mapped size).

[0130] The second processor 213b checks whether the flash memory manager 219d is ready to perform partial write operations (S155), and when the data preparation is complete, the second processor 213b issues a write command (S160) to write data a, e, f, and g to the address P2 of the non-volatile memory 220. In some example embodiments, the storage controller 210 can be referenced above. Figure 3 The described data input / output operation provides (e.g., sends) data a, e, f, and g to non-volatile memory 220.

[0131] In this way, when data a, e, f, and g are written to the address P2 of the non-volatile memory 220, the physical address corresponding to the logical address L1 can be updated from P1 to P2 in the mapping table 214a.

[0132] Figure 12 This is a diagram used to illustrate the effect of a storage device according to some example embodiments. Figure 12 A represents the part of the write reader not described above. Figure 1 The storage controller of 219) Figure 1 A diagram illustrating the partial write operation of (210), B is an illustration of the partial write reader (including the one described above). Figure 1 The storage controller of 219) Figure 1 A diagram illustrating the partial write operation of (210).

[0133] First, refer to Figure 12In case A, the storage controller receives partial write commands (S1, e.g., RPWC) and requests and accepts partial write data from the host device. Figure 11 (S2, e.g., RDH). Furthermore, the storage controller reads data stored in the non-volatile memory (S3) and updates the data buffer with the read data (S4, e.g., BU). Thereafter, the storage controller performs a partial write operation on the non-volatile memory (S5).

[0134] However, refer to Figure 12 Following the write command received by the storage controller (S11), the read operation of the data stored in the non-volatile memory is immediately executed (S13). Furthermore, data is written from the request and receive section of the host device. Figure 11 Operation (S12) is performed independently and in parallel with the data read operation (S13) stored in the non-volatile memory. Therefore, the start time of the partial write operation (S15) performed on the non-volatile memory is significantly shortened, and the completion time of the partial write operation (S15) is also shortened. Thus, the speed of partial write operations on the storage device can be improved, and the operational performance of the storage device can be enhanced.

[0135] Figure 13 These are diagrams illustrating the operation of a storage device according to some example embodiments. In the following, repeated descriptions of the example embodiments described above will not be provided, and the differences will be primarily described.

[0136] In some example embodiments, in S140, before the storage controller 210 receives the first data in S150, the second data may be received from the non-volatile memory 220. For example, refer to... Figure 13 In some example embodiments, when receiving read data from non-volatile memory 220 ( Figure 10 After (d, e, f, and g) (S140), data is received from the host device 100. Figure 10 (a)(S150).

[0137] In this case, data e, f, and g are first stored in data buffer 216a, and data a can be stored later.

[0138] Figure 14 and Figure 15 This is a diagram illustrating the operation of a storage device according to some example embodiments.

[0139] Reference Figure 14 and Figure 15 The storage controller 210 receives a write command from the host device 100 (S200).

[0140] Write commands provided (e.g., sent) from host device 100 may be provided (e.g., sent) to command distributor 219a of storage controller 210.

[0141] The command distributor 219a of the storage controller 210 determines whether the write command received from the host device 100 is a partial write command (S210).

[0142] If the write command received from the host device 100 is a partial write command, the command allocator 219a issues the command for reading data needed for the partial write to the unloading engine 219b (S212), and at the same time issues the command for the data requested from the host device 100 for the write operation to the non-volatile memory 220 to the first processor 213a (S222).

[0143] In response, the first processor 213a requests data from the host device 100 (S220), and the address converter 219c of the offloading engine 219b searches for the physical address of the non-volatile memory 220 based on the logical address received by the write command (S214).

[0144] Therefore, the data request (S220) sent from the storage controller 210 to the host device 100 can be executed before the read command application operation (S230) provided (e.g., sent) from the storage controller 210 to the non-volatile memory 220.

[0145] The subsequent operations—including the read command application operation (S230), the operation of receiving data a from the host device 100 (S240), the operation of reading data d, e, f, and g from the non-volatile memory 220 in response to the read command applied from the flash memory manager 219d (S250), the operation of checking whether the second processor 213b is ready to execute the partial writing of data to the flash memory manager 219d (S255), and the operation of issuing write commands to the non-volatile memory 220 for writing data a, e, f, and g—are the same as in the embodiments described above. Therefore, repeated descriptions will not be provided.

[0146] Such as at least Figures 14 to 15As shown, the storage controller 210 may send a request signal (e.g., via host interface 211) in S220 to request first data, and then, after the request signal is sent in S220, provide (e.g., send) a read command to the non-volatile memory 220 in S230 (e.g., via memory interface 212), and the storage controller 210 may receive the first data in S240 after the read command is provided (e.g., sent) to the non-volatile memory 220 in S230. Therefore, the storage controller 210 may send the request signal in S220 before providing (e.g., sending) the read command to the non-volatile memory 220 in S230. As at least... Figures 14 to 15 As further shown, before the storage controller 210 receives the second data from the non-volatile memory in S250, the storage controller 210 may receive the first data from the host device 100 in S240.

[0147] Figure 16 These are diagrams illustrating the operation of a storage device according to some example embodiments. In the following, repeated descriptions of the example embodiments described above will not be provided, and the differences will be primarily described.

[0148] In some example embodiments, the storage controller 210 may receive second data (e.g., data d, e, f, and g) from the non-volatile memory 220 before receiving first data (e.g., data a) from the host device 100. For example, refer to... Figure 16 In some example embodiments, when receiving read data from non-volatile memory 220 ( Figure 15 After (d, e, f, and g) (S240), data is received from the host device 100. Figure 15 a)(S250).

[0149] In this case, data e, f, and g are first stored in data buffer 216a, and data a can be stored later.

[0150] In concluding with the detailed description, those skilled in the art will understand that many variations and modifications can be made to the preferred embodiments without substantially departing from the principles of the inventive concept. Therefore, the preferred embodiments disclosed in the inventive concept are used only in a general and descriptive sense and not for limiting purposes.

Claims

1. A storage device, comprising: Non-volatile memory, configured to store data written in units of mapped size; as well as The storage controller is configured to send commands to non-volatile memory. The storage controller includes: The host interface is configured to receive write commands from a host device, the write commands including commands for writing first data to a first address, the first data having a first size smaller than the mapped size, and The processing circuitry is configured to: in response to determining that a first size is less than a mapped size and before the first data is received at the storage controller via the host interface, send a read command to the non-volatile memory to cause the non-volatile memory to read second data stored in the non-volatile memory, addressed to the first address. The storage device further includes a buffer memory, and The processing circuit system is configured as follows: Requesting and receiving first data from the host device. In response to receiving the first data from the host device, the first data is stored in the buffer memory. Second data is read from non-volatile memory in units equal to the mapped size, such that the second data has a second size equal to the mapped size, and The third data is stored in a buffer memory. The third data is a finite portion of the second data that is read, such that the third data has a third size equal to the difference between the mapped size and the first size. The finite portion of the second data read does not include the separate portion of the second data that has a size equal to the first size.

2. The storage device according to claim 1, wherein, The processing circuit system is configured as follows: Determine if the first size is less than the mapped size, and Based on the determined output of whether the first size is less than the mapped size, read commands are selectively sent to non-volatile memory.

3. The storage device according to claim 2, wherein, The processing circuitry is configured as a memory-mapped table, where a second address of the non-volatile memory is stored, corresponding to the first address. The processing circuit system is configured as follows: Searching for the second address based on the reference mapping table, and The read command is sent to the non-volatile memory using the second address that has already been searched.

4. The storage device according to claim 1, wherein, The processing circuit system includes: A first processor is configured to: request and receive first data from a host device, and subsequently store the first data in a buffer memory, and The second processor is configured to write the first and third data stored in the buffer memory into the non-volatile memory.

5. The storage device according to any one of claims 1 to 4, in, The buffer memory is configured to store data in units of the mapped size, and Some of the second data and the first data are stored in a buffer memory to correspond to the mapping size.

6. A storage device, comprising: Non-volatile memory, configured to store data written in units of mapped size; as well as The storage controller is configured to send commands to non-volatile memory. The storage controller includes: The host interface is configured to receive write commands from a host device, the write commands including commands for writing first data to a first address, the first data having a first size smaller than the mapped size. The memory interface is configured to send a memory command corresponding to a write command to non-volatile memory, and The processing circuitry is configured to: in response to determining that the first size is less than the mapped size and before the first data is received via the host interface, send a read command to the non-volatile memory, causing the non-volatile memory to read the second data stored in the non-volatile memory based on the first address via the memory interface. The storage device further includes: a buffer memory, and The processing circuit system is configured as follows: Requesting and receiving first data from the host device, In response to receiving the first data from the host device, the first data is stored in the buffer memory. Second data is read from non-volatile memory in units equal to the mapped size, such that the second data has a second size equal to the mapped size, and The third data is stored in a buffer memory. The third data is a finite portion of the second data that is read, such that the third data has a third size equal to the difference between the mapped size and the first size. The finite portion of the second data read does not include the separate portion of the second data that has a size equal to the first size.

7. The storage device according to claim 6, wherein, The processing circuit system is configured as follows: Send read commands to non-volatile memory via the memory interface; and The request signal is sent to the host device via the host interface to request the first data.

8. The storage device according to claim 7, wherein, The processing circuitry is configured to receive second data from a non-volatile memory before receiving first data from the host device.

9. The storage device according to claim 6, wherein, The processing circuitry is configured to send a request signal to the host device via the host interface to request first data before providing a read command to the non-volatile memory via the memory interface.

10. The storage device according to claim 9, wherein, The processing circuitry is configured to receive second data from a non-volatile memory before receiving first data from the host device.

11. A method for operating a storage device, the method comprising: Provides non-volatile memory and a memory controller, data is written to the non-volatile memory in mapped-size units, and the memory controller is configured to send memory commands to the non-volatile memory; Receive a write command at the storage controller, the write command including a command for writing a first amount of first data to a first address; Before the first data is received at the storage controller, in response to determining that the first size is less than the mapped size, a read command is sent to the non-volatile memory to cause the non-volatile memory to read the second data stored in the non-volatile memory based on the first address; The storage controller receives second data from the non-volatile memory, the second data having a size equal to the mapped size; This causes the storage controller to store the first data in the buffer memory; as well as The storage controller stores a finite portion of the received second data in a buffer memory such that the finite portion of the received second data has a size equal to the difference between the mapped size and the first size, and the finite portion of the received second data does not include a separate portion of the received second data having a size equal to the first size.

12. The method for operating a storage device according to claim 11, further comprising: In response to determining that the first size is the same as the mapped size, the storage controller selectively restricts the sending of read commands to the non-volatile memory.

13. The method for operating a storage device according to claim 11, further comprising: This enables the memory controller to search for a second address in the non-volatile memory based on the first address. The read command includes a command for reading second data addressed to a second address stored in non-volatile memory.

14. The method for operating a storage device according to any one of claims 11 to 13, further comprising: The storage controller sends a read command to the non-volatile memory, and then sends a request signal after the read command is sent to the non-volatile memory to request the first data; as well as This enables the storage controller to receive the first data.

15. The method for operating a storage device according to claim 14, further comprising: Second data is received from non-volatile memory before the storage controller receives the first data.

16. The method for operating a storage device according to any one of claims 11 to 13, further comprising: The storage controller sends a request signal to request the first data, and then a read command is sent to the non-volatile memory after the request signal is sent. as well as After the read command is sent to the non-volatile memory, the memory controller receives the first data.

17. The method for operating a storage device according to claim 16, further comprising: The first data is received at the storage controller before the second data is received from the non-volatile memory.

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