Display driver including crack resistance measurement circuit

Abstract

A display driver including a crack resistance measurement circuit according to one embodiment of the disclosure includes a crack resistance measurement circuit connected to a crack resistance circuit of a display panel to measure a crack resistance of the crack resistance circuit, wherein the crack resistance measurement circuit includes: a reference resistance generation circuit configured to generate a reference resistance using at least two resistors connected in series and at least two switches connected corresponding to the at least two resistors; a comparator configured to compare a size of the crack resistance with a size of the reference resistance and output a resistance comparison result; and a circuit controller configured to output a reference resistance control signal for controlling the at least two switches according to the resistance comparison result.

Description

Technical Field

[0001] This disclosure relates to a display driver including a crack resistance measurement circuit and a method for measuring cracks in a display panel. Background Technology

[0002] With the development of display technology, flexible displays and transparent display panels are constantly evolving. Flexible displays refer to bendable display devices.

[0003] Flexible displays use a plastic film instead of the glass substrate surrounding the liquid crystal in traditional liquid crystal displays (LCDs) and organic light-emitting diodes (OLEDs), thus giving them the flexibility to be folded or unfolded.

[0004] Flexible displays are not only thin and light, but also highly impact-resistant. Furthermore, they can be folded and bent, and can be manufactured into various shapes. Specifically, flexible displays can be applied in industrial fields where traditional glass-based displays have been limited or even not yet used.

[0005] However, this flexible display may develop cracks when bent. Summary of the Invention

[0006] Therefore, the purpose of this disclosure is to provide a display driver including a crack resistance measurement circuit and a method for measuring cracks in a display panel, the crack resistance measurement circuit being able to measure the resistance of the display panel to detect defects caused by cracks in the display panel.

[0007] A display driver according to one embodiment of the present disclosure includes a crack resistance measurement circuit connected to a display panel to measure the crack resistance of the crack resistance circuit. The crack resistance measurement circuit includes: a reference resistance generation circuit configured to generate a reference resistance using at least two resistors connected in series and at least two switches connected corresponding to the at least two resistors; a comparator configured to compare the magnitude of the crack resistance with the magnitude of the reference resistance and output a resistance comparison result; and a circuit controller configured to output a reference resistance control signal for controlling the at least two switches based on the resistance comparison result. Attached Figure Description

[0008] The accompanying drawings are included to provide a further understanding of this disclosure and are incorporated in and constitute a part of this application. The drawings illustrate embodiments of the disclosure and, together with the description, serve to illustrate the principles of the disclosure. In the drawings:

[0009] Figure 1 This is a block diagram of a display device according to one embodiment of the present disclosure;

[0010] Figure 2 This is a block diagram of a data-driven integrated circuit according to one embodiment of the present disclosure;

[0011] Figure 3 This is a block diagram of a crack resistance measurement circuit according to one embodiment of the present disclosure;

[0012] Figure 4 This is a circuit diagram of a reference resistor generation circuit according to one embodiment of the present disclosure;

[0013] Figure 5 This is a flowchart of a method for measuring cracks in a display panel according to one embodiment of the present disclosure; and

[0014] Figure 6 This is a diagram illustrating a method for measuring crack resistance according to one embodiment of the present disclosure. Detailed Implementation

[0015] In this specification, it should be noted that similar reference numerals already used to refer to similar elements in other figures are used for those elements whenever possible. In the following description, detailed descriptions of functions and configurations known to those skilled in the art that are unrelated to the basic configuration of this disclosure will be omitted. The terms described in this specification should be understood as follows.

[0016] The advantages and features of this disclosure, and its implementation methods, will become clear from the following embodiments described with reference to the accompanying drawings. However, this disclosure may be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of this disclosure to those skilled in the art. Furthermore, this disclosure is limited only by the scope of the claims.

[0017] The shapes, dimensions, scales, angles, and quantities shown in the accompanying drawings to describe embodiments of this disclosure are merely examples, and therefore this disclosure is not limited to the details shown. Similar reference numerals always refer to similar elements. In the following description, detailed descriptions of relevant known functions or configurations will be omitted where it is determined that they would unnecessarily obscure the essential points of this disclosure.

[0018] When using the terms "comprising," "having," and "including" as described in this specification, another component may be added unless "only" is used. Unless the opposite is mentioned, singular terms may include plural forms.

[0019] When interpreting components, even if not explicitly described, the components are interpreted as including a range of tolerances.

[0020] When describing temporal relationships, such as when time sequence is described as “after,” “following,” “next,” and “before,” discontinuous cases may be included unless “exactly” or “immediately following” is used.

[0021] It will be understood that although the terms “first,” “second,” etc., may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0022] The term "at least one" should be understood to include any and all combinations of one or more of the related listed items. For example, "at least one of the first, second, and third items" means a combination of all items derived from two or more of the first, second, and third items, as well as the first, second, or third item.

[0023] As will be fully understood by those skilled in the art, the features of the various embodiments of this disclosure can be linked or combined with each other in part or in whole, and can be technically interoperable and driven with each other in various ways. The embodiments of this disclosure can be implemented independently of each other, or they can be implemented together in a mutually dependent relationship.

[0024] In the following text, reference will be made to Figure 1 and Figure 2 A detailed description of the display device according to this disclosure.

[0025] Figure 1 This is a block diagram of a display device according to one embodiment of the present disclosure, and Figure 2 This is a diagram illustrating the connection relationship between a display panel and a crack resistance measurement circuit according to one embodiment of the present disclosure.

[0026] Reference Figure 1 According to one embodiment of the present disclosure, a display device 1000 includes a display panel 100 and a display driver 200.

[0027] The display device 1000 may include a flexible display panel and may include one or more thin-film transistors (TFTs) and organic light-emitting diodes (OLEDs), but this disclosure is not limited thereto. In addition to OLED displays, the display device 1000 may also be implemented as another display such as a liquid crystal display, a field emission display, an electroluminescent display, or an electrophoretic display.

[0028] The display panel 100 includes multiple gate lines G1 to Gm, multiple data lines D1 to Dn, and multiple pixels P.

[0029] Each of the multiple gate lines G1 to Gm receives a scan pulse during the display period (DP). Each of the multiple data lines D1 to Dn receives a data signal during the DP. The multiple gate lines G1 to Gm and the multiple data lines D1 to Dn are positioned to intersect each other on the substrate to define multiple pixel regions. Each of the multiple pixels P may include a TFT (not shown) connected to the adjacent gate line and the adjacent data line, a pixel electrode (not shown) connected to the TFT, and a storage capacitor (not shown) connected to the pixel electrode.

[0030] According to one embodiment of this disclosure, the display panel 100 may include a cracked resistor circuit. For example... Figure 2 As shown, the crack resistor circuit includes a first pad portion 111, a crack resistor Rpanel, a crack resistor line 112, and a second pad portion 113.

[0031] The first pad portion 111 receives a first voltage VDD from the power supply. The first pad portion 111 may be located at one end of the display panel 100.

[0032] The magnitude of the crack resistance Rpanel is measured by the crack resistance measurement circuit 520, which will be described below.

[0033] The crack resistance line 112 can be disposed along the edge of the display panel 100. Specifically, according to one embodiment of the present disclosure, the display panel 100 has a rectangular shape extending in a first direction D1 and a second direction D2 and has four edges extending in the first direction D1 and the second direction D2. The crack resistance line 112 can be positioned along at least one edge of the display panel 100 extending in the first direction D1 and one edge of the display panel 100 extending in the second direction D2. Therefore, by measuring the magnitude of the crack resistance Rpanel of the crack resistance circuit, it is possible to measure whether a crack has appeared in the display panel 100 in the first direction D1 and the second direction D2.

[0034] The second pad portion 113 is connected to the crack resistance measurement circuit 520 of the data driver 500. The second pad portion 113 may be located at the other end of the display panel 100. Although the first pad portion 111 and the second pad portion 113 are... Figure 2 The first pad portion 111 and the second pad portion 113 are illustrated as being located at different corners, but this disclosure is not limited thereto. The first pad portion 111 and the second pad portion 113 may be located at one corner of the display panel 100.

[0035] The display driver 200 allows data signals to be provided to a plurality of pixels P included in the display panel 100, thereby allowing images to be displayed through the display panel 100.

[0036] Display driver 200 includes timing controller 300, strobe driver 400, and data driver 500.

[0037] The timing controller 300 receives various timing signals from an external system (not shown), including a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a data enable (DE) signal, and a clock signal Clk, and generates a gating control signal (GCS) for controlling the gating driver 400 and a data control signal (DCS) for controlling the data driver 500. Furthermore, the timing controller 300 receives an image signal RGB from the external system and converts the received image signal RGB into an image signal RGB′ in a form that the data driver 500 can process, and outputs the image signal RGB′.

[0038] The host system converts the digital image data into a format suitable for display on the display panel 100. The host system sends a timing signal along with the digital image data to the timing controller 300. The host system can be implemented as any of a television system, set-top box, navigation system, digital optical disc (DVD) player, Blu-ray player, personal computer (PC), home theater system, or telephone system to receive input images.

[0039] The gating driver 400 receives the GCS from the timing controller 300. The GCS may include a gating start pulse (GSP), a gating shift clock (GSC), a gating output enable signal, etc. The gating driver 400 generates gating pulses (scan pulses) synchronized with the data signal based on the received GCS, and shifts the generated gating pulses to sequentially provide the gating pulses to gating lines G1 to Gm. For this purpose, the gating driver 400 may include multiple gating driver integrated circuits (ICs) (not shown). Under the control of the timing controller 300, the gating driver ICs sequentially provide gating pulses synchronized with the data signal to gating lines G1 to Gm to select the data line to which the data signal is applied. The gating pulses oscillate between gating high voltage and gating low voltage.

[0040] According to one embodiment of this disclosure, such as Figure 2 As shown, the data driver 500 includes a data signal generation circuit 510 and a crack resistance measurement circuit 520.

[0041] The data signal generation circuit 510 receives the DCS and image signal RGB′ from the timing controller 300. The DCS may include a source start pulse (SSP), a source sampling clock (SSC), and a source output enable (SOE) signal. The SSP controls the data sampling start timing of the n source driver ICs (not shown) that constitute the data driver 500. The SSC is a clock signal that controls the data sampling timing in each source driver IC. The SOE signal controls the output timing of each source driver IC.

[0042] In addition, the data signal generation circuit 510 converts the received image signal RGB′ into an analog data signal and provides the analog data signal to the pixel P through multiple data lines D1 to Dn.

[0043] The crack resistance measurement circuit 520 is connected to the crack resistance circuit of the display panel 100 via the second pad portion 113 to measure the crack resistance Rpanel of the crack resistance circuit. The crack resistance measurement circuit 520 can measure the crack resistance Rpanel of the crack resistance circuit to determine whether a crack has appeared in the display panel 100.

[0044] The following will refer to Figure 3 and Figure 4 A detailed description of a crack resistance measurement circuit 520 according to one embodiment of the present disclosure is provided.

[0045] In the following text, reference will be made to Figure 3 and Figure 4 A crack resistance measurement circuit according to one embodiment of the present disclosure is described in detail. Figure 3 This is a block diagram of a crack resistance measurement circuit according to one embodiment of the present disclosure, and Figure 4 This is a circuit diagram of a reference resistor generation circuit according to one embodiment of the present disclosure.

[0046] The crack resistance measurement circuit 520 measures the magnitude of the resistance being measured. Specifically, as described above, the crack resistance measurement circuit 520 is connected to the crack resistance circuit of the display panel 100 to measure the magnitude of the crack resistance Rpanel of the crack resistance circuit. According to one embodiment of this disclosure, the magnitude of the crack resistance Rpanel measured by the crack resistance measurement circuit 520 can be used to determine whether a defect caused by a crack has occurred in the display panel 100.

[0047] Reference Figure 3 The crack resistance measurement circuit 520 includes a reference resistance generation circuit 521, a comparator 522, and a circuit controller 523.

[0048] The reference resistance generation circuit 521 generates a reference resistance Rref that will be compared with the measured resistance. Specifically, the reference resistance generation circuit 521 generates a reference resistance Rref for comparison with the crack resistance Rpanel to be measured.

[0049] Reference Figure 4 The reference resistor generation circuit 521 may include multiple resistors and can generate a reference resistor Rref by combining the multiple resistors according to signals from the circuit controller 523, which will be described below. Specifically, the reference resistor generation circuit 521 includes a first resistor R1 to an Nth resistor R Nand the first switch SW1 to the Nth switch SW corresponding to each resistor. N .

[0050] First resistor R1 to Nth resistor R N Connected in series between input node Node1 and output node Node2, and from the first switch SW1 to the Nth switch SW N Located between input node Node1 and output node Node2, it is connected in parallel with the corresponding resistor. Therefore, it can be determined according to the first switch SW1 to the Nth switch SW. N The resistor connected under the control of [the circuit] generates a reference resistor Rref. That is, the first switch SW1 to the Nth switch SW... N Each of them is turned on or off by the reference resistor control signal RCS received from the circuit controller 523, thereby controlling the magnitude of the reference resistor Ref generated by the reference resistor generation circuit 521.

[0051] First resistor R1 to Nth resistor R N These can be resistors with the same resistance. The first resistor R1 to the Nth resistor R... N The resistance of each of them can have the same resolution as the reference resistance Rref generated by the reference resistance generation circuit 521. Alternatively, the reference resistance Rref generated by the reference resistance generation circuit 521 can have a range from 0 to the first resistor R1 to the Nth resistor R. N The resistance value of each resistor in the series is the product of the resistance value of the total number of resistors (N) and the expected crack resistance range. For example, the first resistor R1 to the Nth resistor R N Each of the components can have a 1kΩ resistance; therefore, the reference resistance generation circuit 521 can have a 1kΩ resolution, and the reference resistance Rref can be within the expected crack resistance range of 0Ω to N×1kΩ. In this case, the expected crack resistance range represents the range expected to include the value of the crack resistance Rpanel. According to one embodiment of this disclosure, the expected crack resistance range can be reduced by half based on a clock signal.

[0052] According to this disclosure, crack resistance can be measured more accurately by increasing the resolution of the crack resistance measurement circuit.

[0053] Comparator 522 compares the measured resistance with the reference resistance Rref of the reference resistance generation circuit 521. Specifically, according to one embodiment of this disclosure, comparator 522 compares the crack resistance Rpanel of the display panel 100 with the reference resistance Rref of the reference resistance generation circuit 521 and outputs the resistance comparison result.

[0054] According to one embodiment of this disclosure, comparator 522 compares the crack resistance Rpanel of display panel 100 with the reference resistance Rref of reference resistance generation circuit 521 based on the clock signal Clk output from timing controller 300.

[0055] The circuit controller 523 provides a signal to the reference resistor generation circuit 521 to control the magnitude of the reference resistor Rref. Specifically, in order to control the magnitude of the reference resistor Rref based on the comparison result of the comparator 522, the circuit controller 523 provides switches SW1 to SW1 of the reference resistor generation circuit 521 for controlling the reference resistor generation circuit. N The reference resistor control signal RCS is used. Specifically, based on the comparison result of comparator 522, circuit controller 523 changes the expected crack resistance range by changing the maximum or minimum value of the expected crack resistance range. The median value of the changed expected crack resistance range is calculated, and the reference resistor control signal RCS is provided to reference resistor generation circuit 521 so that the reference resistor Rref has the calculated median value of the expected crack resistance range.

[0056] In the following text, reference will be made to Figure 5 and Figure 6 A method for determining whether a crack appears in a display panel according to one embodiment of the present disclosure is described in detail. Figure 5 This is a flowchart of a method for measuring cracks in a display panel according to one embodiment of the present disclosure, and Figure 6 This is a diagram illustrating a method for measuring crack resistance according to one embodiment of the present disclosure.

[0057] According to one embodiment of this disclosure, the circuit controller 523 receives from the comparator 522 a comparison result between a reference resistor Rref generated by the reference resistor generation circuit 521 and a crack resistance Rpanel of the display panel 100. According to one embodiment of this disclosure, the circuit controller 523 controls the size of the reference resistor Rref by outputting a reference resistor control signal RCS for adjusting the size of the reference resistor Rref based on the comparison result received from the comparator 522. This process is then repeated until the reference resistor Rref of the reference resistor generation circuit 521 has the same value as the resistance Rpanel of the panel crack measurement circuit, thereby controlling the size of the reference resistor Rref of the reference resistor generation circuit 521 to measure the size of the resistance Rpanel of the panel crack measurement circuit.

[0058] First, the crack resistance Rpanel is compared with the reference resistance Rref (S511). According to one embodiment of this disclosure, the crack resistance Rpanel is compared with the reference resistance Rref based on the clock signal Clk output from the timing controller 300.

[0059] When the crack resistance Rpanel is greater than the reference resistance Rref, determine whether the reference resistance Rref has the same value as the maximum reference resistance Rref_max (S512).

[0060] When the crack resistance Rpanel is greater than the reference resistance Rref and the reference resistance Rref has the same value as the maximum reference resistance Rref_max, the circuit controller 523 determines that a crack has appeared in the display panel 100 (S513). Specifically, when the crack resistance Rpanel is greater than the reference resistance Rref and the reference resistance Rref has the same value as the maximum reference resistance Rref_max, the circuit controller 523 determines that the crack resistance circuit is open due to the crack.

[0061] When the crack resistance Rpanel is greater than the reference resistance Rref and the reference resistance Rref has a value different from the maximum reference resistance Rref_max, the circuit controller 523 changes the minimum value of the expected crack resistance range to the reference resistance Rref (S514). Specifically, when the crack resistance Rpanel is greater than the reference resistance Rref and the reference resistance Rref has a value different from the maximum reference resistance Rref_max, the circuit controller 523 changes the minimum value of the expected crack resistance range to the reference resistance Rref, thus changing the expected crack resistance range.

[0062] Subsequently, the circuit controller 523 outputs a reference resistance control signal RCS (S521) to control the reference resistor Rref to the median value of the changed expected crack resistance range. Specifically, the circuit controller 523 calculates the median value of the changed expected crack resistance range and outputs the reference resistance control signal RCS to the reference resistance generation circuit 521 to control the reference resistor Rref to the calculated median value of the expected crack resistance range.

[0063] Next, the reference resistor generation circuit 521 changes the value of the reference resistor Rref (S522). Specifically, the reference resistor generation circuit 521 controls the first switch SW1 to the Nth switch SW according to the received reference resistor control signal RCS. N This is to change the value of the reference resistor Rref.

[0064] On the other hand, when the crack resistance Rpanel is less than the reference resistance Rref, the circuit controller 523 changes the maximum value of the expected crack resistance range to the reference resistance Rref (S515). Specifically, when the crack resistance Rpanel is less than the reference resistance Rref, the circuit controller 523 changes the maximum value of the expected crack resistance range to the reference resistance Rref, thereby changing the expected crack resistance range.

[0065] Subsequently, the circuit controller 523 outputs a reference resistance control signal RCS (S521) to control the reference resistor Rref to the median value of the changed expected crack resistance range. Specifically, the circuit controller 523 calculates the median value of the changed expected crack resistance range and outputs the reference resistance control signal RCS to the reference resistance generation circuit 521 to control the reference resistor Rref to the calculated median value of the expected crack resistance range.

[0066] Next, the reference resistor generation circuit 521 changes the value of the reference resistor Rref (S522). Specifically, the reference resistor generation circuit 521 controls the first switch SW1 to the Nth switch SW according to the received reference resistor control signal RCS. N This is to change the value of the reference resistor Rref.

[0067] According to one embodiment of this disclosure, operations S511 to S522 are repeated until the crack resistance Rpanel has the same size as the reference resistance Rref.

[0068] The measurement of crack resistance Rpanel is complete when the crack resistance Rpanel has the same value as the reference resistance Rref (S531).

[0069] [Table 1]

[0070]

[0071] As shown in Table 1 and Figure 6 The following example illustrates the resistance measurement process when the crack resistance Rpanel is 27.5kΩ. When the rising edge of the first clock signal Clk occurs, the circuit controller 523 sets the first reference resistor 1... st Rref is controlled to be the maximum value Rref_max of the reference resistor Rref. Therefore, comparator 522 compares the crack resistor Rpanel with the first reference resistor 1, which has the maximum value Rref_max. st Rref is compared. That is, the first reference resistor 1 of the reference resistor generation circuit 521 is used for comparison. st Rref has a maximum value of 32kΩ, and the crack resistance Rpanel is compared with a first reference resistance 1 having a maximum value of 32kΩ Rref_max. st Rref is compared. In this case, circuit controller 523 receives a value where the crack resistance Rpanel is less than the first reference resistance 1. st The comparison result of Rref. Therefore, the circuit controller 523 changes the maximum value of the expected crack resistance range to the first reference resistance 1. st Rref calculates the median of the expected crack resistance range and outputs the second reference resistor 2 used in the reference resistance generation circuit 521.nd Rref is controlled by a signal representing the median of the expected crack resistance range. That is, circuit controller 523 receives a first reference resistor 1 where the crack resistance Rpanel is less than 32kΩ. st The comparison result of Rref, and the current first reference resistor of 32kΩ 1 st Rref is stored as the maximum value of the expected crack resistance range. Additionally, circuit controller 523 calculates the median value (16kΩ) of the expected crack resistance range and outputs a reference resistance control signal RCS, causing the second reference resistor 2 of reference resistance generation circuit 521 to... nd Rref has a median (16kΩ) of the expected crack resistance range (0kΩ to 32kΩ).

[0072] Next, when the rising edge of the second clock signal occurs, the crack resistor Rpanel is connected to the second reference resistor 2 of the reference resistor generation circuit 521. nd Rref is compared. In other words, the crack resistor Rpanel is compared to the 16kΩ second reference resistor 2 of the reference resistor generation circuit 521. nd Rref is compared. In this case, circuit controller 523 receives a value where the crack resistance Rpanel is greater than the second reference resistance 2. nd The comparison result of Rref. Therefore, the circuit controller 523 changes the minimum value of the expected crack resistance range to the second reference resistance 2. nd Rref calculates the median of the expected crack resistance range (24kΩ) and outputs the reference resistance control signal RCS, causing the third reference resistor 3 of the reference resistance generation circuit 521 to... rd Rref has a median (24kΩ) of the expected crack resistance range (16kΩ to 32kΩ).

[0073] Next, when the rising edge of the third clock signal occurs, the crack resistor Rpanel is connected to the third reference resistor 3 of the reference resistor generation circuit 521. rd Rref is compared. That is, the crack resistance Rpanel is compared to the 24kΩ third reference resistance 3 of the reference resistance generation circuit 521. rd Rref is compared. In this case, circuit controller 523 receives a value where the crack resistance Rpanel is greater than the third reference resistance 3. rd The comparison result of Rref. Therefore, the circuit controller 523 changes the minimum value of the expected crack resistance range to the third reference resistor 3. rd Rref calculates the median of the expected crack resistance range (28kΩ) and outputs the reference resistance control signal RCS, causing the fourth reference resistor 4 of the reference resistance generation circuit 521 to... thRref has a median (28kΩ) of the expected crack resistance range (24kΩ to 32kΩ).

[0074] Next, when the rising edge of the fourth clock signal occurs, the crack resistor Rpanel is connected to the fourth reference resistor 4 of the reference resistor generation circuit 521. th Rref is compared. That is, the crack resistance Rpanel is compared to the 28kΩ fourth reference resistor 4 of the reference resistance generation circuit 521. th Rref is compared. In this case, circuit controller 523 receives a value where the crack resistance Rpanel is less than the fourth reference resistance 4. th The comparison result of Rref. Therefore, the circuit controller 523 changes the maximum value of the expected crack resistance range to the fourth reference resistor 4. th Rref calculates the median of the expected crack resistance range (26kΩ) and outputs the reference resistance control signal RCS, causing the fifth reference resistor 521 of the reference resistance generation circuit 521 to... th Rref has a median (26kΩ) of the expected crack resistance range (24kΩ to 28kΩ).

[0075] Next, when the rising edge of the fifth clock signal occurs, the crack resistor Rpanel is connected to the fifth reference resistor 5 of the reference resistor generation circuit 521. th Rref is compared. That is, the crack resistance Rpanel is compared to the 26kΩ fifth reference resistance 5 of the reference resistance generation circuit 521. th Rref is compared. In this case, circuit controller 523 receives a value where the crack resistance Rpanel is greater than the fifth reference resistance 5. th The comparison result of Rref. Therefore, the circuit controller 523 changes the minimum value of the expected crack resistance range to the fifth reference resistor 5. th Rref calculates the median of the expected crack resistance range and outputs the reference resistance control signal RCS, causing the sixth reference resistor 6 of the reference resistance generation circuit 521 to... th Rref has a median (27kΩ) of the expected crack resistance range (26kΩ to 28kΩ).

[0076] Next, although not shown, when the rising edge of the sixth clock signal occurs, the crack resistor Rpanel is compared with the sixth reference resistor 6 of the reference resistor generation circuit 521. th Rref is compared. That is, the crack resistance Rpanel is compared to the 27kΩ sixth reference resistor 6 of the reference resistance generation circuit 521. thRref is compared. In this case, circuit controller 523 receives a value where the crack resistance Rpanel is greater than the sixth reference resistance 6. th The comparison results for Rref. However, the crack resistance Rpanel of 27.5kΩ is better than the sixth reference resistance of 27kΩ. th Rref is 0.5kΩ, but the resolution of the reference resistor generation circuit 521 is 1kΩ, and the expected value of the crack resistance range is the same as the resolution of the reference resistor generation circuit 521. Therefore, the circuit controller 523 can determine the crack resistance Rpanel and the sixth reference resistor 6. th Rref has the same value.

[0077] Although not shown, according to this disclosure, the value of the crack resistance Rpanel can be measured by such a process, and the measured value of the crack resistance Rpanel can be used to determine the degree of defect caused by cracks in the display panel.

[0078] According to one embodiment of this disclosure, for each clock signal, the crack resistance range is expected to be halved; therefore, the maximum time t required to measure the crack resistance Rpanel is calculated according to Equation 1. detect .

[0079] [Formula 1]

[0080]

[0081] In this case, Range represents the maximum value of the expected crack resistance range, Resolution represents the resolution of the reference resistance generation circuit 521, and t clk This indicates the period of the clock signal output from the timing controller 300.

[0082] According to this disclosure, since crack resistance is measured based on a clock signal, crack resistance can be measured quickly.

[0083] According to the display device including a crack resistance measuring circuit and the method for measuring cracks in a display panel disclosed herein, the crack resistance of the display panel can be measured, thereby determining the defects in the display panel caused by the crack by using the measured crack resistance value.

[0084] Furthermore, the display device including a crack resistance measurement circuit and the method for measuring cracks in the display panel according to the present disclosure can improve the resolution of the crack resistance measurement circuit, thereby measuring the crack resistance more accurately.

[0085] Furthermore, according to the display device including a crack resistance measuring circuit and the method for measuring cracks in the display panel disclosed herein, since the crack resistance is measured based on a clock signal, the crack resistance can be measured quickly.

[0086] It will be apparent to those skilled in the art that various changes and modifications can be made without departing from the spirit and scope of this disclosure.

[0087] Furthermore, at least a portion of the methods described herein can be implemented using one or more computer programs or components. These components may be provided as a series of computer instructions via a computer-readable or machine-readable medium including volatile and non-volatile memory. The instructions may be provided as software or firmware and may be implemented wholly or partially in hardware constructs such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), or other similar devices. The instructions may be configured to be executed by one or more processors or other hardware components, and when one or more processors or other hardware components execute the series of computer instructions, one or more processors or other hardware components may perform the methods and processes disclosed herein, wholly or partially.

[0088] Therefore, the above embodiments should be understood as exemplary rather than restrictive. The scope of this disclosure will be defined by the appended claims rather than the detailed description above, and all variations and modifications derived from the meaning and scope of the claims and their equivalents should be understood to be included within the scope of this disclosure.

[0089] Cross-references to related applications

[0090] This application claims priority to Korean Patent Application No. 10-2021-0000754, filed on January 5, 2021, which is incorporated herein by reference as if fully set forth herein.

Claims

1. A display driver including a crack resistance measurement circuit connected to a crack resistance circuit of a display panel to measure the crack resistance of the crack resistance circuit. in, The crack resistance measurement circuit includes: A reference resistor generation circuit is configured to generate a reference resistor using at least two resistors connected in series and at least two switches connected corresponding to the at least two resistors. A comparator configured to compare the magnitude of the crack resistance with the magnitude of the reference resistance and output a resistance comparison result; and A circuit controller configured to output a reference resistor control signal for controlling the at least two switches based on the resistance comparison result.

2. The display driver according to claim 1, wherein, The at least two resistors are connected in series between the input node and the output node, and The at least two switches are each connected in parallel to a corresponding resistor in the resistor array between the input node and the output node.

3. The display driver according to claim 1, wherein, The at least two switches are turned on or off according to the reference resistor control signal output from the circuit controller, and The reference resistor is controlled by the at least two switches.

4. The display driver according to claim 1, wherein, The at least two resistors have the same resistance.

5. The display driver according to claim 4, wherein, The reference resistor generation circuit has the same resistance resolution as the resistor.

6. The display driver according to claim 1, wherein, The comparator compares the magnitude of the crack resistance with the magnitude of the reference resistance based on a clock signal input from the timing controller.

7. The display driver according to claim 1, wherein, The circuit controller changes the maximum or minimum value of the expected crack resistance range based on the resistance comparison result, and outputs a reference resistance control signal to control the reference resistance to the median value of the changed expected crack resistance range.

8. The display driver according to claim 7, wherein, Whenever a clock signal is output from the timing controller, the value of the expected crack resistance range is reduced by half.

9. The display driver according to claim 7, wherein, The circuit controller compares the reference resistance with a maximum reference resistance when the crack resistance is greater than the reference resistance, and determines that a crack has occurred in the display panel when the reference resistance is the same as the maximum reference resistance. The circuit controller compares the reference resistance with the maximum reference resistance when the crack resistance is greater than the reference resistance, and changes the minimum value of the expected crack resistance range to the reference resistance when the reference resistance is different from the maximum reference resistance. When the crack resistance is less than the reference resistance, the circuit controller changes the maximum value of the expected crack resistance range to the reference resistance.

10. A display driver, the display driver comprising: A crack resistance measurement circuit is connected to a crack resistance circuit of a display panel, measures the crack resistance of the crack resistance circuit, and compares the measured crack resistance with a reference resistance to determine whether a crack has appeared in the display panel. as well as A timing controller configured to output a clock signal to the crack resistance measurement circuit. Specifically, the crack resistance measurement circuit compares the magnitude of the crack resistance with the magnitude of the reference resistance based on the clock signal. The crack resistance measurement circuit includes: A reference resistor generation circuit configured to generate the reference resistor; A comparator configured to compare the magnitude of the crack resistance with the magnitude of the reference resistance; and A circuit controller is configured to determine, based on a resistance comparison result, that a crack has appeared in the display panel, or to output a reference resistance control signal to the reference resistance generation circuit for controlling the magnitude of the reference resistance. The circuit controller compares the reference resistance with the maximum reference resistance when the crack resistance is greater than the reference resistance, and determines that a crack has appeared in the display panel when the reference resistance is equal to the maximum reference resistance.

11. The display driver according to claim 10, wherein, The circuit controller compares the reference resistance with the maximum reference resistance when the crack resistance is greater than the reference resistance, and changes the minimum value of the expected crack resistance range to the reference resistance when the reference resistance is different from the maximum reference resistance. When the crack resistance is less than the reference resistance, the circuit controller changes the maximum value of the expected crack resistance range to the reference resistance and outputs a reference resistance control signal to the reference resistance generation circuit to control the reference resistance to be changed to the median value of the changed expected crack resistance range.

12. The display driver according to claim 11, wherein, Whenever the clock signal is output from the timing controller, the value of the expected crack resistance range is reduced by half.

13. A display driver including a crack resistance measuring circuit configured to measure the magnitude of crack resistance. in, The crack resistance measurement circuit includes: A reference resistor generation circuit is configured to generate a reference resistor using at least two resistors connected in series and at least two switches connected corresponding to the at least two resistors. A comparator configured to compare the magnitude of the crack resistance with the magnitude of the reference resistance and output a resistance comparison result; and A circuit controller configured to output a reference resistor control signal for controlling the at least two switches based on the resistance comparison result.

14. The display driver according to claim 13, wherein, The at least two resistors are connected in series between the input node and the output node, and The at least two switches are each connected in parallel to a corresponding resistor in the resistor array between the input node and the output node.

15. The display driver according to claim 13, wherein, The at least two switches are turned on or off according to the reference resistor control signal output from the circuit controller, and The reference resistor is controlled by the at least two switches.

16. The display driver according to claim 13, wherein, The at least two resistors have the same resistance.

17. The display driver according to claim 13, wherein, The comparator compares the magnitude of the crack resistance with the magnitude of the reference resistance based on a clock signal input from the timing controller.

18. The display driver according to claim 13, wherein, The circuit controller changes the maximum or minimum value of the expected crack resistance range according to the resistance comparison result, and outputs a reference resistance control signal to the reference resistance generation circuit to control the reference resistance to the median value of the changed expected crack resistance range.

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