A semiconductor epitaxial structure, its fabrication method, and power and radio frequency devices

Abstract

This invention relates to a semiconductor epitaxial structure, its fabrication method, and power and radio frequency devices. The semiconductor epitaxial structure includes a substrate, a buffer layer, a stress-modulating layer, and a drift layer stacked together; the stress-modulating layer comprises a semiconductor material and a doping material; the semiconductor material includes AlN, GaN, and Al... x Ga 1‑x N or In b Al a Ga 1‑a‑b Any one or at least two combinations of N, where 0 < x < 1, 0 < a < 1, 0 < b < 1. The stress-adjusting layer provided by the present invention contains semiconductor material and added doping material, and is located between the buffer layer and the drift layer. The stress-adjusting layer is used to adjust the strain tension effect of the epitaxial layer, thereby mitigating screw dislocations and edge dislocations caused by the difference in lattice constants and thermal expansion coefficients between the substrate and the buffer layer, and reducing dislocations in the subsequent growth of the drift layer, thereby improving the quality of gallium nitride-based epitaxial crystals.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor fabrication technology, and relates to a semiconductor epitaxial structure, and more particularly to a semiconductor epitaxial structure and its fabrication method, as well as power and radio frequency devices. Background Technology

[0002] Gallium nitride (GaN) is considered the most important semiconductor material after silicon. A wide-bandgap semiconductor, GaN's spectrum covers the entire visible light region, allowing it to be fabricated into blue and white light-emitting diodes (LEDs) for displays, television backlighting, and general lighting; green / blue LEDs, along with AlGaInP-based red LEDs, for full-color displays; and ultraviolet lasers for data storage. Besides its excellent optical properties, GaN also boasts outstanding electrical properties: a wide bandgap, high critical breakdown electric field, high thermal conductivity, and high electron drift saturation velocity. Furthermore, it exhibits high spontaneous and piezoelectric polarization effects, enabling the generation of high-mobility, high-area-density two-dimensional electron gases in epitaxial heterostructures. These characteristics allow for devices with high current density, low on-resistance, high operating frequency, high thermal stability, and small size. Therefore, GaN can also be used in microwave devices and high-power switching devices. The voltage withstand capability and electron mobility of GaN semiconductor materials are the main performance indicators.

[0003] In existing technologies, the doping process of general planar devices typically creates an impurity diffusion junction with a certain curvature beneath the semiconductor material surface. This junction often has a much lower voltage withstand capability than an ideal parallel planar junction without curvature, which affects the final operating voltage of the semiconductor device. Therefore, many methods have emerged to improve the breakdown voltage of curved junctions generated by planar processes; these are generally referred to as junction termination techniques.

[0004] CN 108428741A discloses a gallium nitride semiconductor device and a method for fabricating the same. The method includes: growing an indium-containing buffer layer on a first surface of a substrate, the buffer layer comprising indium-containing Al. x Ga 1-x N layers, where 0 ≤ x ≤ 1; a first gallium nitride layer unintentionally doped is formed on the surface of the buffer layer away from the substrate; a second gallium nitride layer containing carbon doping is formed on the surface of the first gallium nitride layer away from the buffer layer; a third gallium nitride layer unintentionally doped is formed on the surface of the second gallium nitride layer away from the first gallium nitride layer; Al is formed on the surface of the third gallium nitride layer away from the second gallium nitride layer. y GaN 1-y N layers, where 0 < y ≤ 1. Gallium nitride (GaN) semiconductor devices fabricated using this method can improve the breakdown voltage of the GaN semiconductor device, reduce the probability of cracks occurring during the fabrication process, and improve the performance of the GaN semiconductor device.

[0005] CN 101330097 discloses a semiconductor structure and manufacturing method for increasing breakdown voltage. The semiconductor structure comprises five parts: a semiconductor material, a main diffusion junction, a breakdown voltage layer, a depletion termination region, and a dielectric layer. The main diffusion junction, breakdown voltage layer, and depletion termination region are all located within the semiconductor material. The conductivity types of the main diffusion junction and the breakdown voltage layer are opposite to those of the semiconductor material, while the conductivity type of the depletion termination region is the same as that of the semiconductor material. This structure can increase the breakdown voltage of the main diffusion junction by more than 25%, enabling the main diffusion junction breakdown voltage to reach more than 75% of the maximum avalanche breakdown voltage of an ideal parallel planar junction in semiconductor materials. This invention can be applied to junction terminations in semiconductor devices ranging from tens of volts to thousands of volts, and is particularly suitable for the structure and manufacturing of high-voltage semiconductor devices and integrated circuits using shallow junction low-temperature processes.

[0006] Although the above technical solutions improve the semiconductor structure and increase the withstand voltage, there are epitaxial crystal quality problems caused by the difference in lattice constant mismatch rate and thermal expansion coefficient between the substrate and the top drift layer, which affects the performance of semiconductor devices.

[0007] Therefore, how to improve the epitaxial crystal quality caused by the difference in lattice constant mismatch rate and thermal expansion coefficient between the substrate and the top drift layer, ensure high withstand voltage and electron mobility, and improve the performance of semiconductor devices are technical problems that urgently need to be solved in the field of semiconductor manufacturing technology. Summary of the Invention

[0008] In view of the problems existing in the prior art, the present invention provides a semiconductor epitaxial structure, its preparation method and power and radio frequency devices. By growing a stress-adjusting layer on the buffer layer, the epitaxial crystal quality problems caused by the difference in lattice constant mismatch rate and thermal expansion coefficient between the substrate and the drift layer are mitigated, thereby improving the device capability.

[0009] To achieve this objective, the present invention adopts the following technical solution:

[0010] In a first aspect, the present invention provides a semiconductor epitaxial structure, the semiconductor epitaxial structure comprising a substrate, a buffer layer, a stress adjustment layer and a drift layer stacked thereon;

[0011] The stress-regulating layer comprises semiconductor materials and doped materials;

[0012] The semiconductor materials include AlN, GaN, and Al. x Ga 1-x N or In b Al a Ga 1-a-b Any combination of one or at least two of N, where 0 < x < 1, 0 < a < 1, and 0 < b < 1.

[0013] This invention grows a stress-adjusting layer between a buffer layer and a drift layer. The stress-adjusting layer contains semiconductor materials and is doped with materials. This allows the stress-adjusting layer to adjust the strain tension effect of the epitaxial layer caused by the difference in lattice constants and thermal expansion coefficients between the substrate and the buffer layer, thereby reducing dislocations and tilting them, and reducing dislocations in the subsequently grown drift layer, thus improving the quality of gallium nitride-based epitaxial crystals.

[0014] The semiconductor materials include AlN, GaN, and Al. x Ga 1-x N or In b Al a Ga 1-a-b Any combination of one or at least two of N, typically but not limitingly including combinations of AlN and GaN, GaN and Al x Ga 1-x The combination of N, Al x Ga 1-x N and In b Al a Ga 1-a-b Combinations of N, AlN, GaN, and Al x Ga 1-x Combinations of N, GaN, Al x Ga 1-x N and In b Al a Ga 1-a-b Combinations of N, or AlN, GaN and Al x Ga 1-x N or In b Al a Ga 1-a-b Combinations of N.

[0015] 0 < x < 1, for example, it can be 0.01, 0.03, 0.05, 0.1, 0.3, 0.5, 0.7 or 0.9, but is not limited to the listed values. Other unlisted values ​​within the range are also applicable. The range of values ​​can be from large to small or from small to large, preferably from large to small.

[0016] 0 < a < 1, for example, it can be 0.01, 0.03, 0.05, 0.1, 0.3, 0.5, 0.7 or 0.9, for example, but not limited to the listed values. Other unlisted values ​​within the value range are also applicable. The value range can be from large to small or from small to large, but it is preferred to be from large to small.

[0017] 0 < b < 1, for example, it can be 0.01, 0.03, 0.05, 0.1, 0.3, 0.5, 0.7 or 0.9, for example, but not limited to the listed values. Other unlisted values ​​within the value range are also applicable. The value range can be from large to small or from small to large, but it is preferred to be from small to large.

[0018] Preferably, the stress-adjusting layer comprises a single-layer structure or a composite-layer structure.

[0019] Preferably, the semiconductor material in the monolayer structure includes AlN, GaN, and Al x Ga 1-x N or In b Al a Ga 1-a-b Any one of N.

[0020] Preferably, the composite layer structure includes at least two layers, such as 2, 4, 10, 40 or 50 layers, but is not limited to the listed values. Other unlisted values ​​within the range are also applicable.

[0021] Preferably, in the composite layer structure, each pair of adjacent layers is periodically stacked.

[0022] Preferably, the semiconductor materials in the two adjacent layers include AlN, GaN, and Al. x Ga 1-x N or In b Al a Ga 1-a-b Any combination of any two of N, for example, a combination of AlN and GaN, or GaN and Al x Ga 1-x The combination of N, Al x Ga 1-x N and In b Al a Ga 1-a-b Combinations of N, AlN and Al x Ga 1-x Combinations of N, AlN and In b Al a Ga 1-a-b Combinations of N, or GaN and In b Al a Ga 1-a-b Combinations of N.

[0023] Preferably, the number of cycles is 1 to 100, for example, it can be 1, 5, 10, 40, 50, 60, 80 or 100, but is not limited to the listed values. Other unlisted values ​​within the range are also applicable.

[0024] The stress-regulating layer composite structure provided by this invention is distributed in a periodic stacking manner with two layers as units. Each layer contains only one type of semiconductor material, and the semiconductor materials of adjacent layers are different. By adjusting different epitaxial growth conditions, different material compositions and their corresponding lattice constants can be modulated on the stress-regulating layer. Finally, the epitaxial lattice constant that conforms to the next layer can be modulated on this layer.

[0025] Preferably, the doping element in the doped material includes any one or a combination of at least two of carbon, beryllium, magnesium, or iron. Typical but non-limiting combinations include combinations of carbon and beryllium, beryllium and magnesium, magnesium and iron, carbon and magnesium, carbon and iron, beryllium and iron, carbon, beryllium and magnesium, beryllium, magnesium and iron, or carbon, beryllium, magnesium and iron.

[0026] This invention utilizes impurities of different elements in the stress-adjusting layer to compensate for unintentionally doped N-type material layers, and uses a deep energy level trapping method to make this layer a neutral material, ultimately achieving high resistance characteristics. This high-resistance layer can reduce leakage paths.

[0027] Preferably, the content of the dopant element in the stress-regulating layer is 1.0×E17~1.0×E19 atoms / cm². 3 For example, it could be 1.0 × E17 atoms / cm 3 5.0 × E17 atoms / cm 3 1.0 × E18 atoms / cm 3 5.0 × E18 atoms / cm 3 Or 1.0 × E19 atoms / cm 3 However, this does not limit the listed values; other unlisted values ​​within the range are also applicable.

[0028] When the doping concentration is greater than 1.0 × E19 atoms / cm 3 When the doping concentration is excessive, the single-crystal material exhibits crystal collapse, generating more dislocations; however, when the doping concentration is less than 1.0 × E17 atoms / cm², the crystal collapses. 3 When this occurs, due to the inability to form n-type material compensation and deep energy level electron capture action, a significant leakage path appears in this layer, which in turn affects the device's operating function.

[0029] Preferably, the substrate comprises any one or a combination of at least two of Al2O3, GaN, AlN, GaO, Si, or SiC. Typical but non-limiting combinations include combinations of Al2O3 and GaN, GaN and AlN, AlN and Si, Al2O3 and GaO, AlN and GaO, GaO and Si, Si and SiC, Al2O3, GaN and AlN, GaN, AlN and Si, AlN, Si and SiC, Al2O3, GaN, AlN and Si, GaN, AlN, Si and SiC, or Al2O3, GaN, AlN, Si and SiC.

[0030] Preferably, the material of the buffer layer includes AlN and / or AlInN.

[0031] Preferably, the drift layer comprises any one or a combination of at least two of AlN, GaN, AlGaN, or AlInGaN. Typical but non-limiting combinations include combinations of AlN and GaN, GaN and AlGaN, GaN and AlInGaN, AlN and AlGaN, AlGaN and AlInGaN, AlN and AlInGaN, AlN, GaN and AlGaN, GaN, AlGaN and AlInGaN, or AlN, AlGaN and AlInGaN.

[0032] Preferably, the thickness of the substrate is 350 μm or more, for example, it can be 350 μm, 400 μm, 450 μm, 500 μm or 600 μm, but is not limited to the listed values, and other unlisted values ​​within the range are also applicable.

[0033] Preferably, the thickness of the buffer layer is 1~500nm, for example, it can be 1nm, 50nm, 100nm, 300nm or 500nm, but is not limited to the listed values. Other unlisted values ​​within the range are also applicable.

[0034] Preferably, the thickness of the stress-adjusting layer is 0.1~50μm, for example, it can be 0.1μm, 1μm, 5μm, 10μm, 15μm, 20μm, 30μm, 40μm or 50μm, but is not limited to the listed values, and other unlisted values ​​within the range are also applicable.

[0035] Preferably, the thickness of the drift layer is 1~50μm, for example, it can be 1μm, 5μm, 10μm, 15μm, 20μm, 30μm, 40μm or 50μm, but is not limited to the listed values, and other unlisted values ​​within the range are also applicable.

[0036] In a second aspect, the present invention provides a method for preparing a semiconductor epitaxial structure according to the first aspect, the method comprising the following steps:

[0037] (1) A buffer layer is grown on the surface of the substrate;

[0038] (2) A stress-regulating layer is grown on the surface of the obtained buffer layer;

[0039] (3) A drift layer is grown on the surface of the obtained stress-adjusting layer.

[0040] The growth described in this invention is a vapor phase epitaxial growth method.

[0041] Preferably, the growth temperature in step (1) is 500~1100℃, for example, it can be 500℃, 600℃, 700℃, 800℃, 900℃, 1000℃ or 1100℃, but is not limited to the listed values. Other unlisted values ​​within the range are also applicable.

[0042] Preferably, the reaction chamber pressure for growth in step (1) is 20 to 500 torr, for example, it can be 20 torr, 50 torr, 100 torr, 200 torr or 500 torr, but is not limited to the listed values. Other unlisted values ​​within the range are also applicable.

[0043] Preferably, the TMA1 flow rate in step (1) is 200~300 slm, for example, it can be 200 slm, 210 slm, 220 slm, 250 slm, 280 slm or 300 slm, but is not limited to the listed values. Other unlisted values ​​within the range are also applicable.

[0044] Preferably, the growth in step (1) is carried out under the condition of ammonia gas being introduced, with a flow rate of 0.5~50 slm, for example, it can be 0.5 slm, 1 slm, 5 slm, 10 slm, 25 slm or 50 slm, but is not limited to the listed values. Other unlisted values ​​within the range are also applicable.

[0045] Preferably, the growth temperature in step (2) is 500~1100℃, for example, it can be 500℃, 600℃, 700℃, 800℃, 900℃, 1000℃ or 1100℃, but is not limited to the listed values. Other unlisted values ​​within the range are also applicable.

[0046] Preferably, the reaction chamber pressure for growth in step (2) is 20 to 500 torr, for example, it can be 20 torr, 50 torr, 100 torr, 200 torr or 500 torr, but is not limited to the listed values. Other unlisted values ​​within the range are also applicable.

[0047] Preferably, the TMA1 flow rate in step (2) is 10~250 slm, for example, it can be 10 slm, 50 slm, 100 slm, 200 slm, 220 slm or 250 slm, but is not limited to the listed values. Other unlisted values ​​within the range are also applicable.

[0048] Preferably, the growth described in step (2) is carried out under the condition of ammonia gas being introduced, with a flow rate of 0.5~50 slm, for example, it can be 0.5 slm, 1 slm, 5 slm, 10 slm, 25 slm or 50 slm, but is not limited to the listed values. Other unlisted values ​​within the range are also applicable.

[0049] Preferably, the growth temperature in step (3) is 500~1100℃, for example, it can be 500℃, 600℃, 700℃, 800℃, 900℃, 1000℃ or 1100℃, but is not limited to the listed values. Other unlisted values ​​within the range are also applicable.

[0050] Preferably, the reaction chamber pressure for growth in step (3) is 20 to 500 torr, for example, it can be 20 torr, 50 torr, 100 torr, 200 torr or 500 torr, but is not limited to the listed values. Other unlisted values ​​within the range are also applicable.

[0051] Preferably, the TMA1 flow rate in step (3) is 10~300 slm, for example, it can be 10 slm, 50 slm, 100 slm, 200 slm, 220 slm, 250 slm, 280 slm or 300 slm, but is not limited to the listed values. Other unlisted values ​​within the range are also applicable.

[0052] Preferably, the growth described in step (3) is carried out under the condition of ammonia gas being introduced, with a flow rate of 0.5~100 slm, for example, it can be 0.5 slm, 1 slm, 5 slm, 10 slm, 25 slm, 50 slm, 80 slm or 100 slm, but is not limited to the listed values. Other unlisted values ​​within the range are also applicable.

[0053] As a preferred embodiment of the preparation method described in the second aspect of the present invention, the preparation method includes the following steps:

[0054] (1) Under the conditions of a temperature of 500~1100℃, a reaction chamber pressure of 20~500 torr, and a TMAl flow rate of 200~300 slm, ammonia gas with a flow rate of 0.5~50 slm is introduced to grow a buffer layer on the surface of the substrate.

[0055] (2) Under the conditions of a temperature of 500~1100℃, a reaction chamber pressure of 20~500 torr, and a TMA1 flow rate of 10-250 slm, ammonia gas with a flow rate of 0.5~50 slm is introduced to grow a stress-regulating layer on the surface of the obtained buffer layer.

[0056] (3) Under the conditions of temperature 500~1100℃, reaction chamber pressure 20~500 torr, and TMA1 flow rate 10~300 slm, ammonia gas with a flow rate of 0.5~100 slm is introduced to grow a drift layer on the surface of the obtained stress adjustment layer.

[0057] Thirdly, the present invention provides a power device comprising a semiconductor epitaxial structure as described in the first aspect.

[0058] Fourthly, the present invention provides a radio frequency device comprising a semiconductor epitaxial structure as described in the first aspect.

[0059] Based on the above technical solutions, the beneficial effects of the present invention are as follows:

[0060] This invention grows a stress-regulating layer between a buffer layer and a drift layer. The stress-regulating layer contains semiconductor material and is doped with a dopant material. This allows the stress-regulating layer to mitigate and tilt screw dislocations and edge dislocations caused by differences in lattice constants and thermal expansion coefficients between the buffer layer and the drift layer. This reduces the dislocations in the drift layer, thereby improving the quality of the crystal and enhancing the voltage withstand capability of the semiconductor material. Attached Figure Description

[0061] Figure 1 This is a schematic diagram of the semiconductor epitaxial structure described in Examples 1-3.

[0062] Figure 2 This is a schematic diagram of the semiconductor epitaxial structure described in Example 4.

[0063] Among them, 1-substrate, 2-buffer layer, 3-stress adjustment layer with single-layer structure, 4-drift layer, and 5-stress adjustment layer with composite layer structure. Detailed Implementation

[0064] The technical solution of the present invention will be further described below with reference to the accompanying drawings and specific embodiments. However, the following examples are merely simplified examples of the present invention and do not represent or limit the scope of protection of the present invention. The scope of protection of the present invention is determined by the claims.

[0065] Example 1

[0066] This embodiment provides a semiconductor epitaxial structure ( Figure 1 The semiconductor epitaxial structure includes a substrate 1, a buffer layer 2, a stress adjustment layer 3, and a drift layer 4 stacked together.

[0067] The substrate 1 is made of Al2O3 and has a thickness of 350 μm.

[0068] The buffer layer 2 is made of AlN and has a thickness of 250 nm.

[0069] The stress-regulating layer 3 is a single-layer structure composed of the semiconductor material AlN and a dopant material. The doping concentration of the dopant element Mg in the stress-regulating layer 3 is 1.0 × E18 atoms / cm³. 3 The stress-adjusting layer 3 has a thickness of 2 μm.

[0070] The drift layer 4 is made of AlGaN and has a thickness of 25 μm.

[0071] The method for preparing the semiconductor epitaxial structure includes the following steps:

[0072] (1) Under the conditions of 800℃, 260 torr in reaction chamber pressure and 250 slm in TMA1 flow rate, ammonia gas with a flow rate of 25 slm is introduced to grow a buffer layer 2 on the surface of substrate 1.

[0073] (2) Under the conditions of 800℃, 260 torr in reaction chamber pressure and 130 slm in TMA1 flow rate, ammonia gas with a flow rate of 25 slm is introduced to grow stress adjustment layer 3 on the surface of the obtained buffer layer 2.

[0074] (3) Under the conditions of 800℃, 260 torr in reaction chamber pressure and 150 slm TMA1 flow rate, ammonia gas with a flow rate of 50 slm is introduced to grow a drift layer 4 on the surface of the obtained stress adjustment layer 3.

[0075] Example 2

[0076] This embodiment provides a semiconductor epitaxial structure ( Figure 1 The semiconductor epitaxial structure includes a substrate 1, a buffer layer 2, a stress adjustment layer 3, and a drift layer 4 stacked together.

[0077] The substrate 1 is made of GaN and has a thickness of 400 μm.

[0078] The buffer layer 2 is made of AlN and has a thickness of 1 nm.

[0079] The stress-adjusting layer 3 is a single-layer structure, which is made of semiconductor material Al. 0.6 Ga 0.4 The nitrogen and doped material form Fe6N2, and the doping concentration of Fe in the stress-regulating layer 3 is 1.0 × E17 atoms / cm. 3 The stress-adjusting layer 3 has a thickness of 0.1 μm.

[0080] The drift layer 4 is made of AlInN and has a thickness of 1 μm.

[0081] The method for preparing the semiconductor epitaxial structure includes the following steps:

[0082] (1) Under the conditions of 500℃, 500 torr pressure in reaction chamber and 300 slm flow rate of TMAl, ammonia gas with a flow rate of 50 slm is introduced to grow a buffer layer 2 on the surface of substrate 1.

[0083] (2) Under the conditions of a temperature of 500℃, a reaction chamber pressure of 500 torr, and a TMA1 flow rate of 250 slm, ammonia gas with a flow rate of 50 slm is introduced to grow a stress-adjusting layer 3 on the surface of the obtained buffer layer 2.

[0084] (3) Under the conditions of 500℃, 20 torr pressure in the reaction chamber and 10 slm flow rate of TMA1, ammonia gas with a flow rate of 0.5 slm is introduced to grow a drift layer 4 on the surface of the obtained stress adjustment layer 3.

[0085] Example 3

[0086] This embodiment provides a semiconductor epitaxial structure ( Figure 1 The semiconductor epitaxial structure includes a substrate 1, a buffer layer 2, a stress adjustment layer 3, and a drift layer 4 stacked together.

[0087] The substrate 1 is made of Si and has a thickness of 500 μm.

[0088] The buffer layer 2 is made of AlN and has a thickness of 500 nm.

[0089] The stress-adjusting layer 3 is a single-layer structure, which is made of semiconductor material In. 0.3 Al 0.3 Ga 0.4The nitrogen and doped material form Be3N2, and the doping concentration of the dopant element Be in the stress-adjusting layer 3 is 1.0 × E19 atoms / cm. 3 The stress-adjusting layer 3 has a thickness of 50 μm.

[0090] The drift layer 4 is made of AlInGaN and has a thickness of 50 μm.

[0091] The method for preparing the semiconductor epitaxial structure includes the following steps:

[0092] (1) Under the conditions of 1100℃, 20 torr pressure in reaction chamber and 200 slm flow rate of TMAl, ammonia gas with a flow rate of 0.5 slm is introduced to grow a buffer layer 2 on the surface of substrate 1.

[0093] (2) Under the conditions of a temperature of 1100℃, a reaction chamber pressure of 20 torr, and a TMA1 flow rate of 250 slm, ammonia gas with a flow rate of 0.5 slm is introduced to grow a stress-regulating layer 3 on the surface of the obtained buffer layer 2.

[0094] (3) Under the conditions of 1100℃, 500 torr in reaction chamber pressure and 300 slm in TMA1 flow rate, ammonia gas with a flow rate of 100 slm is introduced to grow a drift layer 4 on the surface of the obtained stress adjustment layer 3.

[0095] Example 4

[0096] This embodiment provides a semiconductor epitaxial structure ( Figure 2 The semiconductor epitaxial structure includes a substrate 1, a buffer layer 2, a stress adjustment layer 5, and a drift layer 4 stacked together.

[0097] The substrate 1 is made of SiC and has a thickness of 350 μm.

[0098] The buffer layer 2 is made of AlN and has a thickness of 300 nm.

[0099] The stress-adjusting layer 5 is a composite layer structure in which adjacent layers are periodically stacked, with a period of 2. One of the adjacent layers is composed of semiconductor material AlN and doped material Mg3N2, and the other layer is composed of semiconductor material Al 0.7 Ga 0.3 The stress-regulating layer 5 is composed of nitrogen and doped material Mg3N2, with the doping concentration of Mg in the stress-regulating layer 5 being 1.0 × E18 atoms / cm. 3 The stress-adjusting layer 5 has a thickness of 2 μm.

[0100] The drift layer 4 is made of AlGaN and has a thickness of 25 μm.

[0101] The method for preparing the semiconductor epitaxial structure includes the following steps:

[0102] (1) Under the conditions of 800℃, 260 torr in reaction chamber pressure and 250 slm in TMA1 flow rate, ammonia gas with a flow rate of 25 slm is introduced to grow a buffer layer 2 on the surface of substrate 1.

[0103] (2) Under the conditions of 800℃, 260 torr in reaction chamber pressure and 130 slm in TMA1 flow rate, ammonia gas with a flow rate of 25 slm is introduced to grow stress adjustment layer 5 on the surface of the obtained buffer layer 2.

[0104] (3) Under the conditions of 800℃, 260 torr in reaction chamber pressure and 150 slm TMA1 flow rate, ammonia gas with a flow rate of 50 slm is introduced to grow a drift layer 4 on the surface of the obtained stress adjustment layer 5.

[0105] Example 5

[0106] This embodiment provides a semiconductor epitaxial structure, which includes a substrate, a buffer layer, a stress adjustment layer and a drift layer stacked together.

[0107] The substrate is made of AlN and has a thickness of 400 μm.

[0108] The buffer layer is made of AlN and has a thickness of 1 nm.

[0109] The stress-regulating layer is a composite layer structure in which adjacent layers are periodically stacked, with each period consisting of one layer. One of the adjacent layers is composed of GaN semiconductor material and CBr4 doping material, and the other layer is composed of Al semiconductor material. 0.7 Ga 0.3 The stress-regulating layer is composed of nitrogen and doped graphite, with the doping concentration of element C in the layer being 1.0 × E17 atoms / cm. 3 The thickness of the stress-adjusting layer is 0.1 μm.

[0110] The drift layer is made of AlN and has a thickness of 1 μm.

[0111] The method for preparing the semiconductor epitaxial structure includes the following steps:

[0112] (1) Under the conditions of 500℃, 500 torr pressure in reaction chamber and 300 slm flow rate of TMAl, ammonia gas with a flow rate of 50 slm is introduced to grow a buffer layer on the surface of the substrate.

[0113] (2) Under the conditions of a temperature of 500℃, a reaction chamber pressure of 500 torr, and a TMA flow rate of 250 slm, ammonia gas with a flow rate of 50 slm is introduced to grow a stress-regulating layer on the surface of the obtained buffer layer.

[0114] (3) Under the conditions of 500℃, 20 torr reaction chamber pressure and 10 slm TMAl flow rate, ammonia gas with a flow rate of 0.5 slm is introduced to grow a drift layer 4 on the surface of the obtained stress adjustment layer 5.

[0115] Example 6

[0116] This embodiment provides a semiconductor epitaxial structure, which includes a substrate, a buffer layer, a stress adjustment layer and a drift layer stacked together.

[0117] The substrate is made of Si and has a thickness of 350 μm.

[0118] The buffer layer is made of AlN and has a thickness of 500 nm.

[0119] The stress-regulating layer is a composite layer structure, in which each pair of adjacent layers is periodically stacked, with a period of 100. One of the adjacent layers is made of semiconductor material In. 0.3 Al 0.3 Ga 0.4 The layer consists of N and the doped material Be3N2, and the other layer is composed of the semiconductor material Al. 0.7 Ga 0.3 The stress-regulating layer is composed of nitrogen and doped material Be3N2, with the doping concentration of the dopant element Be in the layer being 1.0 × E19 atoms / cm. 3 The thickness of the stress-adjusting layer is 50 μm.

[0120] The drift layer is made of AlInGaN and has a thickness of 50 μm.

[0121] The method for preparing the semiconductor epitaxial structure includes the following steps:

[0122] (1) Under the conditions of 1100℃, 20 torr reaction chamber pressure, and 200 slm TMA flow rate, ammonia gas with a flow rate of 0.5 slm was introduced to grow a buffer layer on the surface of the substrate.

[0123] (2) Under the conditions of 1100℃, 20 torr pressure in the reaction chamber and 250 slm flow rate of TMA1, ammonia gas with a flow rate of 0.5 slm is introduced to grow a stress-regulating layer on the surface of the obtained buffer layer.

[0124] (3) Under the conditions of 1100℃, 500 torr in reaction chamber pressure and 300 slm in TMA1 flow rate, ammonia gas with a flow rate of 100 slm is introduced to grow a drift layer 4 on the surface of the obtained stress adjustment layer 5.

[0125] Example 7

[0126] This embodiment provides a semiconductor epitaxial structure, wherein the doping concentration of the dopant element Mg in the stress-regulating layer is 8.0 × E16 atoms / cm. 3 Except for the content of other components and process parameters, they are the same as in Example 1.

[0127] Example 8

[0128] This embodiment provides a semiconductor epitaxial structure, wherein the doping concentration of the dopant element Mg in the stress-regulating layer is 1.2 × E19 atoms / cm. 3 Except for the content of other components and process parameters, they are the same as in Example 1.

[0129] Example 9

[0130] This embodiment provides a semiconductor epitaxial structure, except that the thickness of the stress adjustment layer is 80 nm, and the other composition and process parameters are the same as those in Embodiment 1.

[0131] Example 10

[0132] This embodiment provides a semiconductor epitaxial structure, except that the thickness of the stress adjustment layer is 52 μm, and the other composition and process parameters are the same as those in Embodiment 1.

[0133] Example 11

[0134] This embodiment provides a semiconductor epitaxial structure, except that the doping material Mg3N2 is replaced with Ca3N2 of equal doping concentration, and the other composition and process parameters are the same as in Embodiment 1.

[0135] Example 12

[0136] This embodiment provides a semiconductor epitaxial structure, except that the doping material Mg3N2 is replaced with CoN with the same doping concentration, and the other composition and process parameters are the same as in Embodiment 2.

[0137] Example 13

[0138] This embodiment provides a semiconductor epitaxial structure, except that the doping material graphite is replaced with Si with the same doping concentration, and the other composition and process parameters are the same as in Embodiment 5.

[0139] Example 14

[0140] This embodiment provides a semiconductor epitaxial structure, except that the number of cycles is 120, and the other composition and process parameters are the same as in Embodiment 4.

[0141] Comparative Example 1

[0142] This comparative example provides a semiconductor epitaxial structure. Except for the absence of a stress-adjusting layer and step (2) in the preparation method, the composition and process steps are the same as in Example 1.

[0143] Comparative Example 2

[0144] This comparative example provides a semiconductor epitaxial structure, which is identical to Example 1 in terms of composition, content, and process steps, except that the stress adjustment layer is undoped.

[0145] The following conclusions can be drawn from the above semiconductor epitaxial structures:

[0146] (1) As can be seen from Examples 1-6, the present invention grows a stress adjustment layer between the buffer layer and the drift layer. The stress adjustment layer contains semiconductor materials and adds doping materials, so that the screw dislocations and edge dislocations generated between the buffer layer and the drift layer due to the difference in lattice constant and thermal expansion coefficient are reduced and tilted by the stress adjustment layer, so that the dislocations in the drift layer are slowed down, thereby improving the quality of the crystal and thus improving the voltage resistance of the semiconductor material.

[0147] (2) A comparison of Examples 7 and 8 with Example 1 shows that when the doping concentration is not between 1.0×E17 and 1.0×E19 atoms / cm 3 When the voltage withstand capability of the resulting semiconductor epitaxial structure decreases, the electron mobility decreases, and the crystal quality becomes poor.

[0148] (3) As can be seen from the comparison between Examples 9 and 10 and Example 1, when the thickness of the stress adjustment layer is not in the range of 0.1~50μm, the withstand voltage of the obtained semiconductor epitaxial structure decreases, the electron mobility decreases, and the crystal quality is poor.

[0149] (4) As can be seen from the comparison between Examples 11-13 and Example 1, when the doping element is not carbon, beryllium, magnesium or iron provided by the present invention, the withstand voltage of the obtained semiconductor epitaxial structure is reduced, the electron mobility is reduced and the crystal quality is poor.

[0150] (5) As can be seen from the comparison between Example 14 and Example 1, when the period of the composite layer structure is not between 1 and 100, the withstand voltage of the obtained semiconductor epitaxial structure decreases, the electron mobility decreases, and the crystal quality is poor.

[0151] (6) As can be seen from the comparison of Comparative Examples 1 and 2 with Example 1, when there is no stress adjustment layer or no doping, the withstand voltage of the obtained semiconductor epitaxial structure is reduced, the electron mobility is reduced, and the crystal quality is poor.

[0152] In summary, this invention grows a stress-regulating layer between a buffer layer and a drift layer. The stress-regulating layer contains semiconductor materials and is doped with other materials. This allows screw dislocations and edge dislocations caused by differences in lattice constants and thermal expansion coefficients between the buffer layer and the drift layer to be reduced and tilted by the stress-regulating layer. This slows down the dislocations in the drift layer, thereby improving the quality of the crystal and enhancing the voltage withstand capability of the semiconductor material.

[0153] The present invention has been illustrated with the above embodiments to illustrate its detailed structural features. However, the present invention is not limited to the above detailed structural features, that is, it does not mean that the present invention must rely on the above detailed structural features to be implemented. Those skilled in the art should understand that any improvements to the present invention, equivalent substitutions for the components used in the present invention, additions of auxiliary components, and selection of specific methods, etc., all fall within the protection scope and disclosure scope of the present invention.

Claims

1. A semiconductor epitaxial structure, characterized in that, The semiconductor epitaxial structure includes a substrate, a buffer layer, a stress-adjusting layer, and a drift layer stacked together; The stress-regulating layer comprises a semiconductor material and a doped material; the thickness of the stress-regulating layer is 5~50μm. The doping element in the doped material includes any one or a combination of at least two of carbon, beryllium, magnesium, or iron; the content of the doping element in the stress-regulating layer is 5.0 × E18 ~ 1.0 × E19 atoms / cm. 3 ; The substrate comprises any one or a combination of at least two of Al2O3, GaN, GaO, AlN, Si, or SiC; the thickness of the substrate is 350 μm or more; the material of the buffer layer comprises AlInN; the drift layer comprises any one or a combination of at least two of AlN, AlGaN, or AlInGaN. The semiconductor material includes In b Al a Ga 1-a-b N, where 0 < a < 1, 0 < b < 1.

2. The semiconductor epitaxial structure according to claim 1, characterized in that, The stress-adjusting layer may be a single-layer structure or a composite-layer structure.

3. The semiconductor epitaxial structure according to claim 2, characterized in that, The semiconductor material in the single-layer structure includes In. b Al a Ga 1-a-b N.

4. The semiconductor epitaxial structure according to claim 2, characterized in that, The composite layer structure comprises at least two layers.

5. The semiconductor epitaxial structure according to claim 4, characterized in that, In the composite layer structure, each pair of adjacent layers is periodically stacked.

6. The semiconductor epitaxial structure according to claim 5, characterized in that, The semiconductor materials in the two adjacent layers include AlN, GaN, and Al. x Ga 1-x N or In b Al a Ga 1-a-b N, where 0 < x < 1.

7. The semiconductor epitaxial structure according to claim 5, characterized in that, The number of cycles is 1 to 100.

8. The semiconductor epitaxial structure according to claim 1, characterized in that, The thickness of the buffer layer is 1~500nm.

9. The semiconductor epitaxial structure according to claim 1, characterized in that, The thickness of the drift layer is 1~50μm.

10. A method for preparing a semiconductor epitaxial structure according to any one of claims 1-9, characterized in that, The preparation method includes the following steps: (1) A buffer layer is grown on the surface of the substrate; (2) A stress-regulating layer is grown on the surface of the obtained buffer layer; (3) A drift layer is grown on the surface of the obtained stress-adjusting layer.

11. The preparation method according to claim 10, characterized in that, The growth temperature in step (1) is 500~1100℃.

12. The preparation method according to claim 10, characterized in that, The reaction chamber pressure for growth in step (1) is 20~500 torr.

13. The preparation method according to claim 10, characterized in that, The flow rate of the TMAl grown in step (1) is 200~300 slm.

14. The preparation method according to claim 10, characterized in that, The growth described in step (1) is carried out under the condition of ammonia gas being introduced, with a flow rate of 0.5~50 slm.

15. The preparation method according to claim 10, characterized in that, The growth temperature in step (2) is 500~1100℃.

16. The preparation method according to claim 10, characterized in that, The reaction chamber pressure for growth in step (2) is 20~500 torr.

17. The preparation method according to claim 10, characterized in that, The flow rate of the TMAl grown in step (2) is 10~250 slm.

18. The preparation method according to claim 10, characterized in that, The growth described in step (2) is carried out under the condition of ammonia gas being introduced, with a flow rate of 0.5~50 slm.

19. The preparation method according to claim 10, characterized in that, The growth temperature in step (3) is 500~1100℃.

20. The preparation method according to claim 10, characterized in that, The reaction chamber pressure for growth in step (3) is 20~500 torr.

21. The preparation method according to claim 10, characterized in that, The flow rate of the TMAl grown in step (3) is 10~300 slm.

22. The preparation method according to claim 10, characterized in that, The growth described in step (3) is carried out under the condition of ammonia gas being introduced, with a flow rate of 0.5~100 slm.

23. The preparation method according to claim 10, characterized in that, The preparation method includes the following steps: (1) Under the conditions of a temperature of 500~1100℃, a reaction chamber pressure of 20~500 torr, and a TMAl flow rate of 200~300 slm, ammonia gas with a flow rate of 0.5~50 slm is introduced to grow a buffer layer on the surface of the substrate. (2) Under the conditions of a temperature of 500~1100℃, a reaction chamber pressure of 20~500 torr, and a TMA1 flow rate of 10~250 slm, ammonia gas with a flow rate of 0.5~50 slm is introduced to grow a stress-regulating layer on the surface of the obtained buffer layer. (3) Under the conditions of temperature of 500~1100℃, reaction chamber pressure of 20~500 torr, and TMA1 flow rate of 10~300 slm, ammonia gas with a flow rate of 0.5~100 slm is introduced to grow a drift layer on the surface of the obtained stress adjustment layer.

24. A power device, characterized in that, The power device includes a semiconductor epitaxial structure as described in any one of claims 1-9.

25. A radio frequency device, characterized in that, The radio frequency device includes a semiconductor epitaxial structure as described in any one of claims 1-9.

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