Bipolar transistor

Abstract

A bipolar transistor mainly comprises an emitter region, a base region and a collector region, wherein the edge of the emitter region is cut to the edge of the base region. In addition, the edge of the base region is cut to the edge of the collector region, the edge of the emitter region is cut to the edges of the base region and the collector region, and the edge width of the emitter region is equal to the edge width of the base region. In addition, according to a top view angle of the bipolar transistor, the base region and the collector region each comprise a rectangle.

Description

[0001] This application is a divisional application of Chinese invention patent application (application number: 201710311951.4, application date: May 5, 2017, invention title: bipolar transistor). Technical Field

[0002] The present invention relates to a bipolar transistor having a low collector and base area. Background Technology

[0003] Bipolar junction transistors (BJTs) are primarily composed of three semiconductor materials with varying degrees of doping. Charge flow within the transistor is mainly due to the diffusion and drift of charge carriers at the PN junction. Taking an NPN transistor as an example, electrons from the highly doped emitter region diffuse to the base. In the base region, holes are the majority carriers, while electrons are the minority carriers. Because the base region is very thin, these electrons drift to the collector, forming a collector current. Therefore, BJTs are classified as minority carrier devices. BJTs can amplify signals and possess good power control, high-speed operation, and durability. Therefore, they are commonly used to construct amplifier circuits or drive devices such as speakers and motors, and are widely applied in aerospace engineering, medical devices, and robotics.

[0004] However, the design of bipolar transistors is still not ideal, especially since the base and collector regions occupy too large an area, thus affecting device performance. Therefore, how to improve the current bipolar transistor structure is an important issue at present. Summary of the Invention

[0005] This invention discloses a bipolar transistor, which mainly includes an emitter region, a base region, and a collector region, wherein the edge of the emitter region is flush with the edge of the base region. Furthermore, the edge of the base region is flush with the edge of the collector region, and the edge of the emitter region is flush with the edges of both the base and collector regions, with the edge width of the emitter region equal to the edge width of the base region. Additionally, from a top-view perspective of the bipolar transistor, both the base region and the collector region are rectangular.

[0006] Another embodiment of the present invention discloses a bipolar transistor, which mainly includes an emitter region, a base region, and a collector region, wherein each of the emitter region, the base region, and the collector region includes a fin-like structure. The emitter region, the base region, and the collector region extend along a first direction, while the fin-like structure extends along a second direction. Furthermore, the edge of the emitter region is flush with the edge of the base region, the edge of the base region is flush with the edge of the collector region, and the edge of the emitter region is flush with the edges of both the base region and the collector region, with the edge width of the emitter region equal to the edge width of the base region. Additionally, from a top-view perspective of the bipolar transistor, both the base region and the collector region are rectangular. Attached Figure Description

[0007] Figure 1 This is a schematic diagram of a bipolar transistor according to a first embodiment of the present invention;

[0008] Figure 2 for Figure 1 A schematic cross-section along the tangent AA';

[0009] Figure 3 This is a schematic diagram of a bipolar transistor according to a second embodiment of the present invention;

[0010] Figure 4 for Figure 1 A schematic cross-sectional view along the tangent BB'.

[0011] Explanation of main component symbols

[0012] 12 Substrate 14 Emitter Region

[0013] 16 Base region 18 Collector region

[0014] 20 First base region 22 Second base region

[0015] 24 Episode 1: Polar Regions 26 Episode 2: Polar Regions

[0016] 28 Shallow trench isolation 30 N trap

[0017] 32 P-well 34 N-well

[0018] 36 Deep N-well

[0019] 42 Substrate 44 Emitter Region

[0020] 46 Base region 48 Collector region

[0021] 50 Fin-like structure 52 Shallow groove isolation

[0022] 54 First firing region 56 Second firing region

[0023] 58 First base region 60 Second base region

[0024] 62 Episode 1: Polar Regions 64 Episode 2: Polar Regions

[0025] 66 N-well 68 P-well

[0026] 70 N-well 72 Deep N-well

[0027] 74 Contact plug 76 Contact plug

[0028] 78 Contact plug 80 Contact plug

[0029] 82 Contact plug 84 Contact plug Detailed Implementation

[0030] Please refer to Figures 1 to 2 , Figures 1 to 2 This is a schematic diagram of a bipolar transistor according to a first embodiment of the present invention, wherein... Figure 1 This is a top view of a bipolar transistor. Figure 2 Then it is Figure 1 A schematic cross-sectional view along the tangent AA'. (See diagram below.) Figure 1 and Figure 2 As shown, the bipolar transistor mainly includes an emitter region 14, two base regions 16, and two collector regions 18 disposed on a substrate 12. The substrate 12 is preferably made of a semiconductor material, such as a silicon substrate, an epitaxial silicon substrate, a silicon-germanium substrate, a silicon carbide substrate, or a silicon-on-insulator (SOI) substrate, but is not limited thereto.

[0031] In this embodiment, a shallow trench isolation 28 is preferably provided within the substrate 12 to define and separate the locations of the emitter region 14, the base region 16, and the collector region 18. Figure 1 As shown, the bipolar transistor disclosed in this embodiment has an emitter region 14 disposed in the middle, two base regions 16 including a first base region 20 and a second base region 22 respectively disposed above and below the emitter region 14, and two collector regions 18 including a first collector region 24 and a second collector region 26 respectively disposed above and below the first base region 20 and the second base region 22. The emitter region 14, base region 16, and collector region 18 are preferably arranged in an alternating manner, or, in detail, the first collector region 24, first base region 20, emitter region 14, second base region 22, and second collector region 26 are preferably arranged along a first direction, for example, in the Y direction of this embodiment, in a straight line from top to bottom.

[0032] From a top-view perspective, the emitter region 14, the two base regions 16, and the two collector regions 18 are all rectangular. The emitter region 14, located in the middle, is preferably a square. The two base regions 16 and 18 are both rectangles. The first base region 20 and the second base region 22 are preferably smaller rectangles, while the first collector region 24 and the second collector region 26 are preferably larger rectangles. Furthermore, the first collector region 24, the first base region 20, the emitter region 14, the second base region 22, and the second collector region 26 preferably have the same width. Therefore, the left and right sidewalls or edges of the first collector region 24, the first base region 20, the emitter region 14, the second base region 22, and the second collector region 26 are preferably tangent to each other along the Y-direction.

[0033] In this embodiment, the bipolar transistor is mainly composed of an NPN transistor. For example, the first collector region 24 includes an N+ region, the first base region 20 preferably includes a P+ region, the emitter region 14 preferably includes an N+ region, the second base region 22 includes another P+ region, and the second collector region 26 preferably includes another N+ region.

[0034] Among them, an N-well 30 is provided in the substrate directly below the first collector region 24, a P-well 32 is provided in the substrate 12 directly below the first base region 20, emitter region 14 and the second base region 22, another N-well 34 is provided in the substrate 12 directly below the second collector region 26, and a deep N-well 36 is provided in the substrate 12 below the N-well 30, P-well 32 and N-well 34.

[0035] Furthermore, the emitter region 14 is a region with a high doping concentration, which mainly injects free electrons into the base region 20 through the P-well 32. Therefore, although the emitter region 14 and the two collector regions 18 in this embodiment are both composed of N-type doped regions, the N+ region concentration of the emitter region 14 is preferably greater than the N+ region concentration of the first collector region 24 and the second collector region 26.

[0036] From an operational perspective, an NPN bipolar transistor can be viewed as two diodes joined together with a common anode. Under normal operating conditions, the emitter junction (the PN junction between base region 16 and emitter region 14) is forward biased, while the collector junction (the PN junction between base region 16 and collector region 18) is reverse biased. Without an applied voltage, the electron concentration in the N-region of the emitter junction is greater than that in the P-region, causing some electrons to diffuse into the P-region. Similarly, some holes in the P-region will diffuse into the N-region. This creates a space charge region, or depletion layer, on the emitter junction, generating an internal electric field pointing from the N-region to the P-region. This electric field hinders further diffusion, achieving a dynamic equilibrium. If a forward voltage is applied to the emitter junction, the dynamic equilibrium between carrier diffusion and the internal electric field in the depletion layer is broken, allowing thermally excited electrons to be injected into the base region.

[0037] It should be noted that although the bipolar transistor disclosed in the above embodiments is an NPN type transistor, it is not limited to this type. The present invention can also apply the above bipolar transistor structure to a PNP type transistor. For example, the conductivity of the emitter region 14, the two base regions 16, the two collector regions 18 and all the well regions in the substrate 12 can be reversed to form another bipolar transistor with a PNP type transistor architecture. This embodiment is also within the scope of the present invention.

[0038] Please continue to refer to Figures 3 to 4 , Figures 3 to 4This is a schematic diagram of a bipolar transistor according to a second embodiment of the present invention, wherein... Figure 3 This is a top view of a bipolar transistor. Figure 4 Then it is Figure 3 A schematic cross-sectional view along the tangent BB'. (See diagram below.) Figure 3 and Figure 4 As shown, the bipolar transistor mainly comprises two emitter regions 44, two base regions 46, and two collector regions 48 disposed on a substrate 52. Each emitter region 44, base region 46, and collector region 48 respectively includes at least one fin structure 50, such as... Figure 3 As shown, each emitter region 44, base region 46, and collector region 48 contains multiple fin structures 50, and the multiple fin structures 50 in each region can be selectively electrically connected to each other through a contact plug. In detail, the emitter region 44 is electrically connected to the multiple fin structures 50 therein using contact plugs 74 and 76, the base region 46 is electrically connected to the multiple fin structures 50 therein using contact plugs 78 and 80, and the collector region 48 is electrically connected to the multiple fin structures 50 therein using contact plugs 82 and 84.

[0039] Overall, if multiple fin structures 50 are electrically connected simultaneously using contact plugs as described above, then each emitter region 44, base region 46, and collector region 48 of the multiple fin structures 50 preferably constitutes a bipolar transistor. Conversely, without the aforementioned contact plugs, this embodiment preferably includes multiple bipolar transistors, wherein the emitter region 44, base region 46, and collector region 48 of each bipolar transistor are interconnected only through a single fin structure 50. As in the aforementioned embodiments, the substrate 42 is preferably made of a semiconductor material, such as a silicon substrate, an epitaxial silicon substrate, a silicon-germanium substrate, a silicon carbide substrate, or a silicon-on-insulator (SOI) substrate, but is not limited thereto.

[0040] In this embodiment, the fin structure 50 is preferably fabricated using techniques such as sidewall image transfer (SIT). The process generally includes: providing a layout pattern to a computer system and performing appropriate calculations to define the corresponding pattern in a photomask. Subsequently, multiple equidistant and equally wide patterned sacrificial layers are formed on the substrate using photolithography and etching processes, giving each layer a strip-like appearance. Then, deposition and etching processes are sequentially performed to form spacers on the sidewalls of the patterned sacrificial layers. The patterned sacrificial layers are then removed, and etching is performed under the cover of the spacers, transferring the pattern formed by the spacers into the substrate. Finally, a fin cut process is performed to obtain the desired patterned structure, such as a strip-shaped patterned fin structure.

[0041] In addition, the formation of the fin structure 50 may also include first forming a patterned mask (not shown) on the substrate 42, and then transferring the pattern of the patterned mask to the substrate 42 through an etching process to form the fin structure 50. Alternatively, the fin structure 50 may be formed by first forming a patterned hard mask layer (not shown) on the substrate 42, and then using an epitaxial fabrication process to grow a semiconductor layer, such as silicon-germanium, on the substrate 42 exposed above the patterned hard mask layer. This semiconductor layer can then serve as the corresponding fin structure 50. These embodiments of forming the fin structure 50 are all within the scope of this invention.

[0042] In this embodiment, the substrate 42 also has multiple shallow trench isolations 52, which define and separate the locations of the emitter region 44, the base region 46, and the collector region 48. Figure 3 As shown, the bipolar transistor disclosed in this embodiment has two emitter regions 44, including a first emitter region 54 and a second emitter region 56 disposed in the middle, two base regions 46, including a first base region 58 and a second base region 60 respectively disposed above and below the first emitter region 54 and the second emitter region 56, and two collector regions 48, including a first collector region 62 and a second collector region 64 respectively disposed above and below the first base region 58 and the second base region 60. Preferably, the emitter regions 44, base regions 46, and collector regions 48 are arranged in an alternating manner, or, in detail, the first collector region 62, first base region 58, first emitter region 54, second emitter region 56, second base region 60, and second collector region 64 are preferably arranged along a first direction, for example, in the Y direction of this embodiment, in a straight line from top to bottom.

[0043] From a top-view perspective, the two emitter regions 44, the two base regions 46, and the two collector regions 48 are all rectangular or more rectangular. The areas of the first emitter regions 54 and the second emitter regions 56 located in the middle are preferably larger than the areas of the first base regions 58 and the second base regions 60, as well as the areas of the first collector regions 62 and the second collector regions 64. The areas of the first collector regions 62 and the second collector regions 64 can be equal to or slightly larger than the areas of the first base regions 58 and the second base regions 60.

[0044] In addition, the first collector region 62, the first base region 58, the first emitter region 54, the second emitter region 56, the second base region 60, and the second collector region 64 preferably have the same width. Therefore, the left and right sidewalls or edges of the first collector region 62, the first base region 58, the first emitter region 54, the second emitter region 56, the second base region 60, and the second collector region 64 are preferably aligned with each other along the Y direction.

[0045] In this embodiment, the bipolar transistor is mainly composed of an NPN type transistor. For example, the first collector region 62 includes an N+ region disposed within the fin structure 50, the first base region 58 includes a P+ region disposed within the fin structure 50, the first emitter region 54 includes an N+ region disposed within the fin structure 50, the second emitter region 56 includes an N+ region disposed within the fin structure 50, the second base region 60 includes another P+ region disposed within the fin structure 50, and the second collector region 64 includes another N+ region disposed within the fin structure 50. The fin structure 50 of the first collector region 62 and the fin structure 58 of the first base region 58... Shallow trench isolation 52 is provided between the fins of the first base region 58 and the first emitter region 54, and they do not contact each other. Shallow trench isolation 52 is provided between the fins of the first emitter region 54 and the second emitter region 56, and they do not contact each other. Shallow trench isolation 52 is provided between the fins of the second emitter region 56 and the second base region 60, and they do not contact each other. Shallow trench isolation 52 is provided between the fins of the second base region 60 and the second collector region 64, and they do not contact each other. Furthermore, the emitter region 44 is preferably a region with a high doping concentration, mainly for injecting free electrons into the base region 62. Therefore, although both emitter regions 44 and both collector regions 48 in this embodiment are composed of N-type doped regions, the N+ region concentration of each emitter region 44 is preferably greater than the N+ region concentration of each collector region 48.

[0046] In addition, an N-well 66 is provided in the substrate 42 directly below the first collector region 62, a P-well 68 is provided in the substrate directly below the first base region 58, the first emitter region 54, the second emitter region 56 and the second base region 60, another N-well 70 is provided in the substrate 42 directly below the second collector region 64, and a deep N-well 72 is provided in the substrate 42 below the N-well 66, the P-well 68 and the N-well 70.

[0047] It should be noted that although the emitter region 44 is divided into two parts in this embodiment due to considerations of manufacturing process design rules, such as including the first emitter region 54 and the second emitter region 56, it is not limited to this state. According to an embodiment of the present invention, the first emitter region 54 and the second emitter region 56 can be merged into one emitter region to form the state in the first embodiment described above, where only a single emitter region 18 is provided between the first base region 20 and the second base region 22. This embodiment is also within the scope of the present invention.

[0048] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention should be included within the scope of the present invention.

Claims

1. A bipolar transistor, comprising: Radiant region; Base region; The collector region, wherein each of the emitter region, the base region, and the collector region comprises multiple fin-like structures; and A shallow trench is disposed between the emitter region and the base region, and between the base region and the collector region, wherein the two opposite sidewalls of each of the plurality of fin structures contained in each emitter region, the base region, and the collector region directly contact the shallow trench. According to a top-down view of the bipolar transistor, the emitter region, the base region, and the collector region extend along a first direction. Each of the plurality of fin structures includes two short sides and two long sides connecting the two short sides. The two long sides extend along a second direction, and the first direction is perpendicular to the second direction.

2. The bipolar transistor of claim 1, wherein the edge of the emitter region is flush with the edge of the base region.

3. The bipolar transistor of claim 1, wherein the edge of the base region is flush with the edge of the collector region.

4. The bipolar transistor of claim 1, wherein the edge of the emitter region is flush with the edges of the base region and the collector region.

5. The bipolar transistor of claim 1, wherein the base region comprises a first base region and a second base region.

6. The bipolar transistor of claim 5, wherein the shallow trench isolation is further disposed between the first base region and the second base region.

7. The bipolar transistor of claim 1, wherein the edge of the emitter region is equal to the edge of the base region.

8. The bipolar transistor of claim 7, wherein shallow trench isolation is further provided at the edge of the emitter region and the edge of the base region.

9. The bipolar transistor of claim 1, wherein the base region comprises a rectangle according to the top view of the bipolar transistor.

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