Thin film transistor and method of manufacturing the same

Abstract

This application discloses a thin-film transistor and a method for fabricating a thin-film transistor. The thin-film transistor includes a substrate, a gate, a gate insulating layer, an active layer, and a source-drain layer. The active layer is disposed on the gate insulating layer and is made of aluminum. The source and drain electrodes are disposed above the active layer. The active layer includes a first portion near the gate insulating layer and a second portion near the source-drain layer. The aluminum content of the first portion is higher than that of the second portion. By making the aluminum content of the first portion of the active layer near the gate insulating layer higher than that of the second portion near the source-drain layer, the mobility of the thin-film transistor is improved.

Description

Technical Field

[0001] This application relates to the field of display technology, specifically to a thin-film transistor and a method for fabricating a thin-film transistor. Background Technology

[0002] Metal oxide thin-film transistors (MOX) have mobility 10 to 100 times higher than amorphous silicon (ASW) MOX, meeting the demands of new high-end display products. Therefore, MOX and their display panels are receiving increasing attention from the industry. However, compared to low-temperature polycrystalline silicon (LTPS), MOX has lower stability and mobility.

[0003] Therefore, existing oxide thin-film transistors suffer from the technical problem of low mobility. Summary of the Invention

[0004] This application provides a thin-film transistor and a method for fabricating a thin-film transistor, which can alleviate the technical problem of low mobility in existing oxide thin-film transistors.

[0005] This application provides a thin-film transistor, including:

[0006] Substrate;

[0007] A gate, the gate being disposed above the substrate;

[0008] A gate insulating layer is disposed above the gate and the substrate;

[0009] An active layer is disposed on the gate insulating layer, and the active layer is made of materials including aluminum, gallium, and zinc.

[0010] A source-drain layer is disposed above the active layer. The source-drain layer includes a source and a drain, and the source and the drain are respectively connected to the active layer.

[0011] The active layer includes a first portion near the gate insulating layer and a second portion near the source-drain layer, wherein the aluminum content of the first portion is higher than that of the second portion.

[0012] Optionally, in some embodiments of this application, the gallium / zinc content of the second part is higher than that of the first part.

[0013] Optionally, in some embodiments of this application, the active layer includes a first portion, a second portion, and a third portion located between the first portion and the second portion, wherein the ratio of the thickness of the first portion / second portion to the thickness of the active layer ranges from 8% to 12%.

[0014] Optionally, in some embodiments of this application, the thickness of the first portion is equal to the thickness of the second portion.

[0015] Optionally, in some embodiments of this application, the active layer includes a first active sub-layer and a second active sub-layer, the first active sub-layer being disposed close to the gate insulating layer, the second active sub-layer being disposed close to the source-drain layer, and the aluminum content of the first active sub-layer being higher than the aluminum content of the second active sub-layer.

[0016] Optionally, in some embodiments of this application, the gallium / zinc content of the second active sublayer is higher than that of the first active sublayer.

[0017] Optionally, in some embodiments of this application, the material used to prepare the gate insulating layer includes aluminum oxide.

[0018] Optionally, in some embodiments of this application, the aluminum content of the first active sublayer ranges from 30% to 50%, the gallium content of the first active sublayer ranges from 20% to 30%, and the zinc content of the first active sublayer ranges from 30% to 40%.

[0019] Optionally, in some embodiments of this application, the aluminum content of the second active sublayer ranges from 10% to 30%, the gallium content of the second active sublayer ranges from 30% to 40%, and the zinc content of the second active sublayer ranges from 40% to 50%.

[0020] This application provides a method for fabricating a thin-film transistor, including:

[0021] Provide a substrate;

[0022] A gate and a gate insulating layer are formed on the substrate;

[0023] The first active sublayer is prepared on the gate insulating layer by sputtering with a first target material.

[0024] A second active sublayer is prepared on the first active sublayer by sputtering with a second target material, wherein the gallium / zinc content of the second target material is higher than that of the first target material, and the aluminum content of the first target material is higher than that of the second target material.

[0025] A source / drain layer is prepared above the second active sublayer.

[0026] Beneficial effects: The thin-film transistor provided in this application embodiment includes a gate insulating layer, an active layer, and a source-drain layer arranged sequentially. The active layer is made of aluminum. By making the aluminum content of the first part of the active layer close to the gate insulating layer higher than the aluminum content of the second part close to the source-drain layer, the mobility of the thin-film transistor is improved. Attached Figure Description

[0027] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a first cross-sectional schematic diagram of a thin-film transistor provided in an embodiment of this application;

[0029] Figure 2 This is a second cross-sectional schematic diagram of the thin-film transistor provided in the embodiments of this application;

[0030] Figure 3 This is a flowchart of the thin-film transistor fabrication method provided in the embodiments of this application.

[0031] Explanation of reference numerals in the attached figures:

[0032] Detailed Implementation

[0033] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application. In addition, it should be understood that the specific embodiments described herein are only for illustration and explanation of this application and are not intended to limit this application. In this application, unless otherwise stated, directional terms such as "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, specifically the drawing directions in the accompanying drawings; while "inner" and "outer" refer to the outline of the device.

[0034] Please see Figure 1The thin-film transistor 1 provided in this application includes a substrate 10, a gate 20, a gate insulating layer 30, an active layer 40, and a source / drain layer 50. The gate 20 is disposed above the substrate 10, the gate insulating layer 30 is disposed above the gate 20 and the substrate 10, and the active layer 40 is disposed on the gate insulating layer 30. The active layer 40 is made of aluminum, gallium, or zinc. The source / drain layer 50 is disposed above the active layer 40 and includes a source 501 and a drain 502. The electrode 501 and the drain electrode 502 are respectively connected to the active layer 40. The active layer 40 includes a first portion 401 near the gate insulating layer 30 and a second portion 402 near the source-drain layer 50. The aluminum content of the first portion 401 is higher than that of the second portion 402. By making the aluminum content of the first portion 401 of the active layer 40 near the gate insulating layer 30 higher than that of the second portion 402 near the source-drain layer 50, the mobility of the thin film transistor 1 is improved.

[0035] This application improves the mobility of the thin-film transistor 1 by making the aluminum content of the first portion 401 of the active layer 40 near the gate insulating layer 30 higher than the aluminum content of the second portion 402 near the source and drain layers 50, thereby solving the technical problem of low mobility in existing oxide thin-film transistors 1.

[0036] The technical solution of this application will now be described in conjunction with specific embodiments.

[0037] In one embodiment, please refer to Figure 1 The gallium / zinc content of the second part 402 is higher than that of the first part 401.

[0038] The gallium content range of the first part 401 is: 0.2≤Ga / (Al+Ga+Zn)≤0.3.

[0039] The zinc content range of the first part 401 is: 0.3≤Zn / (Al+Ga+Zn)≤0.4.

[0040] The gallium content range of the second part 402 is: 0.3≤Ga / (Al+Ga+Zn)≤0.4.

[0041] The zinc content range of the second part 402 is: 0.4≤Zn / (Al+Ga+Zn)≤0.5.

[0042] It is understandable that the high gallium / zinc content film layer of the second part 402 has a low carrier concentration and few defect states, which can improve the stability of the thin film transistor 1.

[0043] In this embodiment, by making the gallium / zinc content of the second portion 402 near the source / drain layer 50 higher than the gallium / zinc content of the first portion 401 near the gate insulating layer 30, the defect states of the second portion 402 are reduced, thereby improving the stability of the thin film transistor 1.

[0044] In one embodiment, the active layer 40 includes a first portion 401, a second portion 402, and a third portion 403 located between the first portion 401 and the second portion 402, wherein the ratio of the thickness of the first portion 401 / the second portion 402 to the thickness of the active layer 40 ranges from 8% to 12%.

[0045] The thickness of the first part 401 / the second part 402 can range from 4 nm to 6 nm.

[0046] The first portion 401 is disposed in contact with the gate insulating layer 30.

[0047] The second part 402 is configured to contact the source 501 and the drain 502.

[0048] Furthermore, the thickness of the first portion 401 / the second portion 402 is 10% of the thickness of the active layer 40.

[0049] It is understandable that the first part 401 is close to the gate insulating layer 30, which has a significant impact on the mobility of the thin film transistor 1.

[0050] It is understandable that the second part 402 is close to the source and drain layers 50, which has a significant impact on the stability of the thin film transistor 1.

[0051] In this embodiment, by limiting the thickness of the first portion 401, which has a greater impact on mobility, and the second portion 402, which has a greater impact on stability, the influence of the first portion 401 on the mobility of the thin-film transistor 1 is improved, while the influence of the second portion 402 on the stability of the thin-film transistor 1 is also improved.

[0052] In one embodiment, the source 501 and the drain 502 are directly disposed on the active layer 40 and the gate insulating layer 30.

[0053] In one embodiment, a passivation layer is further disposed above the active layer 40 and the gate insulating layer 30. The passivation layer is provided with a first via and a second via. The source electrode 501 is connected to the active layer 40 through the first via, and the drain electrode 502 is connected to the active layer 40 through the second via.

[0054] The source electrode 501 and the drain electrode 502 are connected to the second part 402 of the active layer 40.

[0055] In one embodiment, the thickness of the first portion 401 is equal to the thickness of the second portion 402.

[0056] The thickness of the first part 401 and the thickness of the second part 402 are both 5 nm.

[0057] In this embodiment, by making the thickness of the first part 401 and the second part 402 equal, the manufacturing process can be simplified and the cost reduced.

[0058] In one embodiment, please refer to Figure 2 The active layer 40 includes a first active sub-layer 404 and a second active sub-layer 405. The first active sub-layer 404 is disposed close to the gate insulating layer 30, and the second active sub-layer 405 is disposed close to the source-drain layer 50. The aluminum content of the first active sub-layer 404 is higher than that of the second active sub-layer 405.

[0059] The aluminum content of the first active sublayer 404 is in the range of 0.3≤Al / (Al+Ga+Zn)≤0.5.

[0060] The aluminum content of the second active sublayer 405 is in the range of 0.1≤Al / (Al+Ga+Zn)≤0.3.

[0061] It is understandable that aluminum has an atomic radius close to that of zinc. The first active sublayer 404 increases the aluminum content. Aluminum is a group III element and has one more valence electron than zinc. The valence electron is less bound and is more easily excited to generate free electrons, thereby improving the electron mobility of the semiconductor material.

[0062] In this embodiment, by increasing the aluminum content of the first active sublayer 404, the first active sublayer 404 has a greater impact on mobility than the second active sublayer 405, thereby improving the mobility of the thin film transistor 1.

[0063] In one embodiment, the gallium / zinc content of the second active sublayer 405 is higher than that of the first active sublayer 404.

[0064] The gallium content of the first active sublayer 404 is in the range of 0.2≤Ga / (Al+Ga+Zn)≤0.3.

[0065] The zinc content of the first active sublayer 404 is in the range of 0.3≤Zn / (Al+Ga+Zn)≤0.4.

[0066] The gallium content of the second active sublayer 405 is in the range of 0.3≤Ga / (Al+Ga+Zn)≤0.4.

[0067] The zinc content of the second active sublayer 405 is in the range of 0.4≤Zn / (Al+Ga+Zn)≤0.5.

[0068] It is understandable that the second active sublayer 405, with its high gallium / zinc content, has a low carrier concentration and few defect states, which can improve the stability of the thin-film transistor 1.

[0069] In this embodiment, by making the gallium / zinc content of the second portion 402 near the source / drain layer 50 higher than the gallium / zinc content of the first portion 401 near the gate insulating layer 30, the defect states of the second portion 402 are reduced, thereby improving the stability of the thin film transistor 1.

[0070] In one embodiment, the insulating layer of the gate 20 is made of aluminum oxide.

[0071] The active layer 40 of aluminum gallium zinc oxide is prepared by PVD magnetron sputtering, and the insulating layer of aluminum oxide gate 20 is prepared by atomic layer deposition.

[0072] It is understood that the lattice of the aluminum oxide will induce the crystallization behavior of aluminum gallium zinc oxide, resulting in a slight crystallization phenomenon in the obtained aluminum gallium zinc oxide, thereby reducing the defect states of the active layer 40.

[0073] It is understandable that a portion of the gate insulating layer 30 that is in direct contact with the active layer 40 is aluminum oxide. Since both the gate insulating layer 30 and the active layer 40 contain aluminum oxide, the defect states at the transition interface between them are reduced.

[0074] In this embodiment, by using aluminum oxide as the material for preparing the gate insulating layer 30, the defect states at the transition interface between the gate insulating layer 30 and the active layer 40 are further reduced, thereby further improving the stability of the thin film transistor 1.

[0075] In one embodiment, the aluminum content of the first active sublayer 404 ranges from 30% to 50%, the gallium content of the first active sublayer 404 ranges from 20% to 30%, and the zinc content of the first active sublayer 404 ranges from 30% to 40%.

[0076] In one embodiment, the aluminum content of the second active sublayer 405 ranges from 10% to 30%, the gallium content of the second active sublayer 405 ranges from 30% to 40%, and the zinc content of the second active sublayer 405 ranges from 40% to 50%.

[0077] In one embodiment, the thickness of the first active sublayer 404 is 25 nanometers, and the thickness of the second active sublayer 405 is 25 nanometers.

[0078] The annealing temperature is 350°C, the annealing time is 60 minutes, and the atmosphere is clean air.

[0079] The thin-film transistor 1 is a back-channel etched type.

[0080] The gate insulating layer 30 is made of aluminum oxide.

[0081] The source electrode 501 and the drain electrode 502 are made of molybdenum and copper.

[0082] The passivation layer is made of silicon oxide.

[0083] Specifically, when the first active sublayer 404 has Al / (Al+Ga+Zn) = 0.3, Ga / (Al+Ga+Zn) = 0.3, and Zn / (Al+Ga+Zn) = 0.4, and the second active sublayer 405 has Al / (Al+Ga+Zn) = 0.4, Ga / (Al+Ga+Zn) = 0.3, and Zn / (Al+Ga+Zn) = 0.3, the threshold voltage is 1.4V, and the mobility is 10.8cm. 2 / V, the threshold voltage drift is -1.8V.

[0084] Specifically, when the active sublayer Al / (Al+Ga+Zn) = 0.4, Ga / (Al+Ga+Zn) = 0.3, and Zn / (Al+Ga+Zn) = 0.3, and the second active sublayer 405 has Al / (Al+Ga+Zn) = 0.3, Ga / (Al+Ga+Zn) = 0.3, and Zn / (Al+Ga+Zn) = 0.4, the threshold voltage is 1.3V, and the mobility is 14.8cm. 2 / V, the threshold voltage drift is -1.9V.

[0085] Specifically, when the active sublayer Al / (Al+Ga+Zn) = 0.5, Ga / (Al+Ga+Zn) = 0.2, and Zn / (Al+Ga+Zn) = 0.3, and the second active sublayer 405 has Al / (Al+Ga+Zn) = 0.1, Ga / (Al+Ga+Zn) = 0.4, and Zn / (Al+Ga+Zn) = 0.5, the threshold voltage is 0.6V, and the mobility is 22cm. 2 / V, the threshold voltage drift is -1.2V.

[0086] Specifically, when the active sublayer has Al / (Al+Ga+Zn) = 0.1, Ga / (Al+Ga+Zn) = 0.4, and Zn / (Al+Ga+Zn) = 0.5, and the second active sublayer 405 has Al / (Al+Ga+Zn) = 0.5, Ga / (Al+Ga+Zn) = 0.2, and Zn / (Al+Ga+Zn) = 0.3, the threshold voltage is 2.3V, and the mobility is 3.5cm. 2 / V, the threshold voltage drift is -1.3V.

[0087] It is understood that the threshold voltage range is 0V to 3V; the higher the mobility, the better, and the smaller the absolute value of the threshold voltage drift, the better; it can be seen that the higher the aluminum content of the first active sublayer 404, the higher the mobility, and at the same time, the higher the gallium / zinc content of the second active sublayer 405, the better the stability.

[0088] It should be noted that both the threshold voltage value and the threshold voltage drift value mentioned above have an error of ±0.3V.

[0089] In this embodiment, by defining the first active sublayer 404 and the second active sublayer 405, when Al / (Al+Ga+Zn) = 0.5, Ga / (Al+Ga+Zn) = 0.2, and Zn / (Al+Ga+Zn) = 0.3 for the active sublayer, and Al / (Al+Ga+Zn) = 0.1, Ga / (Al+Ga+Zn) = 0.4, and Zn / (Al+Ga+Zn) = 0.5 for the second active sublayer 405, the mobility of the active layer 40 is 22 cm⁻¹. 2 / V, the threshold voltage drift is -1.2V, at which point the active layer 40 has high mobility and good stability.

[0090] Please see Figure 3 This application provides a method for fabricating a thin-film transistor 1, comprising:

[0091] S1: Provide a substrate 10;

[0092] S2: A gate 20 and a gate insulating layer 30 are formed on the substrate 10;

[0093] S3: A first active sublayer 404 is prepared on the gate insulating layer 30 by sputtering a first target material;

[0094] S4: A second active sublayer 405 is prepared on the first active sublayer 404 by sputtering with a second target material, wherein the gallium / zinc content of the second target material is higher than the gallium / zinc content of the first target material, and the aluminum content of the first target material is higher than the aluminum content of the second target material.

[0095] S5: A source / drain layer 50 is prepared above the second active sublayer 405.

[0096] The materials and components used to prepare the first active sublayer 404 are the same as those used to prepare the first target material.

[0097] The materials and components used to prepare the second active sublayer 405 are the same as those used to prepare the second target material.

[0098] This application also discloses a display panel, a display module, and a display device, wherein the display panel includes an array layer, a light-emitting functional layer, and an encapsulation layer, and the array layer includes the aforementioned thin-film transistors. The display module and the display device both include the aforementioned thin-film transistors, which will not be described in detail here.

[0099] The thin-film transistor provided in this embodiment includes a substrate, a gate, a gate insulating layer, an active layer, and a source-drain layer. The active layer is disposed on the gate insulating layer, and the active layer is made of aluminum, gallium, or zinc. The source and drain are disposed above the active layer. The active layer includes a first portion near the gate insulating layer and a second portion near the source-drain layer. The aluminum content of the first portion is higher than that of the second portion. By making the aluminum content of the first portion of the active layer near the gate insulating layer higher than that of the second portion near the source-drain layer, the mobility of the thin-film transistor is improved.

[0100] In the above embodiments, the descriptions of each embodiment have different focuses. For parts not described in detail in a certain embodiment, please refer to the relevant descriptions in other embodiments.

[0101] The foregoing has provided a detailed description of a thin-film transistor and a method for fabricating a thin-film transistor according to the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A thin film transistor, characterized by comprising: include: Substrate; A gate, the gate being disposed above the substrate; A gate insulating layer is disposed above the gate and the substrate; An active layer is disposed on the gate insulating layer, and the active layer is made of materials including aluminum, gallium, and zinc. A source-drain layer is disposed above the active layer. The source-drain layer includes a source and a drain, and the source and the drain are respectively connected to the active layer. The active layer includes a first active sub-layer and a second active sub-layer. The first active sub-layer is disposed close to the gate insulating layer, and the second active sub-layer is disposed close to the source and drain layers. The aluminum content of the first active sublayer ranges from 30% to 50%, the gallium content of the first active sublayer ranges from 20% to 30%, and the zinc content of the first active sublayer ranges from 30% to 40%. The aluminum content of the second active sublayer ranges from 10% to 30%, the gallium content of the second active sublayer ranges from 30% to 40%, and the zinc content of the second active sublayer ranges from 40% to 50%.

2. The thin film transistor according to claim 1, wherein The material used to prepare the gate insulating layer includes aluminum oxide.

3. A method of fabricating a thin film transistor, comprising: include: Provide a substrate; A gate and a gate insulating layer are formed on the substrate; The first active sublayer is prepared on the gate insulating layer by sputtering with a first target material. A second active sublayer is prepared on the first active sublayer by sputtering with a second target material, wherein the aluminum content of the first active sublayer ranges from 30% to 50%, the gallium content of the first active sublayer ranges from 20% to 30%, and the zinc content of the first active sublayer ranges from 30% to 40%. The aluminum content of the second active sublayer ranges from 10% to 30%, the gallium content of the second active sublayer ranges from 30% to 40%, and the zinc content of the second active sublayer ranges from 40% to 50%. A source / drain layer is prepared above the second active sublayer.

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