Method for dicing semiconductor wafers

Abstract

A method of singulating a semiconductor wafer, comprising: forming one or more epitaxial layers on a semiconductor wafer; forming a plurality of device structures in the one or more epitaxial layers; forming a metallization layer and / or a passivation layer over the plurality of device structures; attaching a carrier plate to the semiconductor wafer having the one or more epitaxial layers, the carrier plate protecting the plurality of device structures and mechanically stabilizing the semiconductor wafer; forming a separation region within the semiconductor wafer, the separation region having at least one altered physical property that increases a thermo-mechanical stress within the separation region relative to a remainder of the semiconductor wafer; and, applying an external force to the semiconductor wafer such that at least one crack propagates along the separation region and the semiconductor wafer is singulated into two separate workpieces, one of the workpieces retaining the plurality of device structures.

Description

Background Technology

[0001] Wafer costs account for a large proportion of the total production cost of silicon carbide (SiC) semiconductor devices. Reducing these costs can create a competitive advantage. One way to reduce wafer costs is to use standard wafers at least twice—after manufacturing the device structure, the SiC wafer is diced, and thinner, recycled wafer portions that do not include the device structure are reused to form additional device structures. Integrating SiC wafer dicing into the standard SiC production process is involved and complex, and requires changes / modifications to the production process to achieve efficient production.

[0002] Therefore, there is a need to integrate SiC wafer dicing and SiC manufacturing processes in an efficient and cost-sensitive manner. Summary of the Invention

[0003] Of course, the present invention is not limited to the features and advantages described above. In fact, those skilled in the art will recognize additional features and advantages after reading the following detailed description and reviewing the accompanying drawings.

[0004] According to one embodiment of a method for dicing a semiconductor wafer, the method includes: forming one or more epitaxial layers on a semiconductor wafer; forming a plurality of device structures in the one or more epitaxial layers; forming a metallization layer and / or a passivation layer over the plurality of device structures; attaching a carrier plate to the semiconductor wafer having the one or more epitaxial layers, the carrier plate protecting the plurality of device structures and mechanically stabilizing the semiconductor wafer; forming a separation region within the semiconductor wafer, the separation region having at least one altered physical property that increases thermomechanical stress within the separation region relative to the remainder of the semiconductor wafer; and applying an external force to the semiconductor wafer such that at least one crack propagates along the separation region, and the semiconductor wafer is divided into two separate workpieces, one of which holds the plurality of device structures.

[0005] According to another embodiment of the method for dicing a semiconductor wafer, the method includes: forming one or more epitaxial layers on a semiconductor wafer; forming a plurality of device structures in the one or more epitaxial layers; forming a metallization layer and / or a passivation layer over the plurality of device structures; attaching a carrier plate to the semiconductor wafer having the one or more epitaxial layers, the carrier plate protecting the plurality of device structures and mechanically stabilizing the semiconductor wafer; applying laser radiation to a separation region within the semiconductor wafer, such that the separation region increases thermomechanical stress relative to the remainder of the semiconductor wafer, and at least one crack propagates along the separation region; and dividing the semiconductor wafer into two separate workpieces along the at least one crack, one of the workpieces holding the plurality of device structures.

[0006] According to one embodiment of a method for slicing a semiconductor wafer from a semiconductor ingot, the method includes: forming a separation region within the semiconductor ingot, the separation region having at least one altered physical property that increases thermomechanical stress within the separation region relative to the remainder of the semiconductor ingot; and applying an external force to the semiconductor ingot such that at least one crack propagates along the separation region, and the wafer is sliced ​​from the semiconductor ingot.

[0007] Those skilled in the art will recognize the additional features and advantages after reading the following detailed description and reviewing the accompanying drawings. Attached Figure Description

[0008] The elements in the accompanying drawings are not necessarily proportional to each other. The same reference numerals denote corresponding similar parts. Features of the various illustrated embodiments can be combined unless they are mutually exclusive. Embodiments are described in the accompanying drawings and detailed in the following description.

[0009] Figures 1A to 1E Cross-sectional views of a semiconductor wafer during different stages of a wafer dicing process, according to one embodiment; Figure 2 A cross-sectional view of another embodiment of the carrier used during the wafer dicing process is shown; Figure 3 A portion of a separation region formed within a semiconductor substrate is shown, and it includes microcracks that are at least partially disconnected from each other within the separation region; Figure 4A The graph shows the storage modulus versus temperature of a polymer used during the wafer dicing process, which does not contain fillers; Figure 4B Show Figure 4A The graph shows the storage modulus of the polymer versus temperature, but the polymer contains one or more fillers; Figures 5A to 5D A cross-sectional view of the bevel of a semiconductor wafer according to different embodiments is shown. Detailed Implementation

[0010] It is worth noting that those skilled in the art, benefiting from the teachings presented in the foregoing description and related drawings, should be able to conceive of modifications and other embodiments of the disclosed invention. Therefore, it should be understood that the invention is not limited to the specific embodiments disclosed, and that modifications and other embodiments should be included within the scope of this disclosure. Although specific terms may be used herein, they are used only in a general and descriptive sense and not for limiting purposes.

[0011] The embodiments described herein relate to a semiconductor wafer dicing process that reduces manufacturing costs associated with producing semiconductor devices. While the focus is on SiC wafers and SiC devices produced using SiC wafers, the embodiments described herein are not intended to be limited to SiC wafers and can be used with other semiconductor wafer technologies such as silicon (Si), gallium arsenide (GaAs), gallium nitride (GaN), sapphire, etc. Device structures are fabricated in a substrate (thick) semiconductor wafer, which is then diced into thinner device wafers comprising the device structures and thinner reclaimed wafers. The reclaimed wafers can be processed, and other devices can be produced within them.

[0012] The wafer dicing technique described herein includes at least two main steps: (i) forming a separation region within a semiconductor wafer having at least one altered physical property that increases thermomechanical stress in the separation region relative to the rest of the semiconductor wafer; and applying an external force to the semiconductor wafer such that at least one crack propagates along the separation region, and the semiconductor wafer is divided into two separate workpieces.

[0013] In some embodiments, forming a separation region includes forming microcracks that are at least partially disconnected from each other within the separation region. The microcracks connect with each other in response to an external force applied to the semiconductor wafer, forming at least one crack that propagates along the separation region and separates the semiconductor wafer into two separate workpieces. In contrast to cracks that connect during a single step / process, material waste / loss can be reduced by first generating microcracks and then connecting them.

[0014] The external force applied to a semiconductor wafer may include, for example, ultrasonic vibration or the application of a polymer layer. Due to the effect of sound reflections that occur during cleaving as at least one crack develops, cleaving a semiconductor wafer using only ultrasonic vibration or a polymer layer without first creating a cleavage zone with at least one altered physical property (which increases thermomechanical stress within the cleavage zone) may result in uncontrolled cleaving and / or unwanted surface structures, such as Wallner lines, river lines, etc.

[0015] The following describes various embodiments of the semiconductor wafer dicing process.

[0016] Figures 1A to 1ECross-sectional views of a semiconductor wafer 100 during different stages of a dicing process according to one embodiment are shown. As described above, the semiconductor wafer 100 can be any type of wafer used to manufacture semiconductor devices. For example, the semiconductor wafer can be a SiC wafer such as 4H-SiC, and can have a thickness (T_wafer) that varies depending on the wafer diameter. Typically, 4-inch and 6-inch SiC wafers have a thickness of 350 μm (micrometers), with an accuracy, for example, at most ±40 μm or at most ±25 μm. For larger SiC wafer diameters, the thickness can be higher. By correspondingly adjusting the process parameters, the wafer dicing process described herein can also be used with other SiC polymorphs and / or other semiconductor materials, as described above (e.g., Si, GaAs, GaN, sapphire, etc.).

[0017] Figure 1A The diagram illustrates a semiconductor wafer 100 having one or more epitaxial layers 102 formed on it, a device structure 104 formed in the one or more epitaxial layers 102, a metallization layer and / or passivation layer 106 (e.g., at least one passivation layer) formed over the device structure 104, and a carrier plate 108 attached to the semiconductor wafer 100 having the one or more epitaxial layers 102. Layers 106 are shown as continuous in cross-section, but alternatively, they may be discontinuous. For example, in the case of a passivation layer, layer 106 may exist only over the device structure 104. In the case of a metallization layer, layer 106 may be patterned. During and / or after the dicing process, the carrier plate 108 protects the device structure 104 from damage and mechanically stabilizes the semiconductor wafer 100.

[0018] The doped regions 110, 112, and 114 of device structure 104 are generated by implantation with a subsequent annealing step or by doping during the epitaxial process. For example, for power MOSFETs (metal-oxide-semiconductor field-effect transistors) or power diode devices, the first deposited epitaxial layer 114 may be an n-doped drain or emitter layer with a thickness ranging from, for example, 10 μm to 50 μm, or for IGBTs (insulated-gate bipolar transistors), it may be a p-doped emitter layer. A second epitaxial deposition layer (not shown) may be deposited as a buffer layer to prevent the space charge layer from penetrating into the emitter / drain layer 114. The thickness of the buffer layer is typically 1 μm to 40 μm or 2 μm to 30 μm. The n-type drift region band layer 112 can then be deposited using epitaxial techniques. The thickness of the drift region band layer 112 depends on the target breakdown voltage (typically between 8 μm and 12 μm for 1200V devices, and between 25 μm and 35 μm for 3.3 kV devices). The doping level of the drift region band layer 112 can also be adjusted according to the desired breakdown voltage (typically around 10 μm for 1200V devices).16 cm -3 For 3.3 kV devices, it is 10. 15 cm -3 The adjustment can be made by adjusting the p-body and source regions (e.g., for power MOSFETs or IGBTs, or for power diodes) to several times the size of the p-emitter. The front-side device structure 110 (e.g., for the p-body and source regions of a power MOSFET or IGBT, or for the p-emitter of a power diode) can be formed by mask ion implantation and subsequent annealing steps. For switchable devices, the gate structure is also implemented in the form of a planar or trench-based gate.

[0019] After device formation, semiconductor wafer 100 has a front side with device structure 104 and a front metallization layer and / or passivation layer 106. Device structure 104 can be a semiconductor device structure, such as MEMS (Micro-Electro-Mechanical Systems) and / or MOEMS (Micro-Opto-Electro-Mechanical Systems) devices, diodes such as MPS (Merged Pin Schottky) diodes, Schottky diodes, MOS gate-controlled diodes, or transistor devices such as MOSFETs, JFETs (Junction FETs), IGBTs, FinFETs, thyristors, or combinations thereof. If device structure 104 includes a Schottky contact, the front metallization layer 108 can include a Schottky contact metal. Alternatively, or as an alternative in the absence of a Schottky contact, the front metallization layer 108 can include an ohmic contact metal.

[0020] Figure 1B The semiconductor wafer 100 is shown after a separation region 116 has been formed within it. The separation region 116 has at least one altered physical property that increases thermomechanical stress within it relative to the rest of the semiconductor wafer 100. A carrier plate 108, which protects the device structure 104 from damage and mechanically stabilizes the semiconductor wafer 100 during and / or after the dicing process, may be attached to the semiconductor wafer 100 having one or more epitaxial layers 102 before or after the formation of the separation region 116. The carrier plate 108 may be a monolithic material or a carrier plate system comprising multiple layers and / or complex structures.

[0021] The shape of the carrier 108 may be similar to or even identical to that of the semiconductor wafer 100. The semiconductor wafer 100 may have planes diced into one or more sides to indicate the crystal planes of the wafer 100, while the carrier 108 may not have such planes. The carrier 108 may have a diameter larger than that of the semiconductor wafer 100, for example, at least 0.1% larger. The diameter of the carrier 108 may be, for example, at most 3 times, at most 2 times, or at most 1.5 times the diameter of the semiconductor wafer 100. The mechanically stabilizing portion of the carrier 108 and / or the optional fixing layer of the carrier 108 may completely cover the front side of the semiconductor wafer 100, for example, as shown in the image. Figures 1A to 1E As shown. Or, as... Figure 2As shown, the mechanically stabilizing portion and / or optional fixing layer of the carrier 108 divides the front side (active side) of the semiconductor wafer 100 into multiple segments along the surface of the wafer 100. According to this embodiment, the mechanically stabilizing portion and / or optional fixing layer of the carrier 108 may have annular or grid-like shapes, and / or may exist only in the peripheral region of the semiconductor wafer 100, such as intersecting loops at the outer / peripheral portions of the wafer 100. In each case, the morphology of the device structure 104 may be embedded in the carrier 108, for example, through potting material and / or adhesive and / or non-adhesive layers 118 between the carrier 108 and the semiconductor wafer 100 having one or more epitaxial layers 102 and front-side metallization 106.

[0022] The carrier plate 108 can be temporarily (reversibly) or permanently attached to a semiconductor wafer 100 having one or more epitaxial layers 102. In the case of temporary attachment, the carrier plate 108 may include adhesive tape with thermal or UV peeling, an adhesive (organic or inorganic composition) layer bonded to a rigid support (e.g., a transparent substrate, an opaque substrate, a polymer film, etc.), a fixed or movable electrostatic chuck, a fixed or movable vacuum chuck, a movable vacuum carrier plate, etc. In the case of permanent attachment, the carrier plate 108 may include, for example, hot-patterned glass in the form of a grid, ring, etc., glass grids and / or rings attached via solder glass, glass grids and / or rings attached via a laser welding process, a substrate such as a semiconductor, metal, or insulator (e.g., glass) substrate bonded to the semiconductor wafer 100 having one or more epitaxial layers 102 via one or more diffusion bonding layers, or a substrate bonded to the semiconductor wafer 100 having one or more epitaxial layers 102 via aerobic and / or anaerobic adhesives or other adhesive components.

[0023] Separation region 116 can cleave the semiconductor wafer 100 at a defined location. Otherwise, cleaving would occur at random locations that may be affected by crystal damage, etc. Furthermore, without a defined separation region 116, recyclable manufacturing would be more difficult because only some of the device wafers can be used and / or recycled. The defined separation region 116 significantly reduces material loss (also known as kerf loss) during wafer cleaving. The thickness (t_sep) of the separation region 116 can define the kerf loss. For example, losses may originate from the vertical propagation of microcracks, as well as additional losses due to chemical, mechanical, electrochemical, and / or plasma material removal.

[0024] The location of the separation region 116 can be selected such that, after defining the device structure 104, the distance "d1" to the front side of the semiconductor wafer 100 having one or more epitaxial layers 102 is high enough to allow mechanical processing of the thinner device wafer produced by the dicing process, and such that the distance d1 to the front side is low enough so that the distance "d2" to the back side is high enough to still allow processing of the recycled wafer produced by the dicing process. In one embodiment, the separation region 116 is located near the interface between the wafer 100 and the first deposited epitaxial layer 114 (substrate / drain layer for a power MOSFET or substrate / emitter layer for a diode). Typically, the distance between the separation region 116 and the interface between the wafer 100 and the first deposited epitaxial layer 114 is less than 10 μm, or even less than 4 μm, or even less than 2 μm.

[0025] Typically, the thermomechanical stress within the separation region 116 can be increased compared to the rest of the semiconductor wafer 100, thereby simplifying the dicing of the semiconductor wafer 110 into device wafers and recycled wafers, for example, by applying mechanical and / or thermal stress to the wafer 100. The thermomechanical stress generated within the separation region 116 may be sufficient to induce wafer dicing without requiring the application of external force. For example, laser radiation can be applied to the separation region 116, causing the separation region 116 to have increased thermomechanical stress relative to the rest of the semiconductor wafer 100, and at least one crack to propagate along the separation region 116, thereby enabling wafer dicing without the use of external force. However, external force can still be applied to peel off one of the diced wafer components and / or to aid in wafer dicing.

[0026] In one embodiment, the separation region 116 is formed by damaging the material of the semiconductor wafer 100 at the target location. For example, in the case of SiC as the wafer material, the SiC material can be damaged. In some cases, SiC can be at least partially decomposed into, for example, Si and C. This can be accomplished, for example, by generating plasma in the SiC material at the target location within the semiconductor wafer 100. At least some atoms in the plasma can recrystallize into carbon clusters and silicon material, for example, in the form of amorphous carbon and / or amorphous silicon. Alternatively or additionally, at least some atoms can recrystallize, semi-crystallize, and / or reorganize into, for example, SiC (e.g., 4H-SiC, 6H-SiC, or 3C-SiC) or at least one polymorph of amorphous SiC in which both the Si and C phases are amorphous. In some examples, the separation region 106 may include at least one of the following: crystalline portion of SiC or at least one polymorph of silicon or carbon (e.g., in the form of microcrystals), amorphous portion of SiC or silicon or carbon, and / or cavity.

[0027] In one embodiment, plasma is generated in the material at the target location within the semiconductor wafer 100 by focusing laser radiation at that location. The semiconductor wafer 100 can be irradiated via its back side opposite the device structure 104 or via its front side having the device structure 104, and the radiation is focused onto a clearly defined region within the wafer 100 to excite plasma within the wafer 100, which decomposes the laser-irradiated semiconductor material into its constituent components. For example, in the case of SiC, laser-irradiated SiC decomposes as follows: SiC → Si+C. Interaction with the laser radiation can result in different material phases, for example as described above, and / or microcracks within the semiconductor wafer 100. Preferably, irradiation of the semiconductor wafer 100 via the front side using laser radiation is performed before fabricating the device structure 104 or at least before fabricating the front-side metallization 106, because laser radiation may damage the device structure 104 and because the metallization 106 is opaque to laser radiation.

[0028] If the separation region 116 has been predefined, for example, by injection as briefly explained above and explained in more detail below, the laser radiation applied to the separation region 116 can be in a resonant state where single-photon processes (e.g., single-photon absorption) dominate, i.e., the probability of multi-photon processes is very small (e.g., as small as at least one-tenth of the probability of single-photon processes). In the resonant state, the band gap of the material within the separation region 116 can, for example, be within the range of the photon energy of the laser radiation (e.g., at most ±5%, at most ±1%, at most ±0.1%, or at most ±0.01% of the band gap, depending on the laser energy). The laser radiation can be absorbed in the separation region 116 and can cause further damage to the separation region 116 (e.g., SiC decomposition in the case of SiC wafer 100), such that no mechanical force and / or only a small thermal stress is required to cleave the semiconductor wafer 100 at the separation region 116.

[0029] The separation region 116 can be defined, or, in the case of a predefined layer previously formed, for example by ion implantation, the separation region 116 can be further defined by focusing laser radiation onto a specifically defined region (e.g., a region within the semiconductor wafer 100 having at most a target thickness (e.g., 50% of the target thickness)). In this case, the laser radiation can be in a non-resonant state, such that the probability of single-photon processes in the separation region 116 is very small, and the main multiphoton processes (especially multiphoton absorption) may have to be considered. For example, a non-resonant state can be achieved if the band gap of the separation region 116 is greater than the photon energy of the laser radiation (e.g., at least two or at least ten times). In the case of multiphoton processes, damage generation can be further supported by a predefined layer (e.g., formed by ion implantation) that increases absorption in the region where the laser radiation is focused.

[0030] Laser radiation can be pulsed laser radiation. The parameters of laser radiation (such as pulse duration, repetition rate, pulse energy, intensity, wavelength, pulse shape, polarization, etc.) are interrelated and can be optimized for specific applications or requirements. For example, laser radiation can have a pulse duration of 100 fs to 100 ns (e.g., 50 ps to 10 ns), a repetition rate of 10 kHz to 10 MHz, a pulse energy of 100 nJ to 50 μJ, and a peak wavelength of 400 nm to 2100 nm (e.g., 900 nm to 1200 nm).

[0031] Laser radiation can be applied along laser lines (also called scribing) that extend substantially parallel to each other. For each laser line, the laser beam scans along that line. The laser scanning speed can be so fast that adjacent individual laser emissions can be distinguished, for example, without overlapping. Here, an individual laser emission can correspond to an emission caused by, for example,... Figure 3 The damage caused by a single laser radiation pulse is shown.

[0032] In the small segment showing separation zone 116 Figure 3 In the diagram, the dashed ellipse marked "A" corresponds to the location of each / individual laser emission. At each individual laser emission location "A", the material in the separation region 116 is decomposed, and microcracks extending along the crystal planes of the wafer material appear, as indicated by the additional microcracks marked "B" and "C". The microcracks "A", "B", and "C" formed within the separation region 116 are at least partially disconnected from each other. The microcrack marked "C" is generated by the tension between the other microcracks "A", rather than being formed directly by laser emission. For 4H-SiC, the growth direction of the semiconductor wafer 100 (which corresponds to the direction perpendicular to the wafer 100 along its thickness T_wafer) can be slightly tilted relative to the principal crystal axis, typically tilted at 4° (also known as an off-axis angle). Therefore, the crystal plane is tilted.

[0033] If the separation region 116 has only a single large crack, it will be planar but tilted, meaning the separation region 116 will be tilted at 4° relative to the lateral direction (i.e., the direction perpendicular to the vertical direction). This will result in significant losses along the entire diameter of the semiconductor wafer 100. Therefore, for SiC, if the separation surface is not planar but has a zigzag / serrated shape, the segmentation process can be used for 4H-SiC. The microcracks “A”, “B”, and “C” are then joined to enable the segmentation of the semiconductor wafer 100, as described in further detail below.

[0034] In addition to damaging the semiconductor wafer 100 with laser radiation to form the separation region 116, or as an alternative, the material of the semiconductor wafer 100 at the target location can also be damaged by implanting ions into the semiconductor wafer 100 at a depth corresponding to the target location within the wafer 100 to create and / or predefine the separation region 116. Ions can directly lead to higher absorption, for example, due to the higher absorption rate in the separation region 116 where most of the implanted ions reside. In the case of SiC as the semiconductor wafer 100 material, ions can cause the crystal structure of the SiC wafer to transform into different materials, such as different polymorphs (e.g., from 4H-SiC to 3C-SiC) and / or different crystallinities and / or amorphous SiC and / or silicon and carbon (amorphous or crystalline), thereby increasing the absorption coefficient at the wavelength of the laser radiation in the separation region 116. Ions can also cause decomposition of the material of the semiconductor wafer 100 in the separation region 116.

[0035] In one embodiment, the ions can be selected from the group consisting of nitrogen ions, phosphorus ions, hydrogen ions, and helium ions. For example, atoms such as nitrogen and / or phosphorus atoms can be implanted into the separation region 116, where the implantation dose results in the formation of an amorphous layer and / or cavities. Alternatively, helium ions or protons can also be implanted to create a locally damaged layer within the separation region 116. For the same energy, lighter ions (such as helium and hydrogen) penetrate deeper into the semiconductor wafer 100 compared to heavier ions, thereby increasing the depth of the separation region 116 if desired. Lighter ions (such as helium and hydrogen) can preferentially generate vacancy clusters and damaged layers at the ends of the implanted range, making it possible to facilitate the separation process in that region. Phosphorus and / or nitrogen are suitable for achieving highly damaged layers in SiC. In the case of phosphorus and / or nitrogen, the implantation dose can be selected such that an amorphous layer and / or cavities are formed in the separation region 116. Optionally, channeling can be utilized during implantation, resulting in lower surface damage at the surface in which the implantation is performed. Ions can be implanted before the formation of one or more epitaxial layers 102. For example, ions can be implanted through the surface of a semiconductor wafer 100, on which one or more epitaxial layers 102 will be formed.

[0036] Following ion implantation, device structure 104 can be fabricated. Before or after fabrication of device structure 104, laser radiation as described above can irradiate through semiconductor wafer 100, with the focal point approximately located at the implantation layer. The ions and / or the ion-converted semiconductor material will have increased absorption compared to the rest of wafer 100, thus improving, for example, SiC decomposition into Si and C through enhanced local heating of wafer 100. For example, a combination of multiphoton and single-photon processes can occur within a predefined ion implantation layer to increase thermomechanical stress within separation region 116 relative to the rest of semiconductor wafer 100.

[0037] The separation region 116 may be formed before or after the formation of the device structure 104. In some embodiments, a portion of the separation region 116 may be formed before the formation of the device structure 104, for example, even before epitaxial growth, and another portion of the separation region 116 may be formed after the formation of the device structure 104.

[0038] In one embodiment, the separation region 116 is formed by laser irradiation and ion implantation of the semiconductor wafer 100. Specifically, by implanting ions into the semiconductor wafer 100 at a depth corresponding to a target location within the wafer 100, the material of the semiconductor wafer 100 can be damaged at the target location within the semiconductor wafer 100. After ion implantation, laser radiation is then focused onto the target location within the semiconductor wafer 100. According to this embodiment, the implanted ions increase the absorption coefficient of the separation region 116 at the wavelength of the laser radiation, which further increases the thermomechanical stress within the separation region 116 relative to the rest of the semiconductor wafer 100.

[0039] After the separation region 116 is formed, an external force is applied to the semiconductor wafer 100, causing at least one large crack to propagate along the separation region 116, and the semiconductor wafer 100 is separated into two separate workpieces. The force balance of surface energy, bonding forces, and (optionally) external pressure are shifted to favor the external force, thereby overcoming the internal bonding forces still present within the semiconductor wafer 100 at the separation region 116, leading to crack propagation. Alternatively, laser radiation propagates a crack along the separation region 116 sufficient to split the semiconductor wafer 100 without the need for external force. However, external force may still be applied to assist in the peeling process of the separated wafer workpieces and / or wafer splitting.

[0040] The separation region 116 has at least one altered physical property that increases thermomechanical stress within the separation region 116 relative to the remainder of the semiconductor wafer 100, as described above. For example, laser radiation and / or ion implantation can be used to alter at least one physical property of the separation region 116. Laser radiation can form microcracks “A”, “B”, “C” in the separation region 116, while implanted ions can increase the absorption coefficient in the separation region 116 at the wavelength of the laser radiation. The localized increase in thermomechanical stress limits crack propagation into the separation region 116 in a controlled and regenerative manner. The localized increase in thermomechanical stress may be sufficient to propagate enough cracks along the separation region 116 so that external force is not required to divide the semiconductor wafer 100. However, in other embodiments, force may also be used to assist in dividing the semiconductor wafer 100.

[0041] In one embodiment, the external force applied to the semiconductor wafer 100 for cleaving the wafer 100 along the separation region 116 includes applying ultrasonic vibration (sound waves) to the semiconductor wafer 100. The frequency of the ultrasonic vibration can be in the kHz range, for example, at least 20 kHz and up to 60 kHz (e.g., 30-50 kHz, e.g., 35-45 kHz). When ultrasonic vibration is applied, the semiconductor wafer 100 can be placed in a container filled with a fluid, such as pure water, deionized water, common solvents, dimethylformamide, isopropanol, methanol, and / or ethanol. For example, an apparatus similar to an ultrasonic cleaning device can be used to apply ultrasound to the semiconductor wafer 100.

[0042] Figures 1C to 1E Another embodiment is shown in which an external force is applied to a semiconductor wafer 100 to cleave the wafer 100 along a separation region 116. According to this embodiment, as... Figure 1C As shown, polymer 120 is applied to semiconductor wafer 100 and / or carrier 108. Polymer 120 has a CTE (coefficient of thermal expansion) different from that of semiconductor wafer 100. Then, polymer 120 and semiconductor wafer 100 are subjected to a temperature treatment during which polymer 120 applies mechanical stress to semiconductor wafer 100, such as... Figure 1D As indicated by the dashed arrow in the diagram. Mechanical stress caused at least one large crack 122 to propagate along the separation region 116, causing the semiconductor wafer 100 to split into two separate parts 124 and 126, as shown in the diagram. Figure 1E As shown. One workpiece 124 holds the device structure 104. Another workpiece 126 can be used for subsequent device processing.

[0043] The separation zone 116 includes the above-mentioned combination. Figure 3In the case of the explained microcracks "A", "B", and "C", the mechanical stress applied to the semiconductor wafer 100 causes the microcracks "A", "B", and "C" to connect with each other to form a large crack 122 that divides the wafer 100. That is, the individual microcracks "A", "B", and "C" move relative to each other in response to external forces. Therefore, the separation region 116 can be considered not as a single layer within the semiconductor wafer 100, but as a combination of several microcracks "A", "B", and "C" that combine only during the separation process. In the case of SiC as the semiconductor wafer 100 material, the combination of microcracks "A", "B", and "C" results in two separate workpieces 124, 126 having separation surfaces 128, 130 with a serrated pattern. Therefore, in the case of SiC, the resulting device workpiece 124 and the recycled workpiece 126 do not have smooth, flat surfaces. In one embodiment, after the semiconductor wafer 100 is divided into two separate workpieces 124, 126, each separation surface 128, 130 generated by the large crack 122 propagating along the separation region 116 is smoothed. Residual decomposition material may be present at the separation surfaces 128, 130 of each workpiece 124, 126 separated from the wafer 100, and can be removed by a cleaning process.

[0044] Polymer 120 can be attached to semiconductor wafer 100, wherein carrier 108 is already attached to wafer 100. Polymer 120 can be attached to the back face of semiconductor wafer 100 and the back face 132 of carrier 108. Alternatively, polymer 108 can be attached to the outer side 134 of carrier 108 opposite to semiconductor wafer 100. In this case, carrier 108 is located between polymer 120 and semiconductor wafer 100. According to another embodiment, polymer 120 can be attached to both the back face 132 of semiconductor wafer 100 and the outer side 134 of carrier 108. For example, if a glass grid or glass ring is used as carrier 108, then polymer 120 can be applied to the back face 132 of semiconductor wafer 100 having one or more epitaxial layers 102, and additionally to the outer side 134 of carrier 108. Typically, other layers (e.g., adhesive layers such as adhesives, and / or layers that facilitate the subsequent removal of polymer 120) may be applied between polymer 120 and the side on which polymer 120 is applied.

[0045] Polymer 120 can be selected not only based on CTE, but also by considering multiple parameters. The CTE of polymer 120 should differ from the CTE of semiconductor wafer 100. For example, the CTE of polymer 120 is preferably greater than the CTE of semiconductor wafer 100. In addition to the difference in CTE, linear progression of CTE in polymer 120 over a wide temperature range may be advantageous for successful separation.

[0046] Furthermore, polymer 120 should possess sufficiently high thermal conductivity. In one embodiment, one or more fillers (such as ZnO and / or carbon black) are added to polymer 120 prior to temperature treatment. These fillers increase the thermal conductivity of polymer 120 and decrease the slope of its storage modulus, thereby extending the linear progression of the CTE in polymer 120 over a narrower temperature range. By adding ZnO and / or carbon black to polymer 120, the resulting permeation chains can significantly increase the thermal conductivity within polymer 120. If a filler material is used, the polymer material can be selected such that the filler material is easily and uniformly distributed throughout polymer 120.

[0047] For a sufficiently large heat transfer coefficient to the semiconductor wafer 100, adding one or more fillers (e.g., ZnO and / or carbon black) to the polymer reduces the time required to generate sufficient mechanical stress to cleave the semiconductor wafer 100 along the separation zone 116 by more than half. Simultaneously, the increase in elastic modulus is distributed over a wider temperature range, as it is already significant at higher temperatures compared to unfilled polymers. As a result, there is less wafer breakage during the manufacturing process, and higher cleaving efficiency is provided. An example of polymer 120 is PDMS (polydimethylsiloxane), which typically contains at least one filler. PDMS exhibits high adhesion to surfaces. Therefore, attachment may require some pre-processing or conditioning to achieve non-destructive polymer removal. For example, a foil may be placed between the polymer and the surface to which the polymer is attached.

[0048] The attachment of polymer 120 is typically performed at relatively high temperatures (e.g., above room temperature but below 300°C). Bonding processes can be applied to achieve a robust bond throughout the temperature treatment. For example, prior to the application of polymer 120, the application surfaces of polymer 120 and / or semiconductor wafer 100 and / or carrier 108 may undergo chemical and / or physical surface treatments (e.g., with plasma) to achieve a robust bond. Indirect temporary cold plasma activation methods can be used to ensure easy subsequent removal of polymer 120. This has the advantage of achieving contradictory structure-property relationships and not expecting significant thermal diffusion processes at the resulting low temperatures. For example, diffusion can be problematic in the case of metallic impurities, such as those originating from the metal layers of device structure 104. The polymer bonding is sufficient for the separation operation but weak enough for complete removal of polymer 120 in subsequent steps.

[0049] Another additional or alternative method is to apply a bonding (sacrificial) layer between the semiconductor wafer 100 having one or more epitaxial layers 102 (and / or, if applicable, carrier 108) and the polymer 120. The bonding layer can be selected such that adhesion to the polymer 120 can be reduced, for example, by chemicals or by heat treatment.

[0050] The polymer 120 may not be directly formed on the semiconductor wafer 100 having one or more epitaxial layers 102 and / or directly on the carrier 108. Instead, the polymer 120 may be pre-produced and subsequently attached to the semiconductor wafer 100 using one or more epitaxial layers 102 and / or the carrier 108. In other embodiments, the polymer 120 may be formed directly on the semiconductor wafer 100 having one or more epitaxial layers 102 and / or the carrier 108, for example, via spraying or coating.

[0051] After attaching polymer 120 to a semiconductor wafer 100 having one or more epitaxial layers 102 and / or a carrier 108, a temperature treatment is performed. In one embodiment, the temperature treatment is chosen such that polymer 120 undergoes a partial glass transition and partial crystallization during the temperature treatment. This may include a first stage and a second stage, during which polymer 120 and semiconductor wafer 100 undergo a temperature gradient from an initial temperature to room temperature, where the initial temperature is 300°C or lower but above room temperature, and during the second stage, polymer 120 and semiconductor wafer 100 are further cooled to an even lower temperature. For example, the lower temperature may correspond to ±40°C of the boiling point of the cooling liquid (e.g., liquid nitrogen) used for cooling. The lower temperature may be, for example, -170°C, particularly for the entire wafer 100. In some examples, depending on the cooling conditions (e.g., the cooling liquid), the lower temperature may be below the glass transition temperature (Tg) of polymer 120.

[0052] Figure 4A and 4B This indicates that there is no filler ( Figure 4A ) and having one or more fillers ( Figure 4B The storage modulus (elastic modulus) of the same polymer 120 above a temperature in °C, expressed in MPa. During the second stage of the temperature treatment, polymer 120 may undergo partial glass transition and partial crystallization processes, such as... Figure 4A and 4B As shown. The definition of the glass transition temperature (Tg) is not standardized. Several methods exist for determining Tg, which is not a constant material property but depends on the method used to define Tg and the parameters used during said method. For example, if the DMA (Dynamic Mechanical Analysis) method for measuring the viscoelastic modulus is used, the dynamic glass transition temperature and the parameters used for measurement must be specified (e.g., frequency of external load, tilt rate, tilt direction, measurement accuracy, etc.).

[0053] exist Figure 4A In this context, the glass transition temperature Tg is obtained at the inflection point (at least for some methods that define Tg). Figure 4BIn this process, crystallization begins at a temperature higher than the glass transition temperature (which has a higher slope below T2) (with a gentler slope between T1 and T2), where temperature T3 is lower than T2 and T2 is lower than T1. Figure 4A Compared to the same polymer but without fillers, the inflection point can no longer be clearly determined, and therefore Tg cannot be determined.

[0054] By adding one or more fillers to polymer 120, the degrees of freedom of the polymer used crystallize earlier than those of the unfilled polymer. Above the glass transition temperature, the polymer molecules are flexible and can adopt different conformations, for example, by rotating around the bonds of the flexible Si-O-Si siloxane single bond ([R3Si-O-SiR3]n). As the temperature decreases, there are restrictions on the existing degrees of freedom, and therefore the mobility of the elastomer molecules decreases because the necessary activation energy required for binding rotation is statistically less readily available. The frequency of positional changes of polymer molecules decreases with decreasing temperature. The kinetics of polymer molecular rearrangement decrease due to the additional intermolecular interactions that occur between the filler particles and polymer molecules, as group vibrations or the cooperative motion of surrounding chains and molecules are reduced due to the lower free volume. At very high filler contents (e.g., >20 wt%), particle-particle interactions should be considered.

[0055] and Figure 4A Compared to polymers without fillers, for Figure 4B The polymer 120 contains one or more fillers, and the storage modulus (elastic modulus) of the polymer 120 increases at higher temperatures. Therefore, the slope of the increase in storage modulus is lower. The increase in force during the separation process is proportional to the storage modulus. Therefore, the lower slope translates to a lower increase in force, and thus a smoother increase in force, leading to smoother crack propagation. By adding one or more fillers to the polymer 120, the tension within the semiconductor wafer 100 can be reduced with less wafer breakage outside the separation zone 116. Conversely, for a higher increase in force, non-uniformity has a greater impact on the separation process. Polymer crystallization can result in a lower total force, but this can be compensated for, for example, by increasing the thickness of the polymer 120. Preferably, the temperature gradient and temperature treatment are selected such that the local temperature difference within the semiconductor wafer 100 is reduced. Excessive local temperature differences can lead to an excessive increase in stress and cause undesirable cracking within the semiconductor wafer 100.

[0056] Semiconductor wafer 100 may have a beveled edge 136, for example, as Figure 5A As shown. Figure 5A As shown, the inclined side 136 has a beveled outer surface. When the fabrication position is... Figure 5AWhen the separation region 116 is indicated by the dashed line, the shape of the bevel 136 may cause problems. For example, variations in the thickness of the bevel 136 may cause variations in the propagation length of the laser beam. Consequently, the focus of the laser beam changes at the wafer bevel. As a result, the separation region 116 may not extend to the outer edge / edge surface 138 of the semiconductor wafer 100. Variations in thickness and / or position at the outer edge / edge surface 138 of the semiconductor wafer 100 may also hinder ion implantation to define or pre-define the separation region 116.

[0057] To allow access to the separation region 116 from the outer edge / edge face 138, and thus facilitate or at least simplify the segmentation process, the shape of the bevel can be as follows: Figure 5B and 5C The modifications are shown. According to these embodiments, the bevel 136 of the semiconductor wafer 100 is thinned to a depth T_thin located at or below the separation region 116, the position of which is determined by… Figure 5B and 5C The dashed line indicates the area. Depending on the type of thinning used, the thinning zone can be square (…). Figure 5B ) or round ( Figure 5C The bevel 136 of the semiconductor wafer 100 can be thinned by mechanical removal, such as by grinding, cutting, laser ablation, electro-chemical discharge processing, etching, etc.

[0058] Figure 5D Another embodiment is shown, in which a groove 500 is formed in the bevel 136 of the semiconductor wafer 100, and extends laterally to a separation region 116, the separation region being located at... Figure 5D The center is represented by a dashed line. Slot 500 can be formed as... Figure 5B and 5C The thinning portion shown is an alternative or supplement. In each case, the bevel 136 of the semiconductor wafer 100 may be processed before or after the separation region 116 is formed.

[0059] During the wafer dicing process, pressure can be applied to the semiconductor wafer 100. For example, a piston can apply pressure to the semiconductor wafer 100 having one or more epitaxial layers 102. The piston can be pushed in the direction of the wafer 100 with compressed air, or the weight of the piston can be applied to the wafer 100 alone. This process is better controlled than immersing the wafer 100 having polymer 120 in a cryogenic fluid (e.g., nitrogen) (e.g., completely or gradually), especially for the spatial resolution of the cooling process.

[0060] After the semiconductor wafer 100 is diced, the workpiece 124 holding the device structure 104 may be thinner than another workpiece 126. For example, the workpiece 124 holding the device structure 104 may have a thickness of up to 100 μm (e.g., up to 70 μm or up to 50 μm) and a desired thickness of at least the drift zone as described above (or at least 10 μm greater than the desired thickness), and the other workpiece 126 may have a thickness of at least 150 μm (e.g., at least 190 μm).

[0061] To allow for the reuse of polymer 120 and avoid damage to the diced wafer workpieces 124, 126, polymer removal can be employed. For example, polymer 120 can be removed mechanically on the device-side separation surface 128 (if applicable) and on the recycling-side separation surface 130 without chemical etching (typically chemical-free), plasma etching, or other vapor phase sputtering processes. Due to the attachment method described herein, polymer 120 can be removed quickly, in an environmentally friendly, and residue-free manner.

[0062] After wafer dicing, workpieces 124 and 126 are processed on their separation surfaces 128 and 130. For the back side of workpiece 124 with device structure 104, damage removal can be performed, for example, by mechanical polishing and / or chemical mechanical polishing and / or etching. After damage removal, the root mean square (rms) value of the final roughness of separation surface 128 can be less than 5 μm or even less than 2 μm. Further processing can then be performed. In the case of workpiece 126 without device structure 104, separation surface 130 may need to be processed to prepare for subsequent epitaxial growth. In this case, the RMS value of separation surface 130 can be less than 500 nm or even less than 300 nm. The thickness of workpiece 126 without device structure 104 can be adapted to the original thickness of wafer 100, for example, by deposition techniques such as CVD epitaxy, so that the same process described above can be repeated several times for the thickened workpiece 126.

[0063] The embodiments previously described herein relate to dicing new wafers from a substrate semiconductor wafer. Alternatively, the dicing techniques described herein can be applied to dicing semiconductor wafers from a semiconductor ingot. A semiconductor ingot is a single-crystal ingot produced by a synthesis method such as the Bridgman technique, the Czochralski process, etc. The dicing techniques described herein can be applied to dicing semiconductor wafers from a semiconductor ingot by forming a separation region within the semiconductor ingot, the separation region having at least one altered physical property that increases thermomechanical stress within the separation region relative to the rest of the semiconductor ingot. For example, thermomechanical stress within the separation region can be increased by focusing laser radiation at a target location within the semiconductor ingot. An external force is then applied to the semiconductor ingot, causing at least one crack to propagate along the separation region, and the wafer is diced from the semiconductor ingot. In one embodiment, an external force is applied to the semiconductor ingot by applying a polymer having a CTE different from that of the semiconductor ingot. The polymer and the semiconductor ingot are subjected to a temperature treatment during which the polymer applies mechanical stress to the semiconductor ingot. Again, as previously described herein, the thermomechanical stress generated within the separation region of the semiconductor ingot may be sufficient to cause wafer dicing without the need for an external force. In either case, the process can be applied multiple times to produce multiple wafers from a single semiconductor ingot.

[0064] Although this disclosure is not limited thereto, the examples numbered below illustrate one or more aspects of this disclosure.

[0065] Example 1. A method for dicing a semiconductor wafer, the method comprising: forming one or more epitaxial layers on the semiconductor wafer; forming a plurality of device structures in the one or more epitaxial layers; forming a metallization layer and / or a passivation layer over the plurality of device structures; attaching a carrier plate to the semiconductor wafer having the one or more epitaxial layers, the carrier plate protecting the plurality of device structures and mechanically stabilizing the semiconductor wafer; forming a separation region within the semiconductor wafer, the separation region having at least one altered physical property that increases thermomechanical stress within the separation region relative to the remainder of the semiconductor wafer; and applying an external force to the semiconductor wafer such that at least one crack propagates along the separation region, and the semiconductor wafer is diced into two separate workpieces, one of the workpieces holding the plurality of device structures.

[0066] Example 2. The method according to Example 1, wherein forming a separation region within a semiconductor wafer includes: damaging the material of the semiconductor wafer at a target location within the semiconductor wafer.

[0067] Example 3. The method according to Example 2, wherein damaging the material of the semiconductor wafer at the target location within the semiconductor wafer includes: generating plasma in the material at the target location within the semiconductor wafer.

[0068] Example 4. The method according to Example 3, wherein generating plasma in the material at a target location within the semiconductor wafer comprises: focusing laser radiation at the target location within the semiconductor wafer.

[0069] Example 5. The method according to Example 2, wherein damaging the material of the semiconductor wafer at the target location within the semiconductor wafer includes: implanting ions into the semiconductor wafer at a depth corresponding to the target location within the semiconductor wafer.

[0070] Example 6. The method according to Example 5, wherein the ion is selected from the group consisting of nitrogen ions, phosphorus ions, hydrogen ions and helium ions.

[0071] Example 7. The method according to Example 5 or 6, wherein the implantation dose of ions is selected such that the implanted ions damage the material of the semiconductor wafer which is amorphous or create cavities.

[0072] Example 8. The method according to Example 2, wherein damaging the material of the semiconductor wafer at the target location within the semiconductor wafer comprises: implanting ions into the semiconductor wafer at a depth corresponding to the target location within the semiconductor wafer; and, after ion implantation, focusing laser radiation at the target location within the semiconductor wafer, wherein the implanted ions increase the absorption coefficient in the separation region at the wavelength of the laser radiation.

[0073] Example 9. The method according to any one of Examples 1 to 8 further includes: thinning the bevel of the semiconductor wafer to a depth at or below the separation region.

[0074] Example 10. The method according to any one of Examples 1 to 9 further includes: forming a groove in the bevel of the semiconductor wafer that extends laterally into the separation region.

[0075] Example 11. The method according to any one of Examples 1 to 10, wherein applying an external force to the semiconductor wafer comprises: applying ultrasonic vibration to the semiconductor wafer.

[0076] Example 12. The method according to any one of Examples 1 to 11, wherein applying the external force to the semiconductor wafer comprises: applying a polymer to the semiconductor wafer and / or a carrier plate having a CTE (coefficient of thermal expansion) different from that of the semiconductor wafer; and subjecting the polymer and the semiconductor wafer to a temperature treatment during which the polymer applies mechanical stress to the semiconductor wafer.

[0077] Example 13. The method according to Example 12, wherein the temperature treatment is selected such that the polymer undergoes a partial glass transition and partial crystallization during the temperature treatment.

[0078] Example 14. The method according to Example 12 or 13, wherein the temperature treatment includes a first stage and a second stage, during which the polymer and semiconductor wafer undergo a temperature gradient from an initial temperature to room temperature, said initial temperature being 300°C or lower but above room temperature, and during the second stage the polymer and semiconductor wafer are further cooled to a temperature below the glass transition temperature of the polymer.

[0079] Example 15. The method according to any one of Examples 12 to 14 further comprises: prior to the temperature treatment, adding one or more fillers to the polymer, the fillers increasing the thermal conductivity of the polymer and decreasing the slope of the polymer's storage modulus.

[0080] Example 16. The method according to Example 15, wherein the one or more fillers comprise ZnO and / or carbon black.

[0081] Example 17. The method according to any one of Examples 12 to 16 further includes: chemically and / or physically treating the surface of the polymer and / or the surface of the semiconductor wafer and / or the surface of the carrier plate prior to applying the polymer.

[0082] Example 18. The method according to any one of Examples 12 to 17, wherein the at least one crack propagates during partial crystallization of the polymer, the partial crystallization occurring during the temperature treatment.

[0083] Example 19. The method according to any one of Examples 1 to 18, wherein applying the external force to the semiconductor wafer comprises: applying pressure to the semiconductor wafer during the process of dividing the semiconductor wafer into two separate workpieces.

[0084] Example 20. The method according to any one of Examples 1 to 19 further includes: after dividing the semiconductor wafer into two separate workpieces, reducing the surface roughness of the separation surfaces of the two workpieces of the semiconductor wafer, each separation surface being a surface formed as at least one crack propagates along the separation region.

[0085] Example 21. The method according to any one of Examples 1 to 20, wherein at least one altered physical property of the separation zone includes a plurality of microcracks that are at least partially disconnected from each other within the separation zone, and wherein the plurality of microcracks connect with each other in response to the external force to form the at least one crack propagating along the separation zone.

[0086] Example 22. The method according to Example 21, wherein the semiconductor wafer is a SiC wafer, and wherein at least one crack formed by the connection of the plurality of microcracks in response to the external force has a serrated pattern.

[0087] Example 23. A method for dicing a semiconductor wafer, the method comprising: forming one or more epitaxial layers on the semiconductor wafer; forming a plurality of device structures in the one or more epitaxial layers; forming a metallization layer and / or a passivation layer over the plurality of device structures; attaching a carrier plate to the semiconductor wafer having the one or more epitaxial layers, the carrier plate protecting the plurality of device structures and mechanically stabilizing the semiconductor wafer; applying laser radiation to a separation region within the semiconductor wafer such that the separation region has increased thermomechanical stress relative to the remainder of the semiconductor wafer, and at least one crack propagates along the separation region; and dividing the semiconductor wafer into two separate workpieces along the at least one crack, one of the workpieces holding the plurality of device structures.

[0088] Example 24. A method for slicing a semiconductor wafer from a semiconductor ingot, the method comprising: forming a separation region within the semiconductor ingot, the separation region having at least one altered physical property that increases thermomechanical stress within the separation region relative to the remainder of the semiconductor ingot; and applying an external force to the semiconductor ingot such that at least one crack propagates along the separation region, and the wafer is sliced ​​from the semiconductor ingot.

[0089] Example 25. The method according to Example 24, wherein applying an external force to a semiconductor ingot comprises: applying a polymer to the semiconductor ingot, the polymer having a CTE (coefficient of thermal expansion) different from that of the semiconductor ingot; and subjecting the polymer and the semiconductor ingot to a temperature treatment, during which the polymer applies mechanical stress to the semiconductor ingot.

[0090] Terms such as "first" and "second" are used to describe various elements, sections, segments, etc., and are not intended to be restrictive. Throughout the specification, the same term refers to the same element.

[0091] As used herein, the terms “having,” “containing,” “including,” “comprising,” etc., are open-ended terms that indicate the presence of the stated element or feature but do not exclude the existence of other elements or features. The articles “a,” “an,” and “the” are intended to include both plural and singular forms unless the context clearly indicates otherwise.

[0092] It should be understood that, unless otherwise specifically indicated, the features of the various embodiments described herein can be combined with each other.

[0093] Although specific embodiments have been shown and described herein, those skilled in the art will understand that various alternatives and / or equivalent implementations may be made in place of the specific embodiments shown and described without departing from the scope of the invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, the invention is defined only by the claims and their equivalents.

Claims

1. A method for dicing a semiconductor wafer, the method comprising: Forming one or more epitaxial layers on a semiconductor wafer; Multiple device structures are formed in one or more epitaxial layers; Metallization layers and / or passivation layers are formed on the plurality of device structures; A carrier plate is attached to the semiconductor wafer having one or more epitaxial layers, the carrier plate protecting the plurality of device structures and mechanically stabilizing the semiconductor wafer; A separation region is formed within the semiconductor wafer, the separation region having at least one altered physical property that increases thermomechanical stress within the separation region relative to the remainder of the semiconductor wafer, wherein the increased thermomechanical stress within the separation region promotes the cleaving of the semiconductor wafer, and wherein the cleaving of the semiconductor wafer occurs along a direction substantially parallel to the surface of the semiconductor wafer; and An external force is applied to the semiconductor wafer, causing at least one crack to propagate along the separation region, and the semiconductor wafer is divided into two separate workpieces. One of the workpieces retains the plurality of device structures, and the other of the workpieces does not include any of the plurality of device structures and is used to generate other additional devices. The formation of the separation region within the semiconductor wafer includes: Damage to the material of the semiconductor wafer at a target location within the semiconductor wafer. The material of the semiconductor wafer at the target location within the semiconductor wafer that is damaged includes: generating plasma in the material at the target location within the semiconductor wafer.

2. The method according to claim 1, wherein, Generating plasma in the material at the target location within the semiconductor wafer includes: The laser radiation is focused at the target location within the semiconductor wafer.

3. The method according to claim 1, wherein, The material that damages the semiconductor wafer at the target location within the semiconductor wafer also includes: Ions are implanted into the semiconductor wafer at a depth corresponding to the target location within the semiconductor wafer.

4. The method according to claim 3, wherein, The ions are selected from the group consisting of nitrogen ions, phosphorus ions, hydrogen ions and helium ions.

5. The method according to claim 3, wherein, The implantation dose of the ions is selected such that the material of the semiconductor wafer damaged by the implanted ions is amorphous or produces cavities.

6. The method according to claim 3, wherein, The material that damages the semiconductor wafer at the target location within the semiconductor wafer also includes: After ion implantation, laser radiation is focused at the target location within the semiconductor wafer. The injected ions increase the absorption coefficient in the separation region at the wavelength of the laser radiation.

7. The method according to claim 1, further comprising: The bevel of the semiconductor wafer is thinned to a depth at or below the separation region.

8. The method according to claim 1, further comprising: A groove is formed in the inclined edge of the semiconductor wafer, extending laterally into the separation region.

9. The method according to claim 1, wherein, Applying the external force to the semiconductor wafer includes: Ultrasonic vibrations are applied to the semiconductor wafer.

10. The method according to claim 1, wherein, Applying the external force to the semiconductor wafer includes: A polymer is applied to the semiconductor wafer and / or carrier plate, the polymer having a CTE (coefficient of thermal expansion) different from that of the semiconductor wafer; and The polymer and the semiconductor wafer are subjected to a temperature treatment, during which the polymer applies mechanical stress to the semiconductor wafer.

11. The method according to claim 10, wherein, The temperature treatment is selected such that the polymer undergoes a partial glass transition and partial crystallization during the temperature treatment.

12. The method according to claim 10, wherein, The temperature treatment includes a first stage and a second stage. During the first stage, the polymer and the semiconductor wafer undergo a temperature gradient from an initial temperature to room temperature, wherein the initial temperature is 300°C or lower but above room temperature. During the second stage, the polymer and the semiconductor wafer are further cooled to a temperature below the glass transition temperature of the polymer.

13. The method of claim 10, further comprising: Prior to the temperature treatment, one or more fillers are added to the polymer, which increases the thermal conductivity of the polymer and reduces the slope of the polymer's storage modulus.

14. The method according to claim 13, wherein, The one or more fillers include ZnO and / or carbon black.

15. The method of claim 10, further comprising: Prior to applying the polymer, the surfaces of the polymer and / or the semiconductor wafer and / or the carrier are chemically and / or physically treated.

16. The method of claim 10, wherein, The at least one crack propagates during the partial crystallization of the polymer, which occurs during the temperature treatment.

17. The method according to claim 1, wherein, Applying the external force to the semiconductor wafer includes: Pressure is applied to the semiconductor wafer during the process of dividing it into two separate workpieces.

18. The method according to claim 1, further comprising: After the semiconductor wafer is divided into two separate workpieces, the surface roughness of the separation surfaces of the two workpieces of the semiconductor wafer is reduced, each separation surface being formed as at least one crack propagates along the separation region.

19. The method according to claim 1, wherein, The at least one altered physical property of the separation zone includes a plurality of microcracks that are at least partially disconnected from each other within the separation zone, and wherein the plurality of microcracks connect with each other in response to the external force to form the at least one crack propagating along the separation zone.

20. The method according to claim 19, wherein, The semiconductor wafer is a SiC wafer, and wherein at least one crack formed by the connection of the plurality of microcracks in response to the external force has a serrated pattern.

21. A method for dicing a semiconductor wafer, the method comprising: One or more epitaxial layers are formed on the semiconductor wafer; Multiple device structures are formed in one or more epitaxial layers; Metallization layers and / or passivation layers are formed on the plurality of device structures; A carrier plate is attached to the semiconductor wafer having one or more epitaxial layers, the carrier plate protecting the plurality of device structures and mechanically stabilizing the semiconductor wafer; A separation region is formed in the semiconductor wafer, the separation region having at least one altered physical property that increases thermomechanical stress within the separation region relative to the remainder of the semiconductor wafer, wherein the increased thermomechanical stress within the separation region promotes the cleaving of the semiconductor wafer, and wherein the cleaving of the semiconductor wafer occurs along a direction substantially parallel to the surface of the semiconductor wafer; and An external force is applied to the semiconductor wafer, causing at least one crack to propagate along the separation region, and the semiconductor wafer is divided into two separate workpieces. One of the workpieces retains the plurality of device structures, and the other of the workpieces does not include any of the plurality of device structures and is used to generate other additional devices. Applying an external force to the semiconductor wafer includes applying ultrasonic vibration to the semiconductor wafer.

22. A method for dicing a semiconductor wafer, the method comprising: One or more epitaxial layers are formed on the semiconductor wafer; Multiple device structures are formed in one or more epitaxial layers; Metallization layers and / or passivation layers are formed on the plurality of device structures; A carrier plate is attached to the semiconductor wafer having one or more epitaxial layers, the carrier plate protecting the plurality of device structures and mechanically stabilizing the semiconductor wafer; A separation region is formed in the semiconductor wafer, the separation region having at least one altered physical property that increases thermomechanical stress within the separation region relative to the remainder of the semiconductor wafer, wherein the increased thermomechanical stress within the separation region promotes the cleaving of the semiconductor wafer, and wherein the cleaving of the semiconductor wafer occurs along a direction substantially parallel to the surface of the semiconductor wafer; and An external force is applied to the semiconductor wafer, causing at least one crack to propagate along the separation region, and the semiconductor wafer is divided into two separate workpieces. One of the workpieces retains the plurality of device structures, and the other of the workpieces does not include any of the plurality of device structures and is used to generate other additional devices. Applying external force to the semiconductor wafer includes: A polymer is applied to the semiconductor wafer and / or carrier plate, the polymer having a CTE (coefficient of thermal expansion) different from that of the semiconductor wafer; and The polymer and the semiconductor wafer are subjected to a temperature treatment, during which the polymer applies mechanical stress to the semiconductor wafer.

23. The method according to claim 22, wherein, The temperature treatment is selected such that the polymer undergoes a partial glass transition and partial crystallization during the temperature treatment.

24. The method according to claim 22, wherein, The temperature treatment includes a first stage and a second stage. During the first stage, the polymer and the semiconductor wafer undergo a temperature gradient from an initial temperature to room temperature, wherein the initial temperature is 300°C or lower but above room temperature. During the second stage, the polymer and the semiconductor wafer are further cooled to a temperature below the glass transition temperature of the polymer.

25. The method of claim 22, further comprising: Prior to the temperature treatment, one or more fillers are added to the polymer, which increases the thermal conductivity of the polymer and reduces the slope of the polymer's storage modulus.

26. The method of claim 25, wherein, The one or more fillers include ZnO and / or carbon black.

27. The method of claim 22, further comprising: Prior to applying the polymer, the surfaces of the polymer and / or the semiconductor wafer and / or the carrier are chemically and / or physically treated.

28. The method according to claim 22, wherein, The at least one crack propagates during the partial crystallization of the polymer, which occurs during the temperature treatment.

29. A method for dicing a semiconductor wafer, the method comprising: One or more epitaxial layers are formed on the semiconductor wafer; Multiple device structures are formed in one or more epitaxial layers; Metallization layers and / or passivation layers are formed on the plurality of device structures; A carrier plate is attached to the semiconductor wafer having one or more epitaxial layers, the carrier plate protecting the plurality of device structures and mechanically stabilizing the semiconductor wafer; A separation region is formed within the semiconductor wafer, the separation region having at least one altered physical property that increases thermomechanical stress within the separation region relative to the remainder of the semiconductor wafer, wherein the increased thermomechanical stress within the separation region promotes the cleaving of the semiconductor wafer, and wherein the cleaving of the semiconductor wafer occurs along a direction substantially parallel to the surface of the semiconductor wafer; and An external force is applied to the semiconductor wafer, causing at least one crack to propagate along the separation region, and the semiconductor wafer is divided into two separate workpieces. One of the workpieces retains the plurality of device structures, and the other of the workpieces does not include any of the plurality of device structures and is used to generate other additional devices. The at least one altered physical property of the separation zone includes multiple microcracks that are at least partially disconnected from each other within the separation zone. The plurality of microcracks connect with each other in response to the external force to form at least one crack that propagates along the separation zone. The semiconductor wafer is a SiC wafer, and the growth direction of the semiconductor wafer is slightly tilted relative to the main crystal axis. The at least one crack formed by the connection of the plurality of microcracks in response to the external force has a serrated pattern.

30. A method for dicing a semiconductor wafer from a semiconductor ingot, the method comprising: A separation region is formed in the semiconductor ingot, the separation region having at least one altered physical property that increases the thermomechanical stress within the separation region relative to the remainder of the semiconductor ingot, wherein the increased thermomechanical stress within the separation region promotes the dicing of the semiconductor wafer, and wherein the dicing of the semiconductor wafer occurs along a direction substantially parallel to the diameter of the semiconductor ingot; and An external force is applied to the semiconductor ingot, causing at least one crack to propagate along the separation region, and the wafer is separated from the semiconductor ingot. Applying an external force to the semiconductor ingot includes: A polymer is applied to the semiconductor ingot, the polymer having a CTE (coefficient of thermal expansion) different from that of the semiconductor ingot; and The polymer and the semiconductor ingot are subjected to a temperature treatment, during which the polymer applies mechanical stress to the semiconductor ingot.

31. The method according to claim 30, wherein, Forming the separation region within the semiconductor ingot includes: Damage to the material of the semiconductor ingot at the target location within the semiconductor ingot.

32. The method according to claim 31, wherein, The material that damages the semiconductor ingot at the target location within the semiconductor ingot includes: Plasma is generated in the material at the target location within the semiconductor ingot.

33. The method according to claim 32, wherein, Generating plasma in the material at the target location within the semiconductor ingot includes: The laser radiation is focused at the target location within the semiconductor ingot.

34. The method according to claim 31, wherein, The material that damages the semiconductor ingot at the target location within the semiconductor ingot includes: Ions are implanted into the semiconductor ingot at a depth corresponding to the target location within the semiconductor ingot.

35. The method according to claim 34, wherein, The ions are selected from the group consisting of nitrogen ions, phosphorus ions, hydrogen ions and helium ions.

36. The method according to claim 34, wherein, The implantation dose of the ions is selected such that the material of the semiconductor ingot damaged by the implanted ions is amorphous or produces cavities.

37. The method according to claim 31, wherein, The material that damages the semiconductor ingot at the target location within the semiconductor ingot includes: Ions are implanted into the semiconductor ingot at a depth corresponding to a target location within the semiconductor ingot; and After ion implantation, laser radiation is focused at the target location within the semiconductor ingot. The injected ions increase the absorption coefficient in the separation region at the wavelength of the laser radiation.

38. The method according to claim 30, wherein, Applying the external force to the semiconductor ingot includes: Ultrasonic vibrations are applied to the semiconductor ingot.

39. The method according to claim 38, wherein, The ultrasonic vibration has a frequency in the range of 20 kHz to 60 kHz.

40. The method of claim 38, further comprising: When the ultrasonic vibration is applied, the semiconductor ingot is placed in a container filled with fluid, such that the semiconductor ingot is immersed in the fluid.

41. The method according to claim 40, wherein, The fluid is pure water, deionized water, or a solvent.

42. The method according to claim 30, wherein, The temperature treatment is selected such that the polymer undergoes a partial glass transition and partial crystallization during the temperature treatment.

43. The method according to claim 30, wherein, The temperature treatment includes a first stage and a second stage. During the first stage, the polymer and the semiconductor ingot undergo a temperature gradient from an initial temperature to room temperature, the initial temperature being 300°C or lower but above room temperature. During the second stage, the polymer and the semiconductor ingot are further cooled to a temperature below the glass transition temperature of the polymer.

44. The method of claim 30, further comprising: Prior to the temperature treatment, one or more fillers are added to the polymer, which increases the thermal conductivity of the polymer and reduces the slope of the polymer's storage modulus.

45. The method according to claim 44, wherein, The one or more fillers include ZnO and / or carbon black.

46. ​​The method of claim 30, further comprising: Prior to applying the polymer, the surface of the polymer and / or the surface of the semiconductor ingot are chemically and / or physically treated.

47. The method of claim 30, wherein, The at least one crack propagates during the partial crystallization of the polymer, which occurs during the temperature treatment.

48. The method of claim 30, further comprising: After the wafer is separated from the semiconductor ingot, a new separation region is formed in the semiconductor ingot. The new separation region has at least one altered physical property that increases the thermomechanical stress within the new separation region relative to the rest of the semiconductor ingot. as well as An external force is applied to the semiconductor ingot, causing at least one crack to propagate along the new separation zone, and an additional wafer is separated from the semiconductor ingot.

49. A method for dicing a semiconductor wafer, the method comprising: The semiconductor wafer material at a target location within the semiconductor wafer is damaged to form a separation region within the semiconductor wafer. The separation region has at least one altered physical property that increases thermomechanical stress within the separation region relative to the remainder of the semiconductor wafer. This increased thermomechanical stress within the separation region promotes the segmentation of the semiconductor wafer, and the segmentation of the semiconductor wafer occurs along a direction substantially parallel to the surface of the semiconductor wafer. A groove is formed in the edge of a semiconductor wafer, wherein the groove extends laterally into the separation region; Apply a first stress to the semiconductor wafer; as well as Applying a second stress, different from the first stress, to the semiconductor wafer causes the semiconductor wafer to split into two separate pieces. The front side of the semiconductor wafer includes at least one device structure selected from the group consisting of: a plurality of device structures of a semiconductor device; a metallization layer and a passivation layer. The semiconductor wafer is divided into two separate pieces along the separation zone.

50. The method according to claim 49, wherein, The material of the semiconductor wafer at the target location within the semiconductor wafer that damages the semiconductor wafer includes: Plasma is generated in the material at the target location within the semiconductor wafer.

51. The method according to claim 50, wherein, Generating plasma in the material at the target location within the semiconductor wafer includes: The laser radiation is focused at the target location within the semiconductor wafer.

52. The method according to claim 49, wherein, The material of the semiconductor wafer at the target location within the semiconductor wafer that damages the semiconductor wafer includes: Ions are implanted into the semiconductor wafer at a depth corresponding to the target location within the semiconductor wafer.

53. The method according to claim 52, wherein, The ions are selected from the group consisting of nitrogen ions, phosphorus ions, hydrogen ions and helium ions.

54. The method according to claim 52, wherein, The implantation dose of the ions is selected such that the material of the semiconductor wafer damaged by the implanted ions is amorphous or produces cavities.

55. The method according to claim 49, wherein, The material of the semiconductor wafer at the target location within the semiconductor wafer that damages the semiconductor wafer includes: Ions are implanted into the semiconductor wafer at a depth corresponding to a target location within the semiconductor wafer; and After ion implantation, laser radiation is focused at the target location within the semiconductor wafer. The injected ions increase the absorption coefficient in the separation region at the wavelength of the laser radiation.

56. The method according to claim 49, wherein, Applying the first stress to the semiconductor wafer includes: Attaching polymers to semiconductor wafers and / or to carriers attached to semiconductor wafers; and Cool the polymer.

57. The method according to claim 56, wherein, The polymer undergoes a partial glass transition and partial crystallization during the cooling process.

58. The method according to claim 56, wherein, Cooling the polymer includes a first stage and a second stage. During the first stage, the polymer and the semiconductor wafer undergo a temperature gradient from an initial temperature to room temperature, which is 300°C or lower but above room temperature. During the second stage, the polymer and the semiconductor wafer are further cooled.

59. The method of claim 56, further comprising: Before cooling the polymer, one or more fillers are added to the polymer, wherein the fillers increase the thermal conductivity of the polymer and decrease the slope of the polymer's storage modulus.

60. The method according to claim 59, wherein, The one or more fillers include ZnO and / or carbon black.

61. The method of claim 56, further comprising: Before cooling the polymer, the surface of the polymer and / or the surface of the semiconductor wafer are chemically and / or physically treated.

62. The method according to claim 56, wherein, The at least one crack propagates during the partial crystallization of the polymer, which occurs during the cooling of the polymer.

63. The method according to claim 56, wherein, The polymer is attached to the back side of the semiconductor wafer.

64. The method according to claim 56, wherein, The polymer is attached to the outside of the carrier, which faces away from the semiconductor wafer, such that the carrier is located between the polymer and the semiconductor wafer.

65. The method of claim 49, further comprising: A carrier is attached to the front side of a semiconductor wafer, and the carrier protects the device structure.

66. The method according to claim 65, wherein, Applying a second stress to a semiconductor wafer includes: Apply ultrasonic vibrations to a semiconductor wafer.

67. The method according to claim 66, wherein, The ultrasonic vibration has a frequency in the range of 20 kHz to 60 kHz.

68. The method of claim 66, further comprising: The semiconductor wafer is placed in a container filled with fluid such that it is immersed in the fluid during the application of ultrasonic vibration.

69. The method of claim 49, wherein the edge of the semiconductor wafer is a bevel.

70. The method of claim 49, further comprising: Before applying a second stress to the semiconductor wafer, one or more epitaxial layers are formed on the front side of the semiconductor wafer, the one or more epitaxial layers comprising a device structure.

71. A method for dicing a semiconductor wafer, the method comprising: One or more epitaxial layers are formed on the semiconductor wafer; Multiple device structures are formed in one or more epitaxial layers; Metallization layers and / or passivation layers are formed on the plurality of device structures; A carrier plate is attached to the semiconductor wafer having one or more epitaxial layers, the carrier plate protecting the plurality of device structures and mechanically stabilizing the semiconductor wafer; Laser radiation is applied to a separation region within the semiconductor wafer, causing the separation region to have increased thermomechanical stress relative to the rest of the semiconductor wafer, and at least one crack propagates along the separation region, wherein the increased thermomechanical stress within the separation region promotes the separation of the semiconductor wafer, and wherein the separation of the semiconductor wafer occurs along a direction substantially parallel to the surface of the semiconductor wafer. as well as The semiconductor wafer is divided into two separate workpieces along the at least one crack, one of the workpieces retaining the plurality of device structures, and the other of the workpieces not including any of the plurality of device structures, and is used to generate other additional devices.

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