Switched mode power supply control topology

Abstract

The circuit (100) includes a power converter controller (105). In an example, the power converter controller is configured to receive a signal representative of a current of a power converter (110), compare the signal representative of the current of the power converter to an error signal (ERROR), and generate a peak current detection signal (IPEAK) having a value when the signal representative of the current of the power converter is not less than the error signal. A state machine circuit (130) is coupled to the peak current detection circuit. The state machine circuit is configured to receive the peak current detection signal, a clock signal (CLK), and a timer signal (T1), and implement a state machine to generate at least one control signal for controlling a mode of operation and a phase of operation of the power converter based on a value of the peak current detection signal, a value of the clock signal, and a value of the timer signal.

Description

Background Technology

[0001] A switch-mode power supply (SMPS) transfers power from an input power source to a load by switching one or more power transistors coupled to an energy storage element (such as an inductor / transformer and / or capacitor) via switching nodes / terminals. The power transistors may be included in a power converter that includes or is capable of being coupled to the energy storage element. An SMPS may include an SMPS controller to provide one or more gate drive signals to the power transistor(s). Summary of the Invention

[0002] Certain aspects of this specification provide a circuit. In some examples, the circuit includes a peak current detection circuit and a state machine circuit coupled to the peak current detection circuit. The peak current detection circuit is configured to receive an error signal, a feedback signal from the power converter, and a ramp compensation signal, and generate a peak current detection signal based on the error signal, the feedback signal from the power converter, and the ramp compensation signal. The state machine circuit includes a first state configured to generate control signals for controlling the operating mode and operating phase of the power converter, receive the peak current detection signal, a clock signal, and a timer signal, determine that one of the peak current detection signal or the timer signal is asserted and the other is de-asserted, and transition to another state of the state machine based on this determination. The state machine circuit further includes another state of the state machine. The other state of the state machine is configured to generate control signals based on the other state of the state machine for further controlling the operating mode and operating phase of the power converter in a manner different from the first state.

[0003] Other aspects of this specification provide a circuit. In some examples, the circuit includes a power converter controller. The power converter controller includes a peak current detection circuit and a state machine circuit. The peak current detection circuit is coupled to a feedback circuit. The peak current detection circuit is configured to receive a signal representing the current of the power converter. The peak current detection circuit is further configured to compare the signal representing the current of the power converter with an error signal. The peak current detection circuit is further configured to generate a peak current detection signal with an effective value when the signal representing the current of the power converter is not less than the error signal. The state machine circuit is coupled to the peak current detection circuit. The state machine circuit is configured to receive the peak current detection signal, a clock signal, and a timer signal. The state machine circuit is further configured to implement the state machine to generate at least one control signal for controlling the operating mode and operating phase of the power converter based on the values ​​of the peak current detection signal, the clock signal, and the timer signal.

[0004] Other aspects of this specification provide a system. In some examples, the system includes a switch-mode power supply (SMPS). The SMPS includes a power converter, an SMPS controller, and a gate driver. The power converter includes a plurality of transistors, each configured to receive a unique one of a plurality of gate control signals. The SMPS controller includes a feedback circuit, a peak current detection circuit, and a state machine circuit. The feedback circuit has an input terminal coupled to the power converter and an output terminal. The peak current detection circuit has a first input terminal coupled to the power converter, a second input terminal coupled to the output terminal of the feedback circuit, and an output terminal. The state machine circuit has an input terminal coupled to the output terminal of a gate determination circuit and an output terminal. The state machine circuit is configured to receive a peak current detection signal, a clock signal, and a timer signal, and implement the state machine to generate control signals for controlling the operating mode and operating phase of the power converter based on the values ​​of the peak current detection signal, the clock signal, and the timer signal. The gate driver has an input terminal coupled to the output terminal of the state machine circuit and an output terminal coupled to one of the plurality of transistors. Attached Figure Description

[0005] For a detailed description of the various examples, reference will now be made to the accompanying drawings, in which:

[0006] Figure 1 Box diagrams showing illustrative switch-mode power supplies in various examples;

[0007] Figure 2 Schematic diagrams of illustrative buck-boost power converters in various examples are shown;

[0008] Figure 3 Illustrative graphs showing illustrative waveforms of power converters in buck operating mode in various examples;

[0009] Figure 4 Schematic diagrams of illustrative buck-boost power converters in various examples are shown;

[0010] Figure 5 Illustrative graphs showing illustrative waveforms of power converters in buck-boost operating modes in various examples;

[0011] Figure 6 Illustrative graphs showing illustrative waveforms of power converters in buck-boost operating modes in various examples;

[0012] Figure 7 Illustrative graphs showing illustrative waveforms of power converters in buck-boost operating modes in various examples;

[0013] Figure 8Schematic diagrams of illustrative buck-boost power converters in various examples are shown;

[0014] Figure 9 Illustrative graphs showing illustrative waveforms in boost operation mode of power converters in various examples; and

[0015] Figure 10 Illustrative status diagrams for controlling power converters are shown in various examples. Detailed Implementation

[0016] In some architectures (e.g., buck-boost), the switch-mode power supply (SMPS) includes or can be coupled to an output / large-capacity capacitor in parallel with the load. The SMPS controller switches one or more power transistors to form a circuit arrangement with one or more energy storage elements to supply load current to the load and / or the output / large-capacity capacitor to maintain a regulated output voltage (e.g., by filtering the switch-controlled load current). For example, the power transistors can be coupled to an energy storage inductor via switching nodes / terminals. The energy storage inductor is switched by the SMPS controller between charge and discharge cycles to supply inductor current to the load and the output / large-capacity capacitor (e.g., through the energy storage inductor) to filter the inductor current to maintain a regulated output voltage. In some examples, the SMPS can be configured as a constant current source with energy storage elements but no output / large-capacity capacitor.

[0017] The power transistor can be implemented as a metal-oxide-semiconductor field-effect transistor (MOSFET) or any other suitable solid-state transistor device, such as a bipolar junction transistor (BJT). As the input voltage (VIN) or output voltage (VOUT) of the power converter varies, the SMPS controller can control the power converter to operate in different operating modes. For example, when VIN is greater than VOUT, the SMPS controller can control the power converter to operate in buck operation mode. When VIN is less than VOUT, the SMPS controller can control the power converter to operate in boost operation mode. When VIN is approximately equal to VOUT, the SMPS controller can control the power converter to operate in buck-boost mode. The power converter operates in a voltage-controlled mode. To control the operating mode of the power converter, the SMPS controller provides gate control signals to one or more power transistors of the power converter. The value of each of these gate control signals determines whether the corresponding power transistor receiving the gate control signal is in a conductive state (e.g., on) or a non-conductive state (e.g., off). To change the operating mode of the power converter, the SMPS controller modifies the value of one or more of the gate control signals to turn one or more of the power transistors on or off. Furthermore, while maintaining the operating mode of the power converter, the SMPS controller can modify the value of one or more of the gate control signals, for example, to alternately turn one or more power transistors on and off.

[0018] When the switching scheme of a power converter changes, glitches or other potentially undesirable variations may occur in VOUT. The switching scheme is the specific timing and value provided by the SMPS controller for the gate control signal when operating in or transitioning between operating modes. In some implementations, VOUT may experience sudden drops and / or spikes in value when the switching scheme changes. For example, glitches or other potentially undesirable variations may occur in VOUT when changing between buck and buck-boost operating modes, or between buck-boost and boost operating modes. In some circuit architectures, such glitches may be undesirable, for example, causing unexpected or undesirable operation. For example, in some circuits, a sudden drop or spike in VOUT may cause circuit reset and power cycling as a protective measure. Therefore, some customers may value the importance of VOUT having a substantially smooth profile at the point of transition between operating modes to minimize VOUT variation. Some examples in this specification may provide a VOUT variation of approximately + / -1%. Other examples in this specification may provide smaller variations, such as approximately + / - 0.75% VOUT, + / - 0.5% VOUT, + / - 0.25% VOUT, or less.

[0019] Some aspects of this specification relate to controllers suitable for controlling power converters, such as those in SMPS. In at least one example, the controller includes elements suitable for implementing transitions between operating modes that do not interfere with a smooth profile of VOUT at the transition point. Such transitions are hereinafter referred to herein as smooth transitions. To achieve smooth transitions, the controller implements a state machine that controls the value and timing of a gate control signal. In some implementations, the state machine monitors a peak current value (IPEAK), a timer value or signal (T1), and a clock signal value (CLK) associated with the power converter. Based on the value of one or more of these monitored variables at a given point in time, the state machine outputs one or more control signals to control the generation of the gate control signal. For example, based on when at least one of references T1 or CLK is reached, the state machine controls the generation of the gate control signal to keep the power converter in an operating mode or transition between operating modes. In some examples, the state machine, based on the teachings of this specification, prevents extreme shifts in the duty cycle of the power converter during transitions between operating modes. By preventing these extreme shifts, extreme shifts in IPEAK during transitions between operating modes are also avoided, and a smooth profile of VOUT is achieved at the transition point.

[0020] Now go to Figure 1The diagram illustrates a block diagram of an illustrative SMPS 100. In at least one example, the SMPS 100 includes a controller 105 and a power converter 110. The SMPS 100 switches power supplied by a power source 112 from node 185 to load 113, at least via the power converter 110. The power converter 110 is, for example, a buck-boost power converter capable of operating in buck, boost, and buck-boost modes. In at least one example, the controller 105 includes or is configured to be coupled to a feedback circuit 115, a peak current detection circuit 120, a slope compensation circuit 125, a circuit 130, an oscillator 132, and a gate driver 135. At least one example of the SMPS 100 includes aspects of the controller 105 and the power converter 110 on the same semiconductor die and / or in the same component package, while in other examples, the controller 105 and the power converter 110 may be manufactured separately and configured to be coupled together. For example, aspects of the controller 105 may be manufactured separately and coupled together. Therefore, although illustrated to include gate driver 135, in at least one example, controller 105 does not include gate driver 135, but is instead configured to be coupled to gate driver 135. In some examples, circuit 130 is any component or combination of components capable of performing processing to generate one or more output signals based on one or more input signals. In some embodiments, circuit 130 is a state machine circuit. In some examples, circuit 130 is an analog circuit configured to implement a state machine. In other examples, circuit 130 is a digital circuit configured to implement a state machine. In yet another example, circuit 130 is a mixed analog and digital circuit configured to implement a state machine. Based on the values ​​of one or more input signals of circuit 130, the state machine generates one or more control signals for controlling power converter 110, for example, via gate driver 135. In at least one example, gate driver 135 includes a plurality of inverters, wherein each inverter is uniquely coupled between an output terminal of circuit 130 and the gate terminal of a transistor of power converter 110.

[0021] In at least one example, feedback circuit 115 includes a resistor 140 coupled between node 165 and node 170, and a resistor 145 coupled between node 170 and ground node 175. Feedback circuit 115 further includes an amplifier 150 having a first input terminal (e.g., a non-inverting input terminal) coupled to node 180 and configured to receive a reference voltage (VREF) at node 180. Amplifier 150 further has a second input terminal (e.g., an inverting input terminal) coupled to node 170, and an output terminal coupled to node 182. A feedback signal (VFB) is present at node 170 and is a scaled representation of VOUT. Resistor 155 is coupled between node 182 and the top plate of capacitor 160, and the bottom plate of capacitor 160 is coupled to ground node 175.

[0022] Peak current detection circuit 120 has a first input terminal coupled to power converter 110 (e.g., a high-side power transistor (not shown) coupled to power converter 110) and a second input terminal coupled to node 182. Peak current detection circuit 120 further has a third input terminal coupled to the output terminal of ramp compensation circuit 125 and an output terminal coupled to the first input terminal of circuit 130. In at least one embodiment, circuit 130 receives IPEAK from peak current detection circuit 120. Circuit 130 further has a second input terminal coupled to oscillator 132, a third input terminal coupled to oscillator 132, and a fourth input terminal coupled to oscillator 132. In at least one embodiment, circuit 130 receives CLK and T1 from oscillator 132. In at least one example, circuit 130 has a number of output terminals at least equal to the number of power transistors in power converter 110, wherein each of these output terminals is coupled to a corresponding and corresponding input terminal of gate driver 135. The gate driver 135 then has a number of output terminals that are at least equal to the number of power transistors (not shown) of the power converter 110, wherein each output terminal of the gate driver 135 is uniquely coupled to the gate terminal of one of the power transistors of the power converter 110.

[0023] In at least one example, SMPS 100 is configured to receive VTN from power source 112 and provide VOUT at node 165 to supply load 113. VOUT is based at least in part on VIN and VREF received by SMPS 100 at node 180. VREF can be received from any suitable device (not shown), such as a processor, microcontroller, or any other device that exerts control over SMPS 100 to control the value of VOUT. In at least one example, VREF has a value representing the desired (e.g., user-expected, target, pre-configured, programmed, etc.) value of VFB. Therefore, in some embodiments, controller 105 receives one or more signals from power converter 110. For example, controller 105 can receive VOUT from power converter 110 and / or receive a value representing the inductor current (IL) of power converter 110. In various examples, the value representing IL can be a value measured directly from the inductor (not shown) of power converter 110 (or a terminal of another component of power converter 110 to which the inductor is also coupled) or a value sensed from a sensing element (not shown) of power converter 110. The sensing element is, for example, a sensing resistor, a transistor, or any other component or combination of components capable of measuring the IL of the power converter 110 and providing a value representing IL to the controller 105. In at least one example, the value representing IL is provided to the peak current detection circuit 120 and VOUT is provided to the feedback circuit 115.

[0024] In at least one example, feedback circuit 115 is configured to receive VREF and VOUT and generate an error signal indicating a change in VREF from VFB. In some examples, VFB is the output of a voltage divider formed by resistors 140 and 145, where the input of the voltage divider is VOUT. In some examples, amplifier 150 is a transconductance amplifier, where the current value output by amplifier 150 is the error signal (ERROR), which indicates a change in VREF from VFB. ERROR is then filtered by resistor 155 and capacitor 160 and then received by peak current detection circuit 120.

[0025] Peak current detection circuit 120 receives a signal representing IL and an error signal, and compares the signal representing IL with the error signal. When the value of the signal representing IL rises to reach the error signal (e.g., in a peak current system), peak current detection circuit 120 outputs a valid signal indicating that peak detection has been performed. In at least one example, this valid signal is IPEAK with a valid value (such as a logic high value). In other examples, such as in a valley current system, peak current detection circuit 120 outputs a valid signal indicating that valley detection has been performed when the value of the signal representing IL falls to reach the error signal. In some examples, peak current detection circuit 120 resets IPEAK to an invalid value based on a control signal generated when IPEAK is valid. For example, when IPEAK becomes valid, the gate control signal of the high-side transistor of power converter 110 is invalid and the gate control signal of the low-side transistor of power converter 110 is valid. In various examples, IPEAK may be reset by peak detection circuit 120 based on the rising or falling edge of any of these gate control signals.

[0026] In some examples, the peak current detection circuit 120 performs slope compensation before comparing the signal representing IL with the error signal. For example, the peak current detection circuit 120 receives a slope compensation signal from a slope compensation circuit 125. In at least one example, the slope compensation circuit 125 generates the slope compensation signal by charging a capacitor (not shown) with a current proportional to at least one of VIN or VOUT, wherein the voltage at the top plate of the capacitor is the slope compensation signal. Before comparison, the peak current detection circuit 120 adds the slope compensation signal to the signal representing IL or subtracts the slope compensation signal from the error signal. Therefore, in some examples, the peak current detection circuit 120 includes an adder (not shown) configured to add the slope compensation signal to the signal representing IL or subtract the slope compensation signal from the error signal. In some examples, the peak current detection circuit 120 further includes a comparator (not shown) configured to compare the output of the adder with one of the signal representing IL or the error signal. For example, when the adder adds the ramp compensation signal to the signal representing IL, the comparator compares the adder's output with the error signal to generate IPEAK. When the adder subtracts the ramp compensation signal from the error signal, the comparator compares the signal representing IL with the adder's output to generate IPEAK. The ramp compensation signal is generated by the ramp compensation circuit 125 based at least in part on IL and / or VOUT, according to any suitable scheme, processing, or architecture, the range of which is not limited herein. In some examples, the ramp compensation signal provides stability in the SMPS 100 when the SMPS 100 operates at a constant frequency and a duty cycle greater than about 50%. The peak current detection circuit 120 then outputs IPEAK to circuit 130.

[0027] Circuit 130 receives IPEAK, CLK, and T1, and generates one or more signals for controlling gate driver 135 based on the values ​​of IPEAK, CLK, and T1 relative to the state of circuit 130. For example, T1 may have a value that is a percentage of the period of CLK, such that T1 is reached after a rising edge in CLK and before another rising edge in CLK occurs. In some examples, T1 is reset at each rising edge of CLK. When power converter 110 operates in buck operation mode, circuit 130 outputs a control signal to gate driver 135 to keep power converter 110 in buck operation mode when IPEAK is active before T1 is reached. When operating in buck operation mode and IPEAK is active after T1 is reached, circuit 130 outputs a control signal to gate driver 135 to switch power converter 110 to buck-boost operation mode. When the power converter 110 operates in buck-boost mode, circuit 130 outputs a control signal to gate driver 135 to keep the power converter 110 in buck-boost mode when IPEAK is active before the rising edge of CLK. When operating in boost-buck mode and IPEAK is reached after the rising edge of CLK, circuit 130 outputs a control signal to gate driver 135 to switch the power converter 110 to boost mode.

[0028] When power converter 110 operates in boost mode, when IPEAK is active after T1, circuit 130 outputs a control signal to gate driver 135 to keep power converter 110 in boost mode. When operating in boost mode and when IPEAK is active before T1, circuit 130 outputs a control signal to gate driver 135 to switch power converter 110 to buck-boost mode. When power converter 110 operates in buck-boost mode, when IPEAK is active after the rising edge of T1 and before the rising edge of CLK, circuit 130 outputs a control signal to gate driver 135 to keep power converter 110 in buck-boost mode. When operating in buck-boost mode and when IPEAK is active before the rising edge of T1, circuit 130 outputs a control signal to gate driver 135 to switch power converter 110 to buck mode.

[0029] In some examples, oscillator 132 is any one or more circuits capable of generating and / or outputting CLK with a constant frequency and generating T1. In at least one example, T1 is generated by a resistor-capacitor (RC) timer circuit that is cleared or reset on each rising edge of CLK.

[0030] As described above, based on the control signal received from circuit 130, gate driver 135 generates gate control signals for controlling the power transistors of power converter 110. For example, gate driver 135 generates gate control signals that cause the power transistors of the power converter to alternately and selectively turn on and off to energize and de-energize elements such as inductors and / or capacitors. This energizing and de-energizing provides the buck, boost, and / or buck-boost functions described herein. Gate driver 135 can be implemented according to any suitable architecture, the scope of which is not limited herein.

[0031] Now go to Figure 2 A schematic diagram of an illustrative buck-boost power converter 200 is shown. In at least one example, as described above, the buck-boost power converter 200 is adapted to be implemented as Figure 1 The power converter 110 of the SMPS 100. Therefore, in the description Figure 2 Reference Figure 1 Some components or signals. Figure 2 The diagram illustrates a buck-boost power converter 200 during buck operation mode, which in some examples includes a buck excitation phase and a buck deexcitation phase.

[0032] In one example, the buck-boost power converter 200 includes a plurality of metal-oxide-semiconductor field-effect transistors (MOSFETs) 205, 210, 215, and 220, and at least one energy storage device (illustrated as inductor 225 in this example). In another example, the boost-buck power converter 200 further includes a second inductor (not shown) and / or a flying capacitor (not shown). In one example, MOSFETs 205 and 220 are implemented as p-type MOSFETs (PMOS), and MOSFETs 210 and 215 are implemented as n-type MOSFETs (NMOS). In at least one example, the buck-boost power converter 200 further includes a sensing element 230 adapted to sense the IL of inductor 225 and generate a signal representing IL. The sensing element 230 is, for example, a MOSFET, a resistor, or any other suitable circuit capable of sensing, measuring, or detecting IL or having means of sensing, measuring, or detecting IL. In at least one example, the sensing element 230 is implemented by one of MOSFETs 205, 210, 215 or 220, such that the sensing element 230 is not a separate additional component of the buck-boost power converter 200.

[0033] In one example architecture, the source terminal of MOSFET 205 is coupled to node 185 and configured to receive VIN, the drain terminal of MOSFET 205 is coupled to node 235, and the gate terminal of MOSFET 205 is coupled to a controller. The controller is, for example, a gate driver 135. The drain terminal of MOSFET 210 is coupled to node 235, the source terminal of MOSFET 210 is coupled to ground node 175, and the gate terminal of MOSFET 210 is coupled to the controller. The first terminal of inductor 225 is coupled to node 235, and the second terminal of inductor 225 is coupled to node 245. In at least one example, a sensing element 230 is coupled in series between node 235 and the first terminal of inductor 225. The drain terminal of MOSFET 215 is coupled to node 245, the source terminal of MOSFET 215 is coupled to ground node 175, and the gate terminal of MOSFET 215 is coupled to the controller. The source terminal of MOSFET 220 is coupled to node 245, the drain terminal of MOSFET 220 is coupled to node 165 where VOUT exists, and the gate terminal of MOSFET 220 is coupled to the controller. In at least one example, inductor 225 is implemented as an external component, such that buck-boost power converter 200 does not include inductor 225 but is configured to be coupled to inductor 225 between nodes 235 and 245. In at least one example, buck-boost power converter 200 is configured to be coupled to capacitor 250 (e.g., such as a filter capacitor) between the drain terminal of MOSFET 220 and ground node 175.

[0034] In one example, MOSFETs 205, 210, 215, and / or 220 are controlled to be turned on (e.g., conducting current between their respective drain and source terminals) and / or turned off (e.g., stopping current conduction between their respective drain and source terminals) based on signals received at their respective gate terminals. For example, one or more of MOSFETs 205, 210, 215, and / or 220 are controlled to be turned on or off based on a gate control signal received from a controller (e.g., output by gate driver 135 under the control of circuit 130). MOSFETs 205, 210, 215, and / or 220 may be turned on (or off) based on values ​​or relationships between values ​​present at one or more of their respective gate and / or source terminals.

[0035] like Figure 2 Furthermore, in at least one example, the buck-boost power converter 200 is configured to operate in a buck operating mode that includes a buck drive phase and a buck dedrive phase. The buck drive phase and the buck dedrive phase are... Figure 2The diagram shows a dashed line terminating at one end with an arrow indicating the direction of current flow in the buck-boost power converter 200 during the corresponding phase of buck operation mode.

[0036] During the buck-drive phase, at each rising edge of CLK, MOSFETs 205 and 220 are turned on by the controller, and MOSFETs 210 and 215 are turned off by the controller. In this configuration, current flows from node 185 to inductor 225 to charge the inductor until the value of the signal representing IL reaches the value of the error signal and IPEAK is active. When IPEAK is active, the buck-boost power converter 200 enters the buck-de-drive phase. During the buck-de-drive phase, MOSFETs 210 and 220 are turned on by the controller, and MOSFETs 205 and 215 are turned off by the controller. In this configuration, current discharges from the inductor until another rising edge of CLK is received and the buck-boost power converter 200 returns to the buck-drive phase.

[0037] Now go to Figure 3 Figure 300 illustrates an illustrative waveform of the power converter in buck operation mode. In some examples, Figure 300 illustrates... Figure 1 SMPS 100 and / or Figure 2 Some signals exist in the buck-boost power converter 200. For example, Figure 300 illustrates the operation in buck mode. Figure 1 SMPS 100 and / or Figure 2 The signal present in the buck-boost power converter 200. Therefore, in the description Figure 3 Reference Figure 1 and / or Figure 2 Some components or signals. In addition, the signals illustrated in Figure 300 are shown in an idealized manner, and the representation of noise and / or signal ripple is omitted for clarity.

[0038] Figure 300 illustrates two operating cycles of the buck-boost power converter 200, starting with the buck drive phase. When the buck drive phase begins, the value of IL starts to increase. At each rising edge of CLK, a new buck drive phase begins. When the value of IL (or the signal representing IL) increases to the value of ERROR, IPEAK becomes active. When IPEAK becomes active, the buck de-drive phase begins, and the value of IL decreases until the next rising edge of CLK occurs. Figure 3As further shown, when operating in buck mode and controlled to remain in buck mode, IPEAK is valid before T1 expires (e.g., timer T1 expires). In some examples, T1 becomes valid at approximately 90% of the operating cycle corresponding to the buck-boost power converter 200. Although VIN is shown in Figure 300 as having a substantially stable and constant value greater than VOUT, in some examples, as the value of VIN decreases, the duty cycle of the buck-boost power converter 200 (e.g., the duration of the buck excitation phase) increases. When the duty cycle increases sufficiently to cause IPEAK to no longer be valid before T1 expires, the buck-boost power converter 200 is controlled to switch to buck-boost operation mode.

[0039] Now go to Figure 4 This shows another schematic diagram of an illustrative buck-boost power converter 200. Figure 4 The diagram shows the buck-boost power converter 200 during buck-boost operation mode. Figure 4 The diagram also illustrates a buck-boost power converter 200 during the transition to or from buck-boost operating mode. To maintain the above information... Figure 2 and Figure 3 In the described buck operating mode, IPEAK is active before T1. However, when IPEAK becomes active after T1, the controller controls the power converter 110 to switch to buck-boost operating mode. The buck-boost operating mode (including round-trip switching) includes a buck excitation phase, a buck de-excitation phase, and a boost excitation phase. The buck excitation phase, buck de-excitation phase, and boost excitation phase are... Figure 4 The diagram shows a dashed line terminating at one end with an arrow, which indicates the direction of current flow in the buck-boost power converter 200 during the corresponding phase of buck-boost operation mode.

[0040] During the buck-drive phase, at each rising edge of CLK, MOSFETs 205 and 220 are turned on by the controller, while MOSFETs 210 and 215 are turned off. In this configuration, current flows from node 185 to inductor 225 to charge the inductor until the signal value representing IL reaches the error signal value and IPEAK is active. However, if IPEAK is not active before T1, at T1, MOSFETs 205 and 215 are turned on by the controller, and MOSFETs 210 and 220 are turned off. In this configuration, current continues to flow from node 185 to inductor 225 to continue charging the inductor until the signal value representing IL reaches the error signal value and IPEAK is active. When IPEAK is active, the buck-boost power converter 200 enters the buck de-drive phase. During the buck deactivation phase, MOSFETs 210 and 220 are turned on by the controller, while MOSFETs 205 and 215 are turned off by the controller. In this configuration, current discharges from the inductor until another rising edge of CLK is received.

[0041] Now go to Figure 5 Figure 500 illustrates an illustrative waveform of the power converter in buck-boost operating mode. In some examples, Figure 500 is shown in [the original text]. Figure 1 SMPS 100 and / or Figure 4 Some signals in the buck-boost power converter 200. For example, Figure 500 illustrates the transition from buck operation mode to buck-boost operation mode. Figure 1 SMPS 100 and / or Figure 4 The signal present in the buck-boost power converter 200. Therefore, in the description Figure 5 Reference Figure 1 and / or Figure 4 Some components or signals. Furthermore, the signals illustrated in Figure 500 are shown in an idealized manner; for clarity, the representation of noise and / or signal ripple is omitted.

[0042] Figure 500 illustrates the three operating cycles of the buck-boost power converter 200 when transitioning from buck operation mode to buck-boost operation mode. When the buck drive phase begins, the value of IL starts to increase. At each rising edge of CLK, a new buck drive phase begins. When T1 is active and IPEAK is inactive, the boost drive phase begins, and the value of IL increases more rapidly. When the value of IL (or the signal representing IL) increases to the value of ERROR, IPEAK becomes active. When IPEAK becomes active, the buck de-drive phase begins, and the value of IL decreases until the next rising edge of CLK occurs. Figure 5As further shown, when operating in buck-boost mode and controlled to remain in buck-boost mode, IPEAK is valid before T1 expires (e.g., timer T1 expires). In some examples, T1 becomes valid at approximately 90% of the operating cycle of the buck-boost power converter 200, corresponding to the period before the first boost excitation phase occurs. After the first boost excitation phase occurs, in some examples, T1 becomes valid at approximately 85% of the operating cycle of the buck-boost power converter 200. This modification of the T1 validity period provides hysteresis in the buck-boost power converter 200 to prevent rapid or repetitive sequential switching between operating modes. As further shown in Figure 500, when transitioning from buck operating mode to buck-boost operating mode, the value of VIN decreases substantially linearly and the value of VOUT remains substantially constant.

[0043] Now go to Figure 6 Figure 600 illustrates illustrative waveforms of a power converter in buck-boost operating mode. In some examples, Figure 600 illustrates... Figure 1 SMPS 100 and / or Figure 4 Some signals exist in the buck-boost power converter 200. For example, Figure 600 illustrates the operation in buck-boost mode. Figure 1 SMPS 100 and / or Figure 4 The signal present in the buck-boost power converter 200. Therefore, in the description Figure 6 Reference Figure 1 and / or Figure 4 Some components or signals. In addition, the signals illustrated in Figure 600 are shown in an idealized manner, and the representation of noise and / or signal ripple is omitted for clarity.

[0044] Figure 600 illustrates two operating cycles of the buck-boost power converter 200 during operation in buck-boost mode. In buck-boost mode, the buck drive phase begins at the rising edge of CLK. However, since the value of VIN has dropped to approximately equal to VOUT, as shown in Figure 600, a very small change occurs in IL during the buck drive phase. The boost drive phase begins when T1 is active and IPEAK is inactive, and the value of IL increases more rapidly. IPEAK becomes active when the value of IL (or the signal representing IL) increases to the value of ERROR. When IPEAK becomes active, the buck de-drive phase begins, and the value of IL decreases until the next rising edge of CLK occurs. The boost drive phase begins when T1 is active and IPEAK is inactive, and the value of IL increases more rapidly. IPEAK becomes active when the value of IL (or the signal representing IL) increases to the value of the error signal. When IPEAK becomes active, the buck de-drive phase begins, and the value of IL decreases until the next rising edge of CLK occurs. Figure 6 As further shown, when operating in buck-boost mode and controlled to remain in buck-boost mode, IPEAK is valid before T1 becomes active (e.g., timer T1 expires). In some examples, when operating in buck-boost mode, T1 becomes active at approximately 85% of the time corresponding to the operating cycle of the buck-boost power converter 200.

[0045] Now go to Figure 7 Figure 700 illustrates illustrative waveforms of a power converter in buck-boost operating mode. In some examples, Figure 700 illustrates... Figure 1 SMPS 100 and / or Figure 4 Some signals exist in the buck-boost power converter 200. For example, Figure 500 illustrates the transition from buck-boost operation mode to boost operation mode. Figure 1 SMPS100 and / or Figure 4 The signal present in the buck-boost power converter 200. Therefore, in the description Figure 7 Reference Figure 1 and / or Figure 4 Some components or signals. Furthermore, the signals illustrated in Figure 700 are shown in an idealized manner; for clarity, the representation of noise and / or signal ripple is omitted.

[0046] Figure 700 illustrates the three operating cycles of the buck-boost power converter 200 when transitioning from buck-boost operating mode to boost operating mode. When T1 is active and IPEAK is inactive, the boost de-excitation phase ends, and the boost excitation phase begins. The boost excitation phase continues until the value of IL increases to the value of ERROR and IPEAK becomes active. When IPEAK becomes active, the boost excitation phase ends, and the buck de-excitation phase begins. At the rising edge of CLK, the buck de-excitation phase ends, and the boost de-excitation phase begins, continuing until T1 becomes active again. As the value of VTN decreases relative to VOUT, as shown in Figure 700, the active time of IPEAK drifts relative to CLK for each operating cycle of the buck-boost power converter 200. When the active time drift of IPEAK is sufficient for IPEAK to be active no longer than the amount before the rising edge of CLK, the boost excitation phase continues until IPEAK becomes active. Subsequently, the buck-boost power converter 200 is controlled to operate in boost operating mode. Furthermore, when operating in boost mode, T1 again becomes active at approximately 90% of the time corresponding to the operating cycle of the buck-boost power converter 200. This modification of the T1 active time provides hysteresis in the buck-boost power converter 200 to prevent rapid or repetitive sequential switching between operating modes.

[0047] Now go to Figure 8 This shows another schematic diagram of an illustrative buck-boost power converter 200. Figure 8 The diagram illustrates the buck-boost power converter 200 during boost operation mode. To maintain as described above regarding... Figures 4 to 7 In the described buck-boost operating mode, IPEAK is valid before the rising edge of CLK. However, when IPEAK is valid after the rising edge of CLK, the controller controls the power converter 110 to switch from buck-boost operating mode to boost operating mode. The boost operating mode includes a boost drive phase and a boost de-drive phase. The boost drive phase and boost de-drive phase are... Figure 8 The diagram shows a dashed line ending with an arrow, which indicates the direction of current flow in the buck-boost power converter 200 during the corresponding phase of the boost operation mode.

[0048] During the boost phase, at each rising edge of time T1, MOSFETs 205 and 215 are turned on by the controller, and MOSFETs 210 and 220 are turned off. In this configuration, current flows from node 185 to inductor 225 to charge the inductor until the value of the signal representing IL reaches the value of the error signal and IPEAK is active. When IPEAK is active, MOSFETs 205 and 220 are turned on by the controller, and MOSFETs 210 and 215 are turned off. In this configuration, current discharges from the inductor until another rising edge of time T1 is active.

[0049] Now go to Figure 9 Figure 900 illustrates an illustrative waveform in the boost operation mode of the power converter. In some examples, Figure 900 illustrates... Figure 1 SMPS 100 and / or Figure 8 Some signals exist in the buck-boost power converter 200. For example, Figure 900 illustrates the signal when operating in boost mode. Figure 1 SMPS 100 and / or Figure 8 The signal present in the buck-boost power converter 200. Therefore, in the description Figure 9 Reference Figure 1 and / or Figure 8 Some components or signals. In addition, the signals illustrated in Figure 900 are shown in an idealized manner, and the representation of noise and / or signal ripple is omitted for clarity.

[0050] Figure 900 illustrates two operating cycles of the buck-boost power converter 200, starting from the boost excitation phase. When the boost excitation phase begins and T1 is active, the value of IL begins to increase. When the value of IL (or the signal representing IL) increases to the value of ERROR, IPEAK is active. When IPEAK is active, the boost de-excitation phase begins and the value of IL decreases until T1 is active again. Although VIN is shown in Figure 900 as having a substantially stable and constant value less than VOUT, in some examples, as the value of VIN increases, the duty cycle of the buck-boost power converter 200 (e.g., the duration of the boost excitation phase) decreases.

[0051] Now go to Figure 10 This illustrates a state diagram of a state machine 1000 used to control a power converter. In some examples, the state machine 1000 is illustrated... Figure 1The operation of the controller 105 of the SMPS 100 (and therefore implemented therein in some examples). In some examples, the state machine 1000 indicates rules and / or conditions for controlling a power converter (such as the power converter 110 of the SMPS 100) to operate in buck operation mode, boost operation mode, or buck-boost operation mode at a given time. In some examples, as described above, the state machine 1000 is implemented by circuit 130. In some implementations, circuit 130 includes one or more analog and / or digital components to implement the state machine. Furthermore, the state machine 1000 may be implemented at least partially in hardware or software. For example, some implementations of the state machine 1000 are implemented by one or more components capable of and configured to perform logical operations. The logical operations accept any one or more of CLK, T1, or IPEAK as input. Based on the results of those logical operations, one or more control signals (such as those described above with respect to circuit 130) are generated and output by the component performing the logical operations. The control signals control components (such as...) Figure 1 The gate driver 135 controls the power converter to operate in the operating mode and / or phase specified by the state in which the state machine 1000 is operating.

[0052] In state 1, the power converter is controlled in either the buck drive phase or the boost de-drive phase (in...). Figure 10 The diagram shows the operation during the BOD phase. Figure 10 As illustrated in the diagram (BUE), when operating according to state 1, the power converter is controlled to remain in the buck-drive phase until T1 is invalid and IPEAK is valid. When operating in the buck-drive phase and the controller determines that T1 is invalid and IPEAK is valid, state machine 1000 transitions to state 5. When the power converter operates according to state 1 in the boost-deactivation phase, the power converter is controlled to remain in the boost-deactivation phase until T1 is valid and IPEAK is invalid. When operating in the boost-deactivation phase and the controller determines that T1 is valid and IPEAK is invalid, state machine 1000 transitions to state 2. Furthermore, when operating in state 1, MOSFETs 205 and 220 are controlled to be turned on and MOSFETs 210 and 215 are controlled to be turned off.

[0053] In state 2, the power converter is controlled in the boost excitation stage (in... Figure 10The diagram illustrates operation in state 2 (BOE). When operating in state 2, in at least one example, T1 is set to 85% of the power converter's operating cycle. While the power converter operates according to state 2, it is controlled to remain in the boost-driven phase until a rising edge in CLK or IPEAK becomes active. When the power converter operates according to state 2 and a rising edge in CLK occurs, state machine 1000 transitions to state 3. When the power converter operates according to state 2 and IPEAK becomes active, state machine 1000 transitions to state 6. Furthermore, when operating in state 2, MOSFETs 205 and 215 are controlled to be turned on, and MOSFETs 210 and 220 are controlled to be turned off.

[0054] In state 3, the power converter is controlled to operate continuously during the boost phase. When operating in state 3, in at least one example, T1 is set to 90% of the power converter's operating cycle. When the power converter operates according to state 3 and IPEAK becomes active, state machine 1000 transitions to state 4. Furthermore, when operating in state 3, MOSFETs 205 and 215 are controlled to be turned on, and MOSFETs 210 and 220 are controlled to be turned off.

[0055] In state 4, the power converter is controlled to operate in the boost de-drive phase. While the power converter operates according to state 4, it is controlled to remain in the boost de-drive phase until IPEAK becomes invalid. When the power converter operates according to state 4 and IPEAK becomes invalid, state machine 1000 is reset and transitions to state 1. Furthermore, when operating in state 4, MOSFETs 205 and 220 are controlled to be turned on, and MOSFETs 210 and 215 are controlled to be turned off.

[0056] In state 5, the power converter is controlled to operate during the buck de-excitation phase (in... Figure 10 The operation is shown in BUD. When the power converter operates according to state 5, T1 is set to 90% of the power converter's operating cycle, and then the state machine transitions to state 6.

[0057] In state 6, the power converter is controlled to continue operating in the buck de-excitation phase. While the power converter operates according to state 6, it is controlled to remain in the buck de-excitation phase until a rising edge in CLK occurs. When the power converter operates according to state 6 and a rising edge occurs in CLK, state machine 1000 transitions to state 7. Furthermore, while operating in state 6, MOSFETs 205 and 220 are controlled to be turned on, and MOSFETs 210 and 215 are controlled to be turned off.

[0058] In state 7, the power converter is controlled to operate in the buck-drive phase. When the power converter operates according to state 7, it is controlled to remain in the buck-drive phase until CLK, T1, and IPEAK are invalidated. When the power converter operates according to state 7, and CLK, T1, and IPEAK are invalidated, state machine 1000 is reset and transitions to state 1. Furthermore, when operating in state 7, MOSFETs 205 and 220 are controlled to be turned on, and MOSFETs 210 and 215 are controlled to be turned off.

[0059] In the foregoing description, the terms “comprising” and “including” are used in an open-ended manner and therefore mean “including, but not limited to…”. The term “coupled” is used throughout the specification. This term can encompass connection, communication, or signal paths that achieve a functional relationship consistent with the description herein. For example, if device A generates a signal to control device B to perform an action, in a first example, device A is coupled to device B; or in a second example, if intervening component C does not substantially alter the functional relationship between device A and device B, device A is coupled to device B via intervening component C such that device B is controlled by control signals generated by device A. A device “configured” to perform a task or function may be configured by the manufacturer at manufacturing time (e.g., programmed and / or hardwired) to perform that function and / or may be user-configurable (or reconfigurable) after manufacturing to perform that function and / or other additional or alternative functions. Configuration can be achieved through firmware and / or software programming of the device, through the construction and / or layout of hardware components, and the interconnection of the device, or a combination thereof. Furthermore, circuits or devices referred to as including certain components may alternatively be configured to be coupled to those components to form the described circuit or device. For example, a structure described as including one or more semiconductor elements (such as transistors), one or more passive elements (such as resistors, capacitors and / or inductors) and / or one or more sources (such as voltage sources and / or current sources) may alternatively include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or integrated circuit (IC) package) and may be configured to couple some of the passive elements and / or sources to form the described structure during or after manufacturing (e.g. by an end user and / or a third party).

[0060] While certain components are described herein as being made using specific process technologies (e.g., FET, MOSFET, n-type, p-type, etc.), these components can be replaced with components using other process technologies (e.g., replacing FETs and / or MOSFETs with bipolar junction transistors (BJTs), n-type with p-type, and vice versa, etc.) and the circuitry including the replacement components can be reconfigured to provide at least partially similar functionality to that available before the component replacement. Unless otherwise stated, components illustrated as resistors generally represent any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the illustrated resistor. Furthermore, the use of the phrase "ground voltage potential" in the above description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of grounding connection applicable or suitable for the teachings of this specification. Unless otherwise stated, "about," "approximately," or "substantially" preceding a value means + / - 10% of the value.

[0061] The above description illustrates the principles and various examples of this specification. Many variations and modifications within the scope of this specification will be apparent to those skilled in the art. This specification includes all such variations and modifications.

Claims

1. A circuit comprising: The peak current detection circuit is configured as follows: The system receives an error signal, a feedback signal from the power converter, and a ramp compensation signal, wherein the error signal represents the difference between the feedback voltage of the power converter and a reference voltage, the feedback voltage represents the output voltage of the power converter, and the feedback signal represents the current of the power converter. The feedback signal is compared with an error signal, wherein at least one of the error signal or the feedback signal is modified according to the slope compensation signal before the comparison; and In response to comparing the feedback signal with the error signal, a peak current detection signal is generated; as well as A state machine circuit, coupled to the peak current detection circuit, has a first state and another state, wherein: In the first state, the state machine circuit is configured as follows: Generate control signals for controlling the operating mode and operating phase of the power converter; Receive the peak current detection signal, clock signal, and timer signal; The validity of the peak current detection signal is determined before the timer signal becomes valid or after the edge of the clock signal; and Based on the determination, the transition to the other state of the state machine circuit is made; and In the other state, the state machine circuit is configured as follows: The control signal is generated to control the operating mode and operating phase of the power converter in a manner different from the first state.

2. The circuit of claim 1, wherein the state machine circuit has a plurality of states, the plurality of states including the first state and the other state, wherein each state of the state machine circuit corresponds to at least one of a buck excitation operation phase, a buck de-excitation operation phase, a boost excitation operation phase, or a boost de-excitation operation phase, and wherein each of the listed operation phases corresponds to at least two states of the state machine circuit, and wherein the timer signal has a value that is a percentage of the period of the clock signal, such that the timer signal expires after a rising edge in the clock signal and before another rising edge in the clock signal occurs.

3. The circuit of claim 2, wherein the plurality of states includes the first state, a second state, a third state, a fourth state, a fifth state, a sixth state, and a seventh state implemented as the other state, and wherein the first state corresponds to the buck-drive operation phase or the boost-deactivation operation phase, the second state corresponds to the boost-drive operation phase, the third state corresponds to the boost-drive operation phase, the fourth state corresponds to the boost-deactivation operation phase, the fifth state corresponds to the buck-deactivation operation phase, the sixth state corresponds to the buck-deactivation operation phase, and the seventh state corresponds to the buck-drive operation phase.

4. The circuit of claim 2, wherein the plurality of states includes a first state, a second state, a third state, a fourth state, a fifth state, a sixth state, and a seventh state implemented as the other state, and wherein the first state corresponds to the buck-drive operation phase or the boost-deactivate operation phase, the second state corresponds to the boost-drive operation phase, the third state corresponds to the boost-drive operation phase, the fourth state corresponds to the boost-deactivate operation phase, the fifth state corresponds to the buck-deactivate operation phase, the sixth state corresponds to the buck-deactivate operation phase, and the seventh state corresponds to the buck-drive operation phase.

5. The circuit of claim 1, wherein in the first state, the state machine circuit is further configured to transition to a second state implemented as the other state in response to the timer signal being valid and the peak current detection signal being invalid, and in the second state, the state machine circuit is configured to transition back to the first state via at least one additional state.

6. The circuit of claim 5, wherein in the second state, the state machine circuit is further configured to transition to a third state when the clock signal becomes valid and after setting the period of the timer signal to a first value, and in the third state, the state machine circuit is configured to transition to a fourth state in response to the peak current detection signal being valid and after setting the period of the timer signal to a second value, and in the fourth state, the state machine circuit is configured to transition to the first state in response to the peak current detection signal being invalid.

7. The circuit of claim 5, wherein in the second state, the state machine circuit is further configured to transition to a sixth state in response to the peak current detection signal being valid, in the sixth state, the state machine circuit is configured to transition to a seventh state in response to the clock signal being valid, and in the seventh state, the state machine circuit is configured to transition to the first state in response to the peak current detection signal being invalid, the clock signal being invalid, and the timer signal being invalid.

8. The circuit of claim 1, wherein in the first state, the state machine circuit is further configured to transition to a fifth state implemented as the other state in response to the timer signal being invalid and the peak current detection signal being valid, and in the fifth state, the state machine circuit is configured to transition back from the fifth state to the first state via at least one additional state.

9. The circuit of claim 8, wherein in the fifth state, the state machine circuit is further configured to transition to a sixth state after setting the period of the timer signal to a first value, in the sixth state, the state machine circuit is configured to transition to a seventh state in response to the clock signal being valid, and in the seventh state, the state machine circuit is configured to transition to the first state in response to the peak current detection signal being invalid, the clock signal being invalid, and the timer signal being invalid.

10. A circuit comprising: Power converter controller, comprising: A peak current detection circuit having a first input terminal, a second input terminal, and an output terminal, wherein the peak current detection circuit is configured as follows: A signal representing the current of the power converter is received at the first input terminal, and an error signal is received at the second input terminal, wherein the error signal represents the difference between the feedback voltage of the power converter and the reference voltage, and the feedback voltage represents the output voltage of the power converter; The signal representing the current of the power converter is compared with an error signal; and In response to comparing the signal representing the current of the power converter with the error signal, a peak current detection signal having an effective value is generated at its output terminal; and A state machine circuit having corresponding first input terminals, second input terminals, and third input terminals, and corresponding output terminals, wherein the first input terminals are coupled to the output terminals of the peak current detection circuit, and the state machine circuit is configured to: It receives the peak current detection signal at its first input terminal, a clock signal at its second input terminal, and a timer signal at its third input terminal; and A control signal is generated at its output terminal. This control signal is used to control the operating mode and operating phase of the power converter based on the values ​​of the peak current detection signal, the clock signal, and the timer signal. The state machine circuit has a first state and another state, wherein: In the first state, the state machine circuit is configured as follows: Generate control signals for controlling the operating mode and operating phase of the power converter; The validity of the peak current detection signal is determined before the timer signal becomes valid or after the edge of the clock signal; and Based on the determination, the transition to the other state of the state machine circuit is made; and In the other state, the state machine circuit is configured as follows: The control signal is generated to control the operating mode and operating phase of the power converter in a manner different from the first state.

11. The circuit of claim 10, wherein the power converter controller further comprises: A feedback circuit having corresponding input terminals and corresponding output terminals, the output terminal of which is coupled to the second input terminal of the peak current detection circuit, the feedback circuit being configured as follows: It receives the output voltage of the power converter at its input terminal; Generate a feedback voltage signal; and The error signal is generated based on the difference between the feedback voltage signal and the reference voltage signal; A slope compensation circuit, coupled to the peak current detection circuit and configured to generate a slope compensation signal, wherein at least one of the error signal or the signal representing the current of the power converter is modified according to the slope compensation signal before the comparison; and An oscillator, coupled to the state machine circuit and configured to generate and output the clock signal and the timer signal; The timer signal has a value that is a percentage of the period of the clock signal, such that the timer signal expires after a rising edge of the clock signal and before another rising edge of the clock signal occurs.

12. The circuit of claim 10, further comprising a gate driver having a corresponding input terminal coupled to the output terminal of the state machine circuit, and the gate driver being configured to: Receive the control signal from the state machine circuit; and Generate gate control signals for the respective gate terminals of the transistors of the power converter, wherein each received control signal uniquely corresponds to the generated gate control signal.

13. The circuit of claim 12, further comprising the power converter, the power converter including the transistor.

14. The circuit of claim 10, wherein the state machine circuit is configured as follows: The control signal for controlling the operating mode and the operating phase of the power converter is generated based on the first state of the state machine circuit. Monitor at least some of the peak current detection signal, the clock signal, and the timer signal to determine when the value of at least one of the peak current detection signal, the clock signal, or the timer signal changes; The state machine circuit transitions to another state at least in part based on a change in the value of the peak current detection signal, the clock signal, or the timer signal. as well as Based on the other state of the state machine circuit, control signals are generated for controlling the operating mode and the operating phase of the power converter.

15. The circuit of claim 14, wherein the state machine circuit has states, the states including at least the first state and the other state, wherein each state of the state machine circuit corresponds to at least one of a buck excitation operation phase, a buck de-excitation operation phase, a boost excitation operation phase, or a boost de-excitation operation phase, and each of the listed operation phases corresponds to at least two states of the state machine circuit.

16. The circuit of claim 15, wherein the states include the first state, the second state, the third state, the fourth state, the fifth state, the sixth state, and the seventh state, wherein the first state corresponds to the buck-drive operation phase or the boost-de-drive operation phase, the second state corresponds to the boost-drive operation phase, the third state corresponds to the boost-drive operation phase, the fourth state corresponds to the boost-de-drive operation phase, the fifth state corresponds to the buck-de-drive operation phase, the sixth state corresponds to the buck-de-drive operation phase, and the seventh state corresponds to the buck-drive operation phase.

17. A circuit system comprising: Switch-mode power supplies, or SMPS, include: A power converter comprising transistors, each transistor having a corresponding gate terminal; and SMPS controller, which includes: A feedback circuit having an input terminal and an output terminal, the input terminal being coupled to the output voltage of the power converter; A peak current detection circuit has a first input terminal, a second input terminal, and a corresponding output terminal. The first input terminal is coupled to the power converter to receive a signal representing the current of the power converter, and the second input terminal is coupled to the output terminal of the feedback circuit. A state machine circuit having corresponding input terminals and corresponding output terminals, wherein the input terminals are coupled to the output terminals of the peak current detection circuit, the state machine circuit being configured as follows: It receives peak current detection signals, clock signals, and timer signals; and At its output terminals, control signals are generated for controlling the operating mode and operating phase of the power converter based on the values ​​of the peak current detection signal, the clock signal, and the timer signal; and A gate driver having corresponding input and output terminals, wherein its input terminals are coupled to the output terminals of the state machine circuit and its output terminals are coupled to the gate terminals of the transistor. The state machine circuit has a first state and another state, wherein: In the first state, the state machine circuit is configured as follows: Generate control signals for controlling the operating mode and operating phase of the power converter; The validity of the peak current detection signal is determined before the timer signal becomes valid or after the edge of the clock signal; and Based on the determination, the transition to the other state of the state machine circuit is made; and In the other state, the state machine circuit is configured as follows: The control signal is generated to control the operating mode and operating phase of the power converter in a manner different from the first state.

18. The circuit system of claim 17, wherein the feedback circuit is configured as follows: Receive the output voltage of the power converter; Generate a feedback voltage signal; and An error signal is generated based on the difference between the feedback voltage signal and the reference voltage signal. The peak current detection circuit is configured as follows: Receive a signal representing the current of the power converter; The signal representing the current of the power converter is compared with the error signal; and In response to comparing the signal representing the current of the power converter with the error signal, a peak current detection signal with an effective value is generated, and The gate driver is configured as follows: Receive the control signal from the state machine circuit; and A gate control signal corresponding to the control signal is generated, wherein the transistor is controlled by the gate control signal to realize the operating mode and the operating phase of the power converter, wherein the number of output terminals of the state machine circuit, the number of input terminals of the gate driver, and the number of output terminals of the gate driver each correspond to the number of transistors, and wherein each output terminal of the gate driver is uniquely coupled to the gate terminal of one of the transistors of the power converter. The timer signal has a value that is a percentage of the period of the clock signal, such that the timer signal expires after a rising edge of the clock signal and before another rising edge of the clock signal occurs.

19. The circuit system of claim 18, wherein the SMPS controller further comprises: A slope compensation circuit, coupled to the peak current detection circuit and configured to generate a slope compensation signal, wherein at least one of the error signal or the signal representing the current of the power converter is modified according to the slope compensation signal before the comparison; as well as An oscillator, coupled to the state machine circuit, is configured to generate and output the clock signal and the timer signal.

20. The circuit system of claim 17, wherein the state machine circuit is further configured to: The control signal for controlling the operating mode and the operating phase of the power converter is generated based on the first state of the state machine circuit. Monitor at least some of the peak current detection signal, the clock signal, and the timer signal to determine when the value of at least one of the peak current detection signal, the clock signal, or the timer signal changes; The state machine circuit transitions to another state at least in part based on changes in the values ​​of the peak current detection signal, the clock signal, or the timer signal; and The control signal for controlling the operating mode and operating phase of the power converter is generated based on the other state of the state machine circuit.

21. The circuit system of claim 20, wherein the state machine circuit has a plurality of states, the plurality of states including at least the first state and the other state, wherein each state of the state machine circuit corresponds to at least one of a buck excitation operation phase, a buck de-excitation operation phase, a boost excitation operation phase, or a boost de-excitation operation phase, and wherein each of the listed operation phases corresponds to at least two states of the state machine circuit.

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