Electronic circuits, semiconductor modules

Abstract

This invention provides an electronic circuit and semiconductor module capable of preventing damage to a return diode. The electronic circuit includes: a first diode (BD0) having a PN junction with a forward voltage of a first voltage; a second diode (SBD0) having a Schottky junction with a forward voltage of a second voltage lower than the first voltage; a first wiring member (50, 52, 54, 55) connected between a first terminal (U) and a second terminal (P) via the first diode; and a second wiring member (50-53) connected between the first terminal and the second terminal via the second diode, and having an inductance greater than that of the first wiring member.

Description

Technical Field

[0001] This invention relates to electronic circuits and semiconductor modules. Background Technology

[0002] There is a bridge circuit that includes switching elements in the upper arm and switching elements in the lower arm, and serves as a circuit for driving loads (e.g., Patent Document 1). Existing technical documents Patent documents

[0003] Patent Document 1: Japanese Patent Application Publication No. 2020-009834 Summary of the Invention The technical problem that the invention aims to solve

[0004] For example, when the switching element of the lower arm is turned off, the current flowing through the switching element of the lower arm generally flows through the parasitic diode of the switching element of the upper arm and the return diode connected to the switching element of the upper arm.

[0005] However, when the forward voltage of the parasitic diode is greater than that of the return diode, most of the current flowing through the load flows through the return diode, and therefore, the return diode is sometimes damaged.

[0006] The present invention was made in view of the above-mentioned problems, and its object is to provide an electronic circuit and a semiconductor module that can prevent damage to the return diode. Technical means for solving technical problems

[0007] The electronic circuit of the present invention, which solves the above problems, includes: a first diode having a PN junction with a forward voltage of a first voltage; a second diode having a Schottky junction with a forward voltage of a second voltage that is smaller than the first voltage; a first wiring member connecting a first terminal and a second terminal via the first diode; and a second wiring member connecting the first terminal and the second terminal via the second diode, and having an inductance greater than that of the first wiring member.

[0008] Furthermore, the semiconductor module of the present invention includes an electronic circuit comprising: a first diode having a PN junction with a forward voltage of a first voltage; a second diode having a Schottky junction with a forward voltage of a second voltage lower than the first voltage; a first wiring member connecting a first terminal and a second terminal via the first diode; and a second wiring member connecting the first terminal and the second terminal via the second diode, and having an inductance greater than that of the first wiring member. Invention Effects

[0009] According to the present invention, an electronic circuit and semiconductor module that can prevent damage to the return diode can be provided. Attached Figure Description

[0010] Figure 1 This is a diagram showing an example of electronic circuit 10. Figure 2 This is a diagram used to illustrate the current flowing through diodes BD0 and SBD0 in the upper arm. Figure 3 This is a diagram used to illustrate the current flowing through diodes BD2 and SBD2 in the lower arm. Figure 4 This is a top view of semiconductor module 80. Figure 5 This is a schematic diagram illustrating the structure of semiconductor module 80. Figure 6 It is a diagram used to illustrate the wiring pattern conceptually formed on the conductive pattern 220. Figure 7 This is a diagram used to illustrate the current flowing through the components of the upper arm of the semiconductor module 80. Figure 8 This is a diagram showing an example of the equivalent circuit of the upper arm components. Figure 9 This is a diagram used to illustrate the current flowing through the components of the lower arm of the semiconductor module 80. Figure 10 This is a diagram showing an example of the equivalent circuit of the lower arm components. Figure 11 This is a diagram illustrating an example of an implementation of adjusting the length of the lead wire. Figure 12 It is shown Figure 11 A diagram of the equivalent circuit of the implementation method. Figure 13 This is a diagram illustrating an example of an implementation of adjusting the cross-sectional area of ​​the lead wire. Figure 14 This is a diagram illustrating an example of an implementation of adjusting the curvature of the lead wire. Figure 15 This is a diagram illustrating an example of an implementation of adjusting the lead pattern. Figure 16 This is a schematic diagram used to illustrate the thickness of conductive patterns 240 and 250. Figure 17 This is a diagram showing an example of the structure of the upper arm of the semiconductor module 80. Figure 18 It is shown Figure 17 A diagram of the equivalent circuit of the implementation method. Figure 19 This is a diagram showing an example of the structure of the lower arm of semiconductor module 80. Figure 20 It is shown Figure 17 A diagram of the equivalent circuit of the implementation method. Detailed Implementation

[0011] Cross-reference of related applications This application claims priority to and incorporates the contents of Japanese Patent Application No. 2020-075679, filed on April 21, 2020.

[0012] Based on the description in this specification and the accompanying drawings, at least the following matters are clearly defined.

[0013] ======This implementation method====== <<<An Example of Electronic Circuit 10>>> Figure 1 This diagram illustrates the configuration of an electronic circuit 10 according to one embodiment of the present invention. The electronic circuit 10 is a half-bridge circuit for driving loads such as motor coils (not shown), and is configured to include NMOS transistors (n-Type Metal-Oxide-Semiconductor Field-Effect Transistors) M0 to M3, diodes SBD0 to SBD3, positive terminal P, output terminal U, negative terminal N, and control terminals IN1 and IN2.

[0014] The NMOS transistor M0 is the switching element of the upper arm. Its gate electrode (control electrode) is connected to the control terminal IN1 of the upper arm, its source electrode is connected to the output terminal U, and its drain electrode is connected to the positive terminal P. Furthermore, the NMOS transistor M0 includes a diode BD0 as a parasitic diode (i.e., a body diode).

[0015] NMOS transistor M1 is a switching element with the same upper arm as NMOS transistor M0, and includes diode BD1.

[0016] NMOS transistor M2 is the switching element of the lower arm. Its gate electrode is connected to the control terminal IN2 of the lower arm, its source electrode is connected to the negative terminal N, and its drain electrode is connected to the output terminal U. In addition, NMOS transistor M2 includes diode BD2 as a parasitic diode.

[0017] NMOS transistor M3 is a switching element with the same lower arm as NMOS transistor M2, containing diode BD3.

[0018] In this embodiment, a MOS transistor is used as the switching element, but it is not limited to this. As the switching element, an insulated-gate bipolar transistor (IGBT) containing a bipolar transistor and a diode, i.e., an RC (reverse-conducting) IGBT, can be used. In the case of an RC-IGBT, the internal PN junction diode can be diodes BD0 to BD3.

[0019] In this embodiment, diodes BD0 to BD3 are PN junction diodes. Furthermore, the NMOS transistors M0 to M3 in this embodiment are devices manufactured using a wide-bandgap semiconductor, SiC (Silicon Carbide). Therefore, the forward voltage Vf1 (first voltage) of diodes BD0 to BD3, which are body diodes, becomes the value based on the SiC PN junction (e.g., 2.5V).

[0020] Diode SBD0 is a Schottky barrier diode comprising a metal and an n-type SiC Schottky junction, connected in reverse parallel with NMOS transistor M0. Furthermore, diodes SBD1 to SBD3 are also SiC Schottky barrier diodes, connected in reverse parallel with NMOS transistors M1 to M3 respectively. Therefore, diodes SBD0 to SBD3 operate as return current diodes. Additionally, the forward voltage Vf2 (second voltage) of diodes SBD0 to SBD3 is a value based on the Schottky junction (e.g., 0.7V).

[0021] Furthermore, in this embodiment, the switching element and the return diode are fabricated using SiC, but other wide-bandgap semiconductors such as GaN (Gallium Nitride) can also be used. Additionally, the return diode can also be a Schottky barrier diode comprising a Schottky junction containing metal and Si.

[0022] The positive terminal P is the power supply side (or high side) terminal, the negative terminal N is the ground side (or low side) terminal, and the output terminal U is the terminal for connecting the load. Additionally, the control terminal IN1 is the upper arm switching element, receiving signals to control the switching of NMOS transistors M0 and M1. The control terminal IN2 is the lower arm switching element, receiving signals to control the switching of NMOS transistors M2 and M3.

[0023] In this electronic circuit 10, the load is driven by turning on and off the switching elements of the upper arm and the lower arm. When the electronic circuit 10 drives the load, if the switching elements of the upper arm and the lower arm are simultaneously turned on, a larger current flows from the positive terminal P to the negative terminal N. Therefore, when driving the load, a dead time period is set during which the switching elements of the upper arm and the lower arm are both turned off. During the dead time period, for example, current sometimes flows from the output terminal U to the positive terminal P. Furthermore, during the dead time period, for example, current sometimes flows from the negative terminal N to the output terminal U.

[0024] <<<Regarding the current from output terminal U to positive terminal P>>> Figure 2 For example, a diagram illustrating the current flowing through diodes BD0 and SBD0 in the upper arm during the dead time period is provided. Furthermore, in this embodiment, the current flowing through diodes BD0 and SBD0 during the dead time period is the same as the current flowing through diodes BD1 and SBD1; therefore, only the current flowing through diodes BD0 and SBD0 will be described here.

[0025] Figure 2 Node x0 in is Figure 1 The node x1 connects the wiring from the output terminal U, the wiring from the source electrode S1 of the NMOS transistor M0, and the wiring from the anode electrode A0 of the diode SBD0. Additionally, node x1 is a node connecting the wiring from the positive terminal P, the wiring from the drain electrode D1 of the NMOS transistor M0, and the wiring from the cathode electrode K0 of the diode SBD0. Hereinafter, the anode electrode will be referred to as the anode, and the cathode electrode as the cathode.

[0026] Furthermore, here, the wiring between the output terminal U and node x0 is designated as wiring 50 for inductor La, and the wiring between node x0 and the anode A0 of diode SBD0 is designated as wiring 51 for inductor Lb. Additionally, the wiring between the positive terminal P and node x1 is designated as wiring 52 for inductor Lc, and the wiring between node x1 and the cathode K0 of diode SBD0 is designated as wiring 53 for inductor Ld. Furthermore, the wiring between the source electrode S1 of NMOS transistor M0 and node x0 is designated as wiring 54 for inductor Li, and the wiring between the drain electrode D1 of NMOS transistor M0 and node x1 is designated as wiring 55 for inductor Lj. In addition, inductors La to Ld, Li, and Lj are parasitic inductances of wirings 50 to 55.

[0027] Furthermore, as described above, diode BD0 is a body diode with a forward voltage Vf1 (e.g., 2.5V) of a SiC-based PN junction, and diode SBD0 is a Schottky diode with a forward voltage Vf2 (e.g., 0.7V) of a SiC-based Schottky junction.

[0028] Therefore, the current from the output terminal U first flows to the positive terminal P via the path P2 shown by the dotted line through diode SBD0. At this time, the voltage Vx01 between node x0 and node x1 becomes as follows (1).

[0029] Vx01=(Lb+Ld)×di2 / dt+Vf2···(1) In equation (1), the current flowing through path P2 is defined as i2, and di2 / dt is defined as the time variation of the current i2 flowing to path P2. In addition, the time variation of current i2 is determined by the current flowing through the load and the time from the switching element to the switching element from being turned on to being turned off, for example, 0.1 to 10 A / nsec.

[0030] Here, for example, when the values ​​of inductors Lb and Ld are small and the voltage Vx01 does not exceed the forward voltage Vf1 (e.g., 2.5V), all the current flowing from the output terminal U flows in path P2. As a result, the current i2 exceeds the rated current of diode SBD0, and diode SBD0 is sometimes damaged. Therefore, in this embodiment, the values ​​of inductors Lb and Ld are increased so that the current from the output terminal U flows to the positive terminal P not only through path P2, but also through path P1 shown by the dashed line through diode BD0. In addition, the values ​​of inductors Lb and Ld are calculated based on the relationship of equation (2).

[0031] (Lb+Ld)×di2 / dt+Vf2>(Li+Lj)×di1 / dt+Vf1···(2) If we transform equation (2), set the forward voltage Vf1 to 2.5V, the forward voltage Vf2 to 0.7V, and the di2 / dt (=di1 / dt) to 10A / nsec, we get the following relationship as shown in equation (3).

[0032] ((Lb+Ld)-(Li+Lj))>(Vf1-Vf2)×dt / di2>(2.5-0.7)×(1 / 10)>0.18···(3) As a result, if the combined value of inductances Lb and Ld is greater than the combined value of inductances Li and Lj by, for example, 0.18 nH, then currents i1 and i2 flow through paths P1 and P2, preventing large currents from flowing through diode SBD0.

[0033] Therefore, in this embodiment, the inductance of the wiring in path P2 is greater than that in path P1, so that diode SBD0 conducts when current flows in from output terminal U. As a result, the current i2 flowing through diode SBD0 in the current from output terminal U can be reduced, thus preventing damage to diode SBD0.

[0034] Figure 2 For example, as a wiring connected to node x0, three wirings 50, 51, and 54 are modeled. However, when node x0 corresponds to the source electrode S1, the inductance Li of wiring 54 can be ignored, and Li = 0. Furthermore, for example, when node x0 corresponds to the output terminal U, the inductance La of wiring 50 can be ignored, and La = 0. Therefore, although detailed later, by using... Figure 2 The circuit can be used to represent various semiconductor modules using equivalent circuits.

[0035] Furthermore, here, diode BD0 is equivalent to "first diode", and diode SBD0 is equivalent to "second diode". Also, output terminal U is equivalent to "first terminal", and positive terminal P is equivalent to "second terminal". Furthermore, wiring 50, 52, 54, and 55 connected between output terminal U and positive terminal P via diode BD0 is equivalent to "first wiring member", and wiring 50-53 connected between output terminal U and positive terminal P via diode SBD0 is equivalent to "second wiring member".

[0036] In this embodiment, the forward voltage Vf1 is set to 2.5V and the forward voltage Vf2 is set to 0.7V, but these values ​​are just examples. Furthermore, the values ​​of the forward voltages Vf1 and Vf2, and the inductance of the wiring, vary depending on manufacturing tolerances.

[0037] Furthermore, the combined required inductance values ​​Lb and Ld vary depending on the operating temperature, current, and time. Therefore, the inductance of the "second wiring member" should be at least larger than that of the "first wiring member." Preferably, the inductance of the "second wiring member" is at least 0.18 nH larger than that of the "first wiring member." More preferably, the inductance of the "second wiring member" is at least 0.36 nH larger than that of the "first wiring member."

[0038] <<Regarding the current from the negative terminal N to the output terminal U>> Figure 3 For example, a diagram illustrating the current flowing through diodes SBD2 and BD2 in the lower arm during the dead time period is provided. Furthermore, in this embodiment, the current flowing through diodes BD2 and SBD2 during the dead time period is the same as the current flowing through diodes BD3 and SBD3; therefore, only the current flowing through diodes BD2 and SBD2 will be described here.

[0039] Figure 3 Node x2 in the middle is Figure 1The node x3 connects the wiring from the negative terminal N, the wiring from the source electrode S2 of the NMOS transistor M2, and the wiring from the anode electrode A3 of the diode SBD2. Additionally, node x3 is a node that connects the wiring from the output terminal U, the wiring from the drain electrode D2 of the NMOS transistor M2, and the wiring from the cathode K3 of the diode SBD2.

[0040] Furthermore, here, the wiring between the negative terminal N and node x2 is designated as wiring 60 for inductor Le, and the wiring between node x2 and the anode A3 of diode SBD2 is designated as wiring 61 for inductor Lf. Additionally, the wiring between the output terminal U and node x3 is designated as wiring 62 for inductor Lg, and the wiring between node x3 and the cathode K3 of diode SBD2 is designated as wiring 63 for inductor Lh. Furthermore, the wiring between the source electrode S2 of NMOS transistor M2 and node x2 is designated as wiring 64 for inductor Lm, and the wiring between the drain electrode D2 of NMOS transistor M2 and node x3 is designated as wiring 65 for inductor Ln. In addition, inductors Le to Lh, Lm, and Ln are parasitic inductances of wirings 60 to 65.

[0041] In this embodiment, with Figure 2 Similarly, in the upper arm, when current flows in from the negative terminal N, the values ​​of inductances Lf and Lh increase, so that the current i3 flowing through path P3 (shown by the dashed line of diode BD2) and the current i4 flowing through path P4 (shown by the dotted line of diode SBD2) can flow. Specifically, based on the above equation (3), for example, let (Lf+Lh)-(Lm+Ln)>0.18nH. As a result, when current flows in from the negative terminal N, it is possible to prevent a large current from flowing through the lower arm diode SBD2 and damaging diode SBD2.

[0042] Furthermore, in this case, diode BD2 is equivalent to "first diode", and diode SBD2 is equivalent to "second diode". Additionally, the negative terminal N is equivalent to "first terminal", and the output terminal U is equivalent to "second terminal". Furthermore, wiring 60, 62, 64, and 65 connected between output terminal N and output terminal U via diode BD2 is equivalent to "first wiring member", and wiring 60-63 connected between negative terminal N and output terminal U via diode SBD2 is equivalent to "second wiring member".

[0043] ===An example of semiconductor module 80=== Figure 4 This is a top view schematic diagram showing an example of a semiconductor module 80 that embodies the electronic circuit 10. Figure 5This is a schematic diagram illustrating the structure of the semiconductor module 80. Furthermore, in this embodiment, the plurality of switching elements and return diodes of the electronic circuit 10 are mounted in the semiconductor module 80 with the same configuration. Therefore, Figure 5 For simplicity, only the NMOS transistor M0 and diode SBD0 of the upper arm are shown in the diagram.

[0044] Furthermore, the gate electrode G1 and source electrode S1 of the NMOS transistor M0 are formed, for example, on the central axis of the NMOS transistor M0, but they are shown separately here for convenience. In this embodiment, "electrical connection" refers to the connection of structures E1 and E2 via wiring, bonding materials (e.g., solder) to enable them to conduct electricity; it is also simply referred to as "connection". In addition to the case of connection via wiring components, "connection" also includes the case of connection between structures E1 and E2 via conductive patterns provided between structures E1 and E2.

[0045] Semiconductor module 80 is a semiconductor device that includes multiple switching elements and return diodes of electronic circuit 10. Figure 4 In this configuration, the switching elements are NMOS transistors M0 to M3, and the return diodes are diodes SBD0 to SBD3. The semiconductor module 80 is configured to include: multilayer substrates 110 and 111 comprising conductive patterns 210, 220, 230, 310, 320, and 330; switching elements and return diodes disposed on the conductive patterns 220 and 320; terminals disposed on the conductive patterns 210, 220, 310, 320, and 330; and bonding lines electrically connected to the switching elements, return diodes, and conductive patterns. Alternatively, it may be configured to include a substrate 100.

[0046] The terminals, for example, have a prism shape, with one end engaged with a conductive pattern and the other end extending from the semiconductor module 80 and electrically connected to an external device (not shown). The terminals are made of, for example, copper, aluminum, or an alloy containing them.

[0047] The bonding wire is made of copper, aluminum, gold, or an alloy containing them. Furthermore, components other than bonding wires can also be used as wiring components. For example, a lead frame can be used as a wiring component.

[0048] The substrate 100 has a smooth bonding surface on its upper surface to which an insulating circuit substrate is bonded, for example, having a rectangular shape in plan view. The substrate 100 is, for example, a metal plate formed of aluminum, copper, or an alloy containing them. The substrate 100 is as follows... Figure 5 As shown, a laminated substrate 110 is mounted on a bonding material 101 such as solder. In addition, a laminated substrate 111 is also mounted on a substrate 100 with the same structure as the laminated substrate 110.

[0049] <<Laminated substrate 110 on the upper arm side>> The laminated substrate 110 includes an insulating plate 200 and conductive patterns 210, 220, and 230 formed on the surface (upper side) of the insulating plate 200. The insulating plate 200 is made of, for example, ceramic or resin. The conductive patterns 210, 220, and 230 are made of, for example, copper, aluminum, or alloys containing them. The laminated substrate 110 may also have a heat sink 201 on the back side (lower side) of the insulating plate 200. The insulating circuit substrate thus configured is formed, for example, a DCB (Direct Copper Bonding) substrate or an AMB (Active Metal Brazing) substrate. In this embodiment, the laminated substrate 110 is a DBC (Direct Bonded Copper) substrate with components mounted on upper arms.

[0050] <<Conductive Pattern 210>> Conductive pattern 210 is fitted with a control terminal IN1 for inputting signals to the switching elements of the upper arm. Here, as... Figure 5 As shown, the conductive pattern 210 is mounted with a control terminal IN1 via a bonding material 252 (e.g., solder). The conductive pattern 210 is connected to the gate electrode G1 of the NMOS transistor M0 via a bonding wire (hereinafter referred to as a lead) and is connected to the gate electrode of the NMOS transistor M1 via a lead.

[0051] Furthermore, in this embodiment, the connection relationships between NMOS transistor M1 and diode SBD1, output terminal U, positive terminal P, and control terminal IN1 in the upper arm are the same as those between NMOS transistor M0 and diode SBD0, output terminal U, positive terminal P, and control terminal IN1. Therefore, the explanation here will focus on NMOS transistor M0 and diode SBD0.

[0052] <<Conductive Pattern 220>> Conductive pattern 220 is fitted with the positive terminal P on the power supply side, NMOS transistors M0 and M1, and diodes SBD0 and SBD1. Here, as... Figure 5 As shown, the conductive pattern 220 is mounted with a drain electrode D1 formed on the back side of the NMOS transistor M0 via a bonding material 250 (e.g., solder). In this embodiment, the cathode K1 of the diode BD0 is common to the drain electrode D1, and as a result, the cathode K1 of the diode BD0 is also ultimately connected to the conductive pattern 220.

[0053] Furthermore, the cathode K0 of the diode SBD0 is mounted on the conductive pattern 220 via the bonding material 251. Additionally, the positive terminal P is mounted on the conductive pattern 220 via the bonding material.

[0054] Here, the anode A0 formed on the surface of diode SBD0 and the source electrode S1 formed on the surface of NMOS transistor M0 are electrically connected via lead W1. The anode A1 of diode BD0 and the source electrode S1 are common, resulting in the anode A1 of diode BD0 and the anode A0 of diode SBD0 ultimately being connected via lead W1.

[0055] Figure 6 This diagram illustrates the wiring pattern conceptually generated in conductive pattern 220. In conductive pattern 220, for example, current from the cathode K1 of diode BD0 flows along path P10 between cathode K1 and positive terminal P. Furthermore, current from the cathode K0 of diode SBD0 flows along path P11 between cathode K0 and positive terminal P. Therefore, in conductive pattern 220, wiring patterns corresponding to paths P10 and P11 are generated, respectively.

[0056] In this embodiment, the wiring pattern corresponding to path P10 is designated as wiring pattern C10, and the wiring pattern corresponding to path P11 is designated as wiring pattern C11. Path P11 is longer than path P10; therefore, wiring pattern C11 is longer than wiring pattern C10. Consequently, the inductance of wiring pattern C11 is greater than the inductance of wiring pattern C10.

[0057] Additionally, NMOS transistor M1 and diode SBD1 are also mounted on conductive pattern 220 in the same manner as NMOS transistor M0 and diode SBD0; therefore, detailed descriptions are omitted here. Furthermore, the term "wiring pattern" is conceptually defined as wiring formed within a portion of the conductive pattern, but it can be wiring that actually forms a pattern.

[0058] <<Conductive Pattern 230>> Figure 4 The conductive pattern 230 is a pattern electrically connected to the output terminal U. More specifically, it is a pattern with leads attached from the conductive pattern 320 (described later) to which the output terminal U is attached. The conductive pattern 230 is connected via lead W0 to the source electrode S1 of the NMOS transistor M0 and the anode A1 of the diode BD0. The lead W1 from the source electrode S1 is connected to the anode A0 of the diode BD0.

[0059] <<Laminated substrate 111 on the lower arm side>> The stacked substrate 111 is a DBC substrate on which the lower arm component is mounted. The stacked substrate 111 has the same structure as the stacked substrate 110, so detailed description is omitted, but conductive patterns 310, 320, and 330 are formed on the surface of the insulating plate 300 on the stacked substrate 111.

[0060] <<Conductive Pattern 310>> The conductive pattern 310 is fitted with a control terminal IN2 for inputting signals to control the switching elements of the lower arm. The conductive pattern 310 is fitted with the control terminal IN2 via a bonding material (e.g., solder). The conductive pattern 310 is connected via leads to the gate electrode G2 of the NMOS transistor M2 and via leads to the gate electrode of the NMOS transistor M3.

[0061] Furthermore, in the lower arm, the connection relationships between NMOS transistor M2 and diode SBD2, output terminal U, negative terminal N, and control terminal IN2 are the same as those between NMOS transistor M3 and diode SBD3, output terminal U, negative terminal N, and control terminal IN2. Therefore, this explanation will focus on NMOS transistor M2 and diode SBD2.

[0062] <<Conductive Pattern 320>> The conductive pattern 320 is equipped with an output terminal U connected to the load, NMOS transistors M2 and M3, and diodes SBD2 and SBD3. Furthermore, the connection relationships between these components and the conductive pattern 320 are as follows: Figure 5 The connection relationships between the NMOS transistor M0, diode SBD0, and conductive pattern 220 described herein are the same.

[0063] Specifically, the drain electrode D2 on the back side of the NMOS transistor M2 and the cathode K2, which is common to the drain electrode D2, are connected to the conductive pattern 320 via a bonding material. Furthermore, the cathode K3 formed on the back side of the diode SBD2 is connected to the conductive pattern 320 via a bonding material. Additionally, the conductive pattern 320 is fitted with an output terminal U via a bonding material.

[0064] Here, the anode A3 formed on the surface of diode SBD2 and the source electrode S2 formed on the surface of NMOS transistor M2 are electrically connected via lead W3. The anode A2 and source electrode S2 of diode BD2 are common, resulting in the anode A3 of diode SBD2 and the anode A2 of diode BD2 ultimately being connected via lead W3.

[0065] Furthermore, at this time, the distance from the cathode K3 of diode SBD2 to the output terminal U is longer than the distance from the cathode K2 of diode BD2 to the output terminal U. Therefore, the inductance of the wiring pattern from the output terminal U to diode SBD2 is greater than the inductance of the wiring pattern from the output terminal U to diode BD2. Here, the "distance (or path)" from the output terminal U to the cathode K3 of diode SBD2 is determined, for example, by the center of the cathode K3 electrode and the center of the output terminal U.

[0066] In addition, NMOS transistor M3 and diode SBD3 are connected to conductive pattern 320 with the same structure as NMOS transistor M2 and diode SBD2, therefore, detailed description is omitted here.

[0067] <<Conductive Pattern 330>> The conductive pattern 330 is fitted with a negative terminal N on the ground side. The conductive pattern 330 is fitted with the negative terminal N via a bonding material (e.g., solder). The conductive pattern 330 is connected to the source electrode S2 of the NMOS transistor M2 via a lead W2, and is also connected to the source electrode of the NMOS transistor M3 via a lead.

[0068] <<Regarding the current from output terminal U to positive terminal P>> Here, in semiconductor module 80, regarding the current from output terminal U to positive terminal P, refer to... Figure 7 and Figure 8 To illustrate, the current from the output terminal U flows through conductive pattern 320, the lead connecting conductive pattern 320 and conductive pattern 230, conductive pattern 230, and lead W0 to the source electrode S1 of NMOS transistor M0 (anode A1 of diode BD0). Furthermore, the current from lead W0 is supplied to the anode A0 of diode SBD0 via lead W1.

[0069] Here, the wiring from the output terminal U to the source electrode S1 of the NMOS transistor M0 (the anode A1 of the diode BD0) can be equivalently represented as follows: Figure 8 Wiring 50. Furthermore, the lead W1 from the source electrode S1 to the anode A0 of diode SBD0 can be equivalently represented as wiring 51. Additionally, in Figure 8 and Figure 2 In this context, structures with the same labels are identical.

[0070] The current supplied to the anode A1 of diode BD0 passes through the cathode K1 on the back side. Figure 6 The wiring pattern C10 flows towards the positive terminal P. Furthermore, the current supplied to the anode A0 of diode SBD0 flows through the cathode K0 on the back side. Figure 6 The wiring pattern C11 flows to the positive terminal P. Here, the wiring pattern C10 from the cathode K1 to the positive terminal P can be equivalently represented as... Figure 8 Wiring 55, the wiring pattern C11 from cathode K0 to positive terminal P can be equivalently represented as wiring 53.

[0071] In this embodiment, Figure 8The inductance of the wiring path P2 is increased to satisfy the condition of equation (3). Specifically, for example, the inductances Lb and Ld are increased so that the difference between the inductance of path P2 (La+Lb+Ld) and the inductance of path P1 (La+Lj) increases to more than 0.18nH.

[0072] As a result, the current i1 from the output terminal U, which is supplied to the source electrode S1 (anode A1 of diode BD0) on the surface of NMOS transistor M0, flows from the anode A1 on the surface of diode BD0 through diode BD0 to the cathode K1 on the back side, and then flows to the positive terminal P through the wiring pattern C10 in the conductive pattern 220. Furthermore, the current i2 supplied to the anode A0 on the surface of diode SBD0 flows from the anode A0 on the surface of diode SBD0 through diode SBD0 to the cathode K0 on the back side, and then flows to the positive terminal P through the wiring pattern C11 in the conductive pattern 220.

[0073] Therefore, in this embodiment, even if a large current flows into the output terminal U, the current can still flow through both diodes BDO and SBD0, thus preventing damage to diode SBD0. Furthermore, in the semiconductor module 80, the wiring pattern provided in path P1 (e.g., lead W0, wiring pattern C10 in conductive pattern 220) corresponds to the "first wiring pattern," and the wiring pattern provided in path P2 (e.g., leads W0, W1, wiring pattern C11 in conductive pattern 220) corresponds to the "second wiring pattern."

[0074] <<Regarding the current from the negative terminal N to the output terminal U>> Next, in semiconductor module 80, regarding the current from the negative terminal N to the output terminal U, refer to... Figure 9 and Figure 10 To illustrate, the current from the negative terminal N flows through conductive pattern 330 and lead W2 to the source electrode S2 of NMOS transistor M2 (anode A2 of diode BD2). Furthermore, the current from lead W2 is supplied to the anode A3 of diode SBD2 via lead W3.

[0075] Here, the lead W2 connecting the negative terminal N and the source electrode S2 (anode A2 of diode BD2) of NMOS transistor M2 can be equivalently represented as Figure 10 Wiring 60. The lead W3 connecting the source electrode S2 of NMOS transistor M2 and the anode A3 of diode SBD2 can be equivalently represented as Figure 10 Wiring 61. Furthermore, with Figure 6 Similarly, the wiring pattern from cathode K2 to output terminal U can be equivalently represented as wiring 65, and the wiring pattern from cathode K3 to output terminal U can be equivalently represented as wiring 63.

[0076] In this embodiment, the inductance of the wiring in path P4 is increased to satisfy the condition of equation (3). Specifically, for example, the inductances Lf and Lh are increased so that the difference between the inductance of path P4 (Le+Lf+Lh) and the inductance of path P3 (Le+Ln) increases to more than 0.18nH.

[0077] Therefore, the current i3 from the negative terminal N, which is supplied to the source electrode S2 (anode A2 of diode BD2) on the surface of NMOS transistor M2, flows from the anode A2 on the surface of diode BD2 through diode BD2 to the cathode K2 on the back side, and then flows to the output terminal U through the wiring pattern (not shown) in conductive pattern 320. Furthermore, the current i4 supplied to the anode A3 on the surface of diode SBD2 flows from the anode A3 on the surface of diode SBD2 through diode SBD2 to the cathode K3 on the back side, and then flows to the output terminal U through the wiring pattern (not shown) in conductive pattern 320.

[0078] As a result, in this embodiment, even if a large current flows in from the negative terminal N, the current can still flow through both diodes BD2 and SBD2, thus preventing diode SBD2 from being damaged.

[0079] ===Other Implementation Methods=== Here, for example, to prevent the diode SBD0 in the upper arm from being damaged by current, make Figure 2 The inductance Lb of wiring 51 or the inductance Ld of wiring 53 can be increased.

[0080] <<Wire Wiring 51: Case Implemented Using Leads>> When wiring 51 is implemented by leads, the inductance Lb can be increased by increasing the length of the leads, decreasing the cross-sectional area of ​​the leads, or increasing the curvature of the leads.

[0081] <<Adjust the length of the lead>> Figure 11 This is a diagram illustrating an implementation method for adjusting the length of the lead wire. Figure 11 In, with and Figure 4 The structures with the same designations are identical. Therefore, this explanation will focus on the lead W10 to the NMOS transistor M0 and the lead W11 to the diode SBD0. Furthermore, Figure 11 In the conductive pattern 220, diode SBD0 is mounted at a position away from NMOS transistor M0.

[0082] Lead W10 is electrically connected to the conductive pattern 230 of the output terminal U and to the source electrode S1 of the NMOS transistor M0 (the anode A1 of the diode BD0).

[0083] Lead W11 is a longer lead than lead W10 and connects conductive pattern 230 to the anode A0 of diode SBD0. In addition, lead W10 and lead W11 are the same in all aspects except length (e.g., cross-sectional area and curvature of the lead), therefore, the inductance of lead W11 becomes larger than that of lead W10.

[0084] Figure 12 It is shown using the equivalent circuit. Figure 11 The diagram shows the structure. Here, the wiring, including the conductive pattern 230 and lead W10 connecting the source electrode S1 (anode A1 of diode BD0) of the output terminal U and the NMOS transistor M0, can be equivalently represented as wiring 54. Furthermore, the lead W11 connecting the output terminal U and the anode A0 of diode SBDO can be equivalently represented as wiring 51. Additionally, the wiring pattern from the cathode K1 of diode BD0 to the positive terminal P can be equivalently represented as wiring 55, and the wiring pattern from the cathode K0 of diode SBDO to the positive terminal P can be equivalently represented as wiring 53.

[0085] In this embodiment, the inductance (Lb+Ld) of path P2 is made greater than the inductance (Li+Lj) of path P1, and the length of lead W11 is extended to satisfy, for example, equation (3). As a result, damage to diode SBD0 can be prevented even when a large current flows into the output terminal U. Furthermore, here, lead W10 is equivalent to "first lead" and lead W11 is equivalent to "second lead".

[0086] <<Adjusting the cross-sectional area of ​​the lead>> Figure 13 This is a diagram illustrating an implementation method for adjusting the cross-sectional area of ​​the lead wire. Figure 13 In, with and Figure 4 The structures with the same designations are identical. Therefore, this explanation will focus on the lead W20 to the NMOS transistor M0 and the lead W21 to the diode SBD0.

[0087] Lead W20 is a lead with a larger cross-sectional area (i.e., thicker) than lead W21, and connects the conductive pattern 230 to the output terminal U, the source electrode S1 of the NMOS transistor M0, and the anode A1 of the diode BD0. For example, lead W20 has a diameter of 400 μm, and lead W21 has a diameter of 250 μm.

[0088] Lead W21 connects conductive pattern 230 to the anode A0 of diode SBD0. Furthermore, leads W20 and W21 have the same cross-sectional area (e.g., lead length, lead curvature), therefore, the inductance of lead W21 is greater than that of lead W20.

[0089] Figure 13 The connection relationship between the output terminal U and the positive terminal P is Figure 11 The connection relationship between the output terminal U and the positive terminal P is the same, therefore, such Figure 13 The equivalent circuit of the implementation method also becomes Figure 12 If the cross-sectional area of ​​lead W21 is reduced, the inductance Lb increases, thus preventing damage to diode SBD0.

[0090] Furthermore, here, the number of leads W20 (4) is the same as the number of leads W21 (4), and leads W21 with a smaller cross-sectional area are used, but this is not a limitation. For example, even if leads W20 and W21 with equal cross-sectional areas are used, and the number of leads W21 is set to be less than the number of leads W20, the same effect as in this embodiment can be obtained. In addition, here, lead W20 is equivalent to "first lead" and lead W21 is equivalent to "second lead".

[0091] <<Adjusting the curvature of the lead wire>> Figure 14 This is a diagram illustrating an implementation method for adjusting the curvature of the lead wire. Figure 14 In, with and Figure 4 The structures with the same designations are identical. Therefore, this explanation will focus on the lead W30 to the NMOS transistor M0 and the lead W31 to the diode SBD0.

[0092] Lead W30 connects the conductive pattern 230 to the output terminal U, the source electrode S1 of the NMOS transistor M0, and the anode A1 of the diode BD0.

[0093] Lead W31 has a greater curvature than lead W30 and connects conductive pattern 230 to the anode A0 of diode SBD0. If the curvature (degree of bending) of lead W31 increases, the length of lead W31 also increases. Here, for example, the cross-sectional area of ​​leads W30 and W31 is the same; therefore, the inductance of lead W31 becomes greater than the inductance of lead W30.

[0094] Figure 14 The connection relationship between the output terminal U and the positive terminal P is Figure 11 The connection relationship between the output terminal U and the positive terminal P is the same, therefore, such Figure 14 The equivalent circuit of the implementation method also becomes Figure 12 For example, if the curvature of lead W31 is increased, the inductance Lb increases, thus preventing damage to diode SBD0. Furthermore, here, lead W30 is equivalent to "lead 1" and lead W31 is equivalent to "lead 2".

[0095] <<Wirework 53: Cases where wiring patterns are used to achieve the desired result>> Next, regarding Figure 2 The case where wiring 53 is implemented using a wiring pattern will be explained. Here, when wiring 53 is implemented using a wiring pattern, for example, by increasing the length of the wiring pattern, decreasing its thickness, or narrowing its width, the inductance Ld can be increased. Furthermore, increasing the inductance Ld by lengthening the wiring pattern is... Figure 6 The above has already been explained. Therefore, the remaining two methods will be explained here.

[0096] <<Adjust the thickness and width of the wiring pattern>> Figure 15 and Figure 16 This is a diagram illustrating an implementation method for adjusting the thickness and width of a wiring pattern. Figure 15 and Figure 16 In, there is an appendix with Figure 4 and Figure 5 The structures with the same designations are identical. Therefore, conductive patterns 270 and 280, and leads W40 to W42 will be described here.

[0097] The conductive pattern 270 is fitted with the positive terminal P on the power supply side and an NMOS transistor M0.

[0098] Conductive pattern 28 is thinner than conductive pattern 270 and has a diode SBD0 mounted on it. Furthermore, in conductive pattern 280, the width Wx of the area between the region where the diode SBD0 is mounted and the area connected by the lead W40 is narrower. Additionally, conductive patterns 270 and 280 are connected by the lead W40.

[0099] Lead W41 connects the conductive pattern 230, which is electrically connected to the output terminal U, to the source electrode S1 of the NMOS transistor M0 (the anode A1 of the diode BD0).

[0100] Lead W42 connects the source electrode S1 of NMOS transistor M0 (anode A1 of diode BD0) to the anode A0 of diode SBD0.

[0101] Here, current from the conductive pattern 230, which is electrically connected to the output terminal U, flows through the source electrode S1 (anode A1) via lead W41. Current from the source electrode S1 flows through the anode A0 via lead W42. Current from the anode A1 flows to the positive terminal P via diode BD0, the cathode K1 on the back side, and the wiring pattern C21 in the conductive pattern 270. Furthermore, current from the anode A0 flows to the positive terminal P via diode BD0, the cathode K2 on the back side, the wiring pattern C20, lead W40, and the conductive pattern 270. Therefore, Figure 15Implementation methods and Figure 4 The same implementation method can also be used Figure 8 The equivalent circuit shown is used to represent this.

[0102] In this embodiment, the conductive pattern 280 with path P20 is thinner than the conductive pattern 270, and the width Wx of path P20 is also narrower. Therefore, conceptually, the inductance of the wiring pattern C20 formed on path P20 is greater than the inductance of the wiring pattern C21 formed on path P21. Therefore, by using the wiring pattern C20 with greater inductance, it is possible to... Figure 8 The inductance Ld of wiring 53 increases. As a result, by using Figure 15 , 16 The structure shown prevents damage to the diode SBD0.

[0103] <<Other structural examples of a part of a semiconductor module>> Figure 17 This is a diagram showing the structure of the components in the upper arm of a semiconductor module. Figure 17 In the middle, with Figure 4 The structures of the same labels are identical. Therefore, the explanation here will focus on conductive patterns 290, 291, and leads W50, W51.

[0104] The conductive pattern 290 is a pattern with an output terminal U installed. The lead W50 connects the conductive pattern 290 to the source electrode S1 of the NMOS transistor M0 (the anode A1 of the diode BD0).

[0105] Conductive pattern 291 is a pattern in which the positive terminal P, NMOS transistor M0, and diode SBD0 are mounted. Lead W51 connects the source electrode S1 of NMOS transistor M0 (anode A1 of diode BD0) to the anode A0 of diode SBD0.

[0106] Figure 18 It is shown using the equivalent circuit. Figure 17 The diagram shows the structure. Here, the wiring, including the conductive pattern 290 connecting the output terminal U and the source electrode S1 (anode A1 of diode BD0) of NMOS transistor M0, and the lead W50, can be equivalently represented as wiring 50. Furthermore, the lead 51 connecting the source electrode S1 (anode A1 of diode BD0) of NMOS transistor M0 to the anode A0 of diode SBD0 can be equivalently represented as wiring 51. Also, the wiring pattern from the cathode K0 of diode SBD0 to the cathode K1 of diode BD0 can be equivalently represented as wiring 53, and the wiring pattern from the cathode K1 of diode SBD0 to the positive terminal P can be equivalently represented as wiring 52.

[0107] In this embodiment, the inductance (La+Lb+Lc+Ld) of path P2 is necessarily larger than the inductance (La+Lc) of path P1. In this embodiment, for example, the length of lead W51 is increased so that, for example, the relationship Lb+Ld > 0.18nH is satisfied. As a result, damage to diode SBD0 can be prevented even when a large current flows into the output terminal U. Furthermore, here, lead W50 corresponds to "lead 1", and leads W50 and W51 correspond to "lead 2".

[0108] Figure 19 This is a diagram showing the structure of the components in the lower arm of a semiconductor module. Figure 19 In the middle, with Figure 4 The structures of the same labels are identical. Therefore, the explanation here will focus on conductive patterns 340 and 341, and leads W60 and W61.

[0109] Conductive pattern 340 is a pattern with the negative terminal N mounted on it. Lead W60 connects conductive pattern 340 to the source electrode S2 of NMOS transistor M2 (anode A2 of diode BD2). In addition, lead W61 connects conductive pattern 340 to the anode A3 of diode SBD2.

[0110] Conductive pattern 341 is a pattern in which output terminal U, NMOS transistor M2, and diode SBD2 are mounted.

[0111] Figure 20 It is shown using the equivalent circuit. Figure 19 The diagram shows the structure. Here, the wiring pattern formed conceptually from the negative terminal N to position O in the conductive pattern 340 can be equivalently represented as wiring 60. Furthermore, position O is the location in the conductive pattern 340 where the current from the negative terminal N is conceptually shunt to the NMOS transistor M2 and the diode SBD2, corresponding to node x2.

[0112] The wiring pattern, including the wiring pattern from position O to the source electrode S2 of NMOS transistor M2 (the anode A2 of diode BD2) and lead W60, can be equivalently represented as wiring 64. The wiring pattern, including the wiring pattern from position O to the anode A3 of diode SBD2 and lead W61, can be equivalently represented as wiring 61. Furthermore, the wiring pattern from the cathode K3 of diode SBD2 to the cathode K2 of diode BD2 can be equivalently represented as wiring 63, and the wiring pattern from the cathode K2 of diode BD2 to the output terminal U can be equivalently represented as wiring 62.

[0113] In this embodiment, for example, the length of lead W61 is increased so that the inductance of path P4 (Le+Lf+Lg+Lh) is greater than the inductance of path P3 (Le+Lm+Lg). As a result, damage to diode SBD2 can be prevented even when a large current flows into the negative terminal N. Furthermore, in this embodiment, (Lf+Lh)-Lm > 0.18nH is preferred, and (Lf+Lh)-Lm > 0.36nH is more preferred. Thus, by further increasing (Lf+Lh), the current flowing through diode SBD2 can be further reduced, for example, even if there are deviations in the inductance of lead W60 or the characteristics of the component.

[0114] ===Summary=== The electronic circuit 10 and semiconductor module 80 of this embodiment have been described above. Figure 2 As illustrated, the inductance of path P2 in electronic circuit 10 is greater than that of path P1. Therefore, the current from the output terminal U flows through diode BD0 in path P1 in addition to diode SBD0 in path P2. Thus, in electronic circuit 10, damage to diode SBD0, which acts as a return diode, can be prevented.

[0115] Furthermore, a general bipolar transistor can be used as the switching element. Even if a PN diode with a PN junction and a Schottky diode with a Schottky junction are connected to the bipolar transistor as return diodes, the same effect as in this embodiment can be obtained. In this embodiment, an NMOS transistor M0 is used as the switching element. Therefore, the parasitic diode (body diode) of the NMOS transistor M0 can be used as a return diode without providing a separate PN diode.

[0116] Furthermore, the NMOS transistor M0 and the diode SBD0 with a Schottky junction are components that utilize wide-bandgap semiconductors. Therefore, in this embodiment, the breakdown voltage of the electronic circuit 10 can be improved, and the losses when driving the load can be reduced.

[0117] In addition, a diode SBD0 with a Schottky junction is connected in reverse parallel to the NMOS transistor M0 so that it can act as a return diode when the NMOS transistor M0 is turned off.

[0118] Furthermore, the semiconductor module 80 is a device that includes electronic circuitry 10, in which the inductance of path P2 via SBD0 is greater than the inductance of path P1 via NMOS transistor M0. Therefore, when using such a semiconductor module 80, the diode SBD0 with a Schottky junction can be protected from large currents.

[0119] In addition, such as Figure 4As shown, in semiconductor module 80, lead W0 from conductive pattern 230 is connected to diode BD0 having a PN junction, and lead W1 from diode BD0 is connected to diode SBD0 having a Schottky junction. Therefore, the inductance from conductive pattern 230 to diode SBD0 can be made larger than the inductance from conductive pattern 230 to diode BD0.

[0120] In addition, such as Figure 7 As shown, a lead W11 longer than lead W10 can be used to connect conductive pattern 230 to diode SBD0. In this case, the inductance from conductive pattern 230 to diode SBD0 can also be larger than the inductance from conductive pattern 230 to diode SBD0.

[0121] In addition, such as Figure 8 As shown, a lead W21 with a smaller cross-sectional area than lead W20 can be used to connect conductive pattern 230 to diode SBD0. In this case, the inductance from conductive pattern 230 to diode SBD0 can also be larger than the inductance from conductive pattern 230 to diode SBD0.

[0122] In addition, such as Figure 9 As shown, a lead W31 with a curvature greater than that of lead W30 can be used to connect conductive pattern 230 to diode SBD0. In this case, the inductance from conductive pattern 230 to diode SBD0 can also be greater than the inductance from conductive pattern 230 to diode SBD0.

[0123] Furthermore, in the semiconductor module 80, along the long side direction (predetermined direction) of the semiconductor module 80, a U-terminal (or a conductive pattern 230 connected to the U-terminal), an NMOS transistor M0, and a diode SBD0 are arranged sequentially. That is, an NMOS transistor M0 is provided between the U-terminal and the diode SBD0. If the U-terminal, diode SBD0, and NMOS transistor M0 are arranged sequentially along the long side direction, then generally, the inductance of the wiring between the output terminal U and the diode SBD0 is less than the inductance of the wiring between the U-terminal and the diode BD0. However, by arranging the components in the order of this embodiment, the inductance of the wiring between the U-terminal and the diode SBD0 can be made larger than the inductance of the wiring between the U-terminal and the diode BD0, which is a parasitic element.

[0124] Furthermore, in the semiconductor module 80, among the leads connecting the U terminal and the diode SBD0 (e.g., leads W0 and W1), lead W0 is used as the lead connecting the U terminal and the diode BD0. In this case, the inductance of the lead connecting the U terminal and the diode SBD0 must be greater than the inductance of the lead connecting the U terminal and the diode BD0. Additionally, in the semiconductor module 80, leads W0 and W1 are equivalent to "second lead," and lead W0 is equivalent to "first lead."

[0125] Furthermore, for example, to increase the inductance of path P2, the inductance of the wiring pattern can be increased instead of the inductance of the lead. In this case, diode SBD0 can also be protected.

[0126] In addition, such as Figure 6 As shown, when path P2 includes a wiring pattern C11 that is longer than wiring pattern C10, the inductance of path P2 can be increased. In addition, wiring pattern C10 is equivalent to "first wiring pattern" and wiring pattern C11 is equivalent to "second wiring pattern".

[0127] In addition, for example, such as Figure 11 As shown, the thickness of the conceptually formed wiring pattern C20 can be thinner than the thickness of the wiring pattern C21. In this case, the inductance of path P2 can also be increased.

[0128] In addition, for example, such as Figure 10 As shown, even if the width Wx of the wiring pattern C20 is narrowed, the inductance of the path P2 can be increased.

[0129] In addition, such as Figure 6 As shown, wiring pattern C10 is determined based on the distance from the positive terminal P in conductive pattern 220 to the diode BD0, and wiring pattern C11 is determined based on the distance from the positive terminal P in conductive pattern 220 to the diode BD0.

[0130] Furthermore, in the semiconductor module 80, a conductive pattern 220 with a positive P terminal is provided between the conductive pattern 210 on which the control terminal IN1 is mounted and the conductive pattern 230 electrically connected to the output terminal U. Additionally, conductive pattern 220 corresponds to the "first conductive pattern", conductive pattern 230 corresponds to the "second conductive pattern", and conductive pattern 210 corresponds to the "third conductive pattern".

[0131] The above embodiments are provided to facilitate understanding of the present invention, and are not intended to limit or restrict its interpretation. Furthermore, the present invention can be modified or improved without departing from its spirit, and the present invention naturally includes its equivalents. Label Explanation

[0132] 10 Electronic Circuits 50-55, 60-65 wiring 80 Semiconductor Modules 100 substrates 101, 250, 251, 252 Bonding materials 110 and 111 laminated substrates 200 Insulation Board 201 heat sink Conductive patterns: 210, 220, 230, 270, 280, 290, 291, 310, 320, 330, 340, 341 M0~M3 NMOS transistors BD0~BD3, SBD0~SBD3 diodes G1 and G2 gate electrodes S1, S2 source electrodes D1, D2 drain electrodes Cathode electrodes K0~K3 A0~A3 Anode Electrode Inductors La~Lj, Lm, Ln C10 and C11 wiring patterns Paths P1-P4, P20, P21 Lead wires: W0~W3, W10, W11, W20, W21, W30, W31, W40~W42, W50, W51, W60, W61 O position P positive extreme U output terminal N negative extreme IN1 and IN2 are control terminals.

Claims

1. A semiconductor module, characterized in that, include: The first diode has a PN junction with a forward voltage that becomes the first voltage; A second diode having a Schottky junction with a second voltage that is a smaller forward voltage than the first voltage; A first wiring component connects the first terminal and the second terminal via the first diode; as well as A second wiring component, which connects the first terminal and the second terminal via the second diode, and has an inductance greater than that of the first wiring component. The first wiring component includes a first lead disposed between the first terminal and the first diode. The second wiring component includes a second lead disposed between the first terminal and the second diode, and having an inductance greater than that of the first lead. The cross-sectional area of ​​the second lead is smaller than that of the first lead.

2. A semiconductor module, characterized in that, include: The first diode has a PN junction with a forward voltage that becomes the first voltage; A second diode having a Schottky junction with a second voltage that is a smaller forward voltage than the first voltage; A first wiring component connects the first terminal and the second terminal via the first diode; as well as A second wiring component, which connects the first terminal and the second terminal via the second diode, and has an inductance greater than that of the first wiring component. The first wiring component includes a first lead disposed between the first terminal and the first diode. The second wiring component includes a second lead disposed between the first terminal and the second diode, and having an inductance greater than that of the first lead. The curvature of the second lead is greater than that of the first lead.

3. A semiconductor module, characterized in that, include: The first diode has a PN junction with a forward voltage that becomes the first voltage; A second diode having a Schottky junction with a second voltage that is a smaller forward voltage than the first voltage; A first wiring component connects the first terminal and the second terminal via the first diode; as well as A second wiring component, which connects the first terminal and the second terminal via the second diode, and has an inductance greater than that of the first wiring component. The first wiring component includes a first lead disposed between the first terminal and the first diode. The second wiring component includes a second lead disposed between the first terminal and the second diode, and having an inductance greater than that of the first lead. The second lead is longer than the first lead. The first diode is disposed between the first terminal and the second diode.

4. The semiconductor module as described in claim 1 or 2, characterized in that, The second lead is longer than the first lead.

5. The semiconductor module as described in claim 3, characterized in that, The second lead includes the first lead.

6. The semiconductor module as described in any one of claims 1 to 5, characterized in that, The first wiring component includes a first wiring pattern disposed between the second terminal and the first diode. The second wiring component includes a second wiring pattern disposed between the second terminal and the second diode, and having an inductance greater than that of the first wiring pattern.

7. The semiconductor module as described in claim 6, characterized in that, The second wiring pattern is longer than the first wiring pattern.

8. The semiconductor module as described in claim 6 or 7, characterized in that, The second wiring pattern is thinner than the first wiring pattern.

9. The semiconductor module as described in any one of claims 6 to 8, characterized in that, The width of the second wiring pattern is narrower than the width of the first wiring pattern.

10. The semiconductor module as claimed in claim 7, characterized in that, The first diode and the second diode are mounted on a surface and include a first conductive pattern on which the second terminal is mounted. The first wiring pattern is determined based on the distance from the position where the first diode is mounted on the first conductive pattern to the second terminal. The second wiring pattern is determined based on the distance from the position where the second diode is mounted on the first conductive pattern to the second terminal.

11. The semiconductor module as claimed in claim 10, characterized in that, include: The second conductive pattern connected to the first terminal; and A third conductive pattern is connected to the control electrode of the switching element, which includes the first diode. The first conductive pattern is disposed between the second conductive pattern and the third conductive pattern.

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