Time domain synchronization in system on chip

Abstract

The present disclosure relates to time domain synchronization in a system on chip. A method for synchronizing a first time domain with a second time domain of a system on chip, the method comprising: detecting at least one periodic trigger event generated in the first time domain, the second time domain or a third time domain; at an instant of the at least one trigger event, acquiring a current timestamp value representing an instantaneous state of the time domain other than the triggering time domain; in the third time domain, comparing differential durations between respectively consecutively acquired current timestamp values; and synchronizing the second time domain with the first time domain based on the comparison.

Description

[0001] Cross-reference of related applications

[0002] This application claims the benefit of French Application No. 2100697, filed on January 26, 2021, which is incorporated herein by reference. Technical Field

[0003] The embodiments and implementations relate to a system-on-a-chip, specifically to time-domain synchronization within a system-on-a-chip. Background Technology

[0004] In electronic devices that include multiple microprocessors or microcontrollers, they must share a common time perspective.

[0005] A system-on-a-chip is typically defined as a system embedded in the same integrated circuit, which includes a microprocessor or microcontroller and other devices, such as at least one communication interface.

[0006] Shared time can be global time, such as absolute time derived from a real date, or it can be local time, called network time, which does not necessarily have an absolute reference but is the same for all elements of the network.

[0007] The exchanged timing information must be precise, for example, at the microsecond level, and synchronized so that distributed processes can start simultaneously, such as multi-axis motion control of a robot.

[0008] The sharing of time information is accomplished through communication interfaces, such as high-speed PCIe interfaces for interconnecting peripheral components or wired network interfaces commonly known as Ethernet. PCIe and Ethernet interfaces are well known to those skilled in the art.

[0009] Communication interfaces are typically used to operate under specific communication protocols, and these protocols can provide specific time information sharing.

[0010] Therefore, each communication interface is typically suited to a specific time-sharing protocol, and this is called the "time domain," used to describe the different time perspectives obtained by different communication interfaces of the system on chip.

[0011] Specifically, the PCIe interface provides shared time information according to a process called Precision Time Measurement (usually "PTM"), in which "master" devices called root complexes (usually "RC") share time information on a common clock, on which "slave" devices called endpoints (usually "EP") synchronize; and the Ethernet interface provides shared time information according to a process called Precision Time Protocol (usually "PTP") to share a common clock between endpoints.

[0012] Shared time information can be encoded differently depending on the communication protocol used. For example, the PTM protocol can provide a clock encoded by 64-bit binary words incrementing in 250MHz, while the PTP protocol can provide a digital value representing nanoseconds in 32 bits, as well as a digital value representing seconds in 32 bits.

[0013] Traditional techniques for sharing time information and synchronizing on-chip systems face difficulties because the time domains used may be constrained by different protocols that are not directly compatible with each other, such as the PTM protocol for PCIe interfaces and the PTP protocol for Ethernet interfaces.

[0014] Furthermore, it is desirable not to introduce changes to the communication interfaces, as they typically need to be compatible with third-party devices defined by standards or consensus.

[0015] Therefore, it is necessary to be able to synchronize different time domains on the same on-chip system. Summary of the Invention

[0016] According to one aspect, a method is provided for synchronizing a first time domain of a first device with a second time domain of a second device. The method includes detecting at least one periodic trigger event generated in at least one trigger time domain selected from the first time domain, the second time domain, and a third time domain of a third device. The method includes, at the instant of detecting the at least one trigger event, acquiring a current timestamp value representing the instantaneous state of the first, second, and third time domains, excluding the at least one trigger time domain. The method includes, in the third time domain, comparing differential durations between the respective consecutively acquired current timestamp values. The method includes synchronizing the second time domain with the first time domain based on the comparison.

[0017] In other words, the approach of this aspect uses a third time domain as an intermediary in order to measure the possible shift in the passage of time between the perspectives of the first and second time domains, which are potentially not directly comparable to each other.

[0018] In practice, comparing the elapsed time between two timestamp values ​​in the time domain with the elapsed duration in a third time domain between two triggering events, or with the elapsed duration between two timestamp values ​​in at least one other time domain, allows for information about the difference in the rate of elapsed time between two considered domains, i.e., between the time domain providing the timestamp values ​​and the time domain providing the triggering events, or between two time domains that provide timestamp values ​​at the moment defined by the triggering events.

[0019] Furthermore, the approach in this respect does not introduce any functional or structural modifications to the elements of the first or second time domain, but rather advantageously uses the timestamp information that is usually provided to synchronize these time domains from a third-party time domain.

[0020] For example, the current timestamp value can be obtained at the same time when the same periodic triggering event is detected, or at different times when various periodic triggering events are detected.

[0021] According to one implementation, the first time domain is defined by the Precision Time Measurement (PTM) protocol of the high-speed PCIe interface for peripheral component interconnection, the second time domain is defined by the Precision Time Protocol (PTP) of the Ethernet network interface, and the third time domain is clocked by a free-running local clock suitable for software operation.

[0022] In fact, given that PCIe and Ethernet interfaces are commonly used and therefore very widespread, there is a particular problem with traditional on-chip systems that use time domains defined by PTM and PTP.

[0023] Therefore, this implementation allows for the solution of this specific and traditionally very common problem.

[0024] According to one implementation, at least one triggering time domain includes a first time domain, and at least one triggering event generated in the first time domain occurs when a condition is verified on a transition of at least one bit of the current timestamp value representing the instantaneous state of the first time domain, and each bit of the current timestamp value is transmitted on a dedicated channel of the timestamp bus.

[0025] On the one hand, trigger events can be tuned through combinations of bits on the timestamp bus, allowing the construction of "complex" trigger events with periodicity that is unavailable in signals transmitted through the timestamp bus. For example, this could allow the construction of optimized cycles for specific processes in a third time domain.

[0026] On the other hand, it should be noted that the transmission of each bit of the current timestamp value on the dedicated channel of the timestamp bus is specifically handled by the PCIe interface using PTM.

[0027] According to one implementation, at least one trigger time domain does not include a first time domain, each bit representing the current timestamp value of the instantaneous state of the first time domain is transmitted on a dedicated channel of the timestamp bus, and obtaining the current value representing the instantaneous state of the first time domain includes loading a latch with the bits present on each channel of the timestamp bus, controlling the loading of the latch at the instant at which at least one periodic trigger event is detected.

[0028] Note again here that the transmission of each bit of the current timestamp value on the dedicated channel of the timestamp bus is specifically used by the PCIe interface using PTM, and this implementation allows for the simple retrieval of the current timestamp value in the first time domain without modifying the structure or operation of the first time domain.

[0029] According to one embodiment, at least one triggering time domain includes a second time domain, and when a periodic signal is generated in the second time domain, at least one triggering event generated in the second time domain is detected.

[0030] Therefore, when at least one time domain includes both a first time domain and a second time domain, the method includes acquiring a first current timestamp value representing the instantaneous state of a third time domain and acquiring a second current timestamp value at the instant of detecting a first triggering event from the first time domain and at the instant of detecting a second triggering event from the second time domain, respectively. A comparison is made between the duration of the difference between the first current timestamp values ​​and the duration of the difference between the second current timestamp values.

[0031] Furthermore, when at least one second time domain includes only the second time domain, the method includes, at the instant of detecting a second triggering event from the second time domain, acquiring a current timestamp value representing the instantaneous state of the first time domain and acquiring a current timestamp value representing the instantaneous state of the third time domain. A comparison is then made between the differential durations between the respective current timestamp values.

[0032] According to another aspect, for example, a system for integration into an on-chip system is provided, comprising: a first device including a first counter configured to have a current timestamp value representing an instantaneous state of a first time domain; a second device including a second counter configured to have a current timestamp value representing an instantaneous state of a second time domain; and a third device including a local clock generator configured to clock a third time domain. The third device includes a synchronization module configured to detect at least one periodic trigger event generated in at least one trigger time domain selected from the first, second, and third time domains. The synchronization module is configured to, at the instant at which the at least one trigger event is detected, acquire current timestamp values ​​representing the first, second, and third time domains, excluding the at least one trigger time domain. The synchronization module is configured to compare the differential durations between the respective consecutively acquired current timestamp values. The synchronization module is configured to generate control suitable for synchronizing the second time domain with the first time domain based on the comparison.

[0033] The synchronization module can be configured to obtain the current timestamp value at the same detection moment for the same triggered event, or at different detection moments for different triggered events.

[0034] According to one embodiment, the first device includes a high-speed PCIe interface for peripheral component interconnection configured to define a first time domain via the Precision Time Measurement (PTM) protocol, the second device includes an Ethernet network interface configured to define a second time domain via the Precision Time Protocol (PTP), and the third device includes a local clock generator adapted to clock control of software operations.

[0035] According to one embodiment, at least one trigger time domain includes a first time domain, a first counter is configured to transmit each bit of the current timestamp value on a dedicated channel of the timestamp bus, and a synchronization module is configured to detect at least one trigger event generated in the first time domain when a condition is verified on the transition of at least one bit on each channel of the timestamp bus.

[0036] According to one embodiment, at least one trigger time domain does not include a first time domain, a first counter is configured to transmit each bit of the current timestamp value on a dedicated channel of the timestamp bus, and a synchronization module includes a latch on the timestamp bus and is configured to acquire a current value representing the instantaneous state of the first time domain by controlling the loading of the latch using bits present on each channel of the timestamp bus at the instant of at least one trigger event.

[0037] According to one embodiment, at least one triggering time domain includes a second time domain (optionally in addition to the first time domain), and the synchronization module is configured to detect at least one triggering event generated in the second time domain when a periodic signal is generated in the second time domain. Attached Figure Description

[0038] Other advantages and features of the invention will become apparent upon examination of the detailed description of the embodiments and examples, as well as the accompanying drawings, which are in no way limiting, wherein:

[0039] Figure 1A This demonstrates a first alternative to the SoC system;

[0040] Figure 1B This demonstrates a second alternative to the SoC system;

[0041] Figure 1C This demonstrates a third alternative to the SoC system;

[0042] Figure 1D This demonstrates a fourth alternative to the SoC system;

[0043] Figure 2 An example of an on-chip system is shown;

[0044] Figure 3 It is a graph showing the elapsed time in the first time domain compared to the elapsed time in the third time domain; and

[0045] Figure 4 An example of an on-chip system is shown. Detailed Implementation

[0046] Figure 1A , Figure 1B , Figure 1C and Figure 1DFour possible alternatives to a SoC system are illustrated, the SoC system including a first device DIS1, the first device DIS1 including a first counter TMR1 configured to have a current timestamp value representing the instantaneous state of a first time domain DMN1; a second device DIS2, the second device DIS2 including a second counter TMR2 configured to have a current timestamp value representing the instantaneous state of a second time domain DMN2; a third device DIS3, the third device DIS3 including a third counter TMR3 configured to have a current timestamp value representing the instantaneous state of a third time domain DMN3; and a synchronization module MSYNC configured to synchronize SYNC of the second time domain DMN2 on the first time domain DMN1.

[0047] The system SoC can be integrated in the same integrated circuit, which is usually referred to as a "system-on-chip", or integrated in different systems-on-chip interconnected by wire links, each system including at least one of a first device DIS1, a second device DIS2 and a third device DIS3.

[0048] Below, we will consider a non-limiting example of three devices DIS1, DIS2, DIS3 and their respective time-domain DMN1, DMN2, DMN3 belonging to the same system-on-chip (SoC).

[0049] The current timestamp value is a digital representation of an instantaneous time, that is, a "date" in a broad sense. In a System-on-Chip (SoC), the different timestamp "dates" used have a range of many years (hundreds of years) (i.e., the maximum value) and a precision on the order of nanoseconds or even smaller (i.e., the smallest variation).

[0050] Each time domain DMN1, DMN2, and DMN3 is clocked by its respective local clock signal generators clk1, clk2, and clk3. These local clock signal generators can be generated in the form of local oscillators, such as crystal oscillators (e.g., quartz) typically with a phase-locked loop, and optionally temperature-compensated; other types of oscillators, less common in clock generation, include variable frequency oscillators, voltage-controlled oscillators, phase-locked loops, or analog or digital frequency synthesizers.

[0051] According to specific and non-limiting examples, the third device DIS3 may include or constitute a microprocessor or microcontroller, that is, more broadly, a computing unit suitable for implementing software operations, and the local clock generator clk3 of the third device DIS3 is specifically designed to clock the software operations.

[0052] The synchronization module MSYNC can be implemented either through hardware belonging to the third device DIS3 or through software implemented in the third device DIS3.

[0053] exist Figure 1A , Figure 1B , Figure 1C and Figure 1D In the representation, the local clock generators clk1, clk2, and clk3 integrate the corresponding devices DIS1, DIS2, and DIS3, but can come from external sources that belong to the corresponding time domains DMN1, DMN2, and DMN3.

[0054] Based on a specific and non-restrictive example (see below for details) Figures 2 to 4 The first device DIS1 may include or constitute a high-speed “PCIe” interface for peripheral component interconnection, the specification of which is managed and developed by the PCI-SIG (“PCI Interest Group”) alliance and is well known to those skilled in the art.

[0055] Based on a specific and non-restrictive example (below about...) Figures 2 to 4 (As described below), the second device DIS2 may include or constitute a wired physical network interface “Ethernet”, such as that defined by the standard IEEE 802.3 and its variants, which are well known to those skilled in the art.

[0056] However, the first device DIS1 and the second device DIS2 may include or constitute other technologies (typically communication interfaces) suitable for exchanging time information to synchronize different time domains, such as CAN (for “Controller Area Network”) interfaces and FDCAN (for “Flexible Data CAN”) or TTCAN (for “Time Triggered CAN”) variants, and may also include 4G, 5G, LTE communication with microsecond-level synchronization possibilities.

[0057] Figure 1A A first alternative configuration of the synchronization module MSYNC integrated in the third device DIS3 is shown for synchronizing SYNC in the second time domain DMN2 on the first time domain DMN1 of the system-on-chip SoC.

[0058] In this first alternative, the synchronization module MSYNC is configured to detect trigger events TRG that are periodically generated in the first time domain DMN1. In this respect, the first time domain DMN1 is referred to as the "trigger time domain".

[0059] The duration of the period of the triggering event considered in the first time domain DMN1 can be known by constructing the synchronization module MSYNC.

[0060] The synchronization module MSYNC is configured to acquire the current timestamp value TS2, representing the instantaneous state of the second time domain DMN2, at consecutive moments of detection of the periodically triggered event TRG.

[0061] The synchronization module MSYNC is configured to compare the differential duration between consecutively triggered events TRG with the differential duration between consecutively acquired current timestamp values ​​TS2.

[0062] "Differential duration" refers to the difference between two considered measurements, that is, the difference between timestamp values, or the time difference between triggering events.

[0063] The differential duration between consecutive triggering events TRG is obtained, for example, by utilizing prior knowledge of their periodicity in the first time domain DMN1 and / or by measuring the differential duration between the current timestamp value TS31 of the third time domain DMN3 acquired at the moment of detecting a triggering event TRG originating from the first time domain DMN1.

[0064] In practice, the synchronization module MSYNC acquires information about the passage of time in the first time domain DMN1 by detecting the instantaneous triggering event TRG. Therefore, if the period between two detections of the triggering event TRG increases, the synchronization module MSYNC can, for example, detect a slowdown in the passage of time in the first time domain DMN1.

[0065] On the other hand, the synchronization module MSYNC has already obtained information about the elapsed time in the second time domain DMN2 through the current timestamp value TS2. The difference between the timestamp values ​​TS2 actually provides the elapsed duration between the corresponding triggering events, which is taken into account in the second time domain DMN2.

[0066] Finally, the synchronization module MSYNC is configured to generate a control SYNC based on comparison, suitable for synchronizing the second time domain DMN2 with the first time domain DMN1.

[0067] Specifically, the SYNC control is adapted to adjust the frequency of the local clock signal generated by the local clock generator clk2 of the second time domain DMN2, and optionally adjust the phase.

[0068] In fact, from the information about the passage of time in the first time domain DMN1 and the information about the passage of time in the second time domain DMN2, the synchronization module MSYNC can calculate the correction to be applied to the second time domain DMN2 so that it corresponds to the first time domain DMN1.

[0069] For example, if time has slowed down in the first time domain DMN1, controlling SYNC may include reducing the frequency of the clock generated by the local clock generator clk2 in the second time domain DMN2.

[0070] According to another example of synchronization, if the duration between two trigger events TRG, obtained from the difference between timestamp values ​​TS2 and therefore considered in the second time domain DMN2, differs from the duration between corresponding trigger events TRG considered in the first time domain DMN1 or the third time domain DMN3 using periodic prior knowledge of the trigger events TRG, the SYNC control can adjust the frequency of the clock clk2 of the second time domain DMN2 to make the time measurement in the second time domain DMN2 equal to the time measurement in the first time domain DMN1.

[0071] In practice, the synchronization module MSYNC can identify the linear relationship (e.g., "y = ax + b") between the time of the first time domain DMN1 ("y") and the time of the second time domain DMN2 ("x"). Controlling SYNC allows the application of proportional correction ("a") and offset ("b") parameters.

[0072] Figure 1B A second alternative configuration of the synchronization module MSYNC integrated in the third device DIS3 is shown for synchronizing SYNC in the second time domain DMN2 on the first time domain DMN1 of the system-on-chip SoC.

[0073] In this second alternative, the synchronization module MSYNC is configured to detect trigger events TRG that are periodically generated in the second time domain DMN2. In this respect, the second time domain DMN2 is referred to as the "trigger time domain".

[0074] The synchronization module MSYNC is configured to acquire the current timestamp value TS1, representing the instantaneous state of the first time domain DMN1, at consecutive moments of detection of the periodically triggered event TRG.

[0075] The synchronization module MSYNC is configured to compare the differential duration between consecutively triggered events TRG with the differential duration between consecutively acquired current timestamp values ​​TS1.

[0076] The differential duration between consecutive triggering events TRG is obtained, for example, by utilizing prior knowledge of their periodicity in the second time domain DMN2 and / or by measuring the differential duration between the current timestamp value TS32 of the third time domain DMN3 obtained at the moment when the triggering event TRG is detected from the second time domain DMN2.

[0077] Finally, the synchronization module MSYNC is configured to generate a control SYNC based on comparison, suitable for synchronizing the second time domain DMN2 with the first time domain DMN1.

[0078] Here, the synchronization module MSYNC again obtains information representing the first time domain DMN1 and the second time domain DMN2. The differential duration calculated based on this information will allow identification of the relationship between the elapsed time in the second time domain DMN2 and the elapsed time in the first time domain DMN1, so as to set the control SYNC for synchronizing the second time domain DMN2.

[0079] Figure 1C A third alternative configuration of the synchronization module MSYNC integrated in the third device DIS3 is shown for synchronizing SYNC in the second time domain DMN2 on the first time domain DMN1 of the system-on-chip SoC.

[0080] In this third alternative, the synchronization module MSYNC is configured to detect trigger events TRG that are periodically generated in the third time domain DMN3. In this respect, the third time domain DMN3 is referred to as the "trigger time domain".

[0081] To clarify the terminology, it is assumed that the synchronization module MSYNC is part of the third device DIS3 of the third time domain DMN3, and that the synchronization module MSYNC is configured to generate periodic trigger events TRG. However, strictly speaking, the trigger events TRG originate from the time management mechanism TMR3 (typically a "timer") of the local clock clk3, and the trigger events TRG themselves are not directly generated by the synchronization module MSYNC. Therefore, it is assumed that the trigger events TRG are generated by the third device DIS3, and that the synchronization module MSYNC of the third device DIS3 is configured to detect the trigger events TRG.

[0082] The synchronization module MSYNC is configured to acquire the current timestamp value TS1 representing the instantaneous state of the first time domain DMN1 at consecutive moments of detection of the periodically triggered event TRG, and to acquire the current timestamp value TS2 representing the instantaneous state of the second time domain DMN2 at consecutive moments of detection of the periodically triggered event TRG.

[0083] It should be noted that TS1 and TS2 can be acquired at the same moment when the same periodic trigger event TRG is detected, or at different moments when various periodic trigger events are detected. Specifically, the trigger events can be assigned to each of the first device DIS1 and the second device DIS2 respectively.

[0084] The synchronization module MSYNC is configured to compare the differential duration between the current timestamp values ​​TS1 of the first time domain DMN1 acquired consecutively with the differential duration between the current timestamp values ​​TS2 of the second time domain DMN2 acquired consecutively.

[0085] This comparison can further consider the differential duration between the corresponding consecutively triggered events (TRGs), specifically when using several different trigger events.

[0086] Finally, the synchronization module MSYNC is configured to generate a control SYNC based on comparison, suitable for synchronizing the second time domain DMN2 with the first time domain DMN1.

[0087] Here, the synchronization module MSYNC again obtains information representing the first time domain DMN1 and the second time domain DMN2 (i.e., the current timestamp values ​​TS1 and ST2). The differential duration calculated based on this information will allow identification of the relationship between the elapsed time in the second time domain DMN2 and the elapsed time in the first time domain DMN1, so as to set the control SYNC for synchronizing the second time domain DMN2.

[0088] Figure 1D A fourth alternative configuration of the synchronization module MSYNC integrated in the third device DIS3 is shown for synchronizing SYNC in the second time domain DMN2 on the first time domain DMN1 of the system-on-chip SoC.

[0089] In this fourth alternative, the synchronization module MSYNC is configured to detect a first trigger event TRG10 periodically generated in the first time domain DMN1 and a second trigger event TRG20 periodically generated in the second time domain DMN2. In this respect, the first time domain DMN1 and the second time domain DMN2 are referred to as the "trigger time domain".

[0090] The synchronization module MSYNC is configured to acquire the first current timestamp value TS31 representing the instantaneous state of the third time domain DMN3 at consecutive instants of detecting the first periodic trigger event TRG10.

[0091] Similarly, the synchronization module MSYNC is configured to acquire a second current timestamp value TS32 representing the instantaneous state of the third time domain DMN3 at consecutive instants of detecting the second periodic trigger event TRG20.

[0092] The synchronization module MSYNC is configured to compare the differential duration between the first consecutively acquired current timestamp value TS31 with the differential duration between the second consecutively acquired current timestamp value TS32.

[0093] Finally, the synchronization module MSYNC is configured to generate a control SYNC based on the comparison, suitable for synchronizing the second time domain DMN2 with the first time domain DMN1.

[0094] Here, the synchronization module MSYNC again obtains information representing the first time domain DMN1 and the second time domain DMN2 from the perspective of the third time domain DMN3. The differential duration calculated based on this information will allow identification of the relationship between the elapsed time in the second time domain DMN2 and the elapsed time in the first time domain DMN1, so as to set the control SYNC for synchronizing the second time domain DMN2.

[0095] Figure 2 A specific exemplary embodiment of a System-on-Chip (SoC) is shown, wherein the first device DIS1 is a high-speed peripheral component interconnect “PCIe” interface type, and wherein the second device DIS2 is a wired network interface type “Ethernet”.

[0096] The third device, DIS3, is a computing unit of the "CPU" type, which is a microprocessor or microcontroller central processing unit, including a synchronization module MSYNC generated in hardware or software form. The third time domain is the software application time domain APP (DMN3).

[0097] The PCIe interface (DIS1) is configured to share time information related to the first time domain DMN1 via the Precision Time Measurement (PTM) protocol.

[0098] In this context, for example, the local clock pipe_clk (clk1) can have a frequency of 250 MHz (megahertz), or a period of 4 ns (nanoseconds), and the first counter PTM_CNT (TMR1) provides a 64-bit binary word that is incremented by the timing of the 250 MHz local clock pipe_clk. Therefore, the digital value of the first counter PTM_CNT (TMR1) corresponds to a time value in units of 4 ns.

[0099] In the PTM protocol, time information is shared by transmitting each bit of the 64 bits of the current timestamp value PNT_CNT(TMR1) on the corresponding dedicated channel of the timestamp bus PTM_BUS_64. Therefore, the bus PTM_BUS_64 bits are constantly updating timestamp values.

[0100] In addition, the first counter PTM_CNT(TMR1) is capable of receiving and transmitting synchronization update control updt between various devices using the PTM protocol.

[0101] The Ethernet interface ETH(DIS2) is configured to share time information related to the second time domain DMN2 via the Precision Time Protocol (PTP).

[0102] In this context, the local clock ptp_clk (clk2) may, for example, have frequencies between 125MHz and 200MHz, and the second counter PTP_CNT (TMR2) may include two 32-bit binary words, one encoding the timestamp value (32 bits in seconds) in seconds and the other encoding the timestamp value (32 bits in nanoseconds).

[0103] In the PTP protocol, time information sharing can be accomplished through the registers of the Ethernet interface ETH (DIS2). The registers store the timestamp value TS2, which is read by the synchronization module MSYNC. This signal, usually referred to as pulses per second (PPS) but not necessarily limited to one pulse per second, can be configured to trigger the synchronization module MSYNC to read from the registers of the Ethernet interface ETH (DIS2) at the required time.

[0104] Therefore, in the example where the triggering time domain includes the first time domain PTM (DMN1), that is, according to the above regarding... Figure 1A or Figure 1D The described alternative involves generating at least one periodic trigger event TRG1, TRG2 by a first counter PTM_CNT(TMR1).

[0105] By taking advantage of the existing structure of the PTM_BUS_64-bit bus in the PCIe interface, the periodic trigger events TRG1 and TRG2 are defined by the transition (i.e., rising edge or falling edge) of at least one signal on the channel of the PTM_BUS_64-bit bus.

[0106] In fact, through the mechanism of the binary word used to increment the first counter PTM_CNT(TMR1), the least significant bit of the 64-bit bus PTM_BUS_ constitutes a periodic signal with a period of 4ns. Specifically, the weight 17 bits (bit 17) constitute a periodic signal with a period of approximately 1ms, and the weight 20 bits (bit 20) constitute a periodic signal with a period of approximately 8ms.

[0107] Furthermore, in this example, two separate trigger events TRG1 and TRG2 are used. The first trigger event TRG1 occurs during the rising edge of bit 17, and the second trigger event TRG2 occurs during the rising edge of bit 20.

[0108] Furthermore, in an example not shown, each trigger event can be constructed from a logical condition on the transition of several bits of the current timestamp value distributed across the PTM_BUS_64-bit bus. This allows for the construction of “complex” trigger events with periodicity, which is unavailable in signals transmitted through the PTM_BUS_64-bit timestamp bus. For example, a period close to 1.5 ms cannot be directly obtained on the PTM_BUS_64-bit bus, but it can be roughly constructed by checking the “AND” condition on the rising edges of bits 17 and 16.

[0109] In the example shown, two trigger events TRG1 and TRG2 are detected by the synchronization module MSYNC, but only the second trigger event TRG2 (bit 20) controls the acquisition of the current timestamp value (TS2) of PPS representing the instantaneous state of the second PTP time domain (DMN2).

[0110] In this regard, please refer to Figure 3 .

[0111] Figure 3 This is a graph showing the time elapsed in the first time domain DMN1 on the y-axis PCIE_EP_t, compared to the time elapsed in the third time domain APP (DMN3) on the x-axis TMR3_t.

[0112] In the first time domain DMN1, the platform time elapsed is displayed on the external clock of the "root association" RC type PCIe interface and the local clock pipe_clk(clk1) of the "endpoint" EP type PCIe interface.

[0113] The frequency of the external clock for the PCIe RC interface may vary for various reasons, as shown by the dashed line PCIE_RC_t1, corresponding to 249MHz, and then as shown by the dashed line PCIE_RC_t2, corresponding to 248MHz, while the local clock pipe_clk is stable at a frequency of 250MHz.

[0114] The time advance of PCIE_EP_t in the time domain of the PCIe EP interface relative to the time domain of the PCIe RC interface is compensated for by essentially “stopping” the clock pipe_clk (clk1) during plateau.

[0115] Advantageously, after each first trigger event TRG1_1, TRG1_2, TRG1_3, TRG1_4, the PTM synchronization of the PCIe EP interface on the PCIe RC interface is achieved by the third device CPU via the updt signal. Figure 2 )control.

[0116] Therefore, the slower the time domain of the PCIe RC interface, the larger the differential duration t1 and t2 between the triggering event TRG1_i and t2>t1.

[0117] At the same time, the synchronization module MSYNC reads the current timestamp values ​​TS2_1 and TS2_2, which represent the instantaneous state of the second PTP time domain (DMN2), the instantaneous moment it detects the second trigger event TRG2 (PPS).

[0118] Difference "TRG1_ i+1 -TRG1_ i ", that is, the durations t1 and t2 in the third time domain TMR3_t (DMN3), by comparing them with the difference "TS2_" between them and the current timestamp value provided by the Ethernet interface ETH (DIS2). j+1 -TS2_ j "Compare and adjust the local clock generator ptp_clk(clk2) of the Ethernet interface ETH(DIS2) on the first PTM time domain (DMN1) using the discipline SYNC."

[0119] In other words, comparing consecutively triggered events TRG1_i in the third time domain. Figure 3 The difference duration between (1≤i≤4) and the continuously acquired current timestamp value PPS_j( Figure 3 The differential duration between (1≤j≤2) is used to synchronize the second time domain DMN2 with the first time domain DMN1.

[0120] Figure 4 Showing previous information Figure 1B and Figure 1C An advantageous exemplary embodiment of the described system-on-chip (SoC) alternative, wherein the triggering time domain does not include the first time domain.

[0121] In this example, the first device, PCIe RC / EP (DIS1), is again a PCIe interface type, and the first counter, PTM_CNT (TMR1), provides a 64-bit binary word on the 64-bit timestamp bus PTM_BUS_64, as mentioned earlier. Figure 2 As stated above.

[0122] The synchronization module includes 64-bit latches LTCH on each channel of the timestamp bus PTM_BUS_64 bits to acquire the current timestamp value Capt_64 bits (TS1) representing the instantaneous state of the first time domain DMN1. At the instant of at least one trigger event TRG, i.e., by triggering the event TRG itself, the latch is loaded using the bits present on each channel of the timestamp bus PTM_BUS_64 bits.

[0123] Whether it's the EP or RC type, this specifically allows for operation of the PCIe interface without modification, particularly regarding the implementation of the PTM protocol with any other PCIe devices outside the system-on-chip (SoC).

Claims

1. A method for synchronizing a first time domain of a first device with a second time domain of a second device, the method comprising: Detect at least one periodic trigger event, said at least one periodic trigger event being generated in at least one trigger time domain selected from the first time domain, the second time domain, and the third time domain of the third device; At the instant of detecting the at least one periodic triggering event, obtain the current timestamp value representing the instantaneous state of the first time domain, the second time domain, and the third time domain, excluding the at least one triggering time domain; In the third time domain, the difference duration between the currently acquired timestamp values ​​is compared. as well as Based on the comparison, the second time domain is synchronized with the first time domain.

2. The method according to claim 1, wherein obtaining the current timestamp value is performed at the same moment when detecting the same periodic triggering event, or at different moments when detecting different periodic triggering events.

3. The method of claim 1, wherein the first time domain is defined by the Precision Time Measurement Protocol (PTM) of the Peripheral Component Interconnect High-Speed ​​PCIe interface, the second time domain is defined by the Precision Time Protocol (PTP) of the network interface Ethernet, and the third time domain is clocked by a free-running local clock configured to clock software operations.

4. The method of claim 1, wherein the at least one triggering time domain includes the first time domain, and the at least one periodic triggering event generated in the first time domain occurs in response to a condition verified on a transition of at least one bit of the current timestamp value representing the instantaneous state of the first time domain, each bit of the current timestamp value being transmitted on a dedicated channel of the timestamp bus.

5. The method of claim 1, wherein the at least one trigger time domain does not include the first time domain, each bit representing the current timestamp value of the instantaneous state of the first time domain is transmitted on a dedicated channel of the timestamp bus, and obtaining the current timestamp value representing the instantaneous state of the first time domain includes loading a latch with bits present on each channel of the timestamp bus, the loading latch being controlled at the instant of detecting the at least one periodic trigger event.

6. The method of claim 1, wherein the at least one triggering time domain includes the second time domain, and the at least one periodic triggering event generated in the second time domain is detected in response to a periodic signal generated in the second time domain.

7. A system-on-a-chip, comprising: A first device includes a first counter configured to provide a current timestamp value representing an instantaneous state in a first time domain; The second device includes a second counter configured to provide a current timestamp value representing an instantaneous state in the second time domain; as well as The third piece of equipment includes: A local clock generator is configured to clock a third time domain; and The synchronization module is configured as follows: Detect at least one periodic triggering event generated in at least one triggering time domain selected from the first time domain, the second time domain, and the third time domain; At the instant of detecting the at least one periodic triggering event, obtain the current timestamp value representing the first time domain, the second time domain, and the third time domain, excluding the at least one triggering time domain; Compare the difference in duration between the consecutively acquired current timestamp values; and Based on the comparison, a control is generated, which is configured to synchronize the second time domain with the first time domain.

8. The system according to claim 7, wherein the synchronization module is configured to acquire the current timestamp value at the same instant when detecting the same periodic triggering event, or at different instants when detecting different periodic triggering events.

9. The system of claim 7, wherein the first device includes a Peripheral Component Interconnect High-Speed ​​"PCIe" interface configured to define the first time domain via a Precision Time Measurement "PTM" protocol, the second device includes a network interface "Ethernet" configured to define the second time domain via a Precision Time Protocol "PTP", and the local clock generator of the third device is configured to clock control software operations.

10. The system of claim 7, wherein the at least one trigger time domain includes the first time domain, the first counter is configured to transmit each bit of the current timestamp value on a dedicated channel of the timestamp bus, and wherein the synchronization module is configured to detect the at least one periodic trigger event generated in the first time domain in response to a condition verified on a transition of at least one bit on the corresponding channel of the timestamp bus.

11. The system of claim 7, wherein the at least one trigger time domain does not include the first time domain, the first counter is configured to transmit each bit of the current timestamp value on a dedicated channel of the timestamp bus, and wherein the synchronization module includes a latch on the timestamp bus, and the synchronization module is configured to: acquire the current timestamp value representing the instantaneous state of the first time domain by controlling the loading of the latch using bits present on each channel of the timestamp bus at the instant of the at least one periodic trigger event.

12. The system of claim 7, wherein the at least one trigger time domain includes the second time domain, and the synchronization module is configured to detect the at least one periodic trigger event generated in the second time domain in response to a periodic signal generated in the second time domain.

13. A system-on-a-chip, comprising: A high-speed PCIe device for peripheral component interconnection includes a first counter configured to provide a current timestamp value representing an instantaneous state in a first time domain; An Ethernet device includes a second counter configured to provide a current timestamp value representing an instantaneous state in a second time domain; as well as Central processing unit (CPU) device, including: A local clock generator is configured to clock a third time domain; and The synchronization module is configured as follows: Detect at least one periodic triggering event, said at least one periodic triggering event being generated in at least one triggering time domain selected from the first time domain, the second time domain, and the third time domain; At the instant of detecting the at least one periodic triggering event, obtain the current timestamp value representing the first time domain, the second time domain, and the third time domain, excluding the at least one triggering time domain; Compare the duration difference between the consecutively acquired current timestamp values; and Based on the comparison, a control is generated, which is configured to synchronize the second time domain with the first time domain.

14. The system-on-a-chip according to claim 13, wherein the synchronization module is configured to acquire the current timestamp value at the same instant when detecting the same periodic triggering event, or at different instants when detecting different periodic triggering events.

15. The system-on-a-chip of claim 13, wherein the PCIe device includes a PCIe interface configured to define the first time domain via a Precision Time Measurement (PTM) protocol, the Ethernet device includes an Ethernet interface configured to define the second time domain via a Precision Time Protocol (PTP), and the local clock generator of the CPU device is configured to clock-control software operations.

16. The system-on-a-chip of claim 13, wherein the at least one trigger time domain includes the first time domain, the first counter is configured to transmit each bit of the current timestamp value on a dedicated channel of the timestamp bus, and wherein the synchronization module is configured to detect the at least one periodic trigger event generated in the first time domain in response to a condition verified on a transition of at least one bit on the corresponding channel of the timestamp bus.

17. The system-on-a-chip of claim 13, wherein the at least one trigger time domain does not include the first time domain, the first counter is configured to transmit each bit of the current timestamp value on a dedicated channel of the timestamp bus, and wherein the synchronization module includes a latch on the timestamp bus, and the synchronization module is configured to: acquire the current timestamp value representing the instantaneous state of the first time domain by controlling the loading of the latch using bits present on each channel of the timestamp bus at the instant of the at least one periodic trigger event.

18. The system-on-a-chip of claim 13, wherein the at least one trigger time domain includes the second time domain, and the synchronization module is configured to detect the at least one periodic trigger event generated in the second time domain in response to a periodic signal generated in the second time domain.

19. The system-on-a-chip of claim 13, wherein the CPU device is a microprocessor.

20. The system-on-a-chip of claim 13, wherein the CPU device is a microcontroller.

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