Display driving circuit and display device

Abstract

A display driving circuit and a display device are provided. The display driving circuit includes a clock signal generator that generates a clock signal at a frequency in response to a frequency control signal, a frequency change determiner that adaptively changes a frequency change of the clock signal based on a magnitude of a deviation between the frequency of the clock signal and a target frequency calculated based on a reference clock signal supplied from outside, and a frequency controller that generates the frequency control signal based on the frequency change, the frequency control signal updating the frequency of the clock signal and being supplied to the clock signal generator.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0002884, filed on January 8, 2021, and all rights arising therefrom, the contents of which are incorporated herein by reference in their entirety. Background Technology

[0003] Embodiments of the present invention generally relate to a display device, and more specifically, to a display device including a display driving circuit and a method for driving the display device.

[0004] A display device includes a pixel portion, the pixel portion comprising pixels for displaying an image and a display driving circuit for controlling the driving of the pixel portion. The display driving circuit generates a clock signal, the clock signal being a reference for determining the timing of image display and various control signals (e.g., synchronization signals, data signals, and scan signals) for the pixel portion of the display device.

[0005] The frequency of the clock signal can be controlled based on an externally provided reference clock signal. While displaying an image, the frequency of the clock signal can be adjusted according to the driving conditions of the display device. Summary of the Invention

[0006] An embodiment provides a display driving circuit that selects (or updates) frequency changes based on the difference between the frequency of a clock signal and a target frequency, and controls the frequency of the clock signal to approach the target frequency according to the frequency changes.

[0007] The embodiments also provide a display device including a display driving circuit and a method for driving the display device.

[0008] According to an embodiment of the present invention, a display driving circuit is provided, comprising: a clock signal generator that generates a clock signal at a frequency in response to a frequency control signal; a frequency change determiner that adaptively changes the frequency change of the clock signal based on the magnitude of the deviation between the frequency of the clock signal and a target frequency calculated based on a reference clock signal provided externally; and a frequency controller that generates a frequency control signal based on the frequency change, updates the frequency of the clock signal, and provides the frequency control signal to the clock signal generator.

[0009] In an embodiment, the frequency change determiner may include: a first frequency calculator that calculates the current frequency of the clock signal based on a value obtained by counting pulses of the clock signal during a counting-enabled period; a second frequency calculator that calculates the target frequency of the clock signal based on a value obtained by counting pulses of a reference clock signal during a counting-enabled period; and a determiner that determines the frequency change based on a result obtained by comparing a frequency deviation, which is the deviation between the current frequency and the target frequency, with at least one of predetermined reference deviations.

[0010] In an embodiment, the first frequency change determined when the frequency deviation is equal to or less than the first reference deviation may be less than the second frequency change determined when the frequency deviation is greater than the first reference deviation and equal to or less than the second reference deviation.

[0011] In an embodiment, in image display mode, the clock signal generator can change the frequency of the clock signal at predetermined frame intervals to approach the target frequency.

[0012] In this embodiment, the frequency of the clock signal can be gradually reduced as frames pass until the frequency of the clock signal reaches the target frequency.

[0013] In one embodiment, the first frequency calculator may include: a first counter that counts pulses of a clock signal during a counting enable period; and a first calculator that calculates the sum of values ​​provided from the first counter during the counting enable period as a first result corresponding to the current frequency.

[0014] In an embodiment, the second frequency calculator may include: a second counter that counts pulses of a reference clock signal during a counting-enabled period; a multiplier that multiplies the value provided by the second counter by the ratio of the reference frequency to the target frequency; and a second calculator that calculates the sum of the results calculated by the multiplier as a second result corresponding to the target frequency.

[0015] In an embodiment, the determiner may compare the difference between the first result and the second result with at least one of the reference deviations.

[0016] In an embodiment, the second frequency calculator may include: a second counter that counts pulses of a reference clock signal during a counting enable period; a second calculator that calculates the sum of values ​​provided from the second counter during the counting enable period; and a multiplier that multiplies the value provided from the second calculator by the ratio of the reference frequency to the target frequency to generate a second result corresponding to the target frequency.

[0017] In one embodiment, the frequency controller may provide a frequency control signal to the clock signal generator during a predetermined blank period of a frame.

[0018] In an embodiment, the display driving circuit may further include: a frequency compensation controller, which controls the timing of a first frequency calculator, a second frequency calculator, and an output frequency control signal based on a control signal provided from an external source and a target frequency.

[0019] According to another embodiment of the present invention, a method for driving a display device is provided, the method comprising: calculating a first clock quantity corresponding to the current frequency of a clock signal output from a clock signal generator by counting pulses of a clock signal during a counting enable period; calculating a second clock quantity corresponding to a target frequency of a clock signal by counting pulses of a reference clock signal provided externally during the counting enable period; comparing a frequency deviation corresponding to the difference between the first clock quantity and the second clock quantity with at least one reference deviation corresponding to a predetermined reference clock quantity; determining a frequency change of the clock signal based on the comparison result; and updating the frequency of the clock signal during a blank period of a frame based on the frequency change, wherein the frequency change increases as the frequency deviation increases.

[0020] In an embodiment, in calculating the second clock count, the second clock count can be calculated by multiplying the value obtained by counting the pulses of the reference clock signal by the ratio of the reference frequency to the target frequency. The reference frequency can be the frequency of the reference clock signal.

[0021] In an embodiment, the first frequency change determined when the frequency deviation is equal to or less than the first reference deviation may be less than the second frequency change determined when the frequency deviation is greater than the first reference deviation and equal to or less than the second reference deviation.

[0022] In one embodiment, the frequency of the clock signal can be changed at predetermined frame intervals to approximate the target frequency.

[0023] In this embodiment, the frequency of the clock signal can be gradually reduced until the frequency of the clock signal reaches the target frequency.

[0024] According to another embodiment of the present invention, a display device is provided, the display device comprising: a pixel portion, the pixel portion including pixels for displaying an image; and a display driving circuit, the display driving circuit providing a data signal corresponding to the image to the pixel portion and outputting a clock signal controlling the output timing of the data signal, wherein the display driving circuit comprises: a clock signal generator, the clock signal generator generating a clock signal at a frequency in response to a frequency control signal; a frequency change determiner, the frequency change determiner adaptively changing the frequency change of the clock signal based on the magnitude of the deviation between the frequency of the clock signal and a target frequency calculated based on a reference clock signal provided externally; and a frequency controller, the frequency controller generating a frequency control signal based on the frequency change, the frequency control signal updating the frequency of the clock signal, and providing the frequency control signal to the clock signal generator.

[0025] In an embodiment, the frequency change determiner may include: a first frequency calculator that calculates the current frequency of the clock signal based on a value obtained by counting pulses of the clock signal during a counting-enabled period; a second frequency calculator that calculates the target frequency of the clock signal based on a value obtained by counting pulses of a reference clock signal during a counting-enabled period; and a determiner that determines the frequency change based on a result obtained by comparing a frequency deviation, which is the deviation between the current frequency and the target frequency, with at least one of predetermined reference deviations.

[0026] In an embodiment, in image display mode, the clock signal generator can change the frequency of the clock signal at predetermined frame intervals to approach the target frequency.

[0027] In this embodiment, the frequency of the clock signal can be gradually reduced as frames pass until the frequency of the clock signal reaches the target frequency. Attached Figure Description

[0028] The embodiments described below will now be described more fully with reference to the accompanying drawings.

[0029] Figure 1 This is a block diagram illustrating an embodiment of a display device according to the present invention.

[0030] Figure 2 This is a block diagram illustrating an embodiment of a display driving circuit according to the present invention.

[0031] Figure 3 It is shown Figure 2 A block diagram of an embodiment of the display driver circuit shown.

[0032] Figure 4 It is shown Figure 3 The timing diagram shows an embodiment of the operation of the display driver circuit.

[0033] Figure 5A It shows from Figure 3 The diagram shows an embodiment of the frequency variation of the clock signal output by the display driver circuit.

[0034] Figure 5B This is a diagram illustrating an embodiment of the relationship between frequency deviation, reference frequency, and frequency variation.

[0035] Figure 6 It shows from Figure 3 The diagram shows another embodiment of the frequency variation of the clock signal output by the display driver circuit.

[0036] Figure 7 It is shown Figure 3 The timing diagram shows an embodiment of the operation of the display driving circuit during a blank period.

[0037] Figure 8 It is shown Figure 3 The timing diagram shown is an embodiment of a display driver circuit that changes the period of the clock signal frequency.

[0038] Figure 9 It is shown Figure 2 A block diagram of an embodiment of the display driver circuit shown.

[0039] Figure 10 This is a flowchart illustrating an embodiment of a method for driving a display device according to the present invention. Detailed Implementation

[0040] In the following description, embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. Throughout the drawings, the same elements are given the same reference numerals, and any repeated explanations will be omitted.

[0041] What will be understood is that when an element is referred to as being "on" another element, it can be directly on the other element or an intermediary element can be in between. Conversely, when an element is referred to as being "directly on" another element, there is no intermediary element.

[0042] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another. Therefore, without departing from the teachings of this document, “first element,” “first component,” “first region,” “first layer,” or “first part” discussed below may be referred to as a second element, second component, second region, second layer, or second part.

[0043] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, unless explicitly stated otherwise, the singular forms “a,” “an,” and “the” are intended to include the plural forms comprising “at least one.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will be further understood that, when used in this specification, the terms “comprising” and / or “including,” or “comprising” and / or “including,” specify the presence of the said features, regions, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, regions, integers, steps, operations, elements, components, and / or groups thereof.

[0044] Furthermore, related terms such as “lower” or “bottom” and “upper” or “top” may be used herein to describe the relationship of one element to another as shown in the figures. It will be understood that, in addition to the orientation depicted in the figures, the related terms are intended to include different orientations of the device. In embodiments, when a device in a figure is flipped, an element described as being “below” the other element will subsequently be oriented to be “above” the other element. Thus, the exemplary term “lower” can include both “lower” and “upper” orientations, depending on the specific orientation of the figure. Similarly, when a device in a figure is flipped, an element described as being “below” or “under” the other element will subsequently be oriented to be “above” the other element. Thus, the exemplary term “below” or “under” can include both “upper” and “lower” orientations.

[0045] As used herein, “about” or “approximately” includes the value and indicates an acceptable range of deviation from the particular value as determined by one of ordinary skill in the art, taking into account the measurement in discussion and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, “about” may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the value.

[0046] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. It will be further understood that, unless so explicitly defined herein, terms such as those defined in general dictionaries should be interpreted as having meanings consistent with their meanings in the relevant field and in the context of this invention, and will not be interpreted in an idealized or overly formalized sense.

[0047] Figure 1 This is a block diagram illustrating an embodiment of a display device according to the present invention.

[0048] refer to Figure 1The display device 1000 may include a pixel portion 10, a scan driver 20, a data driver 30, and a timing controller 40.

[0049] The display device 1000 can be a flat panel display device, a flexible display device, a curved display device, a foldable display device, a bendable display device, or a stretchable display device. Furthermore, the display device 1000 can be applied to head-mounted display devices and wearable display devices, etc. Additionally, the display device 1000 can be applied to various electronic devices, including smartphones, tablets, smart tablets, televisions (“TVs”), and monitors, etc.

[0050] The display device 1000 can be implemented as a self-emissive display device including a plurality of self-emissive elements. In embodiments, for example, the display device 1000 can be an organic light-emitting display device including organic light-emitting elements, a display device including inorganic light-emitting elements, or a display device including light-emitting elements comprising a combination of inorganic and organic materials. However, this is merely illustrative, and the display device 1000 can be implemented as a liquid crystal display device, a plasma display device, or a quantum dot display device, etc.

[0051] Pixel portion 10 may include scan lines S1 to Sn (n is an integer greater than 1), data lines D1 to Dm (m is an integer greater than 1), and pixel PX. Pixel PX may be electrically connected to data lines D1 to Dm and scan lines S1 to Sn. In some embodiments, at least one scan line may be connected to each of the pixels PX.

[0052] Pixel PX can emit light with grayscale and brightness, which corresponds to the data signals provided from data lines D1 to Dm.

[0053] The scan driver 20 can receive a scan control signal SCS provided by the timing controller 40. The scan driver 20, which is provided with the scan control signal SCS, can provide scan signals to scan lines S1 to Sn. In an embodiment, for example, the scan control signal SCS may include a start signal and a scan clock signal, etc.

[0054] The scan driver 20 may be disposed on one area of ​​the pixel portion 10 (or one area of ​​the display panel). In an alternative embodiment, the scan driver 20 may be implemented as an integrated circuit (“IC”) and disposed (e.g., mounted) on a flexible circuit board connected to the pixel portion 10. In an embodiment, the scan driver 20 may be disposed on both sides, with the pixel portion 10 between them.

[0055] Based on the data control signal DCS and the image data RGB, the data driver 30 can generate a data signal (or data voltage) and provide the data signal to the data lines D1 to Dm. The data control signal DCS is a signal used to control the operation of the data driver 30 and may include sampling signals and source output signals, etc.

[0056] The data driver 30 may be implemented as an IC (e.g., a driver IC) and set (e.g., mounted) on a flexible circuit board connected to the pixel portion 10.

[0057] The timing controller 40 can receive input image data from an external source (e.g., a graphics processor). Based on the control signals provided from the external source, the timing controller 40 can generate a scan control signal SCS and a data control signal DCS. Furthermore, the timing controller 40 can rearrange the input image data into image data RGB corresponding to the pixel arrangement of the pixel portion 10, and output the image data RGB.

[0058] In one embodiment, at least a portion of the functions of the data driver 30 and the timing controller 40 may be integrated into the display driver circuit 100. In another embodiment, the display driver circuit 100 may be provided as an IC, for example, for performing all the functions of the data driver 30 and the timing controller 40.

[0059] Based on the output signal corresponding to the frame rate of the display device 1000, the display driving circuit 100 can generate synchronization signals (vertical and horizontal synchronization signals). (Refer to...) Figure 2 The accompanying drawings describe in detail the configuration of the display driver circuit 100 that outputs the clock signal.

[0060] Although Figure 1 The diagram shows n scan lines S1 to Sn, but the invention is not limited thereto. In an embodiment, corresponding to the circuit structure of pixel PX, a pixel PX disposed on the current horizontal line (or current pixel row) can be additionally connected to scan lines disposed on the previous horizontal line (or previous pixel row) and / or scan lines disposed on the next horizontal line (or next pixel row). For this purpose, virtual scan lines (not shown) can be additionally provided in the pixel portion 10.

[0061] Furthermore, corresponding to the pixel structure of pixel PX, an emission control line can be separately connected to pixel PX. The display device 1000 may also include an emission driver for driving the emission control line.

[0062] Figure 2 This is a block diagram illustrating an embodiment of a display driving circuit according to the present invention.

[0063] refer to Figure 2The display driving circuit 100 included in the display device may include a frequency change determiner 120, a frequency controller 140, and a clock signal generator 160.

[0064] Based on the frequency deviation between reference frequencies as the frequency of the externally provided reference clock signal R_CLK and the frequency of the clock signal CLK, the frequency change determiner 120 can determine the frequency change of the clock signal CLK output from the clock signal generator 160. In an embodiment, for example, based on the feedback clock signal CLK, the clock signal CLK can be fed back to the frequency change determiner 120, and the frequency of the clock signal CLK can be adjusted to achieve the target frequency.

[0065] In an embodiment, the frequency change determiner 120 may include a first frequency calculator 122, a second frequency calculator 124, and a determiner 126.

[0066] The first frequency calculator 122 can receive a feedback clock signal CLK. Based on the value obtained by counting the pulses of the clock signal CLK during the counting enabled period, the first frequency calculator 122 can calculate the current frequency F1 of the clock signal CLK. In an embodiment, for example, the first frequency calculator 122 can output the number of pulses of the clock signal CLK counted during the counting enabled period.

[0067] The number of pulses of the clock signal CLK counted during the counting enable period (e.g., the first clock count) can be understood as the current frequency F1 of the clock signal CLK. In some embodiments, the number of pulses of the clock signal CLK counted during the counting enable period can be converted into the current frequency F1 of the clock signal CLK by additional calculation.

[0068] The counting enable period can be set to a portion of a frame. However, this is merely illustrative, and the counting enable period is not limited to this. In embodiments, for example, the counting enable period can be set to a period comprising multiple consecutive frames.

[0069] From Figure 1 The processor or other external component of the display device 1000 provides a reference clock signal R_CLK. The reference clock signal R_CLK can serve as a reference for generating the clock signal CLK, and is generated to withstand changes in the external environment. That is, the frequency and voltage level of the reference clock signal R_CLK can be relatively less affected by changes in ambient temperature, power supply voltage, etc.

[0070] The display driving circuit 100 can generate a high-frequency clock signal CLK by multiplying a reference clock signal R_CLK. Typically, the reference frequency of the reference clock signal R_CLK and the frequency of the clock signal CLK differ significantly. In an embodiment, for example, the reference frequency can be set to approximately 32.768 kHz, and the frequency of the clock signal CLK can be approximately 1 MHz or higher. In an embodiment, for example, the frequency of the clock signal CLK can be determined in the range of approximately 1 MHz to approximately 150 MHz based on the driving conditions of the display device 1000.

[0071] Based on the value obtained by counting the pulses of the reference clock signal R_CLK during the counting enabled period, the second frequency calculator 124 can calculate the target frequency F2 of the clock signal CLK. In an embodiment, for example, the second frequency calculator 124 can output the number of pulses of the reference clock signal R_CLK counted during the counting enabled period.

[0072] As described above, since the reference frequency and the clock signal frequency differ significantly from the target frequency F2, the number of pulses of the reference clock signal R_CLK counted during the counting enable period may not correspond to the target frequency F2. Therefore, the second frequency calculator 124 can obtain the count (e.g., the second clock count) corresponding to the target frequency F2 by multiplying the count value by the ratio of the reference frequency to the target frequency.

[0073] In some embodiments, for example, the target frequency F2 can be understood as the value obtained by multiplying the number of pulses of the reference clock signal R_CLK counted during the counting enable period by the ratio of the reference frequency to the target frequency (e.g., the second clock count). In some embodiments, the target frequency F2 can be converted by additional calculations to the value obtained by multiplying the number of pulses of the reference clock signal R_CLK counted during the counting enable period by the ratio of the reference frequency to the target frequency.

[0074] Determiner 126 can compare the difference between the current frequency F1 and the target frequency F2 (hereinafter also referred to as frequency deviation) with at least one of a predetermined reference deviation RDV[k:0] (k is a natural number). Determiner 126 can select the output value corresponding to the condition to which the frequency deviation belongs as the frequency change FCA.

[0075] In an embodiment, for example, the reference deviation RDV[k:0] can be represented by k bits and has different values. In an embodiment, for example, each of the reference deviations RDV[k:0] can be understood as a predetermined increment value and includes information associated with the frequency deviation and / or the corresponding number of clock cycles.

[0076] In an embodiment, for example, the reference deviation RDV[k:0] may include the first to the second k Reference bias. The first reference bias can have the smallest increment value (or the smallest number of clock cycles), and the second... k The reference deviation can have the largest increment value (or the largest number of clock cycles). As it approaches the 2nd... k The reference deviation increment can be increased. Therefore, a predetermined increment range with respect to the target frequency F2 can be defined by the reference deviation RDV[k:0].

[0077] In this embodiment, the determiner 126 can determine the frequency change FCA based on the increment range to which the frequency deviation belongs. When the frequency deviation is equal to or less than the first reference deviation, a first frequency change can be output as the frequency change FCA. When the frequency deviation is greater than the first reference deviation and equal to or less than the second reference deviation, a second frequency change can be output as the frequency change FCA. The first frequency change can be less than the second frequency change.

[0078] In this embodiment, as the difference between the current frequency F1 and the target frequency F2 increases, the frequency change FCA can be determined to be a larger value.

[0079] In other words, the determiner 126 can adaptively adjust the frequency variation FCA based on the difference between the current frequency F1 and the target frequency F2. Therefore, the time (e.g., tracking time) required to adjust the output frequency of the clock signal CLK to the level of the target frequency F2 during image display (or in display mode) can be significantly reduced.

[0080] The determiner 126 may include various types of hardware and / or software. The determiner 126 selects a frequency deviation from a reference deviation RDV[k:0] and determines the corresponding output value. In embodiments, for example, the determiner 126 may include computational circuitry such as comparators and memory.

[0081] Based on the frequency change function (FCA), the frequency controller 140 can generate a frequency control signal FCON for updating the frequency of the clock signal CLK. The frequency controller 140 can provide the frequency control signal FCON to the clock signal generator 160 in response to the update control signal UDT_CON.

[0082] The frequency of the clock signal CLK can be updated within a predetermined period by the update control signal UDT_CON.

[0083] Clock signal generator 160 can generate a clock signal CLK at a frequency according to a frequency control signal FCON. The frequency of the clock signal CLK can be higher than a reference frequency. In an embodiment, clock signal generator 160 may include an oscillator for generating the clock signal.

[0084] The clock signal CLK can typically control the driving timing of various driving circuits and logic circuits included in the display device 1000. In an embodiment, for example, the clock signal CLK can determine the output timing of vertical synchronization signals, horizontal synchronization signals, and data enable signals, etc.

[0085] Figure 3 It is shown Figure 2 A block diagram of an embodiment of the display driver circuit shown.

[0086] exist Figure 3 In, and reference Figure 2 The same components described are designated by the same reference numerals, and any repeated descriptions of the above-described elements will be omitted.

[0087] refer to Figure 2 and Figure 3 The display driving circuit 100 may include a frequency change determiner 120, a frequency controller 140, a clock signal generator 160, and a frequency compensation controller 180.

[0088] The frequency compensation controller 180 can receive target frequency information I_FT and control signal CON.

[0089] The target frequency information I_FT can be understood as the target frequency value of the output clock signal CLK. The frequency compensation controller 180 can calculate the ratio of the reference frequency F_R to the target frequency F_T as the frequency coefficient N using the target frequency information I_FT. In an embodiment, for example, the frequency coefficient N can be determined as a value obtained by dividing the target frequency F_T by the reference frequency F_R (e.g., N = F_T / F_R). The frequency coefficient N can be applied to the result obtained by counting the pulses of the reference clock signal R_CLK (e.g., the number of clock cycles).

[0090] The control signal CON can be a signal used to control the drive of the frequency change determiner 120 and the frequency controller 140. In an embodiment, based on the control signal CON, the frequency compensation controller 180 can generate a first enable signal EN1, a second enable signal EN2, and an update control signal UDT_CON.

[0091] The first enable signal EN1 controls the operation (activation) of the first counter 1222 and the second counter 1242. The second enable signal EN2 controls the operation (activation) of the first calculator 1224 and the second calculator 1246.

[0092] The update control signal UDT_CON can control the update time (time period) of the clock signal CLK frequency. In an embodiment, the frequency of the clock signal CLK can be adjusted within a predetermined frame time period, for example, corresponding to the time when the update control signal UDT_CON is provided.

[0093] For reference Figure 2 As described, the frequency change determiner 120 may include a first frequency calculator 122, a second frequency calculator 124, and a determiner 126.

[0094] In an embodiment, the first frequency calculator 122 may include a first counter 1222 and a first calculator 1224.

[0095] Based on the first enable signal EN1, the first counter 1222 can generate a first count value CT1 by counting the pulses of the clock signal CLK during the counting enable period.

[0096] Based on the second enable signal EN2, the first calculator 1224 can calculate a first clock count as the sum of the first count values ​​CT1 provided from the first counter 1222 during the counting enable period, as a first result RV1. The first result RV1 (first clock count) can be understood as the sum of the current frequency of the clock signal CLK. Figure 2 The value corresponding to F1 shown. The first calculator 1224 may include an adder circuit, etc.

[0097] In an embodiment, the second frequency calculator 124 may include a second counter 1242, a multiplier 1244, and a second calculator 1246.

[0098] Based on the first enable signal EN1, the second counter 1242 can generate a second count value CT2 by counting the pulses of the reference clock signal R_CLK during the counting enable period.

[0099] Multiplier 1244 can multiply the second count value CT2 by the frequency coefficient N. The output CV of multiplier 1244 generated during the counting activation period can be provided to the second calculator 1246.

[0100] The second calculator 1246 can calculate the second clock number as the sum of the outputs CV of the multiplier 1244 as the second result RV2. Since the frequency coefficient N is the value obtained by dividing the target frequency F_T by the reference frequency F_R (i.e., N = F_T / F_R), the target frequency F_T can be derived from the second result RV2.

[0101] In other words, the value derived from the second result RV2 (e.g., Figure 2F2 shown can be understood as the value corresponding to the target frequency F_T. The actual target frequency F_T included in the target frequency information I_FT and the target frequency F2 derived from the second result RV2 based on the pulse count of the reference clock signal R_CLK may not be exactly equal to each other. However, this deviation is an error that can be ignored when driving the frequency adjustment clock signal CLK.

[0102] Determiner 126 can compare the difference between the first result RV1 and the second result RV2 with a predetermined reference deviation RDV[k:0]. Determiner 126 can select an output value set as the frequency change FCA within the increment range to which the difference (i.e., frequency deviation) between the current frequency F1 and the target frequency F2 belongs, within the increment range defined by the reference deviation RDV[k:0].

[0103] Frequency controller 140 can provide frequency control signal FCON to clock signal generator 160 in response to update control signal UDT_CON. Clock signal generator 160 can generate clock signal CLK according to frequency and timing based on frequency control signal FCON.

[0104] Figure 4 It is shown Figure 3 The timing diagram shows an embodiment of the operation of the display driver circuit.

[0105] refer to Figure 1 , Figure 3 and Figure 4 The display driving circuit 100 can quickly track the frequency of the clock signal CLK (hereinafter also referred to as the clock frequency F_C) to the target frequency F_T during the period when the display device 1000 displays an image after it has gone into sleep mode.

[0106] When the image display operation of the display device 1000 is activated by the sleep signal SLEEP_OUT, the clock frequency F_C is precisely adjusted. That is, the display driver circuit 100 can operate in image display mode in response to the sleep signal SLEEP_OUT. In one embodiment, the image display operation of the display device 1000 is activated by a high-level sleep signal SLEEP_OUT, but the invention is not limited thereto, and in another embodiment, the image display operation of the display device 1000 is activated by a low-level sleep signal SLEEP_OUT.

[0107] The reference clock signal R_CLK can be provided to the display driver circuit 100 at a constant frequency of reference frequency F_R. In an embodiment, for example, the reference frequency F_R can be approximately 32.768 kHz.

[0108] During the sleep state of the display device 1000, a vertical synchronization signal Vsync can be output in units of frames. The vertical synchronization signal Vsync can be output (activated) for each blank period of a frame.

[0109] The first enable signal EN1 can be activated during a frame period of the displayed image. The period in which the first enable signal EN1 is activated can be defined as a first time period or a counting enable period. The first counter 1222 and the second counter 1242 can count the pulses of the clock signal CLK and the reference clock signal R_CLK, respectively, in response to the first enable signal EN1.

[0110] In one embodiment, the second enable signal EN2 can be activated in a second time period following the first time period. The first calculator 1224 and the second calculator 1246 can respectively calculate the sum of the value CT1 and the output CV provided in response to the second enable signal EN2 during the first time period (e.g., a first result RV1 and a second result RV2). The first calculator 1224 and the second calculator 1246 may include a memory, such as RAM, which temporarily stores the provided values.

[0111] In another embodiment, the second enable signal EN2 can be activated during a time period substantially equal to that of the first enable signal EN1. The first calculator 1224 and the second calculator 1246 can respectively accumulate the sum of the provided values ​​in real time.

[0112] In this embodiment, the clock frequency F_C can be varied during the blank periods that provide the vertical synchronization signal Vsync. During these blank periods, the clock frequency F_C can be adjusted to be close to the target frequency F_T. Furthermore, after the blank period, the clock signal CLK can be output at a frequency that varied during the previous blank period. That is, changing the clock frequency F_C during blank periods when the output of the displayed image is less affected minimizes screen anomalies caused by variations in the clock frequency F_C.

[0113] Figure 5A It shows from Figure 3 The diagram shows an embodiment of the frequency variation of the clock signal output by the display driver circuit. Figure 5B This is a diagram illustrating an embodiment of the relationship between frequency deviation, reference frequency, and frequency variation.

[0114] refer to Figure 3 , Figure 4 , Figure 5A and Figure 5B The display driving circuit 100 can change the frequency (clock frequency F_C) of the clock signal CLK to a frequency close to the target frequency F_T at a predetermined frame interval.

[0115] Figure 5A and Figure 5B Examples are shown for defining the first reference deviations DRV1 to the fourth reference deviations DRV4 for the five frequency change steps FCS in a display driver circuit, and the frequency changes FCA1 to FCA5 corresponding to the five frequency change steps FCS. However, this is merely illustrative, and the forms of change for the clock frequency F_C, reference deviations, and frequency changes are not limited thereto.

[0116] In this embodiment, the frequency change step FCS can be controlled based on the relationship between the first reference deviation DRV1 to the fourth reference deviation DRV4 and the frequency deviation FD, whereby the frequency deviation FD can be understood as the absolute value of the difference between the clock frequency F_C and the target frequency F_T. In this embodiment, for example, the frequency deviation FD can correspond to the difference between the number of clock cycles corresponding to the target frequency F_T and the number of clock cycles corresponding to the clock frequency F_C, and each of the first reference deviations DRV1 to the fourth reference deviations DRV4 can correspond to a predetermined number of clock cycles. However, this is merely illustrative, and the frequency deviation FD and each of the first reference deviations DRV1 to the fourth reference deviations DRV4 can be calculated as a frequency value converted from the number of clock cycles.

[0117] The Frequency Change Step (FCS) can define the amplitude (frequency change) of the frequency that changes over a predetermined frequency change time.

[0118] In an embodiment, each of the first reference deviations DRV1 to the fourth reference deviations DRV4 can be defined as an increment value of the frequency or a predetermined number of clock cycles. In an embodiment, for example, the second reference deviation DRV2 can be greater than the first reference deviation DRV1 and less than the third reference deviation DRV3. The third reference deviation DRV3 can be less than the fourth reference deviation DRV4. Five increment ranges with respect to the target frequency F_T can be defined using the first reference deviations DRV1 to the fourth reference deviations DRV4. The increment ranges can correspond to the first frequency change steps STEP1 to the fifth frequency change steps STEP5. In an embodiment, as... Figure 5B As shown, for example, the frequency change step FCS and its corresponding frequency change FCA can be determined based on the conditions of the incremental range defined by the first reference deviation DRV1 to the fourth reference deviation DRV4.

[0119] Furthermore, as the frequency deviation FD increases, the frequency change FCA can be increased according to the frequency change step FCS. In an embodiment, for example, the second frequency change FCA2 can be greater than the first frequency change FCA1 and less than the third frequency change FCA3. The fourth frequency change FCA4 can be greater than the third frequency change FCA3 and less than the fifth frequency change FCA5.

[0120] When the frequency deviation FD is greater than the fourth reference deviation DRV4, the determiner 126 of the display drive circuit 100 can determine the frequency change step FCS as the fifth frequency change step STEP5, and determine the frequency change FCA as the fifth frequency change FCA5. Therefore, the clock frequency F_C can be changed to be set closer to the target frequency F_T by the fifth frequency change FCA5.

[0121] When the frequency deviation FD is greater than the third reference deviation DRV3 and equal to or less than the fourth reference deviation DRV4, the display drive circuit 100 can change the clock frequency F_C through the fourth frequency change step STEP4. The clock frequency F_C can be changed to be close to the target frequency F_T through the fourth frequency change FCA4.

[0122] When the frequency deviation FD is greater than the second reference deviation DRV2 and equal to or less than the third reference deviation DRV3, the display drive circuit 100 can change the clock frequency F_C through the third frequency change step STEP3. The clock frequency F_C can be changed to be close to the target frequency F_T through the third frequency change FCA3.

[0123] When the frequency deviation FD is greater than the first reference deviation DRV1 and equal to or less than the second reference deviation DRV2, the display driving circuit 100 can change the clock frequency F_C through the second frequency change step STEP2. The clock frequency F_C can be changed to be close to the target frequency F_T through the second frequency change FCA2.

[0124] When the frequency deviation FD is equal to or less than the first reference deviation DRV1, the display driving circuit 100 can change the clock frequency F_C through the first frequency change step STEP1. The clock frequency F_C can be changed to be close to the target frequency F_T through the first frequency change FCA1.

[0125] As described above, the clock frequency F_C can be adjusted (clock tracking) according to the magnitude of the frequency deviation FD through one of the first frequency change steps STEP1 to the fifth frequency change step STEP5.

[0126] In an embodiment, such as Figure 5A As shown, the frequency variation FCA of the clock frequency F_C can gradually decrease towards the target frequency F_T as the frame passes.

[0127] Finally, the clock frequency F_C can be determined to be equal to or close to the target frequency F_T based on the first frequency change FCA1.

[0128] In this embodiment, the first frequency variation FCA1 to the fifth frequency variation FCA5 and / or the first reference deviation DRV1 to the fourth reference deviation DRV4 can be changed based on the frequency deviation FD initially calculated in display mode. The initially calculated frequency deviation FD can be understood as the difference between the target frequency F_T and the current clock frequency F_C initially detected in display mode.

[0129] In an embodiment, for example, the frequency change set according to the fifth frequency change FCA5 with the largest frequency change can increase as the initially calculated frequency deviation FD increases. Other frequency changes (e.g., FCA1 to FCA4) can be changed corresponding to changes in the maximum frequency change.

[0130] The relationship between the initial frequency deviation FD and the maximum frequency change can be set as a linear or exponential relationship.

[0131] In an embodiment, the number of frequency change steps (FCS) set based on the initially calculated frequency deviation FD and the frequency change corresponding to the initially calculated frequency deviation FD can be varied. For example, in an embodiment, as the initially calculated frequency deviation FD decreases, the number of frequency change steps (FCS) set based on the initially calculated frequency deviation FD can be reduced.

[0132] However, this is merely illustrative, and the values ​​and quantities of frequency change steps FCS, frequency change FCA, and reference deviation are not limited thereto.

[0133] The clock signal generator 160, including the oscillator, may be affected by environmental factors, such as changes in ambient temperature or power supply voltage. The frequency of the clock signal CLK output from the clock signal generator 160 can be changed. In an embodiment, for example, the frequency of the clock signal CLK may be changed due to the heat generated when the display device 1000 is used for an extended period.

[0134] like Figure 4 and Figure 5A As shown, Figure 3 The display driver circuit 100 can continuously check the frequency (i.e., clock frequency F_C) of the clock signal CLK fed back in display mode. Therefore, even if the clock frequency F_C deviates from the target frequency F_T due to environmental factors, the clock frequency F_C can be automatically and quickly corrected to the target frequency F_T through the frequency change step FCS. Furthermore, based on the detection results, the configuration for detecting changes in environmental factors (i.e., changes in temperature, changes in voltage levels associated with clock signal generation, etc.) and the separate hardware and software configuration for setting the offset value for frequency correction can be removed (or omitted).

[0135] As described above, in the display driving circuit 100 and the display device 1000 including the display driving circuit 100 in the embodiments of the present invention, the frequency variation FCA can be adaptively adjusted according to the deviation between the current clock frequency F_C and the target frequency F_T (i.e., frequency deviation FD). Therefore, the time (e.g., tracking time) during image display (i.e., in display mode) during which the clock frequency F_C is expected to be adjusted to the level of the target frequency F_T can be significantly reduced. Therefore, screen abnormalities (brightness changes, crosstalk, flicker, etc.) caused by changes in the clock frequency F_C during image display can be reduced or minimized.

[0136] Figure 6 It shows from Figure 3 The diagram shows another embodiment of the frequency variation of the clock signal output by the display driver circuit.

[0137] exist Figure 6 In, and reference Figure 5A and Figure 5B The same components described are designated by the same reference numerals, and any repeated descriptions of the above-described elements will be omitted.

[0138] refer to Figure 3 , Figure 4 and Figure 6 The display driving circuit 100 can change the frequency (clock frequency F_C) of the clock signal CLK to a frequency close to the target frequency F_T at a predetermined frame interval.

[0139] and Figure 5A The embodiments shown are different, in Figure 6 In the drive shown, the clock frequency F_C can be gradually changed towards the target frequency F_T through two frequency change steps (e.g., the first frequency change step STEP1 and the fifth frequency change step STEP5).

[0140] As described above, the display driver circuit 100 can stabilize the clock frequency F_C through various types of frequency variation steps via the optimal path according to the design.

[0141] Figure 7 It is shown Figure 3 The timing diagram shows an embodiment of the operation of the display driving circuit during a blank period. Figure 8 It is shown Figure 3 The timing diagram shown is an embodiment of a display driver circuit that changes the period of the clock signal frequency.

[0142] refer to Figure 1 , Figure 3 , Figure 4 , Figure 7 and Figure 8The clock signal generator 160 can change the frequency of the clock signal CLK in response to the frequency control signal FCON.

[0143] Each blank period VBLANK can be a vertical blank period between the source output periods of the data signal DS for each adjacent output frame.

[0144] The blank period VBLANK may include a period for providing the vertical synchronization signal Vsync, and also includes predetermined periods before / after providing the vertical synchronization signal Vsync. In embodiments, for example, the blank period VBLANK may include a front porch period PFP and a rear porch period PBP that are consecutively set between source output periods. In some embodiments, the front porch period PFP may immediately follow the source output period of each frame, and the rear porch period PBP may immediately follow the source output period of subsequent frames. The vertical synchronization signal Vsync may be provided in the rear porch period PBP.

[0145] In an embodiment, the data driver 30 can output a predetermined front porch voltage VFP during the front porch period (PFP) and a predetermined rear porch voltage VBP during the rear porch period (PBP). The front porch voltage VFP and the rear porch voltage VBP can correspond to grayscale voltages, but the invention is not limited thereto.

[0146] In this embodiment, the frequency control signal FCON can be provided to the clock signal generator 160 during the front porch period (PFP). Therefore, the clock signal generator 160 can change the frequency of the clock signal CLK during the front porch period (PFP). However, this is merely illustrative, and the period during which the frequency control signal FCON is provided is not limited to this.

[0147] In an embodiment, for example, the frequency control signal FCON can be provided throughout the front porch period (PFP) and the rear porch period (PBP). That is, the frequency of the clock signal CLK can be changed during the idle period (VBLANK).

[0148] In an embodiment, such as Figure 8 As shown, a vertical synchronization signal Vsync can be provided for each frame 1F, and a frequency control signal FCON can be provided at three-frame intervals. Therefore, the frequency of the clock signal CLK can be changed at three-frame intervals. Furthermore, the frequency control signal FCON can be provided to overlap with at least a portion of the vertical synchronization signal Vsync.

[0149] As mentioned above, the period of the clock signal CLK can be changed according to different conditions.

[0150] Figure 9 It is shown Figure 2 A block diagram of an embodiment of the display driver circuit shown.

[0151] exist Figure 9 In, and reference Figure 3 Components described identically are designated by the same reference numerals, and repeated descriptions of them will be omitted. Except for the arrangement of the second calculator 1246 and the multiplier 1244, Figure 9 The display driver circuit 100A shown can be used with Figure 3 The display driver circuit 100 shown is the same as or similar to that shown.

[0152] refer to Figure 9 The display driving circuit 100A may include a frequency change determiner 120A, a frequency controller 140, a clock signal generator 160, and a frequency compensation controller 180.

[0153] The frequency change determiner 120A may include a first frequency calculator 122, a second frequency calculator 124A, and a determiner 126.

[0154] In an embodiment, the second frequency calculator 124A may include a second counter 1242, a multiplier 1244, and a second calculator 1246. Figure 3 Unlike the embodiment shown, the second count value CT2 output from the second counter 1242 can be provided to the second calculator 1246.

[0155] The second calculator 1246 can accumulate and calculate the second count value CT2, and output the accumulated and calculated second count value CT2. The output CV' of the second calculator 1246 can be provided to the multiplier 1244.

[0156] Multiplier 1244 can generate a second result RV2 by multiplying the output CV' of the second calculator 1246 by the frequency coefficient N. The second result RV2 can be substantially equal to the reference. Figure 3 The second result described is RV2.

[0157] Based on the difference between the first result RV1 and the second result RV2, the determiner 126 can determine the frequency change FCA.

[0158] Figure 10 This is a flowchart illustrating a method for driving a display device according to the present invention.

[0159] refer to Figure 10 The method may include calculating a first number of clocks corresponding to the current frequency of the clock signal by counting the pulses of the clock signal during the counting enable period (S100), and calculating a second number of clocks corresponding to the target frequency of the clock signal by counting the pulses of the reference clock signal during the counting enable period (S200).

[0160] In addition, the method may include calculating a frequency deviation corresponding to the difference between the first clock quantity and the second clock quantity, and comparing the frequency deviation with at least one of the reference deviations corresponding to a predetermined number of reference clocks (S300).

[0161] Based on the comparison results, the frequency change of the clock signal can be determined (S400). In the method, based on the frequency change, the frequency of the clock signal can be updated during the blank period of a predetermined frame (S500), and the clock signal can be output at the corresponding frequency. As the frequency deviation increases, the updated frequency change can become larger.

[0162] Already referenced Figures 1 to 9 The methods of operating S100 to S500 are described in detail, and therefore, any repeated explanations of the above-mentioned elements will be omitted.

[0163] In the display driving circuit, display device, and method for driving the display device according to the present invention, frequency changes can be adaptively adjusted according to the deviation between the current clock frequency and the target frequency. Therefore, the time (e.g., tracking time) required to adjust the clock frequency to the target frequency level during image display (i.e., in display mode) can be significantly reduced. Consequently, screen anomalies (brightness variations, crosstalk, flicker, etc.) caused by clock frequency changes during image display can be reduced and / or minimized.

[0164] Embodiments have been disclosed herein, and although predetermined terminology has been used, they are used and interpreted in a general and descriptive sense only and are not intended to be limiting. In some instances, as will be apparent to those skilled in the art upon filing this application, features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless expressly indicated otherwise. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the foregoing claims.

Claims

1. A display driving circuit, wherein, The display driving circuit includes: A clock signal generator that generates a clock signal at a frequency in response to a frequency control signal; A frequency change determiner, based on the magnitude of the deviation between the frequency of the clock signal and a target frequency calculated based on an externally provided reference clock signal, adaptively changes the frequency variation of the clock signal; and A frequency controller, based on the frequency change, generates a frequency control signal, which updates the frequency of the clock signal, and provides the frequency control signal to the clock signal generator. The frequency change determiner includes: The determiner determines the frequency change based on a result obtained by comparing a frequency deviation, which is the deviation between the current frequency and the target frequency, with at least one of a predetermined reference deviation.

2. The display driving circuit according to claim 1, wherein, The frequency change determiner also includes: A first frequency calculator calculates the current frequency of the clock signal based on values ​​obtained by counting pulses of the clock signal during a counting-enabled period; and A second frequency calculator calculates the target frequency of the clock signal based on a value obtained by counting pulses of the reference clock signal during the counting enabled period.

3. The display driving circuit according to claim 2, wherein, The first frequency change determined when the frequency deviation is equal to or less than the first reference deviation is less than the second frequency change determined when the frequency deviation is greater than the first reference deviation and equal to or less than the second reference deviation.

4. The display driving circuit according to claim 2, wherein, In image display mode, the clock signal generator changes the frequency of the clock signal at predetermined frame intervals to approach the target frequency; as well as The frequency of the clock signal gradually decreases as frames pass until the frequency of the clock signal reaches the target frequency.

5. The display driving circuit according to claim 2, wherein, The first frequency calculator includes: A first counter, which counts the pulses of the clock signal during the counting enable period; and A first calculator calculates the sum of values ​​provided from the first counter during the counting activation period as a first result corresponding to the current frequency.

6. The display driving circuit according to claim 5, wherein, The second frequency calculator includes: A second counter counts the pulses of the reference clock signal during the counting enable period; A multiplier that multiplies the value provided by the second counter by the ratio of the reference frequency to the target frequency; and A second calculator calculates the sum of the results calculated by the multiplier as a second result corresponding to the target frequency; and The determiner compares the difference between the first result and the second result with at least one of the reference deviations.

7. The display driving circuit according to claim 5, wherein, The second frequency calculator includes: A second counter counts the pulses of the reference clock signal during the counting enable period; A second calculator calculates the sum of values ​​provided from the second counter during the counting activation period; and A multiplier that multiplies the value provided by the second calculator by the ratio of the reference frequency to the target frequency to generate a second result corresponding to the target frequency.

8. The display driving circuit according to claim 2, wherein, The frequency controller provides the frequency control signal to the clock signal generator during a predetermined blank period of the frame.

9. The display driving circuit according to claim 2, further comprising: A frequency compensation controller, based on a control signal provided from the external source and the target frequency, controls the timing of the first frequency calculator and the second frequency calculator, and outputs the frequency control signal.

10. A display device, wherein, The display device includes: The pixel portion includes pixels for displaying an image; and The display driving circuit provides a data signal corresponding to the image to the pixel portion and outputs a clock signal, the clock signal controlling the output timing of the data signal, and the display driving circuit is a display driving circuit according to any one of claims 1 to 9.

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