Display device

Abstract

A display device is provided. The display device includes a plurality of scan lines and a plurality of subpixels, each of the subpixels including a drive transistor, a plurality of transistors each connected to at least one of the plurality of scan lines, and a light emitting element electrically connected to the drive transistor. Each of the subpixels includes an active layer including a channel region of each of the plurality of transistors, a first electrode, and a second electrode. A first scan line of the plurality of scan lines includes a first extension portion extending in a first direction and a first protrusion portion extending in a second direction intersecting the first direction. In a plan view, the active layer overlaps the first protrusion portion.

Description

Technical Field

[0001] This disclosure relates to display devices. Background Technology

[0002] With the development of an information-oriented society, the demand for display devices for displaying images is constantly increasing. For example, display devices are being used in various electronic devices such as smartphones, digital cameras, laptops, navigation devices, and smart TVs. Display devices can be flat panel displays such as liquid crystal displays, field emission displays, and organic light-emitting diode displays.

[0003] Organic light-emitting display devices include light-emitting elements, enabling each pixel in the display panel to emit its own light. Therefore, organic light-emitting display devices can display images without a backlight unit supplying light to the display panel. An organic light-emitting display device may include multiple pixels. Each of the multiple pixels may include a light-emitting element, a drive transistor for controlling the amount of drive current supplied from a power source to the light-emitting element based on a voltage at a gate electrode, and multiple switching transistors that perform switching in response to a scan signal from a scan line. In each of the multiple pixels, the active layer of the drive transistor and the multiple switching transistors may be formed in an island pattern. In this case, a path for discharging static electricity on the active layer cannot be formed. Therefore, when static electricity is applied to the active layer during the manufacturing process, the active layer may be electrostatically burned and damaged. Summary of the Invention

[0004] The present disclosure provides various aspects of a display device capable of preventing damage to the active layer from electrostatic discharge.

[0005] It should be noted that the aspects of this disclosure are not limited to those described above, and other aspects of this disclosure will be apparent to those skilled in the art from the following description.

[0006] According to embodiments of this disclosure, a display device includes: a plurality of scan lines extending in a first direction; a plurality of data lines extending in a second direction intersecting the first direction, wherein a data voltage is applied via the data lines; a first initialization voltage line from which a first initialization voltage is applied; a second initialization voltage line from which a second initialization voltage is applied; and a plurality of sub-pixels, wherein each of the sub-pixels is connected to at least one of the first initialization voltage line, the second initialization voltage line, the plurality of scan lines, and at least one of the plurality of data lines. Each of the sub-pixels includes: a driving transistor that controls a driving current flowing from a first electrode of the driving transistor to a second electrode of the driving transistor according to a data voltage applied to a gate electrode of the driving transistor; a light-emitting element electrically connected to the second electrode of the driving transistor; a first transistor including a first electrode connected to the second initialization voltage line; and a second transistor and a third transistor arranged in series between the first initialization voltage line and the second initialization voltage line. The second electrode of the first transistor of the (i+1)th sub-pixel arranged in the (i+1)th row of the plurality of sub-pixels is connected to the light-emitting element of the i-th sub-pixel arranged in the i-th row of the plurality of sub-pixels, where i is a positive integer. The (i+1)th subpixel and the i-th subpixel are connected to the same data line among multiple data lines.

[0007] The second and third transistors of the i-th sub-pixel can be turned on at different times.

[0008] The gate electrode of the first transistor and the gate electrode of the second transistor of the (i+1)th sub-pixel can be connected to the first scan line of the (i+1)th sub-pixel among multiple scan lines.

[0009] The gate electrode of the third transistor of the i-th sub-pixel can be connected to the second scan line connected to the i-th sub-pixel among multiple scan lines. The scan signal applied to the first scan line connected to the (i+1)-th sub-pixel can be the same as the scan signal applied to the second scan line connected to the i-th sub-pixel.

[0010] The gate electrode of the first transistor and the gate electrode of the third transistor of the i-th sub-pixel can be connected to the second scan line connected to the i-th sub-pixel among multiple scan lines.

[0011] The gate electrode of the second transistor of the i-th sub-pixel can be connected to the first scan line of the i-th sub-pixel among multiple scan lines. The gate electrode of the third transistor of the i-th sub-pixel can be connected to the second scan line of the i-th sub-pixel among multiple scan lines.

[0012] The gate electrode of the first transistor of the i-th sub-pixel can be connected to the third scan line among multiple scan lines connected to the i-th sub-pixel.

[0013] The display device may further include a plurality of emission control lines extending in a first direction and arranged parallel to a plurality of scan lines. Each of the sub-pixels may be connected to at least one of the plurality of emission control lines.

[0014] The gate electrode of the second transistor of the i-th sub-pixel can be connected to the first scan line of the i-th sub-pixel among multiple scan lines. The gate electrode of the third transistor of the i-th sub-pixel can be connected to one of multiple emitt control lines.

[0015] The gate electrode of the second transistor of the i-th sub-pixel can be connected to one of a plurality of emitter control lines. The gate electrode of the third transistor of the i-th sub-pixel can be connected to the first scan line of a plurality of scan lines connected to the i-th sub-pixel.

[0016] The display device may further include a plurality of driving voltage lines extending in a second direction and a plurality of emission control lines extending in a first direction. Each of the sub-pixels may be connected to at least one of the plurality of driving voltage lines and at least one of the plurality of emission control lines. The display device may further include: a fourth transistor disposed between the gate electrode of the driving transistor and a first initialization voltage line; a fifth transistor disposed between one of the plurality of data lines and a first electrode of the driving transistor; a sixth transistor disposed between the gate electrode of the driving transistor and a second electrode of the driving transistor; a seventh transistor disposed between one of the plurality of driving voltage lines and the first electrode of the driving transistor; an eighth transistor disposed between the second electrode of the driving transistor and a first electrode of the light-emitting element; and a capacitor disposed between the one of the plurality of driving voltage lines and the gate electrode of the driving transistor.

[0017] The gate electrodes of the first, second, and fourth transistors of the i-th sub-pixel can be connected to the first scan line connected to the i-th sub-pixel among multiple scan lines. The gate electrodes of the third, fifth, and sixth transistors of the i-th sub-pixel can be connected to the second scan line connected to the i-th sub-pixel among multiple scan lines. The gate electrode of the first transistor of the (i+1)-th sub-pixel can be connected to the third scan line connected to the (i+1)-th sub-pixel among multiple scan lines. The same scan signal can be applied to the second scan line connected to the i-th sub-pixel and the third scan line connected to the (i+1)-th sub-pixel.

[0018] The gate electrodes of the first, third, and fourth transistors of the i-th sub-pixel can be connected to the first scan line connected to the i-th sub-pixel among multiple scan lines. The gate electrodes of the second, fifth, and sixth transistors of the i-th sub-pixel can be connected to the second scan line connected to the i-th sub-pixel among multiple scan lines. The gate electrode of the first transistor of the (i+1)-th sub-pixel can be connected to the third scan line connected to the (i+1)-th sub-pixel among multiple scan lines. The same scan signal can be applied to the second scan line connected to the i-th sub-pixel and the third scan line connected to the (i+1)-th sub-pixel.

[0019] The gate electrodes of the first, second, and fourth transistors of the i-th sub-pixel can be connected to the first scan line connected to the i-th sub-pixel among multiple scan lines. The gate electrodes of the fifth and sixth transistors of the i-th sub-pixel can be connected to the second scan line connected to the i-th sub-pixel among multiple scan lines. The gate electrode of the first transistor of the (i+1)-th sub-pixel can be connected to the third scan line connected to the (i+1)-th sub-pixel among multiple scan lines. The gate electrode of the third transistor of the i-th sub-pixel can be connected to one of multiple emitter control lines. The same scan signal can be applied to the second scan line connected to the i-th sub-pixel and the third scan line connected to the (i+1)-th sub-pixel.

[0020] The gate electrodes of the first and fourth transistors of the i-th sub-pixel can be connected to the first scan line connected to the i-th sub-pixel among multiple scan lines. The gate electrodes of the second, fifth, and sixth transistors of the i-th sub-pixel can be connected to the second scan line connected to the i-th sub-pixel among multiple scan lines. The gate electrode of the first transistor of the (i+1)-th sub-pixel can be connected to the third scan line connected to the (i+1)-th sub-pixel among multiple scan lines. The gate electrode of the third transistor of the i-th sub-pixel is connected to one of multiple emitter control lines. The same scan signal can be applied to the second scan line connected to the i-th sub-pixel and the third scan line connected to the (i+1)-th sub-pixel.

[0021] The gate electrodes of the first, third, and fourth transistors of the i-th sub-pixel can be connected to the first scan line connected to the i-th sub-pixel among multiple scan lines. The gate electrodes of the fifth and sixth transistors of the i-th sub-pixel can be connected to the second scan line connected to the i-th sub-pixel among multiple scan lines. The gate electrode of the first transistor of the (i+1)-th sub-pixel can be connected to the third scan line connected to the (i+1)-th sub-pixel among multiple scan lines. The gate electrode of the second transistor of the i-th sub-pixel can be connected to one of multiple emitter control lines. The same scan signal can be applied to the second scan line connected to the i-th sub-pixel and the third scan line connected to the (i+1)-th sub-pixel.

[0022] The gate electrodes of the first and fourth transistors of the i-th sub-pixel can be connected to the first scan line connected to the i-th sub-pixel among multiple scan lines. The gate electrodes of the third, fifth, and sixth transistors of the i-th sub-pixel can be connected to the second scan line connected to the i-th sub-pixel among multiple scan lines. The gate electrode of the first transistor of the (i+1)-th sub-pixel can be connected to the third scan line connected to the (i+1)-th sub-pixel among multiple scan lines. The gate electrode of the second transistor of the i-th sub-pixel can be connected to one of multiple emitter control lines. The same scan signal can be applied to the second scan line connected to the i-th sub-pixel and the third scan line connected to the (i+1)-th sub-pixel.

[0023] According to embodiments of this disclosure, a display device includes a first initialization voltage line from which a first initialization voltage is applied, a second initialization voltage line from which a second initialization voltage is applied, and a plurality of sub-pixels, wherein each of the sub-pixels is connected to the first initialization voltage line and the second initialization voltage line. Each of the sub-pixels includes: a driving transistor, which controls a driving current flowing from the first electrode of the driving transistor to the second electrode of the driving transistor according to a data voltage applied to the gate electrode of the driving transistor; a light-emitting element electrically connected to the second electrode of the driving transistor; a first transistor, including a first electrode connected to the second initialization voltage line; a second transistor and a third transistor, arranged in series between the first initialization voltage line and the second initialization voltage line; and a fourth transistor, disposed between the gate electrode of the driving transistor and the first initialization voltage line. The second electrode of the first transistor of the (i+1)th sub-pixel arranged in the (i+1)th row of the plurality of sub-pixels is connected to the light-emitting element of the i-th sub-pixel arranged in the i-th row of the plurality of sub-pixels, where i is a positive integer. At least one of the second transistor and the third transistor is turned off in each of the first time period, the second time period, and the third time period, wherein a first initialization voltage is applied to the gate electrode of the driving transistor during the first time period, a data voltage is applied to the gate electrode of the driving transistor during the second time period, and the light-emitting element emits light during the third time period.

[0024] The second and fourth transistors of the i-th sub-pixel can be turned on during the first time period. The first transistor of the (i+1)-th sub-pixel can be turned on during the second time period. The third transistor of the i-th sub-pixel can be turned on during one of the second and third time periods.

[0025] The fourth transistor of the i-th sub-pixel can be turned on during the first time period. The second transistor of the i-th sub-pixel and the first transistor of the (i+1)-th sub-pixel can be turned on during the second time period. The third transistor of the i-th sub-pixel can be turned on during one of the first and third time periods.

[0026] The fourth transistor of the i-th sub-pixel can be turned on during the first time period. The first transistor of the (i+1)-th sub-pixel can be turned on during the second time period. The second transistor of the i-th sub-pixel can be turned on during the third time period. The third transistor of the i-th sub-pixel can be turned on during one of the first and second time periods.

[0027] According to embodiments of this disclosure, a display device includes a plurality of scan lines and a plurality of sub-pixels. Each sub-pixel includes a driving transistor, a plurality of transistors each connected to at least one of the plurality of scan lines, and a light-emitting element electrically connected to the driving transistor. Each sub-pixel includes an active layer, which includes a channel region of each of the plurality of transistors, a first electrode, and a second electrode. A first scan line among the plurality of scan lines includes a first extension extending in a first direction and a first protrusion extending in a second direction intersecting the first direction. In a plan view, the active layer overlaps with the first protrusion.

[0028] The second scan line among multiple scan lines may include a second extension extending in the first direction and a second protrusion extending in the second direction. In a plan view, the active layer overlaps with the second protrusion.

[0029] The active layer of the i-th sub-pixel among multiple sub-pixels can be integrated with the active layer of the (i+1)-th sub-pixel adjacent to the i-th sub-pixel in the second direction, where i is a positive integer.

[0030] The first length between the first protrusion and the second extension may be different from the second length between the second protrusion and the first extension.

[0031] The display device may further include a first initialization voltage line from which a first initialization voltage is applied and a second initialization voltage line from which a second initialization voltage is applied. The driving transistor may control a drive current flowing from a first electrode of the driving transistor to a second electrode of the driving transistor based on a data voltage applied to the gate electrode of the driving transistor. A plurality of transistors may include a first transistor and a second transistor, the first transistor including a first electrode connected to the second initialization voltage line, and the second transistor disposed between the first transistor and the first initialization voltage line. The area where the active layer and the first protrusion overlap in a plan view may be defined as the channel region of the second transistor.

[0032] The plurality of transistors may also include a third transistor disposed between the second transistor and the first initialization voltage line. In the plan view, the area where the active layer and the second protrusion overlap each other can be defined as the channel region of the third transistor.

[0033] The display device may further include a first initialization voltage connection line connected to the first initialization voltage line and extending in a second direction. In a plan view, the active layer may overlap with the first initialization voltage connection line.

[0034] In the planar diagram, the channel region of the third transistor may overlap with the first initialization voltage connection line.

[0035] According to an exemplary embodiment of this disclosure, in a display device, the active layer of a sub-pixel is connected to the active layers of other sub-pixels. Therefore, when static electricity is applied to the active layer during the manufacturing process, a path for dissipating static electricity can be formed through the active layers of multiple sub-pixels, allowing the static electricity to be released or dispersed. Thus, it is possible to prevent the active layers from being burned or damaged by static electricity during the process.

[0036] Furthermore, by preventing short circuits between the first initialization voltage line where the first initialization voltage is applied and the second initialization voltage line where the second initialization voltage is applied, the first initialization voltage and the second initialization voltage do not affect each other and can be applied uniformly. Attached Figure Description

[0037] The above and other aspects and features of this disclosure will become clearer from a detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

[0038] Figure 1 This is a perspective view showing a display device according to an exemplary embodiment of the present disclosure.

[0039] Figure 2 This is a plan view illustrating a display device according to an exemplary embodiment of the present disclosure.

[0040] Figure 3 This is a block diagram illustrating a display device according to an exemplary embodiment of the present disclosure.

[0041] Figure 4 This is a circuit diagram illustrating a sub-pixel according to an exemplary embodiment of the present disclosure.

[0042] Figure 5 It shows that it is applied to Figure 4 The waveform diagram of the signals of the first scan line, the second scan line, and the i-th emission control line connected to the i-th sub-pixel, and the first scan line connected to the (i+1)-th sub-pixel.

[0043] Figures 6 to 8 It is used to show in Figure 5 A circuit diagram of a method for driving the driving transistor, the second to eighth transistors and the light-emitting element of the i-th sub-pixel and the first transistor of the (i+1)-th sub-pixel during the N-th frame.

[0044] Figure 9 This is a plan view illustrating a sub-pixel according to an exemplary embodiment of the present disclosure.

[0045] Figure 10 It is shown Figure 9 A planar view of the active layer of the sub-pixels.

[0046] Figure 11 It is shown Figure 9A planar view of the first and second metal layers of the sub-pixels.

[0047] Figure 12 It is shown Figure 9 A planar view of the third metal layer of the sub-pixel.

[0048] Figure 13 It is along Figure 9 The cross-sectional view taken from line I-I'.

[0049] Figure 14 It is along Figure 9 The cross-sectional view taken from line II-II'.

[0050] Figure 15 This is a circuit diagram illustrating a sub-pixel according to yet another exemplary embodiment of the present disclosure.

[0051] Figure 16 This is a circuit diagram illustrating a sub-pixel according to yet another exemplary embodiment of the present disclosure.

[0052] Figure 17 This is a circuit diagram illustrating a sub-pixel according to yet another exemplary embodiment of the present disclosure.

[0053] Figure 18 This is a circuit diagram illustrating a sub-pixel according to yet another exemplary embodiment of the present disclosure.

[0054] Figure 19 This is a circuit diagram illustrating a sub-pixel according to yet another exemplary embodiment of the present disclosure.

[0055] Figure 20 This is a circuit diagram illustrating a sub-pixel according to yet another exemplary embodiment of the present disclosure.

[0056] Figure 21 This is a circuit diagram illustrating a sub-pixel according to yet another exemplary embodiment of the present disclosure. Detailed Implementation

[0057] In the following description, numerous details are set forth for purposes of explanation to provide a thorough understanding of various embodiments or implementations of this disclosure. As used herein, “implementation” and “method” are interchangeable terms and are non-limiting examples of apparatus or methods employing one or more of the implementations or methods disclosed herein. However, it will be apparent, however, that various embodiments may be practiced without these details or with one or more equivalent arrangements. In other instances, structures and apparatus may be shown in block diagram form to avoid unnecessarily obscuring various embodiments. Furthermore, various embodiments may be different, but not necessarily exclusive. For example, the shape, configuration, and characteristics of an embodiment may be used or implemented in another embodiment without departing from the scope of this disclosure.

[0058] Unless otherwise stated, the embodiments shown should be understood as providing various detailed features that enable the implementation of some or more ways of this disclosure in practice. Therefore, unless otherwise stated, features, components, modules, layers, films, panels, areas and / or aspects of various embodiments (hereinafter individually or collectively referred to as “elements”) may be combined, separated, interchanged and / or rearranged in other ways without departing from this disclosure.

[0059] Crosshairs and / or shading are typically provided in the accompanying drawings to clarify the boundaries between adjacent elements. Thus, unless otherwise stated, the presence or absence of crosshairs or shading does not convey or indicate any preference or requirement for materials, material properties, dimensions, scale, commonalities between illustrated elements, or any other characteristics, properties, performance, etc., of the elements. Additionally, in the drawings, the dimensions and relative dimensions of elements may be exaggerated for clarity and / or descriptive purposes. When embodiments can be implemented differently, the process sequence may be performed differently than the sequence described. For example, two consecutively described processes may be performed substantially simultaneously or in the reverse order of their description. Furthermore, the same reference numerals denote the same elements.

[0060] When an element, such as a layer, is referred to as being "on," "connected to," or "attached to" another element or layer, it may be directly on, directly connected to, or directly attached to the other element or layer, or an intermediary element or layer may be present. However, when an element or layer is referred to as being "directly" on, "directly connected to," or "directly attached to" another element or layer, no intermediary element or layer is present. Therefore, the term "connection" can indicate a physical, electrical, and / or fluid connection, with or without an intermediary element. Furthermore, the X, Y, and Z axes are not limited to the three axes of a Cartesian coordinate system, such as the x, y, and z axes, and can be interpreted in a broader sense. For example, the X, Y, and Z axes may be substantially perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the cluster consisting of X, Y, and Z” can be interpreted as X only, Y only, Z only, or any combination of two or more of X, Y, and Z, such as, for example, XYZ, XYY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0061] The terms “and” and “or” can be used in the sense of combination or separation and can be understood as equivalent to “and / or”.

[0062] Although the terms “first,” “second,” etc., may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Therefore, without departing from the teachings of this disclosure, the first element discussed below may be referred to as the second element.

[0063] Spatial relative terms, such as “beneath,” “below,” “under,” “lower,” “above,” “upper,” “over,” “higher,” and “side” (e.g., in a “sidewall”), may be used herein for descriptive purposes and to describe the relationship of one element to another(s) as shown in the accompanying drawings. In addition to the orientations depicted in the drawings, spatial relative terms are also intended to cover different orientations of the device in use, operation, and / or manufacture. For example, if the device in the drawings is flipped, an element described as “below” or “under” other elements or features will subsequently be oriented “above” other elements or features. Thus, the term “below” can encompass both above and below orientations. Furthermore, the device may be oriented in other ways (e.g., rotated 90 degrees or about 90 degrees or in other orientations), and thus, the spatial relative descriptive terms used herein are interpreted accordingly.

[0064] The terms “overlap” or “overlapped” mean that the first object may be located above or below the second object or to the side of the second object, and vice versa. Additionally, the term “overlap” may include stacking, overlapping, facing or facing each other, extending over, covering or partially covering, or any other suitable term that will be understood and appreciated by one of ordinary skill in the art.

[0065] When an element is described as “not overlapping” or “will not overlap” with another element, this may include elements spaced apart from each other, offset from each other, or separated from each other, or any other suitable terminology as will be understood and appreciated by one of ordinary skill in the art.

[0066] The terms "facing" and "facing each other" mean that the first element can be directly or indirectly opposite the second element. In the case where the third element is between the first and second elements, although they are still facing each other, the first and second elements can be understood as being indirectly opposite each other.

[0067] The use of "as" as used herein is for the purpose of describing embodiments and is not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms "a," "an," and "the" as used herein are intended to include the plural forms as well. Furthermore, the terms "comprises," "comprising," "includes," and / or "including," "has," and / or "having," and variations thereof, when used in this specification, indicate the presence of stated features, integers, steps, operations, elements, components, and / or clusters thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or clusters thereof. It should also be noted that, as used herein, the terms "substantially," "about," and other similar terms are used as terms of approximation rather than terms of degree, and are thus used to explain the inherent biases in measured, calculated, and / or provided values ​​that would be recognized by those skilled in the art.

[0068] For example, taking into account the errors associated with the measurement and a particular number of measurements (i.e., limitations of the measurement system), the terms "about" or "approximately" as used herein include the value and mean within an acceptable range of deviation for a particular value as determined by one of ordinary skill in the art. For example, "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the value.

[0069] Various embodiments are described herein with reference to sectional and / or exploded views, which serve as schematic illustrations of implementations and / or intermediate structures. Therefore, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are expected. Consequently, the embodiments disclosed herein should not necessarily be interpreted as limited to the shapes of the areas shown, but rather include deviations in shape due to, for example, manufacturing processes. In this way, the areas shown in the figures may be schematic in nature, and the shapes of these areas may not reflect the actual shapes of the areas of the device, and are therefore not necessarily intended to be limiting.

[0070] Descriptions of functional blocks, units, and / or modules are presented and illustrated in the accompanying drawings. Those skilled in the art will understand that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuitry such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wiring connections, etc., which can be formed using semiconductor-based fabrication techniques or other manufacturing techniques. Where blocks, units, and / or modules are implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and optionally, they can be driven by firmware and / or software. Furthermore, it is contemplated that each block, unit, and / or module can be implemented by dedicated hardware, or as a combination of dedicated hardware performing some or more functions and processors performing other functions (e.g., one or more programmed microprocessors and associated circuitry). Additionally, each block, unit, and / or module of some or more embodiments can be physically separated into two or more interactive and discrete blocks, units, and / or modules without departing from the scope of this disclosure. Furthermore, some or more implementations of blocks, units and / or modules can be physically combined into more complex blocks, units and / or modules without departing from the scope of this disclosure.

[0071] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms, such as those defined in common dictionaries, shall be interpreted as having the same meaning as they have in the context of the relevant field, and shall not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0072] Figure 1 This is a perspective view showing a display device according to an exemplary embodiment of the present disclosure. Figure 2 This is a plan view illustrating a display device according to an exemplary embodiment of the present disclosure. Figure 3 This is a block diagram illustrating a display device according to an exemplary embodiment of the present disclosure.

[0073] As used herein, the terms “above,” “top,” and “upper surface” refer to the upper side of the display panel 100, i.e., the side opposite to the arrow in the Z-axis direction, while the terms “below,” “bottom,” and “lower surface” refer to the lower side of the display panel 100, i.e., one side in the Z-axis direction. As used herein, the terms “left,” “right,” “upper,” and “lower” refer to the relative positions when the display panel 100 is viewed from above. For example, “left side” refers to the side opposite to the arrow in the X-axis direction, “right side” refers to the side indicated by the arrow in the X-axis direction, “upper side” refers to the side indicated by the arrow in the Y-axis direction, and “lower side” refers to the side opposite to the arrow in the Y-axis direction.

[0074] Reference Figures 1 to 3 The display device 10 is used to display moving or still images. The display device 10 can be used as a display screen for portable electronic devices such as mobile phones, smartphones, tablet PCs, smartwatches, watch phones, mobile communication terminals, e-notebooks, e-book readers, portable multimedia players (“PMPs”), navigation devices, and ultra-mobile PCs (“UMPCs”), as well as for various products such as televisions, laptops, monitors, billboards, and Internet of Things (IoT) devices.

[0075] Display device 10 may be a light-emitting display device, such as an organic light-emitting display device using organic light-emitting diodes, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including inorganic semiconductors, and a micro light-emitting display device using micro light-emitting diodes (“LEDs”). In the following description, organic light-emitting display devices are described as examples of display device 10. However, it should be understood that this disclosure is not limited thereto.

[0076] The display device 10 includes a display panel 100, a display driving circuit 200, and a circuit board 300.

[0077] The display panel 100 may be formed as a rectangular plane having a shorter side in a first direction (X-axis direction) and a longer side in a second direction (Y-axis direction) intersecting the first direction (X-axis direction). Each of the corners where the shorter side in the first direction (X-axis direction) intersects the longer side in the second direction (Y-axis direction) may be rounded with a predetermined curvature or may be a right angle. When viewed from above, the shape of the display panel 100 is not limited to a quadrilateral shape, but may be formed as various polygonal shapes, circular shapes, or elliptical shapes. The display panel 100 may be, but is not limited to, formed as a flat surface. The display panel 100 may include bent portions formed at its left and right ends and having constant or varying curvatures. Furthermore, the display panel 100 may be formed as flexible, such that it can be bent, folded, or rolled.

[0078] The display panel 100 may include a display area DA with sub-pixels SP for displaying images and a non-display area NDA serving as the peripheral area of ​​the display area DA. In the display area DA, in addition to the sub-pixels SP, scan lines SL, emission control lines EL, data lines DL, and a first driving voltage line VDDL connected to the sub-pixels SP may be arranged. The scan lines SL and emission control lines EL may extend in a first direction (X-axis direction), while the data line DL may extend in a second direction (Y-axis direction) intersecting the first direction (X-axis direction). The first driving voltage line VDDL may extend parallel to the display area DA in the second direction (Y-axis direction). The first driving voltage line VDDL extending parallel to the display area DA in the second direction (Y-axis direction) may be arranged in the non-display area NDA.

[0079] Each of the sub-pixels SP can be connected to at least one of the scan lines SL, one of the data lines DL, at least one of the transmit control lines EL, and a corresponding first drive voltage line VDDL. Figure 2 In the example shown, each of the sub-pixels SP is connected to two scan lines SL, one data line DL, one transmit control line EL, and a first drive voltage line VDDL. However, it should be understood that this disclosure is not limited thereto. For example, each of the sub-pixels SP may be connected to three scan lines SL instead of two scan lines SL.

[0080] Each of the sub-pixels SP may include a driving transistor, at least one transistor, a light-emitting element, and a capacitor. The transistor may be turned on in response to a scan signal from the scan line SL, such that a data voltage from the data line DL can be applied to the driving transistor DT (see [link to relevant documentation]). Figure 4 The driving transistor DT supplies a driving current to the light-emitting element when a data voltage is applied to the gate electrode. The driving transistor DT and at least one transistor can be thin-film transistors. The light-emitting element emits light according to the driving current from the driving transistor DT. The light-emitting element can be an organic light-emitting diode (OLED) comprising a first electrode, an organic emitting layer, and a second electrode. A capacitor maintains a constant data voltage applied to the gate electrode of the driving transistor DT.

[0081] The non-display area NDA can be defined as the region extending from the outer edge of the display area DA to the edge of the display panel 100. Within the non-display area NDA, a scan drive circuit 400 for applying scan signals to the scan line SL, a fan-out line FL located between the data line DL and the display drive circuit 200, and a pad DP connected to the display drive circuit 200 can be arranged. The display drive circuit 200 and the pad DP can be arranged at the edge of one side of the display panel 100. The pad DP can be arranged closer to the edge of one side of the display panel 100 than the display drive circuit 200.

[0082] The scan drive circuit 400 can be connected to the display drive circuit 200 via multiple scan control lines SCL. The scan drive circuit 400 can receive scan control signals SCS and transmit control signals ECS from the display drive circuit 200 via the scan control lines SCL.

[0083] like Figure 3 As shown, the scan drive circuit 400 may include a scan driver 410 and a transmit control driver 420.

[0084] Scan driver 410 can generate scan signals according to scan control signal SCS, and can output scan signals sequentially to scan line SL. Transmit control driver 420 can generate transmit signals according to transmit control signal ECS, and can output transmit signals sequentially to transmit control line EL.

[0085] The scan driving circuit 400 may include multiple thin-film transistors. The scan driving circuit 400 may be formed in the same layer as the thin-film transistors of the sub-pixel SP. Although in Figure 2 The scanning drive circuit 400 is formed on both sides of the display area DA, i.e., on the right and left sides, within the non-display area NDA, but this disclosure is not limited thereto. For example, the scanning drive circuit 400 may be formed on one side of the display area DA, such as on the left side, within the non-display area NDA.

[0086] like Figure 3 As shown, the display driving circuit 200 may include a timing controller 210, a data driver 220, and a power supply circuit 230.

[0087] The timing controller 210 receives digital video data DATA and timing signals from the circuit board 300. Based on the timing signals, the timing controller 210 generates a scan control signal SCS for controlling the operating timing of the scan driver 410, a transmit control signal ECS for controlling the operating timing of the transmit control driver 420, and a data control signal DCS for controlling the operating timing of the data driver 220. The timing controller 210 outputs the scan control signal SCS to the scan driver 410 and the transmit control signal ECS to the transmit control driver 420 via the scan control line SCL. The timing controller 210 can also output digital video data DATA and the data control signal DCS to the data driver 220.

[0088] Data driver 220 converts digital video data DATA into analog positive / negative data voltages and supplies them to data line DL via fan-out line FL. Subpixels SP are selected by scan signals from scan drive circuit 400, and data voltages are supplied to the selected subpixels SP.

[0089] The power supply circuit 230 can generate a first driving voltage to supply to the first driving voltage line VDDL. Furthermore, the power supply circuit 230 can generate a second driving voltage to supply to the cathode of the organic light-emitting diode (OLED) in each of the sub-pixels SP. The first driving voltage can be a high-level voltage for driving the OLED, and the second driving voltage can be a low-level voltage for driving the OLED. That is, the first driving voltage can have a higher level than the second driving voltage.

[0090] The display driving circuit 200 may be implemented as an integrated circuit (“IC”) and may be attached to the display panel 100 via chip-on-glass (“COG”) technology, chip-on-plastic (“COP”) technology, or ultrasonic bonding. However, it should be understood that this disclosure is not limited thereto. For example, the display driving circuit 200 may be attached to a circuit board 300.

[0091] The circuit board 300 can be attached to the pad DP using an anisotropic conductive film. In this way, the leads of the circuit board 300 can be electrically connected to the pad DP. The circuit board 300 can be a flexible printed circuit board, a printed circuit board, or a flexible film (such as a flip-chip film).

[0092] Figure 4 This is a circuit diagram illustrating a sub-pixel according to an exemplary embodiment of the present disclosure. Figure 4 In the diagram, for ease of illustration, sub-pixels SP are defined by dashed lines.

[0093] Each of the sub-pixels SP can be connected to a first scan line, a second scan line, an emission control line EL, and a data line DL. The scan signal applied to the first scan line of the sub-pixel SPi in the i-th row can be the same as the scan signal applied to the second scan line of the sub-pixel SP(i-1) (not shown) in the previous row.

[0094] exist Figure 4 In this context, the i-th sub-pixel SPi refers to the sub-pixel SP arranged in the i-th row, and the (i+1)-th sub-pixel SP(i+1) refers to the sub-pixel SP arranged in the (i+1)-th row. The i-th sub-pixel SPi and the (i+1)-th sub-pixel SP(i+1) can be arranged in the second direction (Y-axis direction).

[0095] For example, refer to Figure 4 Subpixels SPi and SP(i+1), where i is an integer greater than or equal to 2, the scan signal applied to the first scan line GI(i+1) of the (i+1)th subpixel SP(i+1) can be substantially the same as the scan signal applied to the second scan line GWi of the ith subpixel SPi.

[0096] Furthermore, each of the sub-pixels SP can be connected to the first driving voltage line VDDL, which supplies the first driving voltage, and the first initialization voltage Vint1, which supplies the first initialization voltage (see [link]). Figure 6 The first initialization voltage line VIL1 supplies the second initialization voltage Vint2 (see...). Figure 7 The second initialization voltage line VIL2 and the second drive voltage line VSSL that supplies the second drive voltage.

[0097] Each of the sub-pixels SP includes a driving transistor DT, a light-emitting element LE, a switching element, and a capacitor C1. The switching element may include a first transistor ST1, a second transistor ST2, a third transistor ST3, a fourth transistor ST4, a fifth transistor ST5, a sixth transistor ST6, a seventh transistor ST7, and an eighth transistor ST8.

[0098] According to an exemplary embodiment of this disclosure, the first transistor ST1 of a sub-pixel SP can initialize the light-emitting element LE of the sub-pixel SP arranged in the preceding row. For example, the first transistor ST1 of the (i+1)th sub-pixel SP(i+1) can be connected to the light-emitting element LE of the i-th sub-pixel SPi. Therefore, in order to initialize the light-emitting element LE of the i-th sub-pixel SPi, the first transistor ST1 of the (i+1)th sub-pixel SP(i+1) should be turned on. In addition, when the first transistor ST1 of the i-th sub-pixel SPi is connected to the second initialization voltage line VIL2 of the i-th sub-pixel SPi and the light-emitting element LE of the (i-1)th sub-pixel SP(i-1), the first transistor ST1 of the i-th sub-pixel SPi should be turned on to initialize the light-emitting element LE of the (i-1)th sub-pixel SP(i-1).

[0099] In other words, to initialize the light-emitting element LE of the i-th sub-pixel SPi, the first transistor ST1 of the (i+1)-th sub-pixel SP(i+1) needs to be turned on. For this purpose, refer to the following... Figures 4 to 8 In the description of driving the i-th sub-pixel SPi, the first transistor ST1 refers to the first transistor ST1 of the (i+1)-th sub-pixel SP(i+1), and the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6, the seventh transistor ST7, and the eighth transistor ST8, as well as the light-emitting element LE, refer to the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6, the seventh transistor ST7, and the eighth transistor ST8, as well as the light-emitting element LE of the i-th sub-pixel SPi, unless otherwise specified.

[0100] The driving transistor DT may include a gate electrode DT_G, a first electrode DT_S, and a second electrode DT_D (see [reference]). Figure 9The gate electrode DT_G is the gate electrode disposed above the active layer of the driving transistor DT.

[0101] The drain-source current Isd (hereinafter referred to as the "drive current") of the drive transistor DT is controlled based on the data voltage applied to the gate electrode DT_G. The drive current Isd flowing through the channel of the drive transistor DT is proportional to the square of the difference between the absolute values ​​of the source-gate voltage Vsg and the threshold voltage Vth of the drive transistor DT, as shown in Equation 1 below:

[0102] [Equation 1]

[0103] Isd = k′ × (Vsg - |Vth|) 2

[0104] Where k' represents the scaling factor determined by the structure and physical properties of the driving transistor DT, Vsg represents the source-gate voltage of the driving transistor DT, and Vth represents the threshold voltage of the driving transistor DT.

[0105] The light-emitting element LE emits light as a driving current Isd flows through it. The amount of light emitted from the light-emitting element LE is proportional to the driving current Isd.

[0106] The light-emitting element LE can be an organic light-emitting diode (OLED) comprising an anode, a cathode, and an organic emitting layer disposed between the anode and the cathode. Alternatively, the light-emitting element LE can be an inorganic light-emitting element comprising an anode, a cathode, and an inorganic semiconductor disposed between the anode and the cathode. Alternatively, the light-emitting element LE can be a quantum dot light-emitting element comprising an anode, a cathode, and a quantum dot emitting layer disposed between the anode and the cathode. Alternatively, the light-emitting element LE can be a micro light-emitting diode (microLED).

[0107] The anode of the light-emitting element LE can be connected to the second electrode of the first transistor ST1 and the first electrode of the eighth transistor ST8, while the cathode of the light-emitting element LE can be connected to the second driving voltage line VSSL. A parasitic capacitance Cel can be formed between the anode and cathode of the light-emitting element LE.

[0108] A first transistor ST1 may be disposed between the light-emitting element LE of the i-th sub-pixel SPi and the second initialization voltage line VIL2 connected to the (i+1)-th sub-pixel SP(i+1). The first transistor ST1 is turned on by a scan signal from a first scan line GI(i+1) connected to the (i+1)-th sub-pixel SP(i+1), thereby connecting the anode of the light-emitting element LE of the i-th sub-pixel SPi to the second initialization voltage line VIL2 connected to the (i+1)-th sub-pixel SP(i+1). The anode of the light-emitting element LE of the i-th sub-pixel SPi may discharge to the second initialization voltage Vint2. The gate electrode of the first transistor ST1 may be connected to the first scan line GI(i+1) connected to the (i+1)-th sub-pixel SP(i+1), the first electrode of the first transistor ST1 may be connected to the second initialization voltage line VIL2 connected to the (i+1)-th sub-pixel SP(i+1), and the second electrode of the first transistor ST1 may be connected to the anode of the light-emitting element LE of the i-th sub-pixel SPi.

[0109] In this case, the scan signal applied to the first scan line GI(i+1) connected to the (i+1)th sub-pixel SP(i+1) can be substantially the same as the scan signal applied to the second scan line GWi connected to the i-th sub-pixel SPi.

[0110] The second transistor ST2 can be turned on by the scan signal of the first scan line GIi. The second transistor ST2 can be arranged between the second initialization voltage line VIL2 and the third transistor ST3. The gate electrode of the second transistor ST2 can be connected to the first scan line GIi, the first electrode of the second transistor ST2 can be connected to the second electrode of the third transistor ST3, and the second electrode of the second transistor ST2 can be connected to the second initialization voltage line VIL2.

[0111] The third transistor ST3 can be disposed between the first initialization voltage line VIL1 and the second transistor ST2. The third transistor ST3 can be turned on by the scan signal of the second scan line GWi. The gate electrode of the third transistor ST3 can be connected to the second scan line GWi, the first electrode of the third transistor ST3 can be connected to the first initialization voltage line VIL1, and the second electrode of the third transistor ST3 can be connected to the first electrode of the second transistor ST2.

[0112] If both the second transistor ST2 and the third transistor ST3 are turned on, there may be a problem where the first initialization voltage line VIL1 is connected to the second initialization voltage line VIL2. Therefore, in an embodiment of the present invention, by alternately applying the turn-on scan signal to the second transistor ST2 and the third transistor ST3, the problem of the second transistor ST2 and the third transistor ST3 being turned on simultaneously can be eliminated. For example, when the second transistor ST2 is turned on by the scan signal of the first scan line GIi, the third transistor ST3 can be turned off by the scan signal of the second scan line GWi (see...). Figure 5 In the first time period t1). When the third transistor ST3 is turned on by the scan signal of the second scan line GWi, the second transistor ST2 can be turned off by the scan signal of the first scan line GIi (see the first time period t1). Figure 5 (The second time period t2). When the second transistor ST2 is turned off by the scan signal of the first scan line GIi, the third transistor ST3 can be turned off by the scan signal of the second scan line GWi (see the second time period t2). Figure 5 (The third time period t3 in the process). Therefore, through the embodiments of the present invention, the first initialization voltage line VIL1 and the second initialization voltage line VIL2 can be electrically separated from each other.

[0113] A fourth transistor ST4 may be disposed between the first initialization voltage line VIL1 and the gate electrode of the driving transistor DT. The fourth transistor ST4 may be implemented as a dual transistor comprising transistor (4-1) ST4-1 and transistor (4-2) ST4-2. Transistors (4-1) ST4-1 and (4-2) ST4-2 are turned on by a scan signal from the first scan line GIi to connect the gate electrode of the driving transistor DT to the first initialization voltage line VIL1. The gate electrode of the driving transistor DT may discharge to the first initialization voltage Vint1 of the first initialization voltage line VIL1. The gate electrode of transistor (4-1) ST4-1 may be connected to the first scan line GIi, and the first electrode of transistor (4-1) ST4-1 may be connected to the second electrode of transistor (4-2) ST4-2. The second electrode of transistor (4-1) ST4-1 may be connected to the gate electrode of the driving transistor DT. (4-2) The gate electrode of transistor ST4-2 can be connected to the first scan line GIi, (4-2) the first electrode of transistor ST4-2 can be connected to the first initialization voltage line VIL1, and (4-2) the second electrode of transistor ST4-2 can be connected to the first electrode of transistor ST4-1 (4-1).

[0114] A fifth transistor ST5 can be disposed between the j-th data line Dj and the first electrode of the driving transistor DT. Here, j is a positive integer. The fifth transistor ST5 is turned on by the scan signal of the second scan line GWi to connect the first electrode of the driving transistor DT and the j-th data line Dj. The gate electrode of the fifth transistor ST5 can be connected to the second scan line GWi, the first electrode of the fifth transistor ST5 can be connected to the j-th data line Dj, and the second electrode of the fifth transistor ST5 can be connected to the first electrode of the driving transistor DT.

[0115] A sixth transistor ST6 can be disposed between the gate electrode of the driving transistor DT and the second electrode of the driving transistor DT. The sixth transistor ST6 can be implemented as a dual transistor comprising transistor (6-1) ST6-1 and transistor (6-2) ST6-2. Transistors (6-1) ST6-1 and (6-2) ST6-2 are turned on by a scan signal from the second scan line GWi to connect the gate electrode of the driving transistor DT to the second electrode of the driving transistor DT. That is, when transistors (6-1) ST6-1 and (6-2) ST6-2 are turned on, the gate electrode and the second electrode of the driving transistor DT are connected, and therefore the driving transistor DT can operate like a diode. The gate electrode of transistor (6-1) ST6-1 can be connected to the second scan line GWi, the first electrode of transistor (6-1) ST6-1 can be connected to the second electrode of transistor (6-2) ST6-2, and the second electrode of transistor (6-1) ST6-1 can be connected to the gate electrode of the driving transistor DT. (6-2) The gate electrode of transistor ST6-2 can be connected to the second scan line GWi, (6-2) The first electrode of transistor ST6-2 can be connected to the second electrode of driving transistor DT, and (6-2) The second electrode of transistor ST6-2 can be connected to the first electrode of transistor ST6-1 (6-1).

[0116] A seventh transistor ST7 may be disposed between the first drive voltage line VDDL and the first electrode of the drive transistor DT. The seventh transistor ST7 is turned on by the emitt signal of the i-th emitt control line ELi to connect the first electrode of the drive transistor DT to the first drive voltage line VDDL. The gate electrode of the seventh transistor ST7 is connected to the i-th emitt control line ELi, the second electrode of the seventh transistor ST7 is connected to the first electrode of the drive transistor DT, and the first electrode of the seventh transistor ST7 is connected to the first drive voltage line VDDL.

[0117] The eighth transistor ST8 can be arranged between the second electrode of the driving transistor DT and the anode of the light-emitting element LE. The eighth transistor ST8 is turned on by the emission signal of the i-th emission control line ELi, connecting the second electrode of the driving transistor DT to the anode of the light-emitting element LE. The gate electrode of the eighth transistor ST8 is connected to the i-th emission control line ELi, the first electrode of the eighth transistor ST8 is connected to the second electrode of the driving transistor DT, and the second electrode of the eighth transistor ST8 is connected to the anode of the light-emitting element LE. When both the seventh transistor ST7 and the eighth transistor ST8 are turned on, a drive current Isd can be supplied to the light-emitting element LE.

[0118] A capacitor C1 is formed between the gate electrode of the driving transistor DT and the first driving voltage line VDDL. One electrode of capacitor C1 can be connected to the gate electrode of the driving transistor DT, and the other electrode of capacitor C1 can be connected to the first driving voltage line VDDL. Therefore, capacitor C1 can maintain the potential difference between the gate electrode of the driving transistor DT and the first driving voltage line VDDL.

[0119] When the first electrode of each of the first transistor ST1, second transistor ST2, third transistor ST3, fourth transistor ST4, fifth transistor ST5, sixth transistor ST6, seventh transistor ST7, eighth transistor ST8, and driving transistor DT is a source electrode, its second electrode can be a drain electrode. Alternatively, when the first electrode of each of the first transistor ST1, second transistor ST2, third transistor ST3, fourth transistor ST4, fifth transistor ST5, sixth transistor ST6, seventh transistor ST7, eighth transistor ST8, and driving transistor DT is a drain electrode, its second electrode can be a source electrode.

[0120] The active layer of each of the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6, the seventh transistor ST7, and the eighth transistor ST8, as well as the driving transistor DT, may be made of polycrystalline silicon, amorphous silicon, and oxide semiconductor. When the semiconductor layer of each of the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6, the seventh transistor ST7, and the eighth transistor ST8, as well as the driving transistor DT, is made of polycrystalline silicon, a low-temperature polycrystalline silicon (“LTPS”) process may be used.

[0121] Although the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6, the seventh transistor ST7, the eighth transistor ST8, and the driving transistor DT are p-type metal-oxide-semiconductor field-effect transistors (“MOSFETs”), this is merely illustrative. In another embodiment, at least one of the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6, the seventh transistor ST7, the eighth transistor ST8, and the driving transistor DT may be an n-type MOSFET. When at least one of the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6, the seventh transistor ST7, the eighth transistor ST8, and the driving transistor DT is an n-type MOSFET, appropriate modifications should be made to suit the characteristics of an n-type MOSFET. Figure 5 The timing diagram.

[0122] The first driving voltage from the first driving voltage line VDDL, the second driving voltage from the second driving voltage line VSSL, the first initialization voltage Vint1 from the first initialization voltage line VIL1, and the second initialization voltage Vint2 from the second initialization voltage line VIL2 can be determined based on the characteristics of the driving transistor DT, the characteristics of the light-emitting element LE, etc. For example, the voltage difference between the first initialization voltage Vint1 and the data voltage supplied to the source electrode of the driving transistor DT can be set to be less than the threshold voltage of the driving transistor DT. Furthermore, the magnitude of the second initialization voltage Vint2 can be different from the magnitude of the first initialization voltage Vint1.

[0123] Figure 5 It shows that it is applied to Figure 4 The waveform diagram of the signals connected to the first scan line, the second scan line, and the i-th emission control line of the i-th sub-pixel, and the first scan line connected to the (i+1)-th sub-pixel.

[0124] Reference Figure 5The scan signal applied to the first scan line GIi connected to the i-th sub-pixel SPi is a signal used to turn on and off each of the second transistor ST2 and the fourth transistor ST4. The scan signal applied to the second scan line GWi connected to the i-th sub-pixel SPi is a signal used to turn on and off each of the third transistor ST3, the fifth transistor ST5, and the sixth transistor ST6. The scan signal applied to the first scan line GI(i+1) connected to the (i+1)-th sub-pixel SP(i+1) is a scan signal used to turn on and off the first transistor ST1 of the (i+1)-th sub-pixel SP(i+1). The emission signal applied to the i-th emission control line ELi connected to the i-th sub-pixel SPi is a signal used to control the seventh transistor ST7 and the eighth transistor ST8.

[0125] In each frame, scan signals can be generated and applied to the first scan line GIi and the second scan line GWi connected to the i-th sub-pixel SPi, as well as to the first scan line GI(i+1) connected to the (i+1)-th sub-pixel SP(i+1). In each frame, a transmission signal can be generated and applied to the i-th transmission control line ELi. A frame can be divided into a first time period t1, a second time period t2, and a third time period t3.

[0126] During the first time period t1, the first initialization voltage Vint1 is applied to the gate electrode DT_G of the driving transistor DT, such that the voltage at the gate electrode DT_G of the driving transistor DT is initialized to the first initialization voltage Vint1.

[0127] During the second time period t2, the data voltage Vdata (see...) Figure 7 A threshold voltage Vth of the driving transistor DT is sampled, and a second initialization voltage Vint2 is applied to the anode of the light-emitting element LE, such that the voltage at the anode of the light-emitting element LE is initialized to the second initialization voltage Vint2.

[0128] During the third time period t3, a drive current Isd, which flows according to the voltage at the gate electrode DT_G of the driving transistor DT, is supplied to the light-emitting element LE, causing the light-emitting element LE to emit light.

[0129] The scan signal applied to the first scan line GIi connected to the i-th sub-pixel SPi may have a gate on voltage Von during a first time period t1 and a gate off voltage Voff during other time periods.

[0130] The scan signal applied to the second scan line GWi connected to the i-th sub-pixel SPi may have a gate on voltage Von during the second time period t2 and a gate off voltage Voff during other time periods.

[0131] The transmit signal applied to the i-th transmit control line ELi connected to the i-th sub-pixel SPi may have a gate on voltage Von during the third time period t3 and a gate off voltage Voff during other time periods.

[0132] The scan signal applied to the first scan line GI(i+1) connected to the (i+1)th sub-pixel SP(i+1) may have a gate on voltage Von during the second time period t2 and a gate off voltage Voff during other time periods.

[0133] Despite Figure 5 In the example shown, the scan signal applied to the first scan line GIi connected to the i-th sub-pixel SPi has a gate on-voltage Von for a period shorter than the first time period t1, but this period may be substantially equal to the first time period t1.

[0134] Despite Figure 5 In the example shown, the scan signal applied to each of the second scan line GWi connected to the i-th sub-pixel SPi and the first scan line GI(i+1) connected to the (i+1)-th sub-pixel SP(i+1) has a gate on-voltage Von for a period shorter than the second time period t2, but this period may be substantially equal to the second time period t2.

[0135] Despite Figure 5 In the example shown, the transmit signal applied to the i-th transmit control line ELi connected to the i-th sub-pixel SPi has a gate on-state voltage Von during the third time period t3, but this disclosure is not limited thereto. For example, the third time period t3 may include a plurality of first sub-time periods in which the transmit signal applied to the i-th transmit control line ELi connected to the i-th sub-pixel SPi has a gate on-state voltage Von and a plurality of second sub-time periods in which the transmit signal has a gate off-state voltage Voff. The plurality of first sub-time periods and the plurality of second sub-time periods may alternate with each other.

[0136] exist Figure 5 In the graph shown, each of the first time period t1 and the second time period t2 is a horizontal time period. A horizontal time period refers to the period during which a data voltage is applied to each of the sub-pixels SP connected to a scan line of the display panel 100, and therefore it can be defined as a horizontal line scan period. The data voltage can be applied to the data line DL synchronously with the gate on-state voltage Von of each of the scan signals.

[0137] The gate turn-on voltage Von corresponds to the turn-on voltage that enables each of the following transistors to conduct: first transistor ST1, second transistor ST2, third transistor ST3, fourth transistor ST4, fifth transistor ST5, sixth transistor ST6, seventh transistor ST7, and eighth transistor ST8. The gate turn-off voltage Voff corresponds to the turn-off voltage that enables each of the following transistors to turn off: first transistor ST1, second transistor ST2, third transistor ST3, fourth transistor ST4, fifth transistor ST5, sixth transistor ST6, seventh transistor ST7, and eighth transistor ST8.

[0138] exist Figure 5 In the graph shown, a frame includes a first time period t1, a second time period t2, and a third time period t3. However, it should be understood that this disclosure is not limited thereto. For example, a frame may include two or more first time periods t1 and two or more second time periods t2. In this case, the first time periods t1 and the second time periods t2 may be arranged alternately and repeatedly, and the number of first time periods t1 may be substantially equal to the number of second time periods t2.

[0139] Figures 6 to 8 It is used to show in Figure 5 A circuit diagram of a method for driving the driving transistor, the second to eighth transistors and the light-emitting element of the i-th sub-pixel and the first transistor of the (i+1)-th sub-pixel during the N-th frame.

[0140] In the following text, the driving transistors DT, ST2, ST3, ST4, ST5, ST6, ST7, and ST8 of the i-th sub-pixel SPi, as well as the light-emitting element LE and the first transistor ST1 of the (i+1)-th sub-pixel SP(i+1), will be discussed. Figure 5 The operations during the Nth frame are described in detail.

[0141] First, during the first time period t1, a scan signal with a gate on-state voltage Von is supplied to the first scan line GIi connected to the i-th sub-pixel SPi. During the first time period t1, as... Figure 6 As shown, each of the second transistor ST2 and the fourth transistor ST4 is turned on by applying a gate turn-on voltage Von to the first scan line GIi connected to the i-th sub-pixel SPi. When the fourth transistor ST4 is turned on, the gate electrode of the driving transistor DT is initialized to the first initialization voltage Vint1 of the first initialization voltage line VIL1.

[0142] Although the second transistor ST2 is turned on during the first time period t1, the third transistor ST3 is turned off, so that the first initialization voltage line VIL1 and the second initialization voltage line VIL2 are electrically isolated from each other.

[0143] Secondly, during the second time period t2, a scan signal with a gate on-state voltage Von is supplied to the second scan line GWi connected to the i-th sub-pixel SPi and the first scan line GI(i+1) connected to the (i+1)-th sub-pixel SP(i+1). During the second time period t2, as... Figure 7 As shown, the first transistor ST1 is turned on by applying a gate on-state voltage Von to the first scan line GI(i+1) connected to the (i+1)th sub-pixel SP(i+1). Each of the third transistor ST3, the fifth transistor ST5, and the sixth transistor ST6 is turned on by applying a gate on-state voltage Von to the second scan line GWi connected to the i-th sub-pixel SPi.

[0144] Although the third transistor ST3 is turned on during the second time period t2, the second transistor ST2 is turned off, which electrically separates the first initialization voltage line VIL1 and the second initialization voltage line VIL2 from each other.

[0145] When the first transistor ST1 of the (i+1)th sub-pixel SP(i+1) is turned on, the anode of the light-emitting element LE of the i-th sub-pixel SPi is initialized to the second initialization voltage Vint2 of the second initialization voltage line VIL2.

[0146] When the sixth transistor ST6 is turned on, the gate and second electrodes of the driving transistor DT are connected to each other, causing the driving transistor DT to operate as a diode. When the fifth transistor ST5 is turned on, the data voltage Vdata is applied to the first electrode of the driving transistor DT. At this time, since the voltage between the first electrode and the gate electrode of the driving transistor DT (Vsg = Vdata – Vint1) is less than the absolute value of the threshold voltage Vth, the driving transistor DT forms a current path until the voltage Vsg between the gate electrode and the source electrode reaches the absolute value of the threshold voltage Vth. Therefore, during the second time period t2, the voltage between the gate electrode and the second electrode of the driving transistor DT increases until the voltage difference (Vdata - |Vth|) between the absolute value of the data voltage Vdata and the threshold voltage Vth of the driving transistor DT is reached. The voltage equal to the voltage difference Vdata - |Vth| can be stored in the capacitor C1.

[0147] Since the driving transistor DT is a p-type MOSFET, the driving current Isd of the driving transistor DT can be proportional to the voltage Vsd between its source and drain electrodes during periods when the voltage Vsd between the source and drain electrodes of the driving transistor DT is greater than 0V. Furthermore, because the driving transistor DT is implemented as a p-type MOSFET, the threshold voltage Vth can be less than 0V.

[0148] Third, during the third time period t3, an emission signal with a gate on-state voltage Von is applied to the i-th emission control line ELi, which is connected to the i-th sub-pixel SPi. During the third time period t3, as... Figure 8 As shown, each of the seventh transistor ST7 and the eighth transistor ST8 is turned on by an emit signal having a gate on-state voltage Von.

[0149] For reference, the third time period t3 of the Nth frame of the i-th sub-pixel SPi may overlap with a portion of the second time period t2 and the third time period t3 of the Nth frame of the (i+1)-th sub-pixel SP(i+1). Figure 8 This is a circuit diagram showing the operation of the i-th sub-pixel SPi during the third time period t3 of the N-th frame and the operation of the (i+1)-th sub-pixel SP(i+1) during the second time period t2 of the N-th frame.

[0150] When the seventh transistor ST7 is turned on, the first electrode of the driving transistor DT is connected to the first driving voltage line VDDL. When the eighth transistor ST8 is turned on, the second electrode of the driving transistor DT is connected to the anode of the light-emitting element LE.

[0151] When the seventh transistor ST7 and the eighth transistor ST8 are turned on, the driving current Isd can be supplied to the light-emitting element LE according to the voltage at the gate electrode of the driving transistor DT. The driving current Isd can be defined as shown in Equation 2 below:

[0152] [Equation 2]

[0153] Isd=K'×(ELVDD-(Vdata-|Vth|)-|Vth|) 2

[0154] Where k' represents a scaling factor determined by the structure and physical properties of the driving transistor DT, Vth represents the threshold voltage of the driving transistor DT, ELVDD represents the first driving voltage from the first driving voltage line VDDL, and Vdata represents the data voltage. The gate voltage of the driving transistor DT is equal to Vdata - Vth, and the voltage at the first electrode is equal to ELVDD. By summarizing Equation 2, the following Equation 3 is derived.

[0155] [Equation 3]

[0156] Isd = K′ × (ELVDD - Vdata) 2

[0157] Therefore, as shown in Equation 3, the drive current Isd does not depend on the threshold voltage Vth of the drive transistor DT. In other words, the threshold voltage Vth of the drive transistor DT is compensated.

[0158] During the third time period t3, the second transistor ST2 and the third transistor ST3 are turned off, so that the first initialization voltage line VIL1 and the second initialization voltage line VIL2 are electrically isolated from each other.

[0159] like Figure 4 As shown, by adding a second transistor ST2 and a third transistor ST3 between the first transistor ST1 and the fourth transistor ST4 of the i-th sub-pixel SPi, the active layer of the first transistor ST1 can be connected to the active layer of the fourth transistor ST4 of the i-th sub-pixel SPi without disconnecting the connection. This will be discussed later. Figure 9 The description is as follows. Therefore, the active layer of a sub-pixel SP can be connected to the active layers of adjacent sub-pixel SPs in the second direction (Y-axis direction). In other words, the active layers of multiple sub-pixel SPs can be integrally formed. Therefore, when static electricity is applied to the active layer during the manufacturing process, a path for dissipating static electricity is formed by the active layers of multiple adjacent sub-pixel SPs in the second direction (Y-axis direction), allowing the static electricity to be released to the outside or dispersed. Therefore, it is possible to prevent the active layer from being electrostatically burned or damaged during the process.

[0160] If the second transistor ST2 and the third transistor ST3 are simultaneously turned on during the first time period t1 to the third time period t3, a short circuit may form between the first initialization voltage line VIL1 and the second initialization voltage line VIL2. Therefore, to prevent a short circuit between the first initialization voltage line VIL1 and the second initialization voltage line VIL2, the second transistor ST2 and the third transistor ST3 are controlled so that they are not turned on simultaneously. As a result, the first initialization voltage line VIL1 and the second initialization voltage line VIL2 can be electrically isolated from each other during the first time period t1 to the third time period t3, that is, during the entire time period t1 to t3. Therefore, the first initialization voltage Vint1 applied to the gate electrode of the driving transistor DT and the second initialization voltage Vint2 applied to the anode of the light-emitting element LE can be applied uniformly without affecting each other.

[0161] Figure 9 This is a plan view illustrating a sub-pixel according to an exemplary embodiment of the present disclosure. Figure 10 It is shown Figure 9 A planar view of the active layer of the sub-pixels. Figure 11 It is shown Figure 9 A planar view of the first and second metal layers of the sub-pixels. Figure 12 It is shown Figure 9 A planar view of the third metal layer of the sub-pixel.

[0162] Reference Figures 9 to 12 Each of the sub-pixels SP may include a driving transistor DT, a first transistor ST1, a second transistor ST2, a third transistor ST3, a fourth transistor ST4, a fifth transistor ST5, a sixth transistor ST6, a seventh transistor ST7, and an eighth transistor ST8, as well as a capacitor C1. Furthermore, multiple sub-pixels SP(i-1), SPi, and SP(i+1) that are adjacent to each other in the second direction (Y-axis direction) may be as follows: Figure 10 The area is divided as shown by the dashed lines.

[0163] In the following text, reference will be made to Figures 9 to 12 The driving transistors DT, ST1, ST2, ST3, ST4, ST5, ST6, ST7, and ST8 of the i-th sub-pixel SPi, which are formed by the active layer ACT and the first metal layer MTL1, the second metal layer MTL2, and the third metal layer MTL3, as well as the capacitor C1, are described.

[0164] The active layer ACT may include the channel regions CH1 to CH8 of the first transistor ST1 to the eighth transistor ST8, the first electrode S1 to S8, and the second electrode D1 to D8.

[0165] Can Figure 10 The active layer ACT is integrally formed in each of the sub-pixels SP(i-1), SPi, and SP(i+1) that are adjacent to each other in the second direction (Y-axis direction). The first metal layer MTL1 may include a first scan line GIi, a second scan line GWi, a gate electrode DT_G of the driving transistor DT, and an i-th emission control line ELi. The first scan line GIi, the second scan line GWi, and the i-th emission control line ELi may extend in the first direction (X-axis direction).

[0166] The first scan line GIi may include a first extension GIi' extending in a first direction (X-axis direction) and a first protrusion GIi protruding in a direction opposite to the second direction (Y-axis direction). The second scan line GWi may include a second extension GWi' extending in the first direction (X-axis direction) and a second protrusion GWi protruding in the second direction (Y-axis direction).

[0167] The first extension GIi' and the second extension GWi' may be arranged parallel to each other and may overlap each other in the second direction (Y-axis direction). The first protrusion GIi” and the second protrusion GWi” may be arranged parallel to each other and may overlap each other in the first direction (X-axis direction).

[0168] The first length L1 between the first protrusion GIi” and the second extension GWi’ in the second direction (Y-axis direction) may be different from the second length L2 between the second protrusion GWi” and the first extension GIi’ in the second direction (Y-axis direction). For example, the first length L1 may be greater than the second length L2.

[0169] The first protrusion GIi” and the second protrusion GWi” may overlap with the active layer ACT in the third direction (Z-axis direction). The active layer ACT may intersect with the first protrusion GIi” of the first scan line GIi, and the active layer ACT may intersect with the second protrusion GWi” of the second scan line GWi.

[0170] In the plan view, the portion of the active layer ACT that overlaps with the first protrusion GIi” can be defined as the channel region CH2 of the second transistor ST2. In the plan view, the portion of the active layer ACT that overlaps with the second protrusion GWi” can be defined as the channel region CH3 of the third transistor ST3. Between the channel region CH2 of the second transistor ST2 and the channel region CH3 of the third transistor ST3, the first electrode S2 of the second transistor ST2 and the second electrode D3 of the third transistor ST3 can be arranged.

[0171] The active layer ACT overlapping the first protrusion GIi” and the active layer ACT overlapping the second protrusion GWi” can overlap each other in the first direction (X-axis direction).

[0172] The second protrusion GWi” may overlap with the first initialization voltage connection line VIL1_2, which will be described later, in the third direction (Z-axis direction), and the first protrusion GIi” may not overlap with the first initialization voltage connection line VIL1_2 in the third direction (Z-axis direction). The channel region CH3 of the third transistor ST3 may overlap with the first initialization voltage connection line VIL1_2 in the third direction (Z-axis direction).

[0173] The first scan line GIi, the second scan line GWi, and the i-th emission control line ELi are arranged sequentially in a direction opposite to the second direction (Y-axis direction), and Figure 9 The i-th sub-pixel SPi is shown, which is the sub-pixel in the i-th row. The gate electrode DT_G of the driving transistor DT can be arranged between the second scan line GWi and the i-th emission control line ELi.

[0174] The second metal layer MTL2 may include a first initialization voltage line VIL1_1, a second initialization voltage line VIL2_1, a (1-1) driving voltage line VDDL1, and a (1-3) driving voltage line VDDL3. The first initialization voltage line VIL1_1, the second initialization voltage line VIL2_1, the (1-1) driving voltage line VDDL1, and the (1-3) driving voltage line VDDL3 may extend in a first direction (X-axis direction) and may not intersect each other.

[0175] (1-3) The driving voltage line VDDL3 can be arranged between the first scan line GIi and the second scan line GWi.

[0176] (1-1) The driving voltage line VDDL1 can be arranged between the second scan line GWi and the i-th emitter control line ELi. (1-1) A portion of the driving voltage line VDDL1 can overlap with the gate electrode DT_G of the driving transistor DT in the third direction (Z-axis direction).

[0177] The first initialization voltage line VIL1_1 and the second initialization voltage line VIL2_1 can be arranged sequentially in the direction opposite to the second direction (Y-axis direction). The first initialization voltage line VIL1_1 and the second initialization voltage line VIL2_1 can be arranged between the first scan line GIi and the (i-1)th emission control line EL(i-1), where the (i-1)th emission control line EL(i-1) is the emission control line of the sub-pixel SP adjacent to the first scan line GIi in the second direction (Y-axis direction).

[0178] The third metal layer MTL3 may include a data line DL, a (1-2) driving voltage line VDDL2, a connecting electrode BE, an anode connecting electrode ANDE for the light-emitting element LE, a first initialization voltage connecting line VIL1_2, and a second initialization voltage connecting line VIL2_2. The data line DL, the (1-2) driving voltage line VDDL2, and the first initialization voltage connecting line VIL1_2 may extend in a second direction (Y-axis direction).

[0179] (1-2) The driving voltage line VDDL2 can be arranged between the data line DL and the first initialization voltage connection line VIL1_2. (1-2) The driving voltage line VDDL2 can intersect with the first scan line GIi, the second scan line GWi, the i-th transmit control line ELi, the first initialization voltage line VIL1_1, the second initialization voltage line VIL2_1 and the driving voltage line VDDL1 (1-1), and can overlap with each of the driving voltage line VDDL3 (1-3) and the active layer ACT in the third direction (Z-axis direction).

[0180] The connecting electrode BE and the anode connecting electrode ANDE can be arranged between the (1-2) drive voltage line VDDL2 and the first initialization voltage connecting line VIL1_2.

[0181] The connecting electrode BE may overlap with each of the (1-1) driving voltage line VDDL1, the gate electrode DT_G of the driving transistor DT, and the active layer ACT in the third direction (Z-axis direction), and may intersect with the second scan line GWi. The connecting electrode BE may overlap with each of the data line DL, the (1-2) driving voltage line VDDL2, and the first initialization voltage connecting line VIL1_2 in the first direction (X-axis direction).

[0182] The anode connection electrode ANDE may overlap with each of the i-th transmit control line ELi and the active layer ACT in the third direction (Z-axis direction). The anode connection electrode ANDE may overlap with each of the data line DL, the (1-2) drive voltage line VDDL2, and the first initialization voltage connection line VIL1_2 in the first direction (X-axis direction). The anode connection electrode ANDE and the connection electrode BE may overlap with each other in the second direction (Y-axis direction).

[0183] The first initialization voltage connection line VIL1_2 may overlap and intersect with the first initialization voltage line VIL1_1 in the third direction (Z-axis direction). The first initialization voltage connection line VIL1_2 may overlap with each of the connecting electrode BE, the anode connecting electrode ANDE, and the second initialization voltage connection line VIL2_2 in the first direction (X-axis direction). The first initialization voltage connection line VIL1_2 may overlap with the connecting electrode BE and the anode connecting electrode ANDE in the second direction (Y-axis direction).

[0184] The second initialization voltage connection line VIL2_2 may be arranged between the first initialization voltage connection line VIL1_2 and the data line DL of the adjacent sub-pixel in the first direction (X-axis direction). The second initialization voltage connection line VIL2_2 may overlap with each of the first scan line GIi, the second initialization voltage line VIL2_1, and the (1-3) driving voltage lines VDDL3 in the third direction (Z-axis direction).

[0185] The driving transistor DT may include a channel region DT_CH, a gate electrode DT_G, a first electrode DT_S, and a second electrode DT_D. The channel region DT_CH of the driving transistor DT may overlap with the gate electrode DT_G of the driving transistor DT. A connection electrode BE may be disposed on the gate electrode DT_G, and the gate electrode DT_G and the connection electrode BE may be connected to each other through a first contact hole CNT1. The gate electrode DT_G may overlap with the channel region DT_CH of the driving transistor DT, and the connection electrode BE may be connected to the second electrode D4-1 of transistor ST4-1 (4-1) through a second contact hole CNT2. The first electrode DT_S of the driving transistor DT may be connected to the second electrode D5 of the fifth transistor ST5 and the second electrode D7 of the seventh transistor ST7. The second electrode DT_D of the driving transistor DT may be connected to the first electrode S6-2 of transistor ST6-2 (6-2) and the first electrode S8 of transistor ST8 (8-2).

[0186] The first transistor ST1 may include a channel region CH1, a gate electrode G1, a first electrode S1, and a second electrode D1. The gate electrode G1 of the first transistor ST1 may be part of a first extension GIi' of the first scan line GIi, wherein the channel region CH1 of the first transistor ST1 and the first extension GIi' of the first scan line GIi overlap each other in a planar view. The first electrode S1 of the first transistor ST1 may be connected to the second initialization voltage connection line VIL2_2 through the tenth contact hole CNT10. The second initialization voltage line VIL2_1 may be connected to the second initialization voltage connection line VIL2_2 through the ninth contact hole CNT9. The second initialization voltage connection line VIL2_2 may be connected to the second electrode D2 of the second transistor ST2 and the first electrode S1 of the first transistor ST1 through the tenth contact hole CNT10. The second initialization voltage connection line VIL2_2 may be arranged to intersect the first scan line GIi. The second electrode D1 of the first transistor ST1 may be connected to the anode connection electrode ANDE of the (i-1)th sub-pixel SP(i-1) through the sixth contact hole CNT6 of the (i-1)th sub-pixel SP(i-1).

[0187] The second transistor ST2 may include a channel region CH2, a gate electrode G2, a first electrode S2, and a second electrode D2. The gate electrode G2 of the second transistor ST2 may be part of a first protrusion GIi” of the first scan line GIi, wherein the channel region CH2 of the second transistor ST2 and the first protrusion GIi” of the first scan line GIi overlap each other in a planar view. The first electrode S2 of the second transistor ST2 may be connected to the second electrode D3 of the third transistor ST3. The second electrode D2 of the second transistor ST2 may be connected to the first electrode S1 of the first transistor ST1.

[0188] The third transistor ST3 may include a channel region CH3, a gate electrode G3, a first electrode S3, and a second electrode D3. The gate electrode G3 of the third transistor ST3 may be part of the second protrusion GWi” of the second scan line GWi, wherein the channel region CH3 of the third transistor ST3 and the second protrusion GWi” of the second scan line GWi overlap each other in a plan view. The first electrode S3 of the third transistor ST3 can be connected to the first initialization voltage connection line VIL1_2 via a fourth contact hole CNT4. The first initialization voltage line VIL1_1 can be connected to the first initialization voltage connection line VIL1_2 via a fifth contact hole CNT5. The first initialization voltage connection line VIL1_2 can be connected to the first electrode S4-2 of transistor ST4-2 and the first electrode S3 of the third transistor ST3 via a fourth contact hole CNT4. The first initialization voltage connection line VIL1_2 may be arranged such that it intersects the first scan line GIi, the second scan line GWi, and the i-th emitter control line ELi.

[0189] The channel region CH2 of the second transistor ST2 and the channel region CH3 of the third transistor ST3 can be connected to each other, and the gate electrode G2 of the second transistor ST2 and the gate electrode G3 of the third transistor ST3 can overlap each other in the first direction (X-axis direction).

[0190] The fourth transistor ST4 can be implemented as a dual transistor. The fourth transistor ST4 may include (4-1) transistor ST4-1 and (4-2) transistor ST4-2.

[0191] (4-1) Transistor ST4-1 may include a channel region CH4-1, a gate electrode G4-1, a first electrode S4-1, and a second electrode D4-1. (4-1) The gate electrode G4-1 of transistor ST4-1 may be part of a first extension GIi' of the first scan line GIi, wherein (4-1) the channel region CH4-1 of transistor ST4-1 and the first extension GIi' of the first scan line GIi overlap each other in a planar view. (4-1) The first electrode S4-1 of transistor ST4-1 may be connected to the second electrode D4-2 of transistor ST4-2. (4-1) The second electrode D4-1 of transistor ST4-1 may be connected to the gate electrode DT_G of the driving transistor DT through a second contact hole CNT2. (4-2) Transistor ST4-2 may include a channel region CH4-2, a gate electrode G4-2, a first electrode S4-2, and a second electrode D4-2. (4-2) The gate electrode G4-2 of transistor ST4-2 may be part of the first extension GIi' of the first scan line GIi, wherein the channel region CH4-2 of transistor ST4-2 and the first extension GIi' of the first scan line GIi overlap each other in a planar view. (4-2) The first electrode S4-2 of transistor ST4-2 may be connected to the first initialization voltage connection line VIL1_2 through the fourth contact hole CNT4. (4-2) The second electrode D4-2 of transistor ST4-2 may be connected to the first electrode S4-1 of transistor ST4-1 (4-1). The fifth transistor ST5 may include the channel region CH5, the gate electrode G5, the first electrode S5, and the second electrode D5. The gate electrode G5 of the fifth transistor ST5 may be part of the second extension GWi' of the second scan line GWi, wherein the channel region CH5 of the fifth transistor ST5 and the second extension GWi' of the second scan line GWi overlap each other in a planar view. The first electrode S5 of the fifth transistor ST5 may be connected to the data line DL through the third contact hole CNT3. The second electrode D5 of the fifth transistor ST5 can be connected to the first electrode DT_S of the driving transistor DT. The sixth transistor ST6 can be implemented as a dual transistor. The sixth transistor ST6 may include (6-1) transistor ST6-1 and (6-2) transistor ST6-2.

[0192] (6-1) Transistor ST6-1 may include a channel region CH6-1, a gate electrode G6-1, a first electrode S6-1, and a second electrode D6-1. (6-1) The gate electrode G6-1 of transistor ST6-1 may be part of the second protrusion GWi” of the second scan line GWi, wherein (6-1) the channel region CH6-1 of transistor ST6-1 and the second protrusion GWi” of the second scan line GWi overlap each other in a planar view. (6-1) The first electrode S6-1 of transistor ST6-1 may be connected to (6-2) the second electrode D6-2 of transistor ST6-2. (6-1) The second electrode D6-1 of transistor ST6-1 may be connected to the gate electrode DT_G of the driving transistor DT through the second contact hole CNT2.

[0193] (6-1) The gate electrode G6-1 of transistor ST6-1 and the gate electrode G3 of the third transistor ST3 can overlap each other in the second direction (Y-axis direction).

[0194] (6-2) Transistor ST6-2 may include a channel region CH6-2, a gate electrode G6-2, a first electrode S6-2, and a second electrode D6-2. (6-2) The gate electrode G6-2 of transistor ST6-2 may be part of a second extension GWi' of the second scan line GWi, wherein (6-2) the channel region CH6-2 of transistor ST6-2 and the second extension GWi' of the second scan line GWi overlap each other in a planar view. (6-2) The first electrode S6-2 of transistor ST6-2 may be connected to the second electrode DT_D of the driving transistor DT. (6-2) The second electrode D6-2 of transistor ST6-2 may be connected to the first electrode S6-1 of transistor ST6-1 (6-1). The seventh transistor ST7 may include a channel region CH7, a gate electrode G7, a first electrode S7, and a second electrode D7. The gate electrode G7 of the seventh transistor ST7 may be part of the i-th emitter control line ELi, wherein the channel region CH7 of the seventh transistor ST7 and the i-th emitter control line ELi overlap each other in a planar view. The first electrode S7 of the seventh transistor ST7 can be connected to the (1-2) drive voltage line VDDL2 through the seventh contact hole CNT7. The second electrode D7 of the seventh transistor ST7 can be connected to the first electrode DT_S of the drive transistor DT.

[0195] The eighth transistor ST8 may include a channel region CH8, a gate electrode G8, a first electrode S8, and a second electrode D8. The gate electrode G8 of the eighth transistor ST8 may be part of the i-th emitter control line ELi, wherein the channel region CH8 and the i-th emitter control line ELi of the eighth transistor ST8 overlap each other in a planar view. The first electrode S8 of the eighth transistor ST8 may be connected to the second electrode DT_D of the driving transistor DT. The second electrode D8 of the eighth transistor ST8 may be connected to the anode connection electrode ANDE through the sixth contact hole CNT6.

[0196] The first electrode CE1 of capacitor C1 (see...) Figure 13 The gate electrode DT_G of the driving transistor DT can be substantially the same, and the second electrode CE2 of capacitor C1 (see...) Figure 13 The (1-1) driving voltage line VDDL1 can be defined in the planar diagram as overlapping with the gate electrode DT_G of the driving transistor DT. Capacitor C1 can be maintained at the voltage at the gate electrode DT_G of the driving transistor DT for one frame.

[0197] The capacitance of capacitor C1 is proportional to the area of ​​overlap between the gate electrode DT_G of the driving transistor DT and the driving voltage line VDDL1 (1-1) in the planar diagram. In other words, the capacitance of capacitor C1 increases as the area of ​​overlap between the gate electrode DT_G of the driving transistor DT and the driving voltage line VDDL1 (1-1) in the planar diagram increases.

[0198] like Figure 9 As shown, by adding a second transistor ST2 and a third transistor ST3 between the first transistor ST1 and the fourth transistor ST4, the active layer of the first transistor ST1 can be connected to the active layer of the fourth transistor ST4 without disconnecting the connection. Therefore, the active layer of the sub-pixel SP can be integrally formed with the active layers of adjacent sub-pixel SPs in the second direction (Y-axis direction). Thus, when static electricity is applied to the active layer during the manufacturing process, a static path is formed through the active layers of multiple adjacent sub-pixel SPs in the second direction (Y-axis direction), allowing the static electricity to be released to the outside or dispersed. Therefore, it is possible to prevent the active layer from being electrostatically burned or damaged during the process.

[0199] Figure 13 It is along Figure 9 The cross-sectional view taken from line I-I'. Figure 14 It is along Figure 9 The cross-sectional view taken from line II-II'.

[0200] Reference Figure 13 and Figure 14 The thin-film transistor layer (TFTL), emitter layer (EML), and encapsulation layer (TFE) can be sequentially formed on the first substrate (SUB1). The TFTL includes a buffer film (BF), an active layer (ACT), a first metal layer (MTL1), a second metal layer (MTL2), a third metal layer (MTL3), a gate insulator (130), a first interlayer dielectric layer (141), a second interlayer dielectric layer (142), a protective layer (150), and a planarization layer (160).

[0201] A buffer film BF may be formed on the surface of the first substrate SUB1. The buffer film BF is formed on the surface of the first substrate SUB1 to protect the organic emitter layer 172 of the thin-film transistor and emitter layer EML from moisture that may permeate through the first substrate SUB1. The buffer film BF may be formed from multiple inorganic layers stacked alternately on top of each other. For example, the buffer film BF may be made from a multilayer in which one or more inorganic layers selected from silicon nitride, silicon oxynitride, silicon oxide, titanium oxide, and aluminum oxide are stacked alternately on top of each other. The buffer film BF may be omitted.

[0202] The active layer ACT can be formed on the first substrate SUB1 or the buffer film BF. The active layer ACT may include polycrystalline silicon, monocrystalline silicon, low-temperature polycrystalline silicon, amorphous silicon, or oxide semiconductor.

[0203] When the active layer ACT is made of polycrystalline silicon by doping ions into the active layer ACT, the active layer ACT can be conductive. Therefore, the active layer ACT can include not only the channel region DT_CH of the driving transistor DT and the channel regions CH1 of the first transistor ST1 to CH8 of the eighth transistor ST8, but also the first electrodes DT_S, S1, S2, S3, S4-1, S4-2, S5, S6-1, S6-2, S7 and S8 and the second electrodes DT_D, D1, D2, D3, D4-1, D4-2, D5, D6-1, D6-2, D7 and D8.

[0204] The gate insulator 130 may be formed on the active layer ACT. The gate insulator 130 may be formed from an inorganic layer, such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0205] The first metal layer MTL1 may be formed on the gate insulator 130. The first metal layer MTL1 may include not only the gate electrode DT_G of the driving transistor DT and the gate electrodes G1 of the first transistor ST1 to G8 of the eighth transistor ST8, but also scan lines GIi and GWi and the i-th emitter control line ELi. The first metal layer MTL1 may be made of one or more layers of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd) and copper (Cu) or alloys thereof.

[0206] The first interlayer dielectric layer 141 may be formed on the first metal layer MTL1. The first interlayer dielectric layer 141 may be formed of an inorganic layer, such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The first interlayer dielectric layer 141 may include several inorganic layers.

[0207] The second metal layer MTL2 may be formed on the first interlayer dielectric layer 141. The second metal layer MTL2 may include a first initialization voltage line VIL1_1, a second initialization voltage line VIL2_1, a (1-1) driving voltage line VDDL1, and a (1-3) driving voltage line VDDL3. The second metal layer MTL2 may be made of one or more layers of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or alloys thereof.

[0208] The second interlayer dielectric layer 142 may be formed on the second metal layer MTL2. The second interlayer dielectric layer 142 may be formed of an inorganic layer, such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The second interlayer dielectric layer 142 may include several inorganic layers.

[0209] The third metal layer MTL3 may be formed on the second interlayer dielectric layer 142. The third metal layer MTL3 may include a data line DL, a (1-2) drive voltage line VDDL2, a connection electrode BE, an anode connection electrode ANDE, a first initialization voltage connection line VIL1_2, and a second initialization voltage connection line VIL2_2. The third metal layer MTL3 may be made of one or more layers of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) or alloys thereof.

[0210] A planarization layer 160 may be formed on a third metal layer MTL3 to provide a planar surface over the active layer ACT, the first metal layer MTL1, the second metal layer MTL2, and the third metal layer MTL3. The planarization layer 160 may be formed from an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0211] The protective layer 150 may be further formed between the third metal layer MTL3 and the planarization layer 160. The protective layer 150 may be formed of an inorganic layer, such as a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer.

[0212] Although in the illustrated example, the driving transistor DT and the first transistors ST1 through ST8 are implemented as top-gate transistors with their middle gate electrodes located above the active layer, this disclosure is not limited thereto. That is, the driving transistor DT and the first transistors ST1 through ST8 can be implemented as bottom-gate transistors with their gate electrodes located below the active layer, or as dual-gate transistors with their gate electrodes arranged above and below the active layer.

[0213] The first contact hole CNT1 can be a hole that penetrates the first interlayer dielectric layer 141 and the second interlayer dielectric layer 142, such as... Figure 13 As shown, the gate electrode DT_G of the driving transistor DT is exposed via the first contact hole CNT1. The connection electrode BE can be connected to the gate electrode DT_G of the driving transistor DT through the first contact hole CNT1.

[0214] The second contact hole CNT2 can be formed through the gate insulator 130, the first interlayer dielectric layer 141, and the second interlayer dielectric layer 142. The second electrode D6-1 of the (6-1) transistor ST6-1 is exposed through the second contact hole CNT2. The connection electrode BE can be connected to the second electrode D6-1 of the (6-1) transistor ST6-1 through the second contact hole CNT2.

[0215] The third contact hole CNT3 can be formed through the gate insulator 130, the first interlayer dielectric layer 141, and the second interlayer dielectric layer 142. The first electrode S5 of the fifth transistor ST5 is exposed through the third contact hole CNT3. The data line DL can be connected to the first electrode S5 of the fifth transistor ST5 through the third contact hole CNT3.

[0216] The fourth contact hole CNT4 can be formed through the gate insulator 130, the first interlayer dielectric layer 141, and the second interlayer dielectric layer 142. The first electrode S4-2 of transistor ST4-2 and the first electrode S3 of transistor ST3 are exposed through the fourth contact hole CNT4. The first initialization voltage connection line VIL1_2 can be connected to the first electrode S4-2 of transistor ST4-2 and the first electrode S3 of transistor ST3 through the fourth contact hole CNT4.

[0217] The fifth contact hole CNT5 can be formed through the second interlayer dielectric layer 142, and the first initialization voltage line VIL1_1 is exposed through the fifth contact hole CNT5. The first initialization voltage connection line VIL1_2 can be connected to the first initialization voltage line VIL1_1 through the fifth contact hole CNT5.

[0218] The sixth contact hole CNT6 can be formed through the gate insulator 130, the first interlayer dielectric layer 141, and the second interlayer dielectric layer 142. The second electrode D8 of the eighth transistor ST8 is exposed through the sixth contact hole CNT6. The anode connection electrode ANDE can be connected to the second electrode D8 of the eighth transistor ST8 through the sixth contact hole CNT6.

[0219] The seventh contact hole CNT7 can be formed through the gate insulator 130, the first interlayer dielectric layer 141 and the second interlayer dielectric layer 142, and the first electrode S7 of the seventh transistor ST7 is exposed through the seventh contact hole CNT7. (1-2) The driving voltage line VDDL2 can be connected to the first electrode S7 of the seventh transistor ST7 through the seventh contact hole CNT7.

[0220] The eighth contact hole CNT8 can be formed through the second interlayer dielectric layer 142, and the driving voltage line VDDL1 is exposed through the eighth contact hole CNT8. The driving voltage line VDDL2 can be connected to the driving voltage line VDDL1 through the eighth contact hole CNT8.

[0221] The ninth contact hole CNT9 can be formed through the second interlayer dielectric layer 142, and the second initialization voltage line VIL2_1 is exposed through the ninth contact hole CNT9. The second initialization voltage connection line VIL2_2 can be connected to the second initialization voltage line VIL2_1 through the ninth contact hole CNT9.

[0222] The tenth contact hole CNT10 can be formed through the gate insulator 130, the first interlayer dielectric layer 141, and the second interlayer dielectric layer 142. The first electrode S1 of the first transistor ST1 and the second electrode D2 of the second transistor ST2 are exposed through the tenth contact hole CNT10. The second initialization voltage connection line VIL2_2 can be connected to the first electrode S1 of the first transistor ST1 and the second electrode D2 of the second transistor ST2 through the tenth contact hole CNT10.

[0223] The eleventh contact hole CNT11 can be formed through the second interlayer dielectric layer 142, and the (1-3) driving voltage line VDDL3 is exposed through the eleventh contact hole CNT11. The (1-2) driving voltage line VDDL2 can be connected to the (1-3) driving voltage line VDDL3 through the eleventh contact hole CNT11.

[0224] An anode contact hole AND_CNT can be formed through a protective layer 150 and a planarization layer 160, through which the anode connection electrode ANDE is exposed.

[0225] An emitter layer EML is formed on a thin-film transistor layer (TFTL). The emitter layer EML includes a light-emitting element 170 and a pixel defining layer 180.

[0226] Light-emitting elements 170 and pixel defining layers 180 are formed on planarization layer 160. Each of the light-emitting elements 170 may include a first electrode 171, an organic emitting layer 172, and a second electrode 173.

[0227] The first electrode 171 may be formed on the planarization layer 160. The first electrode 171 may be connected to the anode connection electrode ANDE through the anode contact hole AND_CNT penetrating the protective layer 150 and the planarization layer 160.

[0228] In a top-emitting organic light-emitting diode (OLED) where light exits from the organic emitting layer 172 toward the second electrode 173, the first electrode 171 may be made of a highly reflective metallic material such as a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and ITO (ITO / Al / ITO), an APC alloy, or a stacked structure of APC alloy and ITO (ITO / APC / ITO). The APC alloy is an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0229] A pixel defining layer 180 may be formed on the planarization layer 160 to separate the first electrode 171, thereby defining the emission region EA of each of the sub-pixels SP. The pixel defining layer 180 may be formed to cover the edge of the first electrode 171. The pixel defining layer 180 may be formed of an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and polyimide resin.

[0230] In the emission region EA of each of the sub-pixels SP, the first electrode 171, the organic emission layer 172, and the second electrode 173 are stacked on top of each other in this order, such that holes from the first electrode 171 and electrons from the second electrode 173 combine with each other in the organic emission layer 172 to emit light.

[0231] An organic emitting layer 172 is formed on the first electrode 171 and the pixel defining layer 180. The organic emitting layer 172 may include organic materials and emits light of a certain color. For example, the organic emitting layer 172 may include a hole transport layer, an organic material layer, and an electron transport layer.

[0232] The second electrode 173 is formed on the organic emission layer 172. The second electrode 173 may be formed to cover the organic emission layer 172. The second electrode 173 may be a common layer formed across multiple sub-pixels SP. A capping layer may be formed on the second electrode 173.

[0233] In a top-emitting organic light-emitting diode, the second electrode 173 can be formed of a transparent conductive material (“TCP”) such as ITO and IZO that is capable of transmitting light, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the second electrode 173 is formed of a semi-transmissive conductive material, the light extraction efficiency can be increased by using a microcavity.

[0234] An encapsulation layer TFE may be formed on the emitter layer EML. The encapsulation layer TFE may include at least one inorganic film to prevent oxygen or moisture from penetrating into the emitter layer EML. In addition, the encapsulation layer TFE may include at least one organic film to protect the emitter layer EML from particles such as dust.

[0235] Alternatively, a second substrate, instead of the encapsulation layer TFE, can be disposed on the emitter layer EML, such that the space between the emitter layer EML and the second substrate can be empty or filled with a filler film. The filler film can be an epoxy filler film or a silicon filler film.

[0236] like Figure 14 As shown, since the second transistor ST2 and the third transistor ST3 are arranged between transistor ST4-2 (4-2) and the first transistor ST1, the active layers of the first transistor ST1 and the fourth transistor ST4 can be connected to each other without disconnecting. Therefore, the active layer of the sub-pixel SP can be integrally formed with the active layers of adjacent sub-pixel SPs in the second direction (Y-axis direction). Therefore, when static electricity is applied to the active layer during the manufacturing process, a path for dissipating static electricity is formed by the active layers of multiple adjacent sub-pixel SPs in the second direction (Y-axis direction), allowing the static electricity to be released to the outside or dispersed. Therefore, it is possible to prevent the active layer from being burned or damaged by static electricity during the process.

[0237] Figure 15 This is a circuit diagram illustrating a sub-pixel according to yet another exemplary embodiment of the present disclosure.

[0238] Figure 15 Exemplary implementation methods and Figure 4 The exemplary implementation differs in that the gate electrode of the second transistor ST2 of the i-th sub-pixel SPi is connected to the second scan line GWi, and the gate electrode of the third transistor ST3 of the i-th sub-pixel SPi is connected to the first scan line GIi. The following description will focus on the differences.

[0239] when Figure 5 The signals applied to the first scan line GIi, the second scan line GWi, and the i-th transmit control line ELi, which are connected to the i-th sub-pixel SPi, are applied to Figure 15 When the i-th sub-pixel SPi is in operation, the second transistor ST2 and the third transistor ST3 of the i-th sub-pixel SPi operate as follows during the first time period t1 to the third time period t3.

[0240] During the first time period t1, the third transistor ST3 of the i-th sub-pixel SPi is turned on, while the second transistor ST2 of the i-th sub-pixel SPi is turned off, and the first initialization voltage line VIL1 and the second initialization voltage line VIL2 connected to the i-th sub-pixel SPi are electrically separated from each other.

[0241] During the second time period t2, the second transistor ST2 of the i-th sub-pixel SPi is turned on, while the third transistor ST3 of the i-th sub-pixel SPi is turned off, and the first initialization voltage line VIL1 and the second initialization voltage line VIL2 connected to the i-th sub-pixel SPi are electrically separated from each other.

[0242] During the third time period t3, the second transistor ST2 and the third transistor ST3 of the i-th sub-pixel SPi are turned off, and the first initialization voltage line VIL1 and the second initialization voltage line VIL2 connected to the i-th sub-pixel SPi are electrically separated from each other.

[0243] In other words, during the first time period t1 to the third time period t3, the second transistor ST2 and the third transistor ST3 of the i-th sub-pixel SPi are never turned on simultaneously, and therefore, it is possible to prevent the first initialization voltage line VIL1 and the second initialization voltage line VIL2 connected to the i-th sub-pixel SPi from being electrically connected to each other to form a short circuit.

[0244] Figure 16 This is a circuit diagram illustrating a sub-pixel according to yet another exemplary embodiment of the present disclosure.

[0245] Figure 16 Exemplary implementation methods and Figure 4 The difference in the exemplary implementation is that the gate electrode of the third transistor ST3 of the i-th sub-pixel SPi is connected to the i-th emission control line ELi. The following description will focus on the difference.

[0246] when Figure 5 The signals applied to the first scan line GIi, the second scan line GWi, and the i-th transmit control line ELi, which are connected to the i-th sub-pixel SPi, are applied to Figure 16 When the i-th sub-pixel SPi is in operation, the second transistor ST2 and the third transistor ST3 of the i-th sub-pixel SPi operate as follows during the first time period t1 to the third time period t3.

[0247] During the first time period t1, the second transistor ST2 of the i-th sub-pixel SPi is turned on, while the third transistor ST3 of the i-th sub-pixel SPi is turned off, and the first initialization voltage line VIL1 and the second initialization voltage line VIL2 connected to the i-th sub-pixel SPi are electrically isolated from each other.

[0248] During the second time period t2, the second transistor ST2 and the third transistor ST3 of the i-th sub-pixel SPi are turned off, and the first initialization voltage line VIL1 and the second initialization voltage line VIL2 connected to the i-th sub-pixel SPi are electrically separated from each other.

[0249] During the third time period t3, the third transistor ST3 of the i-th sub-pixel SPi is turned on, while the second transistor ST2 is turned off, and the first initialization voltage line VIL1 and the second initialization voltage line VIL2 connected to the i-th sub-pixel SPi are electrically separated from each other.

[0250] In other words, during the first time period t1 to the third time period t3, the second transistor ST2 and the third transistor ST3 are never turned on simultaneously, and therefore, it is possible to prevent the first initialization voltage line VIL1 and the second initialization voltage line VIL2 connected to the i-th sub-pixel SPi from being electrically connected to each other to form a short circuit.

[0251] Figure 17 This is a circuit diagram illustrating a sub-pixel according to yet another exemplary embodiment of the present disclosure.

[0252] Figure 17 Exemplary implementation methods and Figure 4 The difference in the exemplary implementation is that the gate electrode of the second transistor ST2 of the i-th sub-pixel SPi is connected to the second scan line GWi, and the gate electrode of the third transistor ST3 of the i-th sub-pixel SPi is connected to the i-th emission control line ELi. The following description will focus on the differences.

[0253] when Figure 5 The signals applied to the first scan line GIi, the second scan line GWi, and the i-th transmit control line ELi, which are connected to the i-th sub-pixel SPi, are applied to Figure 17 When the i-th sub-pixel SPi is in operation, the second transistor ST2 and the third transistor ST3 of the i-th sub-pixel SPi operate as follows during the first time period t1 to the third time period t3.

[0254] During the first time period t1, the second transistor ST2 and the third transistor ST3 of the i-th sub-pixel SPi are turned off, and the first initialization voltage line VIL1 and the second initialization voltage line VIL2 connected to the i-th sub-pixel SPi are electrically separated from each other.

[0255] During the second time period t2, the second transistor ST2 of the i-th sub-pixel SPi is turned on, while the third transistor ST3 of the i-th sub-pixel SPi is turned off, and the first initialization voltage line VIL1 and the second initialization voltage line VIL2 connected to the i-th sub-pixel SPi are electrically separated from each other.

[0256] During the third time period t3, the third transistor ST3 of the i-th sub-pixel SPi is turned on, while the second transistor ST2 of the i-th sub-pixel SPi is turned off, and the first initialization voltage line VIL1 and the second initialization voltage line VIL2 connected to the i-th sub-pixel SPi are electrically separated from each other.

[0257] In other words, during the first time period t1 to the third time period t3, the second transistor ST2 and the third transistor ST3 of the i-th sub-pixel SPi are never turned on simultaneously, and therefore, it is possible to prevent the first initialization voltage line VIL1 and the second initialization voltage line VIL2 connected to the i-th sub-pixel SPi from being electrically connected to each other to form a short circuit.

[0258] Figure 18 This is a circuit diagram illustrating a sub-pixel according to yet another exemplary embodiment of the present disclosure.

[0259] Figure 18 Exemplary implementation methods and Figure 4 The difference in the exemplary implementation is that the gate electrode of the second transistor ST2 of the i-th sub-pixel SPi is connected to the i-th emission control line ELi, and the gate electrode of the third transistor ST3 of the i-th sub-pixel SPi is connected to the first scan line GIi. The following description will focus on the differences.

[0260] when Figure 5 The signals applied to the first scan line GIi, the second scan line GWi, and the i-th transmit control line ELi, which are connected to the i-th sub-pixel SPi, are applied to Figure 18 When the i-th sub-pixel SPi is in operation, the second transistor ST2 and the third transistor ST3 of the i-th sub-pixel SPi operate as follows during the first time period t1 to the third time period t3.

[0261] During the first time period t1, the third transistor ST3 of the i-th sub-pixel SPi is turned on, while the second transistor ST2 of the i-th sub-pixel SPi is turned off, and the first initialization voltage line VIL1 and the second initialization voltage line VIL2 connected to the i-th sub-pixel SPi are electrically separated from each other.

[0262] During the second time period t2, the second transistor ST2 and the third transistor ST3 of the i-th sub-pixel SPi are turned off, and the first initialization voltage line VIL1 and the second initialization voltage line VIL2 connected to the i-th sub-pixel SPi are electrically separated from each other.

[0263] During the third time period t3, the second transistor ST2 of the i-th sub-pixel SPi is turned on, while the third transistor ST3 of the i-th sub-pixel SPi is turned off, and the first initialization voltage line VIL1 and the second initialization voltage line VIL2 connected to the i-th sub-pixel SPi are electrically separated from each other.

[0264] In other words, during the first time period t1 to the third time period t3, the second transistor ST2 and the third transistor ST3 of the i-th sub-pixel SPi are never turned on simultaneously, and therefore, it is possible to prevent the first initialization voltage line VIL1 and the second initialization voltage line VIL2 connected to the i-th sub-pixel SPi from being electrically connected to each other to form a short circuit.

[0265] Figure 19 This is a circuit diagram illustrating a sub-pixel according to yet another exemplary embodiment of the present disclosure.

[0266] Figure 19 Exemplary implementation methods and Figure 4 The difference in the exemplary implementation is that the gate electrode of the second transistor ST2 of the i-th sub-pixel SPi is connected to the i-th emission control line ELi, and the gate electrode of the third transistor ST3 of the i-th sub-pixel SPi is connected to the second scan line GWi. The following description will focus on the differences.

[0267] when Figure 5 The signals applied to the first scan line GIi, the second scan line GWi, and the i-th transmit control line ELi, which are connected to the i-th sub-pixel SPi, are applied to Figure 19 When the i-th sub-pixel SPi is in operation, the second transistor ST2 and the third transistor ST3 of the i-th sub-pixel SPi operate as follows during the first time period t1 to the third time period t3.

[0268] During the first time period t1, the second transistor ST2 and the third transistor ST3 of the i-th sub-pixel SPi are turned off, and the first initialization voltage line VIL1 and the second initialization voltage line VIL2 connected to the i-th sub-pixel SPi are electrically separated from each other.

[0269] During the second time period t2, the third transistor ST3 of the i-th sub-pixel SPi is turned on, while the second transistor ST2 of the i-th sub-pixel SPi is turned off, and the first initialization voltage line VIL1 and the second initialization voltage line VIL2 connected to the i-th sub-pixel SPi are electrically separated from each other.

[0270] During the third time period t3, the second transistor ST2 of the i-th sub-pixel SPi is turned on, while the third transistor ST3 of the i-th sub-pixel SPi is turned off, and the first initialization voltage line VIL1 and the second initialization voltage line VIL2 connected to the i-th sub-pixel SPi are electrically separated from each other.

[0271] In other words, during the first time period t1 to the third time period t3, the second transistor ST2 and the third transistor ST3 of the i-th sub-pixel SPi are never turned on simultaneously, and therefore, it is possible to prevent the first initialization voltage line VIL1 and the second initialization voltage line VIL2 connected to the i-th sub-pixel SPi from being electrically connected to each other to form a short circuit.

[0272] As described above, according to an exemplary embodiment of this disclosure, by adding a second transistor ST2 and a third transistor ST3 between the first transistor ST1 and the fourth transistor ST4, the active layer of the first transistor ST1 can be connected to the active layer of the fourth transistor ST4 without disconnecting the connection. Therefore, the active layer of the sub-pixel SP can be integrally formed with the active layers of adjacent sub-pixel SPs in the second direction (Y-axis direction). Therefore, when static electricity is applied to the active layer during the manufacturing process, a path for dissipating static electricity is formed by the active layers of multiple adjacent sub-pixel SPs in the second direction (Y-axis direction), allowing the static electricity to be released to the outside or widely dispersed. Therefore, it is possible to prevent the active layer from being electrostatically burned or damaged during the process.

[0273] Furthermore, since the second transistor ST2 and the third transistor ST3 never conduct simultaneously during the first time period t1 to the third time period t3, a short circuit between the first initialization voltage line VIL1 and the second initialization voltage line VIL2 can be prevented. By doing so, the first initialization voltage Vint1 applied to the gate electrode of the driving transistor DT and the second initialization voltage Vint2 applied to the anode of the light-emitting element LE can be applied uniformly without affecting each other.

[0274] Figure 20 This is a circuit diagram illustrating a sub-pixel according to yet another exemplary embodiment of the present disclosure.

[0275] Figure 20 Exemplary implementation methods and Figure 4 The difference in the exemplary implementation is that the gate electrode of the first transistor ST1 of the (i+1)th sub-pixel SP(i+1) is connected to the second scan line GW(i+1) connected to the (i+1)th sub-pixel SP(i+1). The following description will focus on the difference.

[0276] When the gate electrode of the first transistor ST1 of the (i+1)th sub-pixel SP(i+1) is connected to the second scan line GW(i+1) connected to the (i+1)th sub-pixel SP(i+1), the first transistor ST1 of the (i+1)th sub-pixel SP(i+1) is connected to the light-emitting element LE of the i-th sub-pixel SPi. Therefore, before the emission signal applied to the i-th emission control line ELi connected to the i-th sub-pixel SPi has a gate on-state voltage Von, the scan signal applied to the second scan line GW(i+1) connected to the (i+1)th sub-pixel SP(i+1) should be in the Nth frame (see...). Figure 5 During this period, there is a waveform with gate turn-off voltage Voff – gate turn-on voltage Von – gate turn-off voltage Voff.

[0277] In other words, the period during which the light-emitting element LE of the i-th sub-pixel SPi is initialized to the second initialization voltage Vint2 because the first transistor ST1 of the (i+1)-th sub-pixel SP(i+1) is turned on should be before the period during which the light-emitting element LE of the i-th sub-pixel SPi emits light because the seventh transistor ST7 and the eighth transistor ST8 of the i-th sub-pixel SPi are turned on.

[0278] Figure 21 This is a circuit diagram illustrating a sub-pixel according to yet another exemplary embodiment of the present disclosure.

[0279] Figure 21 Exemplary implementation methods and Figure 4 The difference in the exemplary implementation is that the gate electrode of the first transistor ST1 of the (i+1)th sub-pixel SP (i+1) is connected to the third scan line GB (i+1), instead of the first scan line GI (i+1) and the second scan line GW (i+1) connected to the (i+1)th sub-pixel SP (i+1). The following description will focus on the difference.

[0280] When the gate electrode of the first transistor ST1 of the (i+1)th sub-pixel SP(i+1) is connected to a third scan line GB(i+1) that is different from the first scan line GI(i+1) and the second scan line GW(i+1) connected to the (i+1)th sub-pixel SP(i+1), the first transistor ST1 of the (i+1)th sub-pixel SP(i+1) is connected to the light-emitting element LE of the i-th sub-pixel SPi. Therefore, before the emission signal applied to the i-th emission control line ELi connected to the i-th sub-pixel SPi has a gate on-state voltage Von, the scan signal applied to the third scan line GB(i+1) connected to the (i+1)th sub-pixel SP(i+1) should be in the Nth frame (see Figure 5 During this period, there is a waveform with gate turn-off voltage Voff – gate turn-on voltage Von – gate turn-off voltage Voff.

[0281] In other words, the period during which the light-emitting element LE of the i-th sub-pixel SPi is initialized to the second initialization voltage Vint2 because the first transistor ST1 of the (i+1)-th sub-pixel SP(i+1) is turned on should be before the period during which the light-emitting element LE of the i-th sub-pixel SPi emits light because the seventh transistor ST7 and the eighth transistor ST8 of the i-th sub-pixel SPi are turned on.

Claims

1. A display device, comprising: Multiple scan lines extending in a first direction; Multiple data lines extending in a second direction intersecting the first direction, wherein a data voltage is applied via the multiple data lines; A first initialization voltage line is used to apply a first initialization voltage. A second initialization voltage line, from which a second initialization voltage is applied; and Multiple sub-pixels, each of which is connected to at least one of the first initialization voltage line, the second initialization voltage line, at least one of the multiple scan lines, and at least one of the multiple data lines. Each of the plurality of sub-pixels includes: A driving transistor that controls a driving current flowing from a first electrode to a second electrode of the driving transistor based on the data voltage applied to the gate electrode of the driving transistor; A light-emitting element, wherein the light-emitting element is electrically connected to the second electrode of the driving transistor; A first transistor, the first transistor including a first electrode connected to the second initialization voltage line; and A second transistor and a third transistor, the second transistor and the third transistor being arranged in series between the first initialization voltage line and the second initialization voltage line, and Wherein, the second electrode of the first transistor of the (i+1)th sub-pixel arranged in the (i+1)th row among the plurality of sub-pixels is connected to the light-emitting element of the i-th sub-pixel arranged in the i-th row among the plurality of sub-pixels, where i is a positive integer, and Wherein, the (i+1)th sub-pixel and the i-th sub-pixel are connected to the same data line among the plurality of data lines. Wherein, the first initialization voltage line applies the first initialization voltage to the gate electrode of the driving transistor, and The second initialization voltage line applies the second initialization voltage to the anode of the light-emitting element.

2. The display device according to claim 1, wherein, The second transistor and the third transistor of the i-th sub-pixel are not turned on at the same time.

3. The display device according to claim 1, wherein, The gate electrode of the first transistor and the gate electrode of the second transistor of the (i+1)th sub-pixel are connected to the first scan line of the plurality of scan lines connected to the (i+1)th sub-pixel.

4. The display device according to claim 3, wherein, The gate electrode of the third transistor of the i-th sub-pixel is connected to the second scan line among the plurality of scan lines connected to the i-th sub-pixel, and wherein the scan signal applied to the first scan line connected to the (i+1)-th sub-pixel is the same as the scan signal applied to the second scan line connected to the i-th sub-pixel.

5. The display device according to claim 1, wherein, The gate electrode of the first transistor and the gate electrode of the third transistor of the i-th sub-pixel are connected to the second scan line of the plurality of scan lines connected to the i-th sub-pixel.

6. The display device according to claim 1, wherein, The gate electrode of the second transistor of the i-th sub-pixel is connected to a first scan line among the plurality of scan lines connected to the i-th sub-pixel, and the gate electrode of the third transistor of the i-th sub-pixel is connected to a second scan line among the plurality of scan lines connected to the i-th sub-pixel.

7. The display device according to claim 6, wherein, The gate electrode of the first transistor of the i-th sub-pixel is connected to the third scan line among the plurality of scan lines connected to the i-th sub-pixel.

8. The display device according to claim 1, further comprising: A plurality of emission control lines extend in the first direction and are arranged parallel to the plurality of scan lines, wherein each of the plurality of sub-pixels is connected to at least one of the plurality of emission control lines.

9. The display device according to claim 8, wherein, The gate electrode of the second transistor of the i-th sub-pixel is connected to the first scan line of the plurality of scan lines connected to the i-th sub-pixel, and the gate electrode of the third transistor of the i-th sub-pixel is connected to one of the plurality of emission control lines.

10. The display device according to claim 8, wherein, The gate electrode of the second transistor of the i-th sub-pixel is connected to one of the plurality of emission control lines, and the gate electrode of the third transistor of the i-th sub-pixel is connected to the first scan line of the plurality of scan lines connected to the i-th sub-pixel.

11. The display device according to claim 1, further comprising: Multiple driving voltage lines extending in the second direction; as well as Multiple transmission control lines, which extend in the first direction. Each of the plurality of sub-pixels is connected to at least one of the plurality of driving voltage lines and at least one of the plurality of emission control lines, and each of the plurality of sub-pixels further includes: A fourth transistor is disposed between the gate electrode of the driving transistor and the first initialization voltage line; A fifth transistor, wherein the fifth transistor is disposed between one of the plurality of data lines and the first electrode of the driving transistor; A sixth transistor, the sixth transistor being disposed between the gate electrode of the driving transistor and the second electrode of the driving transistor; A seventh transistor, the seventh transistor being disposed between one of the plurality of driving voltage lines and the first electrode of the driving transistor; An eighth transistor, the eighth transistor being disposed between the second electrode of the driving transistor and the first electrode of the light-emitting element; and A capacitor is disposed between one of the plurality of drive voltage lines and the gate electrode of the drive transistor.

12. The display device according to claim 11, wherein, The gate electrode of the first transistor, the gate electrode of the second transistor, and the gate electrode of the fourth transistor of the i-th sub-pixel are connected to the first scan line among the plurality of scan lines connected to the i-th sub-pixel. Wherein, the gate electrode of the third transistor, the gate electrode of the fifth transistor, and the gate electrode of the sixth transistor of the i-th sub-pixel are connected to the second scan line among the plurality of scan lines connected to the i-th sub-pixel. Wherein, the gate electrode of the first transistor of the (i+1)th sub-pixel is connected to the third scan line among the plurality of scan lines connected to the (i+1)th sub-pixel, and The same scan signal is applied to the second scan line connected to the i-th sub-pixel and the third scan line connected to the (i+1)-th sub-pixel.

13. The display device according to claim 11, wherein, The gate electrode of the first transistor, the gate electrode of the third transistor, and the gate electrode of the fourth transistor of the i-th sub-pixel are connected to the first scan line among the plurality of scan lines connected to the i-th sub-pixel. Wherein, the gate electrode of the second transistor, the gate electrode of the fifth transistor, and the gate electrode of the sixth transistor of the i-th sub-pixel are connected to the second scan line connected to the i-th sub-pixel among the plurality of scan lines. Wherein, the gate electrode of the first transistor of the (i+1)th sub-pixel is connected to the third scan line among the plurality of scan lines connected to the (i+1)th sub-pixel, and The same scan signal is applied to the second scan line connected to the i-th sub-pixel and the third scan line connected to the (i+1)-th sub-pixel.

14. The display device according to claim 11, wherein, The gate electrode of the first transistor, the gate electrode of the second transistor, and the gate electrode of the fourth transistor of the i-th sub-pixel are connected to the first scan line among the plurality of scan lines connected to the i-th sub-pixel. Wherein, the gate electrode of the fifth transistor and the gate electrode of the sixth transistor of the i-th sub-pixel are connected to the second scan line among the plurality of scan lines connected to the i-th sub-pixel. Wherein, the gate electrode of the first transistor of the (i+1)th sub-pixel is connected to the third scan line among the plurality of scan lines connected to the (i+1)th sub-pixel. Wherein, the gate electrode of the third transistor of the i-th sub-pixel is connected to one of the plurality of emission control lines, and The same scan signal is applied to the second scan line connected to the i-th sub-pixel and the third scan line connected to the (i+1)-th sub-pixel.

15. The display device according to claim 11, wherein, The gate electrode of the first transistor and the gate electrode of the fourth transistor of the i-th sub-pixel are connected to the first scan line of the plurality of scan lines connected to the i-th sub-pixel. Wherein, the gate electrode of the second transistor, the gate electrode of the fifth transistor, and the gate electrode of the sixth transistor of the i-th sub-pixel are connected to the second scan line connected to the i-th sub-pixel among the plurality of scan lines. Wherein, the gate electrode of the first transistor of the (i+1)th sub-pixel is connected to the third scan line among the plurality of scan lines connected to the (i+1)th sub-pixel. Wherein, the gate electrode of the third transistor of the i-th sub-pixel is connected to one of the plurality of emission control lines, and The same scan signal is applied to the second scan line connected to the i-th sub-pixel and the third scan line connected to the (i+1)-th sub-pixel.

16. The display device according to claim 11, wherein, The gate electrode of the first transistor, the gate electrode of the third transistor, and the gate electrode of the fourth transistor of the i-th sub-pixel are connected to the first scan line among the plurality of scan lines connected to the i-th sub-pixel. Wherein, the gate electrode of the fifth transistor and the gate electrode of the sixth transistor of the i-th sub-pixel are connected to the second scan line among the plurality of scan lines connected to the i-th sub-pixel. Wherein, the gate electrode of the first transistor of the (i+1)th sub-pixel is connected to the third scan line among the plurality of scan lines connected to the (i+1)th sub-pixel. Wherein, the gate electrode of the second transistor of the i-th sub-pixel is connected to one of the plurality of emission control lines, and The same scan signal is applied to the second scan line connected to the i-th sub-pixel and the third scan line connected to the (i+1)-th sub-pixel.

17. The display device according to claim 11, wherein, The gate electrode of the first transistor and the gate electrode of the fourth transistor of the i-th sub-pixel are connected to the first scan line of the plurality of scan lines connected to the i-th sub-pixel. Wherein, the gate electrode of the third transistor, the gate electrode of the fifth transistor, and the gate electrode of the sixth transistor of the i-th sub-pixel are connected to the second scan line among the plurality of scan lines connected to the i-th sub-pixel. Wherein, the gate electrode of the first transistor of the (i+1)th sub-pixel is connected to the third scan line among the plurality of scan lines connected to the (i+1)th sub-pixel. Wherein, the gate electrode of the second transistor of the i-th sub-pixel is connected to one of the plurality of emission control lines, and The same scan signal is applied to the second scan line connected to the i-th sub-pixel and the third scan line connected to the (i+1)-th sub-pixel.

18. A display device, comprising: A first initialization voltage line is used to apply a first initialization voltage. A second initialization voltage line is used to apply a second initialization voltage. as well as Multiple sub-pixels, each of which is connected to the first initialization voltage line and the second initialization voltage line. Each of the plurality of sub-pixels includes: A driving transistor that controls the driving current flowing from a first electrode to a second electrode of the driving transistor based on a data voltage applied to the gate electrode of the driving transistor; A light-emitting element, wherein the light-emitting element is electrically connected to the second electrode of the driving transistor; A first transistor, the first transistor including a first electrode connected to the second initialization voltage line; A second transistor and a third transistor, the second transistor and the third transistor being arranged in series between the first initialization voltage line and the second initialization voltage line; and A fourth transistor is disposed between the gate electrode of the driving transistor and the first initialization voltage line. Wherein, the second electrode of the first transistor of the (i+1)th sub-pixel arranged in the (i+1)th row among the plurality of sub-pixels is connected to the light-emitting element of the i-th sub-pixel arranged in the i-th row among the plurality of sub-pixels, where i is a positive integer, and At least one of the second transistor and the third transistor is turned off in each of the first time period, the second time period, and the third time period. The first initialization voltage is applied to the gate electrode of the driving transistor during the first time period, the data voltage is applied to the gate electrode of the driving transistor during the second time period, and the light-emitting element emits light during the third time period.

19. The display device according to claim 18, wherein, The second transistor and the fourth transistor of the i-th sub-pixel are turned on during the first time period. Wherein, the first transistor of the (i+1)th sub-pixel is turned on during the second time period, and The third transistor of the i-th sub-pixel is turned on during one of the second time period and the third time period.

20. The display device according to claim 18, wherein, The fourth transistor of the i-th sub-pixel is turned on during the first time period. Wherein, the second transistor of the i-th sub-pixel and the first transistor of the (i+1)-th sub-pixel are turned on during the second time period, and The third transistor of the i-th sub-pixel is turned on during one of the first time period and the third time period.

21. The display device according to claim 18, wherein, The fourth transistor of the i-th sub-pixel is turned on during the first time period. The first transistor of the (i+1)th sub-pixel is turned on during the second time period. Wherein, the second transistor of the i-th sub-pixel is turned on during the third time period, and The third transistor of the i-th sub-pixel is turned on during one of the first time period and the second time period.

22. A display device, comprising: Multiple scan lines; as well as A plurality of sub-pixels, each of the plurality of sub-pixels including a driving transistor, a plurality of transistors respectively connected to at least one of the plurality of scan lines, and a light-emitting element electrically connected to the driving transistor. The display device further includes: A first initialization voltage line, from which a first initialization voltage is applied; and A second initialization voltage line is used to apply a second initialization voltage. The driving transistor controls the driving current flowing from the first electrode to the second electrode of the driving transistor according to the data voltage applied to the gate electrode of the driving transistor; The plurality of transistors include: A first transistor, the first transistor including a first electrode connected to the second initialization voltage line; and A second transistor is disposed between the first transistor and the first initialization voltage line. The plurality of transistors further includes a third transistor disposed between the second transistor and the first initialization voltage line. The first initialization voltage line applies the first initialization voltage to the gate electrode of the driving transistor. The second initialization voltage line applies the second initialization voltage to the anode of the light-emitting element. Each of the plurality of sub-pixels includes an active layer, and the active layer includes a channel region, a first electrode, and a second electrode for each of the plurality of transistors. The first scan line among the plurality of scan lines includes a first extension extending in a first direction and a first protrusion extending in a second direction intersecting the first direction, and In the plan view, the active layer overlaps with the first protrusion.

23. The display device according to claim 22, wherein, The second scan line among the plurality of scan lines includes a second extension extending in the first direction and a second protrusion extending in the second direction, and In the plan view, the active layer overlaps with the second protrusion.

24. The display device according to claim 23, wherein, The active layer of the i-th sub-pixel among the plurality of sub-pixels is integral with the active layer of the (i+1)-th sub-pixel adjacent to the i-th sub-pixel in the second direction, where i is a positive integer.

25. The display device according to claim 23, wherein, The first length between the first protrusion and the second extension is different from the second length between the second protrusion and the first extension.

26. The display device according to claim 23, further comprising: A first initialization voltage line is used to apply a first initialization voltage. as well as A second initialization voltage line is used to apply a second initialization voltage. The driving transistor controls the driving current flowing from the first electrode to the second electrode of the driving transistor according to the data voltage applied to the gate electrode of the driving transistor; The plurality of transistors include: A first transistor, the first transistor including a first electrode connected to the second initialization voltage line; and The second transistor is disposed between the first transistor and the first initialization voltage line, and In the plan view, the area where the active layer and the first protrusion overlap is defined as the channel region of the second transistor.

27. The display device according to claim 26, wherein, The plurality of transistors further includes a third transistor disposed between the second transistor and the first initialization voltage line, and In the plan view, the area where the active layer and the second protrusion overlap are defined as the channel region of the third transistor.

28. The display device according to claim 27, further comprising: A first initialization voltage connection line, the first initialization voltage connection line being connected to the first initialization voltage line and extending in the second direction, and In the planar view, the active layer overlaps with the first initialization voltage connection line.

29. The display device according to claim 28, wherein, In the plan view, the channel region of the third transistor overlaps with the first initialization voltage connection line.

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