Semiconductor memory, refresh method, and electronic device

Abstract

This disclosure provides a semiconductor memory, a refresh method, and an electronic device. The semiconductor memory includes a main storage area and a marker storage area. The main storage area has multiple storage rows, and the marker storage area has multiple first flag bits. Each storage row corresponds to one first flag bit, and the first flag bit indicates whether the storage row is a victim row in a row hammering event. Thus, by adding a marker storage area to the semiconductor memory, victim rows in row hammering events can be marked using the first flag bits. By accurately locating the victim of row hammering and refreshing it, the handling effect of row hammering events is improved, and power consumption is saved.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor memory technology, and more particularly to a semiconductor memory, a refresh method, and an electronic device. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device in computers. It consists of many repeating memory cells, and different memory cells need to be selected via word lines and bit lines. In other words, DRAM contains a large number of word lines arranged adjacently. When a word line is subjected to a row hammer attack, the memory cells on adjacent word lines may become corrupted. To solve this problem, after a row hammer attack is detected, the word line needs to be refreshed. However, the refresh target is randomly determined, which does not significantly mitigate the row hammer attack and results in high power consumption. Summary of the Invention

[0003] This disclosure provides a semiconductor memory, a refresh method, and an electronic device, which can mark the affected row of a row hammering event through a first flag bit, thereby improving the handling effect of row hammering events.

[0004] The technical solution disclosed herein is implemented as follows:

[0005] In a first aspect, embodiments of this disclosure provide a semiconductor memory, the semiconductor memory including a main storage region and a tag storage region, the main storage region being provided with a plurality of storage rows, and the tag storage region being provided with a plurality of first flag bits; wherein each storage row corresponds to one of the first flag bits, and the first flag bit is used to indicate whether the storage row is the victim row of a row hammering event.

[0006] In some embodiments, the portion of the storage row extending into the marked storage area is used to form a first flag bit corresponding to the storage row; wherein the first flag bit occupies one storage unit.

[0007] In some embodiments, the semiconductor memory is configured to adjust a first flag bit of the storage row to a first state when it detects that the number of consecutive accesses of adjacent storage rows within a unit time exceeds a preset threshold; or, after performing a refresh operation on the storage row, adjust the first flag bit of the storage row to a second state and re-accumulate the number of consecutive accesses of the adjacent storage rows within the unit time.

[0008] In some embodiments, the plurality of storage rows are divided into several storage groups, and the marked storage area is further provided with several second flag bits; each storage group corresponds to one of the second flag bits, and the second flag bits are used to indicate at least whether at least one storage unit in the storage group has a specific state, the specific state including being occupied.

[0009] In some embodiments, each storage group includes a storage row, and the portion of the storage row extending into the marked storage area is used to form a second flag bit corresponding to the storage group; or, each storage group includes multiple storage rows, and the portion of one of the storage rows extending into the marked storage area is used to form a second flag bit corresponding to the storage group.

[0010] In some embodiments, the semiconductor memory is further configured to, upon receiving a memory allocation instruction for a memory cell, adjust the second flag bit of the memory group to a third state; or, upon receiving a memory release instruction for the memory group, adjust the second flag bit of the memory group to a fourth state; or, after performing a refresh operation on the memory group, adjust the second flag bit of the memory group to the fourth state; wherein the memory allocation instruction is a word line activation instruction or is constructed using a first reserved code in the memory controller, and the memory release instruction is constructed using a second reserved code in the memory controller.

[0011] In a second aspect, embodiments of this disclosure provide a refresh method applied to a semiconductor memory including multiple storage rows and multiple first flag bits, wherein one of the first flag bits is used to indicate whether a storage row is a victim row of a row hammering event, the method comprising:

[0012] Upon receiving the hammer refresh command, a target storage row is randomly selected from the multiple storage rows.

[0013] The first flag bit of the target storage line is read to obtain the reading result;

[0014] Based on the read result, determine whether to refresh the target storage row.

[0015] In some embodiments, determining whether to refresh the target storage row based on the read result includes:

[0016] When the first flag bit is in the first state, the target storage line is refreshed;

[0017] When the first flag is in the second state, the target storage line is not refreshed; and one of the following steps is performed: terminate the execution of the hammer refresh instruction, or determine a new target storage line and return to the step of reading the first flag of the target storage line.

[0018] In some embodiments, the method further includes:

[0019] After detecting that the number of consecutive accesses to adjacent storage rows within a unit time exceeds a preset threshold, the first flag bit of the storage row is adjusted to a first state; after refreshing the storage row, the first flag bit of the storage row is adjusted to a second state, and the number of consecutive accesses to adjacent storage rows within a unit time is re-accumulated.

[0020] In some embodiments, the semiconductor memory further includes a second flag bit, the plurality of memory rows are divided into several memory groups, and one of the second flag bits is used to indicate at least one memory cell in one of the memory groups whether it is in a specific state, the specific state including being occupied; before refreshing the target memory row, the method further includes:

[0021] Read the second flag bit of the storage group to which the target storage row belongs;

[0022] If the second flag is in the third state, the target storage line is refreshed; if the second flag is in the fourth state, the target storage line is not refreshed; and one of the following steps is executed: terminate the execution of the hammer refresh instruction, or determine a new target storage line and return to the step of reading the first flag of the target storage line.

[0023] In some embodiments, the method further includes:

[0024] Upon receiving a memory allocation instruction, the second flag bit of the storage group corresponding to the memory allocation instruction is adjusted to a third state; upon receiving a memory release instruction, the second flag bit of the storage group corresponding to the memory release instruction is adjusted to a fourth state; or, after refreshing the storage group, the second flag bit of the storage group is adjusted to the fourth state; wherein, the memory allocation instruction is a word line activation instruction or is constructed using a first reserved code in the memory controller; the memory release instruction is constructed using a second reserved code in the memory controller.

[0025] Thirdly, embodiments of this disclosure provide a refresh method applied to a semiconductor memory including multiple storage rows and multiple first flag bits, wherein one of the first flag bits is used to indicate whether a storage row is a victim row of a row hammering event, the method comprising:

[0026] Upon receiving the hammer refresh command, the first flag bit of multiple storage rows is read to obtain the reading result;

[0027] Based on the read results, candidate storage lines are determined from among the multiple storage lines;

[0028] Randomly select a storage row to be refreshed from the candidate storage rows, and perform refresh processing on the storage row to be refreshed.

[0029] In some embodiments, determining candidate storage rows among the plurality of storage rows based on the read results includes:

[0030] The storage line whose first flag bit is in the first state is determined as the candidate storage line.

[0031] In some embodiments, the semiconductor memory further includes a second flag bit, the plurality of memory rows are divided into several memory groups, and one of the second flag bits is used to indicate at least one memory cell in one of the memory groups whether it is in a specific state, the specific state including being occupied; before refreshing the memory row to be refreshed, the method further includes:

[0032] The second flag bit of the storage group to which the storage line to be refreshed belongs is read; if the second flag bit is in the third state, the step of refreshing the storage line to be refreshed is executed; if the second flag bit is in the fourth state, the storage line to be refreshed is not refreshed; and one of the following steps is executed: the execution of the hammer refresh instruction is terminated, or a new storage line to be refreshed is determined and the step of reading the second flag bit of the storage group to which the storage line to be refreshed belongs is returned.

[0033] In some embodiments, the semiconductor memory further includes a second flag bit, wherein the plurality of memory rows are divided into several memory groups, and one of the second flag bits is used to indicate at least whether at least one memory cell in one of the memory groups is in a specific state, the specific state including being occupied; the step of determining candidate memory rows among the plurality of memory rows based on the read result includes:

[0034] The storage line with the first flag bit in the first state is identified as the victim storage line;

[0035] Read the second flag bit of the storage group to which the victim storage row belongs;

[0036] When the second flag bit is in the third state, the victimized storage line is identified as the candidate storage line.

[0037] Fourthly, embodiments of this disclosure provide an electronic device including a semiconductor memory as described in the first aspect.

[0038] This disclosure provides a semiconductor memory, a refresh method, and an electronic device. The semiconductor memory includes a main storage area and a marker storage area. The main storage area has multiple storage rows, and the marker storage area has multiple first flag bits. Each storage row corresponds to one first flag bit, and the first flag bit indicates whether the storage row is a victim row in a row hammering event. Thus, by adding a marker storage area to the semiconductor memory, victim rows in row hammering events can be marked using the first flag bits. By accurately locating the victim of row hammering and refreshing it, the handling effect of row hammering events is improved, and power consumption is saved. Attached Figure Description

[0039] Figure 1 This is a schematic diagram of the structure of a semiconductor memory provided in an embodiment of the present disclosure;

[0040] Figure 2 A schematic diagram of a specific structure of a semiconductor memory provided in this disclosure embodiment. Figure 1 ;

[0041] Figure 3 This is a schematic diagram of another semiconductor memory structure provided in an embodiment of the present disclosure;

[0042] Figure 4 A schematic diagram of a specific structure of a semiconductor memory provided in this disclosure embodiment. Figure 2 ;

[0043] Figure 5 A schematic diagram of a specific structure of a semiconductor memory provided in this disclosure embodiment. Figure 3 ;

[0044] Figure 6 A flowchart illustrating a refresh method provided in this embodiment of the disclosure. Figure 1 ;

[0045] Figure 7 A flowchart illustrating a refresh method provided in this embodiment of the disclosure. Figure 2 ;

[0046] Figure 8 A flowchart illustrating a refresh method provided in this embodiment of the disclosure. Figure 3 ;

[0047] Figure 9A flowchart illustrating a refresh method provided in this embodiment of the disclosure. Figure 4 ;

[0048] Figure 10 A flowchart illustrating a refresh method provided in this embodiment of the disclosure. Figure 5 ;

[0049] Figure 11 A flowchart illustrating a refresh method provided in this embodiment of the disclosure. Figure 6 ;

[0050] Figure 12 This is a schematic diagram of the composition structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0051] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely for explaining the relevant applications and are not intended to limit the applications. Furthermore, it should be noted that, for ease of description, only the parts relevant to the relevant applications are shown in the accompanying drawings.

[0052] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to be limiting of this disclosure.

[0053] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0054] It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are only used to distinguish similar objects and do not represent a specific order of objects. It is understood that "first, second, third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0055] Currently, for volatile memory, the increasing density of memory cells and the decreasing distance between memory rows lead to increased capacitive coupling between adjacent rows. In this situation, repeatedly activating a particular memory row (called a hammered row) can cause electromagnetic interference to adjacent rows (also called victim rows), resulting in data loss in the victim row before the next refresh. This phenomenon is known as row hammering. Row hammering can cause data errors without accessing the target memory region, so victim rows in row hammering events need to be refreshed periodically to prevent data corruption.

[0056] Specifically, when a certain area is detected to be hit by a row hammer, a random word line in that area needs to be refreshed. In other words, the semiconductor memory cannot accurately locate the target of the attack, resulting in poor handling effect and high power consumption.

[0057] Based on this, the present disclosure provides a semiconductor memory. Since a marker storage area is added to the semiconductor memory, the victim row of a row hammering event can be marked by a first flag bit. By accurately locating the victim of the row hammering and refreshing it, the handling effect of the row hammering event is improved and power consumption is saved.

[0058] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0059] In one embodiment of this disclosure, see Figure 1 This illustrates a schematic diagram of the structure of a semiconductor memory 10 provided in an embodiment of this disclosure. For example... Figure 1 As shown, the semiconductor memory 10 includes a main memory region 11 and a tag memory region 12. Multiple memory rows (e.g., ...) are configured in the main memory region 11. Figure 1 Storage rows 111, 112, etc., are marked in storage area 12 with multiple first flag bits (e.g., ...). Figure 1 The first flag bit 121, the first flag bit 122, etc. are in the storage row; where each storage row corresponds to a first flag bit, and the first flag bit is used to indicate whether the storage row is the victim row of the row hammering event.

[0060] It should be noted that the semiconductor memory 10 can be a volatile memory, such as dynamic random access memory (DRAM).

[0061] In this embodiment of the disclosure, a new marker storage area 12 is added to the semiconductor memory 10 to record whether each storage line in the main storage area 11 is a victim line in a row hammering event, which can accurately locate the victim of the row hammering event and improve the handling effect of the row hammering event.

[0062] It should be understood that a semiconductor memory includes multiple different memory arrays (banks). In one case, a portion of each memory array belongs to the main memory region 11, and another portion of each memory array belongs to the tag memory region 12. In another case, a portion of the memory array is used as the main memory region 11, and another portion of the memory array is used as the tag memory region 12.

[0063] In some embodiments, the portion of a storage row extending into the marked storage area 12 is used to form a first flag bit corresponding to the storage row; wherein the first flag bit occupies one storage unit.

[0064] For example, see Figure 2 This illustrates a schematic diagram of the structure of a semiconductor memory provided in an embodiment of this disclosure. Specifically, Figure 2 The diagram illustrates the structure of a memory array in a semiconductor memory; each memory row (or word line) is represented by a Row, each memory column by a Col (or bit line), and the subscript of the memory row or column represents a number. In embodiments of this disclosure, each number is used only to identify the respective memory row or column and does not constitute any positional limitation. Furthermore, the intersection of each memory row and column can be considered as the presence of a memory cell.

[0065] like Figure 2 As shown, the storage row j With bit line Col m Forming a storage row j The first flag bit stores the row. j+1 With bit line Col m Forming a storage row j+1 The first flag bit... others can be understood by referring to the above. In this way, the first flag bit in the tag storage area shares the same storage row as the main storage area. In other embodiments, the main storage area and the tag storage area can be two relatively independent areas, and the flag bits in the tag storage area do not share the same storage row as the main storage area.

[0066] It should be noted that, as Figure 1 or Figure 2 As shown, there is no specific positional relationship between the main storage area 11 and the tag storage area 12. For example, the tag storage area 12 can be located outside the main storage area 11 to store rows. j For example, bit line Col m Located at bit line Col i Far from the bit line Col i+n One side, or bit line Col m Located at bit line Col i+n Far from the bit line Col iOne side; for example, the marker storage area 12 can be set within the main storage area 11 to store rows. j For example, bit line Col m Located at bit line Col i and bit line Col i+n between.

[0067] It should also be noted that a memory array can have 1024 bit lines belonging to the main memory region and 1 bit line belonging to the marker memory region. That is, the ratio of bit lines in the main memory region to the marker memory region is 1024:1, and the area of ​​the marker memory region accounts for less than 0.1%, so setting the marker memory region has a very small impact on the chip area.

[0068] In some embodiments, the semiconductor memory 10 is configured to adjust the first flag bit of a storage row to a first state when it detects that the number of consecutive accesses of adjacent storage rows within a unit time exceeds a preset threshold; or, after performing a refresh operation on the storage row, adjust the first flag bit of the storage row to a second state and re-accumulate the number of consecutive accesses of adjacent storage rows within a unit time.

[0069] Here, adjacent storage lines can refer to multiple storage lines that are adjacent to the storage line. For example, if the storage line is denoted as the i-th line, then the adjacent storage lines can be the (i+a)-(ia)-th storage line, where a and i are both positive integers. Generally, i is less than or equal to 3.

[0070] Specifically, for a given storage row, the number of consecutive accesses of its adjacent storage rows (as storage row 1) and its adjacent storage rows (as storage row 2) can differ. This is because storage row 1 and storage row 2 are refreshed at different times, and their performance may also differ. Within acceptable error limits, for a given storage row, only one consecutive access count can be determined, thereby reducing computational complexity and power consumption.

[0071] In some embodiments, such as Figure 3 As shown, multiple storage rows are divided into several storage groups (e.g., Figure 3 The storage group 131, storage group 132, etc., and the marked storage area 12 are also provided with several second flag bits (e.g. Figure 2 The second flag bit 141, second flag bit 142, etc. in the storage group; each storage group has a corresponding relationship with a second flag bit, and the second flag bit is used to indicate at least one storage cell in the storage group whether it has a specific state, including being occupied.

[0072] It should be noted that the number of storage rows in a storage group needs to be determined based on the actual application scenario. Theoretically, the number of storage rows in each storage group should be the same, but it can differ in special cases. It should be understood that... Figure 3 In this context, each storage group includes two storage rows. For example, storage group 131 includes storage rows 111 and 112, and storage group 132 includes storage rows 113 and 114. However, in actual application scenarios, there may be more or fewer rows.

[0073] It should be noted that the second flag is used to record the status information of the storage group. Here, a specific status includes at least being occupied, but can also include being damaged, locked, released, etc. Furthermore, the occupancy of a storage unit can have different definitions in different application scenarios. For example, being occupied means that the storage unit has been allocated to a user for use, or that the storage unit contains valid data.

[0074] Thus, in a row hammering event, if the affected row is occupied, it needs to be refreshed to prevent data loss; if the affected row is not occupied, it does not need to be refreshed, saving power consumption.

[0075] It should be understood that there is no restrictive relationship between the positions of the first flag bit and the second flag bit. For example, the first flag bit can be adjacent to the second flag bit, or the flag storage area 12 can be divided into two completely independent areas, one area for forming the first flag bit and the other area for forming the second flag bit.

[0076] In some embodiments, each storage group includes a storage line, and the portion of the storage line extending into the marked storage area 12 is used to form a second flag bit corresponding to the storage group.

[0077] Assuming the second flag occupies one memory unit, in Figure 2 Based on, Figure 4 For example, let's explain in detail: Storage Row j With bit line Col i ~Col i+n The resulting storage units constitute a storage group, and storage rows are called Rows. j With bit line Col m+1 Form the second flag bit of this storage group; storage row j+1 With bit line Col i ~Col i+n The resulting storage units constitute another storage group, storage row. j+1 With bit line Col m+1 This forms the second flag bit of the memory group; the others can be understood similarly.

[0078] In other embodiments, each storage group includes multiple storage rows, and one of the storage rows extends into the marked storage area 12 to form a second flag bit corresponding to the storage group.

[0079] Assuming the second flag occupies one memory unit, in Figure 2 Based on, Figure 5 For example, let's explain in detail: Storage Row j ~Row j+a With bit line Col i ~Col i+n The resulting storage units constitute a storage group, and storage rows are called Rows. j With bit line Col m+1 Form the second flag bit of this storage group; storage row j+a+1 ~Row j+2a+1 With bit line Col i ~Col i+n The resulting storage units constitute another storage group, storage row. j+a+1 With bit line Col m+1 This forms the second flag of the storage group; other flags can be understood similarly. Additionally, to avoid wasting storage space, storage rows... j+1 ~Row j+a With bit line Col m+1 This will also form corresponding storage units, which can be attributed to the main storage area.

[0080] Thus, as Figure 4 or Figure 5 As shown, the second flag bit in the marked storage area shares the same storage row as the main storage area; in other embodiments, the second flag bit in the marked storage area may not share the same storage row as the main storage area, for example, by setting up a separate storage array for marking.

[0081] It should be noted that, as Figure 4 or Figure 5 As shown, the bit line Col in the marked storage area m and bit line Col m+1 It can be set on an outer side of the main memory area; or, bit line Col m and bit line Col m+1 They can be set on opposite sides of the main storage area. In this case, the first and second flag bits not only serve as identifiers but also protect the internal storage units. That is, when the storage array is damaged, the flagged storage area will be damaged first, rather than the main storage area, thus ensuring the effectiveness of basic functions; or, the bit line Col m and bit line Col m+1It can be set inside the main storage area. In this case, when the storage array is damaged, the main storage area will be damaged first instead of the marked storage area. However, the main storage area is usually equipped with a redundant area for replacement in case of damage, so as to avoid the marked storage area from becoming unusable.

[0082] It should be noted that when a specific state includes at least two states, each second flag bit includes at least two identifiers, and different identifiers are used to indicate different specific states; each identifier occupies one storage unit. That is to say, a second flag bit can occupy more storage units, depending on the type of specific state.

[0083] It should be noted that, as Figure 4 or Figure 5 As shown, when each storage group includes one storage row, the marker storage region may have at least three bit lines, such that the portion of each storage row extending into the marker storage region can form at least two identifiers of the first flag bit and the second flag bit. Alternatively, when each storage group includes multiple storage rows, the marker storage region may have at least two bit lines, such that the portion of each storage row in each storage group extending into the marker storage region can form a first flag bit with the first bit line, and the portions of at least two storage rows in each storage group extending into the marker storage region can form at least two identifiers of the second flag bit with the second bit line.

[0084] In some embodiments, the state of the second flag bit can be defined using existing instructions / operations in the DRAM. For example, the semiconductor memory 10 is further configured to, upon receiving a memory allocation instruction for a memory cell, adjust the second flag bit of the memory group to which the memory cell belongs to a third state, wherein the memory allocation instruction may be a word line activation instruction Active; or, after performing a refresh operation on the memory group, adjust the second flag bit of the memory group to a fourth state.

[0085] Thus, upon receiving the word line activation instruction "Active", the semiconductor memory 10 activates the specified memory row and adjusts the second flag bit corresponding to that memory row to the third state. Furthermore, upon receiving a refresh instruction, after performing a refresh operation on a memory group, the semiconductor memory 10 adjusts the second flag bit of that memory group to the fourth state. This eliminates the need to define additional state control instructions for the second flag bit, saving signaling resources.

[0086] It should be noted that in other embodiments, after refreshing the storage group, the flag bit of the storage group may not be adjusted, meaning the flag bit of the storage group may remain in the third state. Which operation to perform can be defined by the user or defined at the factory based on the usage scenario. For example, if the storage group will experience read / write operations within a preset time after the refresh, it can be adjusted to a write state after the refresh. If the storage group may not experience read / write operations within the preset time after the refresh, it may be maintained in the third state after the refresh. Both approaches must adhere to the principle of ensuring that the address specified by the memory allocation instruction does not permanently fail to refresh due to the flag bit adjustment. Read / write operations on the storage group will flip the flag bit to the third state, or the flag bit will automatically flip to the third state within a preset time after no read / write operations occur, to ensure timely refresh of the storage group. It is understood that the preset time can be set according to the failure characteristics of the storage group; for example, the slower the leakage rate, the longer the preset time. In other embodiments, the state of the second flag bit can be constructed based on the memory allocation / deletion functions in the DRAM. For example, the semiconductor memory 10 is further configured to, upon receiving a memory allocation instruction for a memory cell, adjust the second flag bit of the memory group to which the memory cell belongs to a third state, wherein the memory allocation instruction is constructed using a first reservation code in the memory controller; or, upon receiving a memory release instruction for the memory group, adjust the second flag bit of the memory group to a fourth state, wherein the memory release instruction is constructed using a second reservation code in the memory controller.

[0087] It should be understood that the semiconductor memory 10 contains several mode registers. Each mode register contains an opcode (OP) to provide different control functions. Some common opcodes are defined by industry standards. Additionally, the mode registers also contain some unused reserved codes (RFUs). These reserved codes can be used to construct entirely new Allocate instructions as memory allocation instructions and entirely new Release instructions as memory release instructions.

[0088] It is important to emphasize that the memory allocation instruction `Allocate` and the memory release instruction `Release` in this case are not software-implemented functions, but rather actual instructions that interact with signals within the memory. These instructions are not specified in the existing memory industry standard JEDEC. If existing memory is required to support these instructions, it must be noted in the corresponding JEDEC. Therefore, it can be assumed that existing memory conforming to the JEDEC standard does not support this hardware function, while this proposal is the first to support and utilize this instruction. Thus, during the operation of the semiconductor memory, a portion of memory can be allocated using the `Allocate` instruction, and the second flag bit of the memory group corresponding to the allocated memory region can be adjusted to the third state based on the `Allocate` instruction. Similarly, a portion of memory can be released using the `Release` instruction, and the second flag bit of the memory group corresponding to the released memory region can be adjusted to the fourth state based on the `Release` instruction. This allows for more precise adjustment of the standard bit state, ensuring accurate execution of refresh operations.

[0089] In some other embodiments, the semiconductor memory 10 is further configured to, upon receiving a memory allocation instruction for a memory cell, adjust the second flag bit of the memory group to a third state, wherein the memory allocation instruction is a word line activation instruction (Active); or, upon receiving a memory release instruction for the memory group, adjust the second flag bit of the memory group to a fourth state, wherein the memory release instruction is constructed using a second reservation code in the memory controller. Thus, after activation and before release, the corresponding second flag bit is always in the third state, which can more accurately identify whether there are occupied memory cells in the memory group.

[0090] In the foregoing description, the first state means that the first flag bit stores data 1, and the second state means that the first flag bit stores data 0; or, the first state means that the first flag bit stores data 0, and the second state means that the first flag bit stores data 1.

[0091] The third state means that the second flag bit (or the corresponding identifier in the second flag bit) stores the data 1, and the fourth state means that the second flag bit (or the corresponding identifier in the second flag bit) stores the data 0; or, the third state means that the second flag bit (or the corresponding identifier in the second flag bit) stores the data 0, and the fourth state means that the second flag bit (or the corresponding identifier in the second flag bit) stores the data 1.

[0092] In summary, the embodiments of this disclosure provide a novel storage structure. Since a marker storage area is added to the semiconductor memory, the victim row of a row hammering event can be marked by the first flag bit. By accurately locating the victim of the row hammering and refreshing it, the handling effect of the row hammering event is improved and power consumption is saved.

[0093] In another embodiment of this disclosure, see Figure 6 The diagram illustrates a flowchart of a refresh method provided in an embodiment of this disclosure. Figure 6 As shown, the method may include:

[0094] S21: After receiving the hammer refresh command, randomly determine the target storage line from multiple storage lines.

[0095] S22: Read the first flag bit of the target storage line to obtain the reading result.

[0096] S23: Based on the read results, determine whether to refresh the target storage row.

[0097] It should be noted that the refresh method provided in this disclosure is applied to a semiconductor memory including multiple storage rows and multiple first flag bits. A first flag bit is associated with a storage row, and a first flag bit is used to indicate whether a storage row is the victim row of a row hammering event. For details, please refer to the foregoing. Figure 1 or Figure 2 .

[0098] Here, the number of target storage rows can be one or more.

[0099] In particular, in this embodiment of the disclosure, "random" is a macroscopic concept, which also includes some pseudo-random mechanisms.

[0100] Thus, this embodiment of the present disclosure provides a low-power row hammer refresh method. After receiving the hammer refresh instruction, the first flag bit of the target storage row can be used to determine whether the target storage row is the victim row in the row hammer event, and then decide whether to refresh the target storage row. This can improve the handling effect of the row hammer event and reduce power consumption.

[0101] In some embodiments, such as Figure 7 As shown, for step S22, if the first flag bit is in the first state, then step S231 is executed; if the first flag bit is in the second state, then step S2321 is executed.

[0102] S231: Perform a refresh process on the target storage row.

[0103] S2321: Do not refresh the target storage line, and end the execution of the hammer refresh instruction.

[0104] In other embodiments, such as Figure 7 As shown, for step S22, if the first flag bit is in the second state, step S2322 can also be executed.

[0105] S2322: Do not refresh the target storage row, determine a new target storage row, and return to step S22.

[0106] In other words, if the first flag is in the first state, it indicates that the target stored line is the victim line in the row hammering event and needs to be refreshed. If the first flag is in the second state, it indicates that the target stored line is not the victim line in the row hammering event and does not need to be refreshed, thus saving power. Furthermore, if the target stored line is not refreshed, there can be at least two different processing mechanisms: (1) wait, see step S2321; (2) skip, see step S2322.

[0107] It should be understood that if the random determination operation determines multiple target storage rows at once, the waiting mechanism or the skip mechanism will only be executed if the first flag bit of all target storage rows is in the second state.

[0108] It should be noted that when determining a new target storage line, it can be randomly determined again from multiple storage lines, or the next storage line of the original target storage line can be used as the new target storage line.

[0109] In some embodiments, the method further includes: after detecting that the number of consecutive accesses of adjacent storage rows within a unit time exceeds a preset threshold, adjusting the first flag bit of the storage row to a first state; after refreshing the storage row, adjusting the first flag bit of the storage row to a second state, and re-accumulating the number of consecutive accesses of adjacent storage rows within a unit time.

[0110] In some embodiments, as described above Figures 3-5 As shown, the semiconductor memory also includes a second flag bit, the multiple storage rows are divided into several storage groups, and a second flag bit is used to indicate whether at least one storage cell in a storage group is in a specific state, including being occupied.

[0111] Therefore, as Figure 8 As shown, when the first flag bit of the target storage line is in the first state, the method further includes:

[0112] S24: Read the second flag bit of the storage group to which the target storage line belongs.

[0113] Here, for step S24, if the second flag is in the third state, then step S231 is executed; if the second flag is in the fourth state, then step S2321 is executed.

[0114] S231: Perform a refresh process on the target storage row.

[0115] S2321: Do not refresh the target storage line, and end the execution of the hammer refresh instruction.

[0116] In other embodiments, such as Figure 8 As shown, for step S24, if the second flag bit is in the fourth state, step S2322 can also be executed.

[0117] S2322: Do not refresh the target storage row, determine a new target storage row, and return to step S22.

[0118] It should be noted that if the second flag is in the third state, it means that the target storage line may be occupied and needs to be refreshed; if the second flag is in the fourth state, it means that the target storage line is definitely not occupied and does not need to be refreshed, thus saving power. Furthermore, in the case of not refreshing the target storage line, there can be at least two different processing mechanisms: (1) wait: see step S2321; (2) skip: see step S2322.

[0119] In other words, for the "wait" mechanism, each hammer refresh instruction may not necessarily result in a refresh operation; for the "skip" mechanism, each hammer refresh instruction will definitely result in a refresh operation. Additionally, the following special case may exist in semiconductor memory: only the storage row... i It is the victim row in the hammering incident, but the stored row is... i If the memory is not occupied, there are actually no memory rows that need to be refreshed in the semiconductor memory. For the "skip" mechanism, this would prevent the semiconductor memory from ending the hammer refresh instruction, or in other words, it would determine that adjacent memory rows of several consecutive target memory rows do not need to be refreshed, resulting in an excessively long execution time for the hammer refresh command. Therefore, for semiconductor memories using the "skip" mechanism, an auxiliary termination mechanism can be set: even if no refresh processing is performed within a certain time after receiving the hammer refresh instruction, the hammer refresh instruction is considered to have ended. In some embodiments, the method further includes: after receiving a memory allocation instruction, adjusting the second flag bit of the memory group corresponding to the memory allocation instruction to a third state; after performing refresh processing on the memory group, adjusting the second flag bit of the memory group to a fourth state. Here, the memory allocation instruction can be a word line activation instruction (Active).

[0120] It should be noted that the refresh process can be executed according to the aforementioned hammer refresh command, or it can be executed according to other commands (such as periodic refresh commands).

[0121] In other embodiments, the method further includes: after receiving a memory allocation instruction, adjusting the second flag bit of the memory group corresponding to the memory allocation instruction to a third state; and after receiving a memory release instruction, adjusting the second flag bit of the memory group corresponding to the memory release instruction to a fourth state. In this case, the memory allocation instruction is an Allocate instruction constructed using a first reservation code, and the memory release instruction is a Release instruction constructed using a second reservation code.

[0122] In some other embodiments, the method further includes: after receiving a memory allocation instruction for a memory cell, adjusting the second flag bit of the memory group to which the memory cell belongs to a third state, wherein the memory allocation instruction may be a word line activation instruction (Active). After receiving a memory release instruction, adjusting the second flag bit of the memory release instruction corresponding to the memory release instruction to a fourth state, wherein the memory release instruction is a Release instruction constructed using a second reservation code.

[0123] Thus, this disclosure provides a novel hammer refresh method that can accurately locate the affected object during the hammer refresh process. Furthermore, it avoids refreshing memory rows in a storage array (bank) that have never been accessed (i.e., are not occupied), thereby improving the handling effect of row hammer events and reducing refresh power consumption. Additionally, the refresh method provided in this disclosure can be combined with the memory allocation / release function in DRAM to perform refresh operations with even higher accuracy.

[0124] In summary, the embodiments of this disclosure provide a hammer refresh method applied to a semiconductor memory with marked storage areas. A first flag bit can be used to locate the affected row in a row hammer event, enabling precise refresh of the affected row, improving the handling effect of row hammer events and reducing power consumption. Furthermore, a second flag bit can indicate whether the affected row is occupied; unoccupied affected rows are not refreshed, saving power consumption.

[0125] In yet another embodiment of this disclosure, see [link to relevant documentation]. Figure 9 The diagram illustrates a flowchart of a refresh method provided in an embodiment of this disclosure. Figure 9 As shown, the method may include:

[0126] S41: After receiving the hammer refresh command, read the first flag bit of multiple storage lines to obtain the read result.

[0127] S42: Based on the read results, determine the candidate storage line from multiple storage lines.

[0128] S43: Randomly select the storage row to be refreshed from the candidate storage rows.

[0129] S44: Perform refresh processing on the stored row to be refreshed.

[0130] It should be noted that the refresh method provided in this disclosure is applied to a semiconductor memory including multiple storage rows and multiple first flag bits. Each first flag bit is used to indicate whether a storage row is the victim row of a row hammer event, as described above. Figure 1 or Figure 2 As shown.

[0131] It should be noted that there is no limit to the number of storage rows to be refreshed; it can be one or more rows.

[0132] In some embodiments, such as Figure 10 As shown, the candidate stored row refers to the victim row in the row hammering event. Step S42 may specifically include:

[0133] S421: Determine the storage line whose first flag bit is in the first state as a candidate storage line.

[0134] Thus, this embodiment of the present disclosure provides a low-power row hammer refresh method. After receiving the hammer refresh instruction, the affected rows of the row hammer event can be filtered according to the first flag bit of the stored row, and then the refresh process can be performed, which can improve the handling effect of the row hammer event and reduce power consumption.

[0135] As mentioned above Figures 3-5 As shown, the semiconductor memory also includes a second flag bit, the multiple storage rows are divided into several storage groups, and a second flag bit is used to indicate whether at least one storage cell in a storage group is in a specific state, including being occupied.

[0136] Therefore, in some embodiments, such as Figure 10 As shown, after step S43, the method may further include:

[0137] S45: Read the second flag bit of the storage group to which the storage row to be refreshed belongs.

[0138] Here, for step S45, if the second flag is in the third state, then step S44 is executed; if the second flag is in the fourth state, then step S461 is executed.

[0139] S44: Perform refresh processing on the stored row to be refreshed.

[0140] S461: Do not refresh the stored line to be refreshed, and end the execution of the hammer refresh command.

[0141] In other embodiments, such as Figure 10 As shown, for step S45, if the second flag is in the fourth state, step S462 can also be executed.

[0142] S462: Do not refresh the storage row to be refreshed, determine a new storage row to be refreshed, and return to step S44.

[0143] Similarly, a new storage line to be refreshed can be randomly determined from the candidate storage lines, or the next storage line in the candidate storage lines that follows the original storage line to be refreshed can be determined as the new storage line to be refreshed.

[0144] Thus, if the second flag is in the third state, it indicates that the storage line to be refreshed may be occupied and needs to be refreshed; if the second flag is in the fourth state, it indicates that the storage line to be refreshed is definitely not occupied and does not need to be refreshed, thus saving power. Similarly, when not performing refresh processing on the storage line to be refreshed, there can be at least two different processing mechanisms: (1) wait: see step S461; (2) skip: see step S462.

[0145] Similarly, for semiconductor memories that employ a skip mechanism, an auxiliary termination mechanism can also be set, as described above.

[0146] It should be noted that if the candidate storage row is the victim row of the row hammer event, the candidate storage row can also be screened a second time according to the second flag bit to determine the occupied victim row before the refresh operation is performed.

[0147] Accordingly, in some embodiments, such as Figure 11 As shown, step S42 may specifically include:

[0148] S4221: The storage line whose first flag bit is in the first state is identified as the victim storage line.

[0149] S4222: Read the second flag bit of the storage group to which the victim storage line belongs.

[0150] S4223: When the second flag bit is in the third state, the victimized storage line is identified as a candidate storage line.

[0151] In this way, the range of candidate storage lines can be further narrowed by using the second flag bit. That is, the secondary candidate storage lines refer to the storage lines that are "victims of the row hammering event" and "occupied". Therefore, a row randomly selected from the secondary candidate lines can be refreshed directly.

[0152] In summary, the embodiments of this disclosure provide a hammer refresh method applied to a semiconductor memory with a marked storage area. The first flag bit can accurately locate the victim row in a row hammer event, improving the handling effect of the row hammer event and reducing power consumption. At the same time, the second flag bit can determine whether the victim row is occupied, thereby deciding whether to refresh the victim row and saving power consumption.

[0153] In yet another embodiment of this disclosure, see [link to relevant documentation]. Figure 12 This illustrates a structural schematic diagram of an electronic device 50 provided in an embodiment of this disclosure. For example... Figure 12 As shown, the electronic device 50 may include the aforementioned semiconductor memory 10.

[0154] In this embodiment of the disclosure, the semiconductor memory 10 can be a DRAM chip.

[0155] This disclosure provides an electronic device 50, which includes a semiconductor memory 10. The semiconductor memory 10 has a newly added marker storage area. The victim row of a row hammering event can be marked by a first flag bit. By accurately locating the victim of the row hammering and refreshing it, the handling effect of the row hammering event is improved and power consumption is saved.

[0156] The above are merely preferred embodiments of this disclosure and are not intended to limit the scope of protection of this disclosure.

[0157] It should be noted that, in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0158] The sequence numbers of the embodiments disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0159] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments or device embodiments without conflict.

[0160] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A semiconductor memory, characterized in that, The semiconductor memory includes a main memory region and a tag memory region. The main memory region has multiple memory rows, and the tag memory region has multiple first flag bits. Each of the stored rows corresponds to a first flag bit, and the first flag bit is used to indicate whether the stored row is the victim row of the row hammering event; The multiple storage rows are divided into several storage groups, and the marked storage area is also provided with several second flag bits; Each of the storage groups corresponds to a second flag bit, and the second flag bit is used to indicate at least whether at least one storage cell in the storage group has a specific state, the specific state including being occupied; The semiconductor memory is further configured to, upon receiving a memory allocation instruction for a memory cell, adjust the second flag bit of the memory group to which the memory cell belongs to a third state; or, Upon receiving a memory release instruction for the memory group, the second flag bit of the memory group is adjusted to the fourth state; or, After refreshing the storage group, the second flag bit of the storage group is adjusted to the fourth state; The memory allocation instruction is either a word line activation instruction or constructed using the first reserved code in the memory controller, and the memory release instruction is constructed using the second reserved code in the memory controller.

2. The semiconductor memory according to claim 1, characterized in that, The portion of the storage row extending into the marked storage area is used to form the first flag bit corresponding to the storage row; The first flag bit occupies one storage unit.

3. The semiconductor memory according to claim 1, characterized in that, The semiconductor memory is configured to adjust the first flag bit of the storage row to a first state when it is detected that the number of consecutive accesses of adjacent storage rows of the storage row exceeds a preset threshold within a unit time. or, After refreshing the storage row, the first flag of the storage row is adjusted to the second state, and the number of consecutive accesses of the adjacent storage rows within the unit time is re-accumulated.

4. The semiconductor memory according to claim 1, characterized in that, Each of the storage groups includes a storage line, and the portion of the storage line extending into the marked storage area is used to form a second flag bit corresponding to the storage group; or Each of the storage groups includes multiple storage rows, and a portion of one of the storage rows extending into the marked storage area is used to form a second flag bit corresponding to the storage group.

5. A refresh method, characterized in that, Applied to a semiconductor memory comprising multiple storage rows and multiple first flag bits, wherein one of the first flag bits is used to indicate whether a storage row is a victim row in a row hammering event, the method includes: Upon receiving the hammer refresh command, a target storage row is randomly selected from the multiple storage rows. The first flag bit of the target storage line is read to obtain the reading result; Based on the read result, determine whether to refresh the target storage row; The semiconductor memory further includes a second flag bit, wherein the plurality of memory rows are divided into several memory groups, and one of the second flag bits is used to indicate whether at least one memory cell in one of the memory groups is in a specific state, the specific state including being occupied; before refreshing the target memory row, the method further includes: Read the second flag bit of the storage group to which the target storage row belongs; If the second flag is in the third state, the target storage row is refreshed. If the second flag is in the fourth state, the target storage line is not refreshed; and one of the following steps is performed: terminate the execution of the hammer refresh instruction, or determine a new target storage line and return to the step of reading the first flag of the target storage line; The method further includes: Upon receiving a memory allocation instruction, the second flag bit of the memory group corresponding to the memory allocation instruction is adjusted to the third state; Upon receiving a memory release instruction, the second flag bit of the storage group corresponding to the memory release instruction is adjusted to the fourth state; or, after refreshing the storage group, the second flag bit of the storage group is adjusted to the fourth state. The memory allocation instruction is either a word line activation instruction or constructed using the first reserved code in the memory controller; the memory release instruction is constructed using the second reserved code in the memory controller.

6. The refresh method according to claim 5, characterized in that, The step of determining whether to refresh the target storage row based on the read result includes: When the first flag bit is in the first state, the target storage line is refreshed; When the first flag is in the second state, the target storage line is not refreshed; and one of the following steps is performed: terminate the execution of the hammer refresh instruction, or determine a new target storage line and return to the step of reading the first flag of the target storage line.

7. The refresh method according to claim 6, characterized in that, The method further includes: After detecting that the number of consecutive accesses of adjacent storage rows of a storage row exceeds a preset threshold within a unit of time, the first flag bit of the storage row is adjusted to the first state. After refreshing the storage row, the first flag of the storage row is adjusted to the second state, and the number of consecutive accesses of the adjacent storage rows within a unit of time is re-accumulated.

8. An electronic device, characterized in that, The electronic device includes at least the semiconductor memory according to any one of claims 1-4.

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