Method for judging semiconductor defects, computer device, and readable storage medium

Abstract

This disclosure pertains to the field of semiconductor manufacturing technology, specifically relating to a method for determining semiconductor defects, a computer device, and a readable storage medium. The determination method includes: providing a semiconductor structure, the semiconductor structure including a substrate and a plurality of bit line structures spaced apart along a second direction, the bit line structures extending in a first direction, and the bit line structures including a first region and a second region in the first direction; irradiating the sidewalls of the bit line structures with a charged particle beam along a third direction; obtaining the width of the first region and the width of the second region of the bit line structures, the width of the first region being the width of the first region along the second direction, and the width of the second region being the width of the second region along the second direction; and determining whether a defect exists in the semiconductor structure based on the width of the first region and the width of the second region. This determination method enables real-time monitoring of semiconductor structure defects, which is beneficial for improving semiconductor structure performance.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a method for determining semiconductor defects, a computer device, and a readable storage medium. Background Technology

[0002] Semiconductor memories consist of many repeating memory cells. Each memory cell typically includes a capacitor structure and a transistor structure. The gate of the transistor structure is connected to the word line, the drain to the bit line, and the source to the capacitor structure. During the fabrication of the bit line, a necking phenomenon can easily occur, where the size of the bottom structure of the bit line shrinks. This necking phenomenon may lead to failure in subsequent electrical measurements.

[0003] In related technologies, semiconductor structures are typically sliced ​​and analyzed to determine the presence of defects by measuring the cross-sectional dimensions of the bitline structure. However, these technologies cannot monitor the semiconductor structure in real time during the fabrication process, leading to a decrease in device performance. Summary of the Invention

[0004] This disclosure provides a method for determining semiconductor defects, a computer device, and a readable storage medium.

[0005] In a first aspect, embodiments of this disclosure provide a method for determining semiconductor defects, including:

[0006] A semiconductor structure is provided, the semiconductor structure including a substrate and a plurality of bit line structures spaced apart along a second direction, the bit line structures extending in a first direction, the first direction being perpendicular to the second direction, the bit line structures including a first region and a second region in the first direction;

[0007] Irradiate the sidewalls of the bitline structure with a beam of charged particles in a third direction;

[0008] Obtain the first height of the bit line structure, the width of the first region and the width of the second region, wherein the first height is the height of the bit line structure located above the substrate, the width of the first region is the width of the first region along the second direction, and the width of the second region is the width of the second region along the second direction;

[0009] The presence of defects in the semiconductor structure is determined based on the width of the first region and the width of the second region.

[0010] In one possible implementation, the angle between the first direction and the third direction is 3°-8°.

[0011] In one possible implementation, the semiconductor structure further includes a bit line contact hole, and the bit line structure further includes a third region located within the bit line contact hole;

[0012] Obtaining the first height of the bitline structure, the width of the first region, and the width of the second region further includes:

[0013] The width of the third region and the second height of the bit line structure are obtained, wherein the second height is the height of the bit line structure located above the bottom of the bit line contact hole, and the width of the third region is the width of the third region along the second direction;

[0014] The presence of defects in the semiconductor structure is determined based on the width of the first region, the width of the second region, and the width of the third region.

[0015] In one possible implementation, determining whether the semiconductor structure has defects based on the widths of the first region, the second region, and the third region includes:

[0016] If the width of the first region is less than a first preset value, and / or if the width of the second region is less than a second preset value, and / or if the width of the third region is less than a third preset value, the semiconductor structure is determined to have a defect.

[0017] In one possible implementation, obtaining the first height of the bitline structure, the width of the first region, and the width of the second region further includes:

[0018] Obtain the line edge roughness of the bit line structure;

[0019] Determining whether the semiconductor structure has defects based on the widths of the first region, the second region, and the third region further includes:

[0020] If the width of the first region is greater than or equal to the first preset value, and the width of the second region is greater than or equal to the second preset value, and the width of the third region is greater than or equal to the third preset value, the presence of defects in the semiconductor structure is determined based on the line edge roughness.

[0021] In one possible implementation, determining whether the semiconductor structure has defects based on the line edge roughness includes:

[0022] If the roughness of the line edge is greater than a fourth preset value, the semiconductor structure is determined to have a defect.

[0023] In one possible implementation, obtaining the first height of the bitline structure, the width of the first region, and the width of the second region further includes:

[0024] Obtain the linewidth roughness of the bitline structure;

[0025] Determining whether the semiconductor structure has defects based on the widths of the first region, the second region, and the third region further includes:

[0026] If the width of the first region is greater than or equal to the first preset value, and the width of the second region is greater than or equal to the second preset value, and the width of the third region is greater than or equal to the third preset value, the presence of defects in the semiconductor structure is determined based on the line edge roughness and the line width roughness.

[0027] In one possible implementation, determining whether the semiconductor structure has defects based on the line edge roughness and the linewidth roughness includes:

[0028] If the line edge roughness is greater than a fourth preset value, and / or if the line width roughness is greater than a fifth preset value, the semiconductor structure is determined to have a defect.

[0029] In one possible implementation, obtaining the width of the first region, the width of the second region, and the width of the third region further includes:

[0030] Obtain the middle width of the first region, the middle width of the second region, and the middle width of the third region;

[0031] The widths of the first region, the second region, and the third region are obtained based on the middle widths of the first region, the second region, and the third region, respectively.

[0032] In one possible implementation, the second region is a conductive layer covering the substrate, and the first region is an insulating layer covering the first region.

[0033] In one possible implementation, the second region includes a tungsten layer and a titanium nitride layer, the titanium nitride layer being located between the tungsten layer and the substrate.

[0034] In one possible implementation,

[0035] Verification of the judgment result includes:

[0036] The semiconductor structure is sliced ​​and measured to obtain the slice measurement width of the first and second regions of the bit line structure.

[0037] The reliability of the judgment result is determined based on the correlation between the width of the first region and the width of the second region and the slice measurement width of the first region and the second region.

[0038] In one possible implementation, if the relevance is greater than or equal to a preset relevance, the judgment result is considered reliable; otherwise, the judgment result is considered unreliable.

[0039] In one possible implementation, the preset relevance is 0.9.

[0040] Secondly, embodiments of this disclosure also provide a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the method described above.

[0041] Thirdly, embodiments of this disclosure also provide a readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the above-described method.

[0042] This disclosure provides a method for determining semiconductor defects, comprising: providing a semiconductor structure, the semiconductor structure including a substrate and a plurality of bit line structures spaced apart along a second direction, the bit line structures extending in a first direction, the first direction being perpendicular to the second direction, and the bit line structures including a first region and a second region in the first direction; irradiating the sidewalls of the bit line structures with a charged particle beam along a third direction; obtaining a first height of the bit line structures, the width of the first region, and the width of the second region, wherein the first height is the height of the bit line structures located above the substrate, the width of the first region is the width of the first region along the second direction, and the width of the second region is the width of the second region along the second direction; and determining whether a defect exists in the semiconductor structure based on the width of the first region and the width of the second region. This determination method enables real-time monitoring of semiconductor structure defects, which is beneficial for improving semiconductor structure performance. Attached Figure Description

[0043] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 A flowchart illustrating the steps of a method for determining semiconductor defects provided in this embodiment of the disclosure;

[0045] Figure 2 A schematic diagram of the semiconductor structure provided in a semiconductor defect determination method according to an embodiment of this disclosure;

[0046] Figure 3 A schematic diagram of the structure used in a semiconductor defect determination method provided in this disclosure, which involves irradiation with a charged particle beam along a third direction. Figure 1 ;

[0047] Figure 4 A schematic diagram of the structure used in a semiconductor defect determination method provided in this disclosure, which involves irradiation with a charged particle beam along a third direction. Figure 2 ;

[0048] Figure 5 A function curve of the fitting function provided in a semiconductor defect determination method according to an embodiment of this disclosure;

[0049] Figure 6 This is a schematic diagram of a defective semiconductor structure provided in an embodiment of this disclosure. Detailed Implementation

[0050] This disclosure provides a method for determining semiconductor defects, which is described below according to embodiments. Figure 1 This includes steps S101 to S104.

[0051] Step S101: Provide a semiconductor structure, the semiconductor structure including a substrate and a plurality of bit line structures spaced apart along a second direction, the bit line structures extending in a first direction, the first direction and the second direction being perpendicular, the bit line structures including a first region and a second region in the first direction.

[0052] Reference Figure 2 The semiconductor structure includes a substrate 10 and a plurality of bit line structures 20 disposed on the substrate 10. For example... Figure 2 As shown, the first direction is perpendicular to the plane of the substrate 10, and the second direction is parallel to the plane of the substrate 10, with the first direction perpendicular to the second direction. Multiple bit line structures 20 are spaced apart along the second direction and are parallel to each other. The extension direction of the bit line structure 20 is parallel to the first direction. Each bit line structure 20 includes a first region 21 and a second region 22 in the first direction, both located above the substrate 10. The first region 21 can be an insulating layer, and the second region 22 can be a conductive layer. The first region 21 covers the end of the second region 22 facing away from the substrate 10, and the second region 22 is located between the first region 21 and the substrate 10. In one specific implementation, the material of the first region 21 may include one or more of silicon nitride, silicon oxide, and silicon oxynitride to further improve the insulating effect of the first region 21. In this embodiment, the second region 22 may include a tungsten layer and a titanium nitride layer, wherein the tungsten layer covers the end of the titanium nitride layer away from the substrate 10, and the titanium nitride layer is located between the tungsten layer and the substrate 10, and the titanium nitride layer facilitates the connection between the tungsten layer and the substrate 10.

[0053] Step S102: Irradiate the sidewalls of the bitline structure with a charged particle beam along a third direction.

[0054] Since the bit line structure 20 is a high aspect ratio structure, the spacing between the bit line structures 20 continuously decreases as the device density increases. If traditional vertical angle charged particle measurement is used, defects located at the bottom or middle of the bit line structure 20 cannot be measured. At the same time, the material of the bit line structure 20 is different from bottom to top, and the target critical dimensions are also different. The semiconductor defect judgment method provided in this embodiment determines whether defects exist in different regions of the bit line structure 20.

[0055] Reference Figure 3 and Figure 4 In this embodiment, a significant linewidth scanning electron microscope (SEM) can be used to irradiate the bit line structure 20. For example, in some embodiments, the significant linewidth SEM is equipped with an electron gun for emitting charged particles, which can be tilted so that the emitted charged particles irradiate the sidewalls of the bit line structure 20 in a third direction. In other embodiments, the carrier disk supporting the semiconductor structure can be tilted so that the charged particles irradiate the sidewalls of the bit line structure 20 in a third direction. After the charged particle beam irradiates the sidewalls of the bit line structure 20, the reflected secondary electrons are collected by the detector of the significant linewidth SEM, thereby obtaining a topographic image of the sidewalls of the bit line structure 20. Based on the topographic image of the sidewalls, the width of each region of the bit line structure 20 can be further obtained to determine whether there are defects in the semiconductor structure.

[0056] In some embodiments, the angle A between the first direction and the third direction can be 3°-8°. For example, the angle A between the first direction and the third direction can be 3°, 5°, or 8°, so that conductive particles can irradiate the sidewalls of the bitline structure 20, thereby obtaining a clear topographic image of the bitline structure 20. In this embodiment, the angle A between the first direction and the third direction can be 5°, which is beneficial for further determining whether there are defects in the semiconductor structure.

[0057] In this embodiment, after irradiating the sidewall of the bit line structure 20 with a charged particle beam along a third direction, the method further includes:

[0058] Step S103: Obtain the first height of the bit line structure, the width of the first region and the width of the second region. The first height is the height of the bit line structure located above the substrate, the width of the first region is the width of the first region along the second direction, and the width of the second region is the width of the second region along the second direction.

[0059] In this embodiment, based on the topographic image of the sidewall of the bitline structure 20, the first height of the bitline structure 20, the width of the first region 21, and the width of the second region 22 are obtained. The widths of both the first region 21 and the second region 22 are widths along a second direction, that is, the widths of the first region 21 and the second region 22 are widths parallel to the substrate 10. The first height is the height of the bitline structure 20 located above the substrate 10; that is, the first height is the sum of the heights of the first region 21 and the second region 22 along the first direction.

[0060] In this embodiment, obtaining the width of the first region 21 and the width of the second region 22 further includes obtaining the middle width of the first region 21 and the middle width of the second region 22.

[0061] Based on the topographic image of the sidewall of bitline structure 20, the mid-width of the first region 21 and the mid-width of the second region 22 can be obtained. The mid-width of the first region 21 is the width in the topographic image of the sidewall. Similarly, the mid-width of the second region 22 is the width in the topographic image of the sidewall.

[0062] In this embodiment, after obtaining the middle width of the first region 21 and the middle width of the second region 22, the method further includes: obtaining the width of the first region 21 and the width of the second region 22 based on the middle width of the first region 21 and the middle width of the second region 22, respectively.

[0063] In this embodiment, the middle width of the first region 21 and the middle width of the second region 22 can be substituted into the fitting function to obtain the widths of the first region 21 and the second region 22, respectively. The fitting function is:

[0064] y = C1x + C2;

[0065] In the formula:

[0066] C1 is the first coefficient, which can be, for example, 1.4261;

[0067] C2 is the second coefficient, which can be, for example, -11.046.

[0068] As can be seen, after substituting the middle width of the first region 21 into the x value of the fitting function, the resulting y value is the width of the first region 21. Similarly, after substituting the middle width of the second region 22 into the x value of the fitting function, the resulting y value is the width of the second region 22.

[0069] Reference Figure 5 The following is a brief introduction to the process of obtaining the fitting function:

[0070] After obtaining the morphological images of the sidewalls of the bit line structure 20 through steps S101 to S102 of the above-described semiconductor structures, the center width at a certain position in the bit line structure 20 is obtained. Then, this batch of semiconductor structures is sliced ​​and measured to obtain the slice measurement width along the direction parallel to the substrate 10 at the same position.

[0071] Establish a coordinate system, using the middle width as the X-coordinate and the width of the corresponding slice as the Y-coordinate. Obtain multiple coordinate points in the coordinate system, and the fitted line obtained from these multiple coordinate points is the fitted function.

[0072] In this embodiment, after obtaining the first height of the bit line structure 20, the width of the first region 21, and the width of the second region 22, the method further includes:

[0073] Step S104: Determine whether there are defects in the semiconductor structure based on the width of the first region and the width of the second region.

[0074] In this embodiment, if the width of the first region 21 is less than a first preset value, it indicates that the first region 21 of the bit line structure 20 has a necking phenomenon, that is, the first region 21 has a defect; Figure 3 As shown, if the width of the second region 22 is less than the second preset value, it indicates that the second region 22 of the bit line structure 20 has a necking phenomenon, that is, the second region 22 has a defect. Therefore, if the width of the first region 21 is less than the first preset value, and / or the width of the second region 22 is less than the second preset value, it is determined that the semiconductor structure has a defect.

[0075] This disclosure provides a method for determining semiconductor defects, comprising: providing a semiconductor structure, the semiconductor structure including a substrate 10 and a plurality of bit line structures 20 spaced apart along a second direction, the bit line structures 20 extending in a first direction, the first direction being perpendicular to the second direction, and the bit line structures 20 including a first region 21 and a second region 22 in the first direction; irradiating the sidewalls of the bit line structures 20 with a charged particle beam along a third direction; obtaining a first height of the bit line structures 20, the width of the first region 21, and the width of the second region 22, wherein the first height is the height of the bit line structures 20 located above the substrate 10, the width of the first region 21 is the width of the first region 21 along the second direction, and the width of the second region 22 is the width of the second region 22 along the second direction; and determining whether there are defects in the semiconductor structure based on the width of the first region 21 and the width of the second region 22. This determination method enables real-time monitoring of semiconductor structure defects, which is beneficial for improving semiconductor structure performance.

[0076] Furthermore, the semiconductor defect determination method provided by the embodiments of this disclosure does not require slicing measurement, which helps to reduce wafer loss and save the manufacturing cost and time of semiconductor structures.

[0077] Continue to refer to Figure 1 and Figure 2 In this embodiment, the step of providing the semiconductor structure further includes a bit line contact hole 30, and the bit line structure 20 further includes a third region 23 located within the bit line contact hole 30. For example, the third region 23 covers the substrate 10 and is located within the bit line contact hole 30. A second region 22 is located between the first region 21 and the third region 23. The material of the third region 23 may be, for example, doped polysilicon, to achieve contact between the second region 22 and the substrate 10.

[0078] After providing the semiconductor structure, the first height of the bit line structure 20, the width of the first region 21, and the width of the second region 22 are obtained. The method further includes obtaining the width of the third region 23 and the second height of the bit line structure 20, wherein the second height is the height of the bit line structure 20 located above the bottom of the bit line contact hole 30, and the width of the third region 23 is the width of the third region 23 along the second direction.

[0079] In this embodiment, the second height and the width of the third region 23 of the bitline structure 20 are obtained based on the topographic image of the sidewall of the bitline structure 20. The width of the third region 23 is the width along the second direction, that is, the width of the third region 23 is the width parallel to the direction of the substrate 10. The second height is the height of the bitline structure 20 located above the bitline contact hole 30, that is, the second height is the sum of the heights of the first region 21, the second region 22, and the third region 23 along the first direction.

[0080] After obtaining the first height of the bit line structure 20, the width of the first region 21 and the width of the second region 22, obtaining the width of the first region 21, the width of the second region 22 and the width of the third region 23, further includes obtaining the middle width of the first region 21, the middle width of the second region 22 and the middle width of the third region 23.

[0081] Similarly, based on the topographic image of the sidewall of bitline structure 20, while obtaining the middle width of the first region 21 and the middle width of the second region 22, the middle width of the third region 23 can also be obtained. The middle width of the third region 23 is the width in the topographic image of the sidewall.

[0082] In this embodiment, after obtaining the middle width of the first region 21, the middle width of the second region 22, and the middle width of the third region 23, the method further includes: obtaining the width of the first region 21, the width of the second region 22, and the width of the third region 23 based on the middle width of the first region 21, the middle width of the second region 22, and the middle width of the third region 23, respectively.

[0083] For example, by substituting the middle width of the first region 21 and the middle width of the second region 22 into the above fitting function to obtain the widths of the first region 21 and the second region 22 respectively, the middle width of the third region 23 is also substituted into the above fitting function to obtain the width of the third region 23. Specifically, the y-value obtained by substituting the middle width of the third region 23 into the x-value of the fitting function is the width of the third region 23.

[0084] After obtaining the width of the first region 21, the width of the second region 22, and the width of the third region 23, the method of determining whether there is a defect in the semiconductor structure based on the width of the first region 21 and the width of the second region 22 further includes: determining whether there is a defect in the semiconductor structure based on the width of the first region 21, the width of the second region 22, and the width of the third region 23.

[0085] In this embodiment, if the width of the first region 21 is less than a first preset value, it indicates that the first region 21 of the bit line structure 20 has a necking phenomenon, that is, the first region 21 has a defect; Figure 3 As shown, if the width of the second region 22 is less than the second preset value, it indicates that the second region 22 of the bit line structure 20 has a necking phenomenon, that is, the second region 22 has a defect; as Figure 4 As shown, if the width of the third region 23 is less than the third preset value, it indicates that the third region 23 of the bit line structure 20 has a necking phenomenon, that is, the third region 23 has a defect. It can be seen that if the width of the first region 21 is less than the first preset value, and / or the width of the second region 22 is less than the second preset value, and / or the width of the third region 23 is less than the third preset value, then it is determined that the semiconductor structure has a defect.

[0086] In some embodiments, the step of obtaining the first height of the bitline structure 20, the width of the first region 21, and the width of the second region 22 further includes: obtaining the edge roughness of the bitline structure 20. The edge roughness is the roughness of the graphic edge, describing the deviation between the graphic edge and the ideal shape.

[0087] Reference Figure 6 , Figure 6 This is a cross-sectional view of the bitline structure. The bitline structure in region B is a normal bitline structure 20, while the bitline structure 20 in region C has defects. Taking region 21 as an example, the edge of the bitline structure 20 is actually a line with a certain roughness. After multi-point measurement of the edge, the center line L1 of the edge of the bitline structure 20 is obtained. The line edge roughness characterizes the deviation between the edge point C1 in different regions of the bitline structure 20 and the center line L1 of the line edge. By obtaining the line edge roughness of the bitline structure 20 in region C, it is possible to further determine whether there are defects in different regions of the bitline structure 20.

[0088] After obtaining the edge roughness of the bit line structure 20, the determination of whether there are defects in the semiconductor structure based on the widths of the first region 21, the second region 22, and the third region 23 further includes: if the width of the first region 21 is greater than or equal to a first preset value, the width of the second region 22 is greater than or equal to a second preset value, and the width of the third region 23 is greater than or equal to a third preset value, it indicates that there is no necking phenomenon in the first region 21, the second region 22, and the third region 23 of the bit line structure 20. At this time, the determination of whether there are defects in the semiconductor structure is based on the edge roughness.

[0089] For example, determining whether a semiconductor structure has defects based on edge roughness includes: if the edge roughness is greater than or equal to a fourth preset value, determining that the semiconductor structure has defects. If the edge roughness is greater than the fourth preset value, it indicates that the deviation between the edge shape of the bit line structure 20 and the ideal shape is large, and the bit line structure 20 has defects.

[0090] Continue to refer to Figure 6 In the bit line structure 20 located in region C, the width of region 21 is greater than or equal to the first preset value, and the roughness of the line edge of region 21 is greater than the fourth preset value. It can be determined that region 21 does not have a necking phenomenon, but region 21 has a defect.

[0091] In some embodiments, obtaining the first height of the bitline structure 20, the width of the first region 21, and the width of the second region 22 further includes obtaining the linewidth roughness of the bitline structure 20. The linewidth roughness describes the deviation of the linewidth from a target value due to edge roughness.

[0092] Reference Figure 6 Bitline structure 20 in region B is a normal structure, while bitline structure 20 in region D has defects. Taking region 21 as an example, after obtaining a large amount of measurement data using multi-point measurements on the edge, the average value is taken to obtain the average linewidth value W2. The linewidth roughness is used to characterize the deviation between the linewidth value W1 (located between edge point D1 and edge point D2) and the average linewidth value W2 in different regions. By obtaining the linewidth roughness of bitline structure 20, it can be used to further determine whether there are defects in different regions of bitline structure 20.

[0093] After obtaining the linewidth roughness, the determination of whether there are defects in the semiconductor structure based on the widths of the first region 21, the second region 22, and the third region 23 further includes: if the width of the first region 21 is greater than or equal to a first preset value, and the width of the second region 22 is greater than or equal to a second preset value, and the width of the third region 23 is greater than or equal to a third preset value, it indicates that there is no necking phenomenon in the first region 21, the second region 22, and the third region 23 of the bit line structure 20. At this time, the determination of whether there are defects in the semiconductor structure is based on the line edge roughness and the linewidth roughness.

[0094] For example, determining whether a semiconductor structure has defects based on line edge roughness and linewidth roughness includes: if the line edge roughness is greater than a fourth preset value, and / or if the linewidth roughness is greater than a fifth preset value, then the semiconductor structure is determined to have defects. If the linewidth roughness is greater than the fifth preset value, it indicates that the linewidth deviates significantly from the target value, and the bit line structure 20 has defects. If either the line edge roughness or the linewidth roughness does not meet the preset value, then the semiconductor structure is determined to have defects.

[0095] Continue to refer to Figure 6 In the bitline structure 20 located in region D, the width of the first region 21 is greater than or equal to a first preset value, and the line width roughness of the first region 21 is greater than a fifth preset value. It can be determined that the first region 21 does not exhibit necking, but it does have a defect. In this embodiment, after determining whether the semiconductor structure has a defect based on the width of the first region 21 and the width of the second region 22, the determination result needs to be verified. The verification process includes: performing slice measurements on the semiconductor structure to obtain the slice measurement widths of the first region 21 and the second region 22 of the bitline structure 20; and determining the reliability of the determination result based on the correlation between the width of the first region 21 and the width of the second region 22 and the slice measurement widths of the first region 21 and the second region 22.

[0096] In this embodiment, after slicing and measuring the semiconductor structure, the obtained slice measurement width is the width along the plane direction of the substrate 10, that is, the width along the second direction. Here, correlation refers to the percentage of mutual connection between two things. By comparing the correlation between the slice measurement width of the first region 21 and the width of the first region 21, the reliability of the judgment result of the first region 21 can be determined; by comparing the correlation between the slice measurement width of the second region 22 and the width of the second region 22, the reliability of the judgment result of the second region 22 can be determined. Similarly, by comparing the correlation between the slice measurement result of the third region 23 and the width of the third region 23, the reliability of the judgment result of the third region 23 can be determined.

[0097] In this embodiment, if the correlation is greater than or equal to a preset correlation, the judgment result is considered reliable; otherwise, the judgment result is considered unreliable. A higher correlation indicates a stronger correlation between the slice measurement result and the width measured in this application, thus indicating a reliable judgment result for the semiconductor structure; conversely, a lower correlation indicates an unreliable result. In this embodiment, the preset correlation can be, for example, 0.9. Of course, in some other embodiments, the preset correlation can also be set to any value between 0.9 and 1, such as 0.92, 0.94, etc.

[0098] This disclosure also provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of the method in any of the above embodiments.

[0099] This disclosure also provides a readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the methods in any of the above embodiments.

[0100] For specific limitations on the semiconductor defect judgment method in the above embodiments, please refer to the limitations on the semiconductor defect judgment method above, which will not be repeated here.

[0101] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional modules is merely an example. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. The specific working process of the device described above can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0102] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A method for determining semiconductor defects, characterized in that, include: A semiconductor structure is provided, the semiconductor structure including a substrate and a plurality of bit line structures spaced apart along a second direction, the bit line structures extending in a first direction, the first direction being perpendicular to the second direction, the bit line structures including a first region and a second region in the first direction; Irradiate the sidewalls of the bitline structure with a beam of charged particles in a third direction; Obtain the first height of the bit line structure, the width of the first region and the width of the second region, wherein the first height is the height of the bit line structure located above the substrate, the width of the first region is the width of the first region along the second direction, and the width of the second region is the width of the second region along the second direction; Determine whether the semiconductor structure has defects based on the width of the first region and the width of the second region; The semiconductor structure further includes a bit line contact hole, and the bit line structure further includes a third region located within the bit line contact hole; The width of the third region and the second height of the bit line structure are obtained, wherein the second height is the height of the bit line structure located above the bottom of the bit line contact hole, and the width of the third region is the width of the third region along the second direction; The presence of defects in the semiconductor structure is determined based on the width of the first region, the width of the second region, and the width of the third region. Determining whether the semiconductor structure has defects based on the widths of the first region, the second region, and the third region includes: If the width of the first region is less than a first preset value, and / or if the width of the second region is less than a second preset value, and / or if the width of the third region is less than a third preset value, the semiconductor structure is determined to have a defect. Obtaining the first height of the bitline structure, the width of the first region, and the width of the second region further includes: Obtain the edge roughness and linewidth roughness of the bitline structure; Determining whether the semiconductor structure has defects based on the widths of the first region, the second region, and the third region further includes: If the width of the first region is greater than or equal to the first preset value, and the width of the second region is greater than or equal to the second preset value, and the width of the third region is greater than or equal to the third preset value, the presence of defects in the semiconductor structure is determined based on the line edge roughness and the line width roughness.

2. The method for determining semiconductor defects according to claim 1, characterized in that, The angle between the first direction and the third direction is 3°-8°.

3. The method for determining semiconductor defects according to claim 1, characterized in that, Determining whether the semiconductor structure has defects based on the line edge roughness includes: If the roughness of the line edge is greater than a fourth preset value, the semiconductor structure is determined to have a defect.

4. The method for determining semiconductor defects according to claim 1, characterized in that, Determining whether the semiconductor structure has defects based on the line edge roughness and the line width roughness includes: If the line edge roughness is greater than a fourth preset value, and / or if the line width roughness is greater than a fifth preset value, the semiconductor structure is determined to have a defect.

5. The method for determining semiconductor defects according to claim 1, characterized in that, Obtaining the width of the first region, the width of the second region, and the width of the third region further includes: Obtain the middle width of the first region, the middle width of the second region, and the middle width of the third region; The widths of the first region, the second region, and the third region are obtained based on the middle widths of the first region, the second region, and the third region, respectively.

6. The method for determining semiconductor defects according to claim 1, characterized in that, The second region is a conductive layer that covers the substrate, and the first region is an insulating layer that covers the first region.

7. The method for determining semiconductor defects according to claim 6, characterized in that, The second region includes a tungsten layer and a titanium nitride layer, the titanium nitride layer being located between the tungsten layer and the substrate.

8. The method for determining semiconductor defects according to claim 1, characterized in that, Verification of the judgment result includes: The semiconductor structure is sliced ​​and measured to obtain the slice measurement width of the first and second regions of the bit line structure. The reliability of the judgment result is determined based on the correlation between the width of the first region and the width of the second region and the slice measurement width of the first region and the second region.

9. The method for determining semiconductor defects according to claim 8, characterized in that, If the relevance is greater than or equal to the preset relevance, the judgment result is considered reliable; otherwise, the judgment result is considered unreliable.

10. The method for determining semiconductor defects according to claim 9, characterized in that, The preset relevance is 0.

9.

11. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 10.

12. A readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 10.

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