Semiconductor device and corresponding method of manufacture

Abstract

An in-package antenna semiconductor device includes a semiconductor chip coupled to a planar substrate. An encapsulant encapsulates the semiconductor chip. The encapsulant includes a through cavity extending to the planar substrate. A straight wire antenna is mounted within the through cavity and extends, for example, from the planar substrate along an axis transverse to a surface of the planar substrate to which the semiconductor chip is coupled. The straight wire antenna is electrically coupled to the semiconductor chip. An insulating material fills the cavity to encapsulate the straight wire antenna.

Description

[0001] Priority requirements

[0002] This application claims priority to Italian Patent Application No. 102021000001301, filed on January 25, 2021, the contents of which are incorporated herein by reference in their entirety to the fullest extent permitted by law. Technical Field

[0003] This specification relates to semiconductor devices including wire antennas.

[0004] One or more embodiments can be applied to millimeter-wave RF products operating at (very) high frequencies (70 GHz or higher), as anticipated in the automotive sector or consumer electronics devices (e.g., 5G communication devices). Background Technology

[0005] Antenna-in-package (AiP) arrangements, including one or more antennas integrated into a semiconductor device package, are an area that has attracted increasing attention and research.

[0006] The following literature demonstrates the growing interest in this research area:

[0007] Varanasi et al., “On-chip bonded wire antennas on CMOS-level silicon substrates,” IEEE Antenna and Propagation Society International Symposium, San Diego, California, 2008, pp. 1-4;

[0008] Dowon et al., “High-efficiency, low-cost wire-bonded loop antennas for CMOS wafers”, IEEE International Symposium on Antenna Propagation, USNC / URSI National Conference on Radio Science (2009), from page 4 onwards;

[0009] Zhang et al., “In-package antenna for wire bonding interconnection with highly integrated 60 GHz radio”, IEEE Transactions on Antennas and Propagation 57(10), pp. 2842-2852.

[0010] Mitomo et al., “2Gb / s throughput CMOS transceiver chipset with in-package antenna for 60GHz short-range wireless communication”, IEEE Solid State Circuits Journal, Vol. 47, No. 12, December 2012.

[0011] Ndip et al.: “Modeling of shape, length and radiation characteristics of bonded wire antennas”, IET Microwave, Antennas and Propagation, 6 (2012), No. 10, pp. 1187-1194.

[0012] Johannsen et al., “Bonded wires: off-the-shelf integrated millimeter-wave antennas”, 42nd European Microwave Conference, Amsterdam, 2012, pp. 197-200;

[0013] Valenta et al., “Experimental evaluation of differential chip-to-antenna bonding wire interconnects above 110 GHz”, 10.1109 / EuMC 2014 6986608, 2014, from page 5 onwards;

[0014] QIN, Ivy, et al.: "Advances in wire bonding technology for 3D die stacking and fan-out wafer-level packaging", IEEE 67th Conference on Electronic Components and Technology, 2017, pp. 1309-1315.

[0015] Tsutsumi et al., “Bonding Wire Loop Antenna Built into Standard BGA Package for 60 GHz Short-Range Wireless Communication,” IEEE MTT-S International Microwave Symposium Abstracts 1-4.10.1109 / MWSYM.2011.5972652; and

[0016] US Patent No. 8,087,155B2.

[0017] All of the aforementioned references are incorporated herein by reference.

[0018] The solutions discussed in the literature listed above primarily include loop wire bonding antennas (e.g., in ball grid arrays or BGA packages), planar antennas (e.g., metal traces), or "dangling bonding" antennas (see U.S. Patent No. 8,087,155).

[0019] The resulting layout is not as compact as expected for various applications.

[0020] There is a need in this field to help solve the problems discussed above. Summary of the Invention

[0021] According to one or more embodiments, a semiconductor device is disclosed.

[0022] Square flat no-lead (QFN), ball grid array (BGA), or wafer-level chip-scale package (WLCSP) semiconductor devices can be examples of such devices.

[0023] One or more embodiments may relate to corresponding manufacturing methods.

[0024] One or more embodiments facilitate the integration of antennas into integrated circuit packages such as QFN, BGA, and WLCSP packages.

[0025] One or more embodiments facilitate the formation of an in-package antenna arrangement using vertical wires such as QFN leads bonded to a WLCSP package or wires on a redistribution layer (RDL).

[0026] One or more embodiments offer good RF performance in terms of gain and radiation efficiency, and also take into account the possibility of using metal portions as ground planes and feeders in semiconductor device packages.

[0027] One or more embodiments can be advantageously applied to provide a compact implementation of an antenna array.

[0028] For example, in a WLCSP package, one or more embodiments may involve drilling a cavity in a packaging molding compound (insulating encapsulation) adjacent to the die or chip to expose the redistribution layer (RDL), forming vertical conductors in the cavity (e.g., by wire bonding technology), and filling the cavity with encapsulation material. Attached Figure Description

[0029] One or more embodiments will now be described by way of example only with reference to the accompanying drawings, wherein:

[0030] Figure 1 and Figure 2 This is a cross-sectional view of a square flat leadless (QFN) semiconductor device package including an antenna arranged on a lead frame, according to an embodiment of this specification.

[0031] Figure 3 This is a cross-sectional view of a semiconductor device package including an antenna disposed on a redistribution layer (RDL) according to an embodiment of this specification; and

[0032] Figures 4A to 4M These are examples of possible steps or operations in manufacturing a semiconductor device package according to embodiments of this specification, under exemplary circumstances of manufacturing a wafer-level chip-scale packaged (WLCSP) semiconductor device.

[0033] It should be understood that, for simplicity and ease of explanation, the various figures may not be drawn to the same scale. Detailed Implementation

[0034] In the following description, one or more specific details are shown to provide a thorough understanding of examples of embodiments of this specification. Embodiments may be obtained without one or more specific details, or by utilizing other methods, components, materials, etc. In other instances, known structures, materials, or operations have not been shown or described in detail so as not to obscure certain aspects of the embodiments.

[0035] References to "embodiment" or "an embodiment" within the scope of this specification are intended to indicate that a particular configuration, structure, or feature described with respect to that embodiment is included in at least one embodiment. Therefore, phrases such as "in an embodiment" or "in one embodiment," which may appear at one or more points in this specification, do not necessarily refer to the same embodiment.

[0036] Furthermore, in one or more embodiments, a particular construction, structure, or characteristic may be combined in any suitable manner.

[0037] The title / reference numerals used herein are provided for convenience only and therefore do not limit the extent or scope of protection of the embodiments.

[0038] It is also understood that, unless the context otherwise requires, the same reference numerals will be used to denote the same parts or elements in all the figures, and for the sake of brevity, detailed descriptions will not be repeated for each figure.

[0039] Figure 1 and Figure 2 This is a cross-sectional view of a square flat no-lead (QFN) semiconductor device package 10.

[0040] These packages include a lead frame 12 in a manner known to those skilled in the art, the lead frame having one or more semiconductor chips or dies 14 disposed thereon.

[0041] For simplicity, only one chip or die 14 is shown here.

[0042] The term lead frame (or lead frame) is currently used (for example, see the USPC Uniform Terminology) to indicate a metal frame (e.g., at die pad or solder pad 12A) that provides support for the semiconductor chip or die 14 and electrical leads 12B to couple the semiconductor chip or die to 14 other electrical components or contacts.

[0043] Essentially, the lead frame, as indicated by reference numeral 12 in the figure, includes an array of conductive structures (leads) 12B that extend inward from a peripheral location in the direction of the semiconductor chip or die 14, thereby forming an array of conductive structures from the die pad 12A (on which at least one semiconductor chip or die is attached).

[0044] This can be via die-attach adhesive (e.g., die-attach film (DAF)) 14A, such as Figure 1 As shown, or via pillars 16 (e.g., copper) grown on the front or top surface of a semiconductor chip or die 14, such as Figure 2 As shown.

[0045] like Figure 1As shown, the electrical coupling between the lead 12B in the lead frame 12 and the semiconductor chip or die 14 can be achieved through a wire 18 that forms a wire bonding pattern around the chip or die 14.

[0046] like Figure 2 As shown, the electrical coupling between the lead 12B in the lead frame 12 and the semiconductor chip or die 14 can be achieved through a number of pillars 16 disposed around the periphery of the semiconductor chip or die 14 (front or top surface).

[0047] like Figure 1 and Figure 2 The device package shown is accomplished by providing an insulating encapsulation 20 of an encapsulation body, which is formed by molding a compound such as epoxy resin onto a lead frame 12 and one or more semiconductor chips 14 attached thereto.

[0048] The possibility of providing electrical coupling between leads 12B in leadframe 12 and semiconductor chip or die 14 by using laser direct structuring (LDS) technology is also considered (see, for example, U.S. Patent Publications 2018 / 0342453, 2020 / 0203264 or 2020 / 0321274, the disclosures of which are incorporated herein by reference).

[0049] Unless otherwise noted below, the semiconductor device architecture described above is conventional in the art, which makes it unnecessary to provide a more detailed description herein.

[0050] Figure 1 and Figure 2 This is an example of the possibility of implementing the semiconductor device package as an antenna-in-package (AiP) device by providing (forming) a straight “vertical” bonding wire antenna 100 in the semiconductor device package 10.

[0051] As used herein, “vertical” means the fact that the antenna extends along the antenna axis X100 in a direction transverse to (i.e., orthogonal or substantially orthogonal to) the “horizontal” plane of the planar substrate provided by the lead frame 12 (in other words, perpendicular to the main or top surface of the lead frame).

[0052] The terms “vertical” and “horizontal” refer to the orientation of the device 10 as shown in the figure; the orientation of the lead frame (substrate) 12 and the antenna 100 can therefore be changed (e.g., in the device 10 mounted “on the edge”, the substrate 12 will be vertical and the antenna 100 will be horizontal), while the antenna 100 remains “lateral” to each other relative to the plane of the substrate 12.

[0053] The metallic (conductive) structures (pads and lines or traces, not visible in the figure) in the substrate provide a ground plane and a feed line, which provides electrical coupling between the antenna 100 and the chip 14 for transmitting and / or receiving RF signals.

[0054] A linear antenna 100 having a length (measured in the direction of the longitudinal antenna axis X100) that is equivalent to (i.e., approximately equal to or less than) the height or thickness of a conventional chip or die (e.g., approximately 300 to 500 μm) was found to provide a 77 GHz peak gain of 5.39 dB and a 77 GHz peak radiation efficiency of -1.21 dB.

[0055] Figure 3 In a semiconductor device 10, a substantially similar implementation is achieved in a semiconductor chip or die 14 coupled to a planar substrate 12 in the form of a redistribution layer (RDL). Figure 1 and Figure 2 An example of the possibilities for antenna arrangement within the package (AiP).

[0056] The name redistribution layer is currently applied to a layer that redistributes input / output lines to the wire metal interconnects on portions of the chip. This redistribution layer helps couple chip 14 to ball grid array 24 for electrical connection to external circuitry (e.g., a printed circuit board (PCB), not visible in the figure).

[0057] Regardless of the implementation details Figures 1 to 3 The straight wire antenna 100 illustrated in the figure can be implemented by employing, for example, the vertical wire technique discussed in the paper by Qin et al. for providing vertical interconnection (which has been cited herein).

[0058] Furthermore, it will be understood that, regardless of the implementation details, such as Figures 1 to 3 The straight wire antenna 100 illustrated herein will ultimately be protected by the encapsulation material 20 of the encapsulation body.

[0059] This helps the wire antenna 100 maintain its straight shape and desired orientation (e.g., "vertical", orthogonal to the support substrate 12).

[0060] In all the figures, the straight wire antenna 100 is illustrated as extending (protruding) from the substrate 12. It will also be understood that, although not shown for the purpose of brevity, in the semiconductor device illustrated herein, one or more straight wire antennas such as 100 may be arranged on the respective semiconductor chip (e.g., by bonding to pads available on its top or front surface).

[0061] For simplicity, all figures illustrate a separate device package 10 comprising a single chip or die 14 coupled to a single straight wire antenna 100.

[0062] It will be understood that one or more embodiments may actually include: a single chip or die 14 coupled to a plurality of straight wire antennas 100; a plurality of chips or dies 14 coupled to a single straight wire antenna 100; or a plurality of chips or dies 14 coupled to a plurality of straight wire antennas 100.

[0063] Figures 4A to 4M Manufacturing in an exemplary case of manufacturing a wafer-level chip-scale packaged (WLCSP) semiconductor device Figure 3 Examples of possible steps in a method for packaging a semiconductor device of the type illustrated in the diagram.

[0064] Those skilled in the art will further understand that, for the purposes of the following, Figures 4A to 4M The order of steps is merely exemplary: a) one or more steps shown (e.g., one or more wafer flipping steps may be omitted for certain package types) may be omitted and / or replaced by other steps; b) additional steps may be added; and c) one or more steps may be performed in an order different from that shown.

[0065] In addition, although Figures 4A to 4M In and in Figure 3 The example provided in the semiconductor device package of the type illustrated in (basically WLCSP) is a wire antenna 100, but the steps related to providing antenna 100 can be modified as necessary to apply to other applications. Figure 1 and Figure 2 The semiconductor device package 10 illustrated in the figure provides a wire antenna 100.

[0066] Figures 4A to 4M This involves the simultaneous manufacture of multiple devices 10, which are ultimately used in, for example... Figure 4M The "separation" step shown is separated, as are other conventional steps in the prior art.

[0067] Furthermore, for simplicity and ease of understanding, unless the context otherwise indicates otherwise, [the following will be used] in conjunction with [other terms]. Figures 1 to 3 The components or elements discussed are similar to those in Figures 4A to 4M Similar reference numerals are used in the accompanying drawings, and detailed descriptions will not be repeated for the sake of brevity; and for simplicity, Figures 1 to 3 Some details may be shown in Figures 4A to 4M This will not be repeated.

[0068] Figures 4A to 4M The steps illustrated are as follows:

[0069] Figure 4A - Provides carrier belt T

[0070] Figure 4B - Placement of die 14 (face down in the example shown)

[0071] Figure 4C - Molding of encapsulating material 20 (for subsequent formation of the encapsulation body)

[0072] Figure 4D -Removal of carrier T

[0073] Figure 4E - The wafer is flipped so that die 14 faces upwards.

[0074] Figure 4F - A passivation / metallization / passivation layer is provided (to provide a redistribution layer serving as substrate 12), wherein the metallization is patterned to provide metal leads.

[0075] Figure 4G -Wafer flipping

[0076] Figure 4H - A laser-drilled hole (via laser beam LB) is made through the encapsulation material 20 down to the redistribution layer (or lead frame) of the substrate 12 to provide a (e.g., cylindrical) cavity 100A for housing the antenna 100.

[0077] Figure 4I - Formation of antenna 100: This may involve performing a "first bonding" step (ball plus wire) on the bottom of the cavity 100A drilled in the encapsulation material 20 using conventional wire bonding equipment, followed by vertical "capillary" extraction and cutting of the leads at the desired controlled length of antenna 100.

[0078] Figure 4J - A filler block 100B of insulating material (e.g., spherical top resin or the same compound as encapsulating material 20) fills the cavity 100A in the encapsulating material 20 (with the antenna 100 in the cavity).

[0079] Figure 4K -Wafer flipping

[0080] Figure 4L -Ball 24's attachment

[0081] Figure 4M - Separate to define the package using its encapsulation.

[0082] Such as combination Figure 4I The formation of the antenna 100 may include employing conventional wire bonding techniques that use wires made of materials such as gold, aluminum, or copper (e.g., 15-micron wires), as is common in wire bonding techniques.

[0083] In short, a semiconductor device (e.g., 10) as illustrated herein may include: one or more semiconductor chips (e.g., 14) coupled to a planar substrate (e.g., 12); and one or more straight-wire antennas (e.g., 100) extending along an antenna axis (e.g., X100) laterally (e.g., orthogonal or substantially orthogonal to the planar substrate), said one or more straight-wire antennas being electrically coupled (e.g., via...) Figure 1 and Figure 2 In the lead frame or Figure 3 (The redistribution layer in the semiconductor) is applied to one or more semiconductor chips.

[0084] In a semiconductor device as illustrated herein, one or more straight wire antennas may protrude from a planar substrate.

[0085] Although not shown for the sake of brevity, note again that in the semiconductor device illustrated herein, one or more straight wire antennas may be arranged on one or more semiconductor chips (e.g., by bonding to pads available on their top or front surfaces).

[0086] The semiconductor device illustrated herein may include an encapsulation material (e.g., 20 and possibly 100B) that encapsulates one or more semiconductor chips coupled to a substrate and one or more straight-wire antennas within the encapsulation.

[0087] In a semiconductor device as illustrated herein, one or more straight wire antennas may be located on the side of one or more semiconductor chips (i.e., at a position offset from the outer peripheral edge).

[0088] In a semiconductor device as illustrated herein, one or more semiconductor chips may have a thickness in the direction of the antenna axis, and one or more straight wire antennas may have a length approximately equal to or less than the thickness of one or more semiconductor chips.

[0089] As used herein, “approximately” specifically refers to tolerances of the features considered in manufacturing and measurement, and more generally means within (+ / -) 1% to 5% of the nominal or design-specified values.

[0090] In the semiconductor device illustrated herein, a planar substrate may include a lead frame comprising die pads on which one or more semiconductor chips or dies are disposed (e.g., Figure 1 and 2 12A in the middle) and the lead array around the die pad (e.g., Figure 1 and 2 (12B) wherein one or more straight wire antennas are arranged at the lead array.

[0091] In the semiconductor device illustrated herein, the planar substrate may include a redistribution layer disposed on one or more semiconductor chips (e.g., see...). Figure 3 To facilitate electrical contact between one or more semiconductor chips and an array of contact structures (e.g., 24), wherein one or more straight wire antennas and the array of contact structures are located on opposite sides of the redistribution layer.

[0092] The methods illustrated herein may include: providing one or more semiconductor chips (e.g., 14) coupled to a planar substrate (e.g., 12); and providing one or more straight-wire antennas (e.g., 100) extending along an antenna axis (e.g., X100) transverse to the planar substrate, said one or more straight-wire antennas being electrically coupled to said at least one semiconductor chip.

[0093] The methods illustrated herein may include bonding one or more straight wire antennas to a planar substrate, wherein one or more straight wire antennas protrude from the planar substrate.

[0094] The methods illustrated herein may include providing an encapsulation material (e.g., 20 and possibly 100B) that encapsulates one or more semiconductor chips coupled to a substrate, wherein the encapsulation material encapsulates one or more semiconductor chips coupled to the substrate and one or more straight wire antennas.

[0095] The methods illustrated herein may include: providing (e.g., see below) one or more semiconductor chips coupled to a planar substrate (12). Figures 4C to 4G Encapsulation material (20) blocks; forming (see, e.g.) within the encapsulation material blocks Figure 4H The at least one cavity (e.g., 100A) of the laser-drilled hole illustrated in LB extends along the antenna axis (e.g., into a planar substrate) through the encapsulation material; and a straight wire antenna (e.g., 100) (e.g., protruding from the planar substrate) is bonded (e.g., to the bottom of the at least one cavity) to the planar substrate, the straight wire antenna extending in the at least one cavity formed in the encapsulation material block.

[0096] The methods illustrated herein may include bonding a straight wire antenna to a planar substrate at the bottom of at least one cavity, optionally by ball-and-lead bonding of wire material at the bottom of at least one cavity.

[0097] The methods illustrated herein may include filling an insulating encapsulating material (e.g., 100B) into at least one cavity having a straight wire antenna extending therein.

[0098] Without prejudice to the fundamental principles, details and embodiments may vary, even significantly, relative to what is described by way of example only, without departing from the scope of protection.

[0099] The claims are an integral part of the technical teachings of the embodiments provided herein.

[0100] The scope of protection is determined by the appended claims.

Claims

1. A semiconductor device, comprising: A planar substrate having a first primary surface; A semiconductor chip is mounted on the first main surface of the planar substrate; A first encapsulating material forms an encapsulation body that encapsulates the semiconductor chip coupled to the substrate, the encapsulation body including a cavity extending through the encapsulation body to the planar substrate; A straight wire antenna is installed inside the cavity; The straight wire antenna has an antenna axis extending perpendicular to the first main surface of the planar substrate; The straight wire antenna is electrically coupled to the semiconductor chip. as well as A second encapsulating material is used to fill the cavity to encapsulate the straight wire antenna.

2. The semiconductor device of claim 1, wherein the straight wire antenna protrudes from the planar substrate.

3. The semiconductor device of claim 1, wherein the straight wire antenna is mounted to the planar substrate at a position offset from the outer peripheral edge of the semiconductor chip.

4. The semiconductor device of claim 1, wherein the semiconductor chip has a thickness in the direction of the antenna axis, and the straight wire antenna has a length in the direction of the antenna axis equal to or less than the thickness of the semiconductor chip.

5. The semiconductor device of claim 1, wherein the semiconductor chip is electrically connected to the planar substrate via bonding wires.

6. The semiconductor device of claim 1, wherein the semiconductor chip is electrically connected to the planar substrate via a pillar.

7. The semiconductor device of claim 1, wherein the planar substrate is formed of a lead frame having a die pad to which the semiconductor chip is mounted, and the lead frame further having a plurality of leads extending away from the die pad, wherein the straight wire antenna is mounted to and electrically connected to one of the plurality of leads.

8. The semiconductor device of claim 1, wherein the planar substrate is formed of a redistribution layer comprising at least one insulating layer and at least one conductive layer, the conductive layer being patterned to form a plurality of redistribution leads, wherein the straight conductor antenna is mounted to and electrically connected to one of the plurality of redistribution leads.

9. The semiconductor device of claim 1, wherein the planar substrate includes a lead frame, the lead frame including a die pad and a lead array around the die pad, the die pad having the semiconductor chip disposed on the die pad, wherein the straight wire antenna is coupled to a lead in the lead array.

10. The semiconductor device of claim 1, wherein the planar substrate includes a redistribution layer disposed on the semiconductor chip to facilitate electrical contact between the semiconductor chip and an array of contact structures at a second main surface of the planar substrate, wherein the straight wire antenna is mounted on a first side of the redistribution layer, and wherein the array of contact structures is located on a second side of the redistribution layer opposite to the first side.

11. The semiconductor device of claim 10, wherein the redistribution layer includes a redistribution lead having a surface on the first side, and wherein the straight wire antenna is mounted to and electrically connected to the surface on the first side of the redistribution lead.

12. A method for manufacturing a semiconductor device, comprising: The semiconductor chip is mounted onto the first main surface of the planar substrate; The semiconductor chip is encapsulated within an encapsulation coupled to the substrate; A cavity is formed that extends through the encapsulation into the planar substrate; A straight wire antenna is installed inside the cavity; The straight wire antenna has an antenna axis extending perpendicular to the first main surface of the planar substrate; The straight wire antenna is electrically coupled to the semiconductor chip; as well as The cavity is filled with a second encapsulating material to encapsulate the straight wire antenna.

13. The method of claim 12, further comprising bonding the straight wire antenna to the planar substrate, wherein the straight wire antenna protrudes from the first main surface of the planar substrate.

14. The method of claim 12, further comprising forming an electrical contact on a second main surface of the planar substrate opposite to the first main surface.

15. The method of claim 12, wherein the straight wire antenna is mounted to the planar substrate at a location offset from the outer peripheral edge of the semiconductor chip.

16. The method of claim 12, wherein the semiconductor chip has a thickness in the direction of the antenna axis, and the straight wire antenna has a length in the direction of the antenna axis equal to or less than the thickness of the semiconductor chip.

17. The method of claim 12, further comprising electrically connecting the semiconductor chip to the planar substrate via bonding wires.

18. The method of claim 12, further comprising electrically connecting the semiconductor chip to the planar substrate via a pillar.

19. The method of claim 12, wherein the planar substrate is formed of a lead frame.

20. The method of claim 12, wherein the planar substrate is formed of a redistribution layer.

21. A method for manufacturing a semiconductor device, comprising: Couple semiconductor chips to a planar substrate; A block of encapsulating material is provided to encapsulate the semiconductor chip coupled to the planar substrate; A cavity is formed that extends through the encapsulating material block in a direction perpendicular to the planar substrate; A straight wire antenna is bonded to the bottom of the cavity; as well as The cavity is filled with insulating material that encapsulates the straight conductor antenna.

22. The method of claim 21, wherein the straight wire antenna is bonded by ball bonding wire material on the bottom of the cavity.

23. The method of claim 21, further comprising forming an electrical contact on a second main surface of the planar substrate opposite to the first main surface.

24. The method of claim 21, wherein the straight wire antenna has an antenna axis extending within the cavity, and wherein the semiconductor chip has a thickness in the direction of the antenna axis, and the straight wire antenna has a length in the direction of the antenna axis equal to or less than the thickness of the semiconductor chip.

25. The method of claim 21, further comprising electrically connecting the semiconductor chip to the planar substrate via bonding wires.

26. The method of claim 21, further comprising electrically connecting the semiconductor chip to the planar substrate via a pillar.

27. The method of claim 21, wherein the planar substrate is formed of a lead frame.

28. The method of claim 21, wherein the planar substrate is formed of a redistribution layer.

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