Vertical interconnect structure in three-dimensional integrated circuits

Abstract

This disclosure relates to vertical interconnect structures in three-dimensional integrated circuits. The 3D IC structure includes multiple die layers, such as a top die layer and a bottom die layer. Each of the top and / or bottom die layers includes devices such as computing units, analog-to-digital converters, analog circuits, RF circuits, logic circuits, sensors, input / output devices, and / or memory devices. Devices on the first and second die layers are laterally surrounded by or laterally adjacent to a vertical interconnect structure (VIS).

Description

Technical Field

[0001] This disclosure relates to vertical interconnect structures in three-dimensional integrated circuits. Background Technology

[0002] Three-dimensional (3D) stacked chips, or integrated circuits (ICs), are integration technologies used in modern computing and electronic systems. Through-silicon vias (TSVs) are used to electrically connect two or more stacked dies. For example, TSVs can enable heterogeneous integration of computing dies and memory dies to reduce the footprint of stacked dies. Summary of the Invention

[0003] According to one embodiment of this disclosure, a 3D integrated circuit structure is provided, comprising: a first die layer including: one or more first devices; and a first plurality of vertical interconnect structures (VIS) formed in the first die layer and arranged in a first grid layout around the one or more first devices; and a second die layer disposed on the first die layer in a vertical direction and including: a plurality of second devices; and a second plurality of VIS formed in the second die layer and arranged in a second grid layout around the plurality of second devices, wherein: the first grid layout is different from the second grid layout; and the density of the second plurality of VIS is greater than the density of the first plurality of VIS.

[0004] According to another embodiment of this disclosure, an integrated circuit system is provided, including: a 3D integrated circuit structure; and a power supply operable to connect to the 3D integrated circuit structure, wherein the 3D integrated circuit structure includes: a first die layer, the first die layer including: a first plurality of first devices; and a first plurality of vertical interconnect structures (VIS) formed in the first die layer and arranged in a first grid layout; a second die layer disposed on the first die layer in a vertical direction, the second die layer including: a second plurality of second devices; and a second plurality of VIS formed in the second die layer and arranged in a second grid layout, wherein: the arrangement of the first plurality of VIS in the first grid layout is different from the arrangement of the second plurality of VIS in the second grid layout; and a first density of the first plurality of VIS is different from a second density of the second plurality of VIS.

[0005] According to another embodiment of this disclosure, a method for manufacturing a 3D integrated circuit structure is provided, the method comprising: processing a first die layer to generate devices and a first plurality of vertical interconnect structures (VISs) on the first die layer, the first plurality of VISs being arranged in a first grid layout; processing an intermediate conductive layer above the first die layer to generate signal lines; processing a second die layer to generate a plurality of devices and a second plurality of VISs on the second die layer, the second plurality of VISs being arranged in a second grid layout; and attaching the second die layer to the first die layer, wherein: the arrangement of the first plurality of VISs in the first grid layout is different from the arrangement of the second plurality of VISs in the second grid layout; and the signal lines electrically connect corresponding VISs in the first plurality of VISs to corresponding VISs in the second plurality of VISs. Attached Figure Description

[0006] The various aspects of this disclosure are best understood through the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, according to standard industry practice, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily enlarged or reduced.

[0007] Figure 1 A 3D IC package according to some embodiments is shown;

[0008] Figure 2 A first example 3D IC structure according to some embodiments is shown;

[0009] Figure 3 The connection between vertical interconnect structures on different die layers in a 3D IC according to some embodiments is shown;

[0010] Figure 4 A first example of the layout of vertical interconnect structure units according to some embodiments is shown;

[0011] Figure 5 A second example of the layout of vertical interconnect structure units according to some embodiments is shown;

[0012] Figure 6 A block diagram of a first example of a die layer according to some embodiments is shown;

[0013] Figure 7 A block diagram of a second example of a die layer according to some embodiments is shown;

[0014] Figure 8 A second example of a 3D IC structure according to some embodiments is shown;

[0015] Figure 9A third example of a die layer according to some embodiments is shown;

[0016] Figure 10 A fourth example of a die layer according to some embodiments is shown;

[0017] Figure 11 A fifth example of a die layer according to some embodiments is shown;

[0018] Figure 12 A flowchart illustrating an example method for manufacturing an IC layer according to some embodiments is shown;

[0019] Figure 13 A flowchart illustrating an example method for manufacturing a 3D IC structure according to some embodiments is shown;

[0020] Figure 14 Example systems suitable for designing 3D IC structures according to some embodiments are shown; and

[0021] Figure 15 A block diagram of an example integrated circuit manufacturing system and manufacturing process according to some embodiments is shown. Detailed Implementation

[0022] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely exemplary and not limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples throughout this disclosure. Such repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0023] In addition, this document may use spatially related terms (e.g., "below," "under," "down," "above," "up," etc.) to facilitate the description of the relationship between one element or feature shown in the accompanying drawings and another element(s) or feature(s). These spatially related terms are intended to cover devices in use or operation in orientations other than those shown in the accompanying drawings. Devices may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein can be interpreted similarly.

[0024] The embodiments disclosed herein provide a 3DIC structure comprising multiple die layers (e.g., a top die layer and a bottom die layer). The top die layer and / or the bottom die layer includes devices such as computing units, analog-to-digital converters (ADCs), analog circuitry, RF circuitry, logic circuitry, sensors, input / output (I / O) devices, and / or memory devices. Example memory devices include static random access memory (SRAM), resistive random access memory (RRAM), dynamic random access memory (DRAM), cache, and / or flash memory. Example computing units are microprocessors, field-programmable gate arrays (FPGAs), and graphics processing units, etc.

[0025] A vertical interconnect structure (VIS) is formed in the die layer of the 3D IC structure. The VIS can be any suitable type of vertical interconnect structure, such as through-silicon via (TSV), through-glass via (TGV), and through-dielectric via (TDV). As will be described in more detail later, in one embodiment, the floor plan of the devices and the VIS in at least one die layer of the 3D IC differs from the floor plan of the devices and the VIS in another die layer of the 3D IC.

[0026] VIS (Vibration Indicators) can be used to transmit power signals, data signals, and bias voltage signals (e.g., analog bias signals). VISs in each die layer are arranged in a grid layout on the die layer. VISs in a die layer can be arranged in a grid layout around one or more devices on the die layer. The grid layout of the VISs can improve the manufacturing process used to fabricate the die layer, which in turn can increase the yield of the VISs. Additionally or alternatively, when the density of VISs is uniform across the die layer, this uniform density reduces the resistance between the VISs and the devices, and can reduce the IR drop in the power signal.

[0027] Figure 1 A 3D IC package according to some embodiments is illustrated. The 3D IC package 100 includes a substrate 102. The substrate 102 can be any suitable type of substrate, such as a silicon-based substrate or a printed circuit board. An electrical connector 104 is disposed between the substrate 102 and an internal insert 106. In the illustrated embodiment, the electrical connector 104 is a solder bump, but other embodiments are not limited to this implementation. The electrical connector 104 can be any suitable electrical connector, such as a wire bond or a ball grid array.

[0028] Electrical connector 104 transmits power signals, data signals, and / or bias signals between substrate 102 and internal insert 106. Internal insert 106 is configured to route signals between electrical connector 104 and 3D IC 108. 3D IC 108 includes two or more vertically stacked die layers and one or more VISs in each die layer for electrically connecting the die layers to each other. In some embodiments, 3D IC 108 is a heterogeneous 3D IC, where the device type on one die layer differs from the device type on another die layer. For example, the device type on the bottom die layer may be a memory device, while the device type on the top die layer may be a computing unit. In other embodiments, 3D IC 108 is a homogeneous 3D IC, where the same type of device is formed in and / or on the die layers.

[0029] As described in more detail later, the arrangement of VIS in one die layer of the 3D IC 108 can differ from the arrangement of VIS in another die layer. These different arrangements can vary to meet improved or optimal occupancy and / or routing requirements. For example, electronic design applications (EDA) can be used to determine the optimal or best arrangement of VIS in that die layer based on the power requirements of the devices on that die layer and the power requirements of devices located on any die layer above that die layer.

[0030] Additionally or alternatively, the diameter, spacing, and density of VISs may be the same on one die layer, but different on another die layer. The VIS layout, diameter, spacing, and density in each die layer are based, for example, on: the power requirements of the devices on the die layer; the power requirements of the devices on one or more upper die layers; and / or the IR drop experienced by power signals, data signals, and / or analog bias signals at one or more upper die layers. For example, when a 3D IC is formed with two die layers, the layout of the VIS in the bottom die layer is based on: the power requirements of the devices on the bottom die layer; the power requirements of the devices on the top die layer; and / or the IR drop experienced by power signals, data signals, and / or analog bias signals at the top die layer. The layout of the VIS in the top die layer is based on the power requirements of the devices on the top die layer. When the power signal is input to the 3D IC at the bottom die layer, the density of VIS in the bottom die layer is usually greater than that in the top die layer. This is because the VIS in the bottom die layer needs to provide sufficient and minimal power to the devices on the top die layer to maintain the integrity of the operation of the devices on the top die layer.

[0031] Figure 2An example 3D IC structure according to some embodiments is shown. The 3D IC structure 200 includes multiple die layers. For illustrative purposes, Figure 2 Includes selected portions of the 3D IC structure. Other components, not shown, may be included in the 3D IC structure. For example, it may include microbumps, molded regions, dummy regions, adhesive layers, heat sinks, interconnects, ball grid array (BGA) connectors, in-silicon inserts, and other components or structural elements.

[0032] In the illustrated embodiment, the 3D IC structure 200 includes a die layer 200A and a die layer 200B disposed on top of the die layer 200A. Other embodiments of the 3D IC structure may include additional die layers (e.g., 3, 5, or 8). In some embodiments, the peripheral structure 202 may provide mechanical support and / or provide thermal conduction for heat dissipation.

[0033] Die layer 200A includes device 204. Example device 204 includes, but is not limited to, memory devices and I / O devices. Die layer 200B includes device 206. Device 206 on die layer 200B can be of the same type or various different devices. In a non-limiting embodiment, device 206 is a computing unit. In other embodiments, when the 3D IC structure is a heterogeneous 3D IC structure, die layer 200A may include one or more computing units, while die layer 200B may include RF and analog circuitry. In another example embodiment of a heterogeneous 3D IC, die layer 200A may include logic circuitry and memory devices, while die layer 200B may include sensors, input / output (I / O) devices, and one or more computing units.

[0034] Die layer 200B is electrically connected to die layer 200A via VIS 208 on die layer 200A and VIS 210 on die layer 200B. One or more devices 204 are electrically connected to one or more corresponding devices 206 via VIS 208, 210. As previously described, VIS 208, 210 include TSV, TDV, or other types of vertical interconnect structures. In the illustrated embodiment, VIS 208, 210 are TSVs. TSVs can be power TSVs, data signal TSVs, and bias TSVs. For example, VIS 208a, placed around the periphery of the bottom die layer 200A, can be a data signal TSV, while VIS 208b, disposed between devices 204, can be a power TSV.

[0035] VIS 208 in die layer 200A is arranged in a first layout, while VIS 210 on die layer 200B is arranged in a different second layout. As previously described, the layout of VIS 208 on die layer 200A is based at least on factors such as: the power requirements of device 204 on die layer 200A; the power requirements of device 206 on die layer 200B; and / or the IR voltage drop experienced by power signals, data signals, and / or analog bias signals. The layout of VIS 210 on die layer 200B is based at least on the power requirements of device 206 on die layer 200B. In some cases, the layout of VIS 208, 210 may also be based on improved or optimized die area consumption on die layers 200A, 200B.

[0036] In the illustrated embodiment, the power supply 212 is connected via an electrical connector (e.g., Figure 1 Electrical connector 104 is electrically connected to 3D IC structure 200. Power supply 212 supplies power to devices 204 and 206 on die layers 200A and 200B. Power is supplied to die layers 200A and 200B through at least some of VISs 208 and 210.

[0037] like Figure 2 As shown, the planar arrangement of devices 204 and VIS 208 on die layer 200A differs from the planar arrangement of devices 206 and VIS 210 on die layer 200B. The number of devices 204, the number of VIS 208, and the layout of VIS 208 in die layer 200A differ from the number of devices 206, the number of VIS 210, and the layout of VIS 210 in die layer 200B. Accordingly, the design or manufacturing of each die layer 200A and 200B can be optimized or selected based on the requirements of the respective die layers 200A and 200B. For example, when device 206 is a processing unit, a more expensive manufacturing process can be used to manufacture die layer 200B due to the high-speed requirements of the processing unit. Alternatively, when devices 204 on die layer 200A include memory devices, analog devices, and / or logic devices, a cheaper manufacturing process can be used to manufacture die layer 200A due to the slower speed requirements of these types of devices.

[0038] Figure 3 The diagram illustrates the connections between VISs in different die layers of a 3D IC according to some embodiments. The 3D IC 300 includes a die layer 302 located beneath a die layer 304. VISs 306a-306e on die layer 302 are arranged in a first layout 308. VISs 310a-310c on die layer 304 are arranged in a second layout 312. As previously discussed, the first layout 308 and the second layout 312 may differ based on improved die area consumption and / or power requirements of die layers 302, 304.

[0039] For example, the distance or spacing 314 (the “spacing” of VISs 306a-306e) between VISs 306a-306e in die layer 302 is generally the same, and the spacing 316 of VISs 310a-310c in die layer 304 is generally the same. However, in the illustrated embodiment, spacing 314 and spacing 316 are different. The spacing of VISs in a particular die layer can be based on several factors. For example, spacings 314 and 316 are defined by one or more design rules of the 3D IC. Furthermore, in some embodiments, the minimum distance between spacings 314 and 316 is limited by the manufacturing process used to manufacture the respective die layers 302 and 304. Each die layer in the 3D IC can be manufactured using a specific manufacturing process for that die layer. For example, when forming processing units on a die layer, a more expensive manufacturing process can be used to manufacture the die layer due to the high-speed requirements of the processing units. Alternatively, when the die layer includes memory devices, analog devices, and / or logic devices, a cheaper manufacturing process can be used to fabricate the die layer due to the slower speed requirements of these types of devices.

[0040] Additionally or alternatively, the density of VIS 306a-306e and the density of VIS 310a-310c are based on one or more factors. The following factors are considered when determining the density of VIS in the die layer: the type of device on that die layer (e.g., device 204 on die layer 200A); the power requirements of the device on that die layer (e.g., device 204 on die layer 200A); the power requirements of devices on any die layer above and over that die layer (e.g., device 206 on die layer 200B); and / or the IR voltage drop experienced by the signal at any die layer above and over that die layer. Furthermore, the density of VIS can vary over the die layer base region based on these factors. For example, the density of VIS in one part of the die layer may differ from that in another part of the die layer based on factors such as: the device type in each part of the die layer; the power requirements of the devices in each part of the die layer; the power requirements of devices on any die layers above and above the die layer; and / or the IR voltage drop experienced by the signal at any die layer above and above the die layer.

[0041] Located between die layers 302 and 304 is an intermediate conductive layer 318 (e.g., a redistribution layer). Electrical connections between die layers 302 and 304 are achieved through the intermediate conductive layer 318. The intermediate conductive layer 318 is patterned to create one or more contacts (collectively referred to as contacts 320) and one or more signal lines (collectively referred to as signal lines 322). Contacts 320 are used to electrically connect a VIS (e.g., VIS 306a) in die layer 302 to a VIS (e.g., VIS 310a) in die layer 304. The electrical connection between VIS 306a and VIS 310a is indicated by dashed line 324.

[0042] Because the second layout 312 of VIS 310a-310c in die layer 304 differs from the first layout 308 of VIS 306a-306e in die layer 302, signal line 322 is used to route signals from a VIS in one die layer to a corresponding VIS in another die layer. For example, as Figure 3 As shown, signal line 322 electrically connects VIS 306b on die layer 302 to VIS 310b on die layer 304. The electrical connection between VIS 306b and VIS 310b is indicated by dashed line 326.

[0043] Although Figure 3 Only one contact 320 and one signal line 322 are shown, but other embodiments may include any suitable number of contacts and signal lines in the intermediate conductive layer 318. Additionally, although in Figure 3 Not shown, but insulating material is disposed around the contact 320 and signal line 322 to electrically isolate the contact 320 and signal line 322 from each other and from other contacts and / or signal lines in the intermediate conductive layer 318.

[0044] Figure 4 A first example of the layout of a VIS cell according to some embodiments is shown. Lines 400, 402, 404, and 406 of VIS cell 408 are disposed adjacent to edges 410, 412, 416, and 414 of device 418, respectively. VIS cell 408 includes a VIS 420 and an unused die region 422. The dimensions of the unused die region 422 may be based on one or more design rules and / or requirements of the manufacturing process used to manufacture the die layer.

[0045] VIS cells 408 form a grid around device 418. When device 418 is one of multiple devices on a die layer, a VIS cell 408 adjacent to another device can be part of a grid surrounding the VIS cell of that other device (see, for example...). Figure 6 and 7 Device 418 can be the bottom die layer in a 3D IC structure (e.g., Figure 2 Devices on the die layer 200A, top die layer (e.g.) Figure 2 Devices on the die layer 200B or in the intermediate die layer (between the bottom die layer and the top die layer). VIS 420 is formed in VIS unit 408. Although device 418, VIS unit 408 and VIS 420 are shown to have a rectangular shape, other embodiments are not limited to this implementation.

[0046] In the illustrated embodiment, VIS cells 408 surround device 418 to form a grid, and lines 400, 402, 404, 406 adjoin edges 410, 412, 416, 414 of device 418. As previously mentioned, the spacing of VIS 420 is typically the same for VIS in each die layer due to one or more design rules and / or requirements of the manufacturing process used to manufacture the die layer. In other embodiments, the number of lines 400, 402, 404, 406 of VIS cells 408 may be fewer or more.

[0047] Figure 5 A second example of the layout of a VIS unit according to some embodiments is depicted. Figure 4 Similarly, lines 400, 402, 404, and 406 of VIS cells 408 are arranged adjacent to each edge 410, 412, 416, and 414 of device 418, respectively. The VIS cells 408 in lines 400, 402, 404, and 406 form a grid around device 418.

[0048] The second line 500 of VIS unit 408 is adjacent to and adjacent to line 400, and the second line 502 of VIS unit 408 is adjacent to and adjacent to line 402. The number of VIS units 408 in each line 400, 402, 404, 406, 500, 502 can be the same, or the number of VIS units 408 in one line can be different from the number of VIS units 408 in another line. As mentioned above, the spacing of VIS 420 is the same for VIS 420 on the die layer.

[0049] In several embodiments, the number of lines 400, 402, 404, 406, 500, 502 adjacent to device 418 may be fewer or more. For example... Figure 5 As shown, the number of lines 400 and 500 adjacent to edge 410 is N, where N = 2. The number of lines 402 and 502 adjacent to edge 412 is M, where M = 2. The number of lines 404 and 406 adjacent to the corresponding edges 416 and 414 is P and O, where O = P = 1. In other embodiments, M, N, O, and P can each be any suitable number. For example, M, N, O, and P can each be equal to one (1), such as Figure 4 As shown. Alternatively, M can be equal to one (1), N can be equal to one (1), O can be equal to one (1), and P can be equal to three (3).

[0050] The number of lines 400, 402, 404, 406, 500, and 502 of VIS unit 408 is based on the density of VIS 420 on the die layer. As previously mentioned, the density of VIS 420 is based on one or more factors. The following factors are considered when determining the density of VIS 420 on the die layer: the type of device on the die layer; the power requirements of the device on the die layer; the power requirements of the device on any die layer above and over the die layer; and / or the IR voltage drop experienced by the signal at any die layer above and over the die layer. Furthermore, the density of VIS 420 can vary on the die layer based on one or more factors. For example, the density of VIS 420 in one part of the die layer may differ from the density of VIS 420 in another part of the die layer based on the following factors: the device type in each part of the die layer; the power requirements of the devices in each part of the die layer; the power requirements of devices on any die layers above and over this die layer; and / or the IR voltage drop experienced by the signal at any die layer above and over this die layer.

[0051] Figure 6 A block diagram of a first example of a die layer according to some embodiments is shown. In a non-limiting example, die layer 600 is... Figure 2 The bottom die layer 200A is located within the die layer 600. Multiple devices 602 are disposed within or above the die layer 600. As previously described, example devices 602 include, but are not limited to, SRAM, RRAM, DRAM and flash memory devices, ADCs, I / O devices, and / or computing units.

[0052] exist Figure 6 In this embodiment, device 602 can be of the same type (e.g., memory), or at least one type of device 602 (e.g., memory) can be different from another type of device 602 (e.g., logic circuit). In an example embodiment, a first grid 604 of VIS is formed on die layer 600 such that each device 602 is laterally surrounded by a second grid 605 of VIS. Figure 6 The diagram shows a first line 606 (e.g., a vertical line or a line perpendicular to edge 608) and a second line 610 (e.g., a horizontal line or a line parallel to edge 608) of the VIS, as well as a center line 612 of the VIS. The number and arrangement of the VIS are for illustrative purposes, and other embodiments may have fewer or more VIS in any given layout.

[0053] The VIS can be a power VIS configured to send power signals to device 602 and devices attached to one or more additional die layers of die layer 600. In one embodiment, the VIS located in the center line 612 of grid 604 can be a data signal VIS for transmitting data signals between die layers in a 3D IC structure. Therefore, center line 612 is a signal relay. In other embodiments, the data signal VIS can be located at other locations within the die layer. For example, the data signal VIS can be located at one or more first lines 606 (e.g., first lines 606') located around the periphery of die layer 600.

[0054] In some embodiments, one or more signal lines electrically connect the VIS to the corresponding device. For example, such as Figure 6 As shown, signal line 614 electrically connects device 602' to the VIS in the center line 612 of the VIS. Although in Figure 6 Only one signal line 614 is shown, but other embodiments may use any suitable number of signal lines to connect the VIS to the corresponding device.

[0055] Figure 7 A block diagram of a second example of a die layer according to some embodiments is shown. Figure 7 This demonstrates that at least one device can consume a larger area on die layer 700 compared to other devices. Furthermore, the area of ​​one or more unused die regions may differ from the areas of other unused die regions. Therefore, in some embodiments, the die area used by the device and / or the die area used by unused die regions can vary.

[0056] In a non-limiting example, the die layer 700 is Figure 2 The bottom IC layer 200A is located within and / or on the die layer 700. Multiple devices 602 are disposed within and / or on top of the die layer 700. (Example...) Figure 7 As shown, each device 702, 704 uses a larger area on the die layer 700 compared to the area used by each of the other devices 602. Furthermore, the unused die region 706 around the VIS adjacent to the edge of device 704 (e.g., Figure 4 The area occupied by the unused die region 422 in the VIS is greater than the area occupied by the unused die region 708 around the VIS adjacent to device 702. In some embodiments, the size or area of ​​the unused die region is based on the device type and / or the size of devices 602, 702, 704 adjacent to the VIS unit.

[0057] Additionally or alternatively, one or more VISs (see area 710) may be removed to provide additional die area and / or wiring signal lines for a larger device 602'. The determination of which VISs to remove is based on the following factors: the power requirements of device 602'; the power requirements of devices 602 surrounding device 602'; and / or the power requirements of devices on any die layers above and over die layer 700.

[0058] Figure 8 A second example of a 3D IC structure according to some embodiments is shown. The 3D IC structure 800 includes a top die layer 802, a bottom die layer 804, and intermediate die layers 806, 808. The top die layer 802 includes devices 206, and each die layer 804, 806, 808 includes one or more devices 204.

[0059] In one embodiment, the lines 810 of the VIS unit 408 are arranged in a grid on each die layer 802, 804, 806, 808. The VIS in the VIS unit 408 (e.g., Figure 4 The VIS 420 is configured to transmit power signals, data signals, and / or analog bias signals between die layers 802, 804, 806, and 808. The centerline 812 of the VIS cells 408 on the top die layer 802, bottom die layer 804, and middle die layers 806 and 808 can be configured to transmit data signals between die layers 802, 804, 806, and 808. Other embodiments may use any suitable grid layout of the VIS cells 408 on each die layer 802, 804, 806, and 808 to transmit data signals, power signals, and / or analog bias signals.

[0060] In one embodiment, power supply 814 is operable to connect to bottom die layer 804 to provide a power signal to 3D IC 800. In such an embodiment, the VIS density in bottom die layer 804 is greater than the VIS density in middle die layer 808. The VIS density in middle die layer 808 is greater than the VIS density in middle die layer 806. The VIS density in middle die layer 806 is greater than the VIS density in top die layer 802. The VIS density on each die layer 802, 804, 806, 808 increases from top die layer 802 to bottom die layer 804. Due to the power requirements of devices 204, 206 on all die layers 802, 804, 806, 808, the VIS density in bottom die layer 804 is the highest. Since the VIS in the bottom die layer 804 provides power signals to all die layers 802, 804, 806, and 808, the density of the VIS in the bottom die layer 804 is based on the following factors: the power requirements of the device 204 on the bottom die layer 804; the power requirements of the device 204 on the middle die layer 808; the power requirements of the device 204 on the middle die layer 806; the power requirements of the device 206 on the top die layer 802; and / or the IR voltage drop generated when the power signal is transmitted from the bottom die layer 804 to the middle die layer 808, from the middle die layer 808 to the middle die layer 806, and from the middle die layer 806 to the top die layer 802.

[0061] The density of VIS in the intermediate die layer 808 is based on the following factors: the power requirements of device 204 on intermediate die layer 808; the power requirements of device 204 on intermediate die layer 806; the power requirements of device 206 on top die layer 802; and / or the IR voltage drop generated when power signals are transmitted from intermediate die layer 808 to intermediate die layer 806 and from intermediate die layer 806 to top die layer 802. Similarly, the density of VIS in intermediate die layer 806 is based on the following factors: the power requirements of device 204 on intermediate die layer 806; the power requirements of device 206 on top die layer 802; and / or the IR voltage drop generated when power signals are transmitted from intermediate die layer 806 to top die layer 802. The density of VIS in top die layer 802 is based on the power requirements of device 206 on top die layer 802.

[0062] Furthermore, as previously mentioned, the spacing and diameter of the VISs in each of the die layers 802, 804, 806, and 808 are the same, but the spacing and diameter of the VISs in one die layer may differ from those in another die layer. In some embodiments, the density, spacing, and diameter of the VISs in each die layer differ from the spacing, density, and diameter of the VISs in all other die layers.

[0063] In other embodiments, the power supply is operable to connect to the top die layer. In such embodiments, the density of VIS is highest at the top die layer and decreases with each die layer below the top die layer. Figures 9 to 11 The diagram shows the die layers in a 3D IC, where the density of VIS is highest at the top die layer and decreases with each die layer below the top die layer. Figure 9 A third example of a die layer according to some embodiments is shown. Die layer 900 is the bottom die layer in a 3D IC structure formed by die layers 900, 1000, and 1100, and die layer 900 includes device 902. An example of device 902 is a computing unit. The VIS in die layer 900 has a first density and is arranged in a grid layout around device 902.

[0064] Figure 10 A fourth example of a die layer according to some embodiments is shown. Die layer 1000 is an intermediate die layer in a 3D IC structure formed by die layers 900, 1000, and 1100, and die layer 1000 includes an array of four (4) devices 1002. Devices 1002 may be devices of the same type or devices of different types. Example devices 1002 include RF devices, logic devices, analog devices, memory devices, computing units, or combinations thereof. The VISs in die layer 1000 have a second density, and these VISs are arranged in a grid layout on die layer 1000 and around each device 1002 in a grid layout. The second density of VISs in die layer 1000 is greater than the first density of VISs in die layer 900.

[0065] Figure 11 A fifth example of a die layer according to some embodiments is shown. Die layer 1100 is the top die layer of a 3D IC structure formed by die layers 900, 1000, and 1100, and die layer 1100 includes an array of sixteen (16) devices 1102. As previously stated, these devices 1102 may be devices of the same type or devices of different types. Example devices 1102 include, but are not limited to, ADCs, analog circuits, RF circuits, logic circuits, I / O devices, memory devices, or combinations thereof.

[0066] The VISs in die layer 1100 have a third density. These VISs are arranged in a grid layout on die layer 1100 and around each device 1102. Power supply 1104 is operable to connect to die layer 1100. Therefore, the VISs in die layer 1100 support the power requirements of all devices 902, 1002, and 1102 in the 3D IC structure. Therefore, the density of VISs in die layer 1100 is greater than the density of VISs in die layers 900 and 1000.

[0067] Figure 12 A flowchart illustrating an example method for fabricating a die layer according to some embodiments is shown. First, as shown in block 1200, a substrate is provided. The substrate can be any suitable type of substrate. Example substrates include (but are not limited to) silicon substrates, silicon-on-insulator (SOI) substrates, sapphire substrates, or compound substrates (e.g., gallium arsenide substrates, gallium nitride substrates).

[0068] Next, as shown in block 1202, the locations of the devices and the VIS are determined. In one embodiment, the locations of the devices and the VIS are determined based on the device specifications and layout diagram. Alternatively, EDA can be used to determine these locations. In some embodiments, some or all of these locations are manually established.

[0069] A VIS is formed in block 1204. The VIS can be a TSV, TDV, or other types of vertical interconnect structure. Any suitable process can be used to construct the VIS. For example, one technique for forming a TSV includes forming a first mask layer on a substrate and patterning the first mask layer to include openings from which the VIS will be formed.

[0070] A conductive material is formed (e.g., deposited) in the opening. In a non-limiting example, a PVD or CVD process is used to deposit the conductive material. The conductive material can be made of any suitable conductive material, such as copper, cobalt, aluminum, tungsten, doped polycrystalline silicon, other suitable conductive materials, and / or combinations thereof.

[0071] The first mask layer is then removed, and a second mask layer is formed on the substrate. The second mask layer is patterned to include openings where an insulating material is formed around the conductive material. An insulating material is formed around the conductive material within these openings to electrically isolate the TSV. The second mask layer is then removed.

[0072] In block 1206, a device is formed within and / or on the substrate. Any suitable method can be used to fabricate the device. In block 1208, one or more signal lines are formed to connect one or more devices to a selected VIS in the die layer. The signal lines electrically connect one or more devices to the corresponding VIS.

[0073] Figure 13 A flowchart illustrating an example method for fabricating a 3D IC structure according to some embodiments is shown. First, as shown in block 1300, a first die layer is processed. The processing of the first die layer includes forming devices, VIS, and signal lines within and / or on the first die layer. Any suitable fabrication process can be used to construct the devices, VIS, and signal lines.

[0074] An intermediate conductive layer is formed on the surface of the first die layer and patterned to create one or more contacts and / or one or more signal lines (block 1302). In the example process, a conductive material (e.g., copper) is deposited on the surface of the first die layer. A mask layer is formed on the conductive material and patterned to define the locations of one or more contacts and / or one or more signal lines. The conductive material exposed in the patterned mask layer is removed (etched) to create one or more contacts and / or one or more signal lines. An insulating material is then formed between the one or more contacts and / or one or more signal lines. As previously described, the intermediate conductive layer is used to route signals between the first die layer and a second die layer located above the first die layer.

[0075] At block 1304, the second die layer is processed. Similar to the processing of the first die layer, the processing of the second die layer includes forming devices and VIS within and / or on the second die layer. The second die layer is processed to align with the first die layer.

[0076] Next, as shown in block 1306, a second die layer is attached to the intermediate conductive layer and the first die layer to produce a 3DIC structure. In one embodiment, at least one of the spacing, density, and / or diameter of the VISs in the first die layer differs from at least one of the spacing, density, and / or diameter of the VISs in the second die layer. Additionally or alternatively, the VISs in the first die layer are arranged on the first die in a first grid layout, and the VISs in the second die layer are arranged on the second die in a second grid layout. The arrangement of the VISs in the first grid layout differs from the arrangement of the VISs in the second grid layout.

[0077] In other embodiments, the operations specified in these blocks may not be in accordance with Figure 12 and 13 The blocks are executed in the order shown. For example, two blocks shown consecutively can be executed virtually simultaneously. Alternatively, depending on the functions / actions involved, the blocks can be executed in the reverse order.

[0078] Figure 14 Example systems suitable for designing 3D IC structures according to some embodiments are described. The design process can be implemented by a computer system (e.g., an ECAD system). Some or all of the operations of the design (e.g., layout) methods disclosed herein can be performed in a design room (e.g., in combination below). Figure 15 The design process is carried out as part of the design process discussed in Design Room 1502.

[0079] In some embodiments, system 1400 includes an Automatic Layout and Routing (APR) system. In some embodiments, system 1400 includes a processing device 1402 and a non-transitory computer-readable storage medium 1404 (“storage device”). Processing device 1402 is any suitable one or more processing devices. Example processing devices include, but are not limited to, a central processing unit, a microprocessor, a distributed processing system, an application-specific integrated circuit, a graphics processing unit, a field-programmable gate array, or combinations thereof.

[0080] Storage device 1404 may be encoded or stored, for example, computer program code (e.g., a set of executable instructions 1406). Execution of the executable instructions 1406 by processing device 1402 represents (at least partially) an ECAD tool that implements some or all of the methods described herein to produce a design for the structure and IC disclosed herein. Additionally, manufacturing tools 1408 may be included for IC placement and physical implementation. In one or more embodiments, storage device 1404 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or apparatus or device). For example, storage device 1404 includes semiconductor or solid-state memory, magnetic tape, removable computer floppy disk, random access memory (RAM), read-only memory (ROM), hard disk, and / or optical disk. In one or more embodiments using optical disk, storage device 1404 includes optical disc read-only memory (CD-ROM), optical disc read / write (CD-R / W), and / or digital video disc (DVD).

[0081] Processing device 1402 is operable to connect to storage device 1404 via bus 1410. Processing device 1402 is also operable to connect to input / output (I / O) interface 1412 and network interface 1414 via bus 1410. Network interface 1414 is operable to connect to network 1416, enabling processing device 1402 and storage device 1404 to connect to external components via network 1416. In one or more embodiments, network 1416 describes any type of wired and / or wireless network, such as an intranet and / or distributed computing network (e.g., the Internet).

[0082] Network interface 1414 allows system 1400 to communicate with other computing or electronic devices (not shown) via network 1416. Network interface 1414 includes a wireless network interface and / or a wired network interface. Example wireless network interfaces include Bluetooth, Wi-Fi, WiMAX, GPRS, or WCDMA. Example wired network interfaces include Ethernet, USB, or IEEE-1364. In one or more embodiments, some or all of the techniques and / or methods disclosed herein are implemented in a distributed system via network 1416.

[0083] Processing device 1402 is configured to execute executable instructions 1406 encoded in memory device 1404 so that system 1400 can be used to perform some or all of the processes and / or methods. For example, electronic design applications (e.g., in an ECAD system or as a standalone application) can be configured to execute... Figures 1 to 13 The methods and techniques shown.

[0084] In one or more embodiments, storage device 1404 stores executable instructions 1406 configured to make system 1400 available to perform some or all of the processes and / or methods. In one or more embodiments, storage device 1404 also stores some or all of the information that facilitates the execution of the processes and / or methods. In one or more embodiments, storage device 1404 stores a cell library 1418 comprising (at least partially) standard and / or previously designed cells.

[0085] I / O interface 1412 is operable to connect to I / O device 1420. In one or more embodiments, I / O device 1420 includes an image capture device, microphone, scanner, keyboard, keypad, mouse, touchpad, touchscreen, and / or cursor arrow keys for transmitting information and commands to processing device 1402. I / O device 1420 may also include one or more displays, one or more speakers, printer, headphones, haptic or haptic feedback devices, etc.

[0086] System 1400 is configured to receive information via I / O interface 1412. The information received via I / O interface 1412 includes one or more of instructions, data, design rules, cell libraries, and / or other parameters, for processing by processing device 1402. The information is transmitted to processing device 1402 via bus 1410. System 1400 is configured to receive information related to the user interface (UI) via I / O interface 1412. The information is stored in storage device 1404 as UI 1422 or used for presentation in UI 1422.

[0087] In some embodiments, part or all of the process and / or method is implemented as a standalone software application (e.g., EDA) executed by a processing device (e.g., processing device 1402). In some embodiments, part or all of the process and / or method is implemented as a software application as part of an additional software application. In some embodiments, part or all of the process and / or method is implemented as a plug-in to a software application. In some embodiments, at least one of the process and / or method is implemented as a software application as part of an EDA tool. In some embodiments, part or all of the process and / or method is implemented as a software application used by system 1400. In some embodiments, a layout diagram including standard and / or previously designed cells is generated using a tool (e.g., VIRTUOSO, available from CADENCEDESIGN SYSTEMS, Inc., or other suitable layout generation tool).

[0088] In some embodiments, the process is implemented as the function of a program stored in a non-transitory computer-readable recording medium (e.g., storage device 1404). Examples of non-transitory computer-readable recording media include, but are not limited to, one or more of external / removable and / or internal / built-in storage devices or storage units, such as optical discs (e.g., DVDs), magnetic disks (e.g., hard disks), semiconductor memories (e.g., ROM, RAM), memory cards, etc.

[0089] As described above, embodiments of system 1400 may include manufacturing tool 1408 for implementing processes and / or methods stored in storage device 1404. For example, synthesis may be performed in a design, wherein the desired behavior and / or functionality of the design is translated into a functionally equivalent logic gate-level circuit description by matching the design with cells selected from cell library 1418. Synthesis produces a functionally equivalent logic gate-level circuit description, such as a gate-level netlist. Based on the gate-level netlist, a photomask for fabricating an IC using manufacturing tool 1408 can be generated. Figure 15 Other aspects of device manufacturing were disclosed. Figure 15 This is a block diagram of an integrated circuit manufacturing system and associated manufacturing processes according to some embodiments. In some embodiments, based on the layout diagram, the manufacturing system 1500 manufactures at least one of the following: (a) one or more semiconductor masks; or (b) at least one component in a semiconductor IC layer.

[0090] Figure 15The illustration shows a block diagram of an example integrated circuit manufacturing system and manufacturing process according to some embodiments. In the illustrated embodiment, IC manufacturing system 1500 includes entities such as design room 1502, mask room 1504, and IC manufacturer / fab (“fab”) 1506, which interact with each other in the design, development, and manufacturing cycle and / or services associated with manufacturing IC 1508 (such as the IC disclosed herein). The entities in system 1500 are operable to connect via a communication network (not shown). In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an intranet and the Internet. The communication network includes wired and / or wireless communication channels.

[0091] Each entity interacts with one or more other entities and provides services to and / or receives services from one or more other entities. In some embodiments, two or more of design room 1502, mask room 1504, and IC fab 1506 are owned by a single company. In some embodiments, two or more of design room 1502, mask room 1504, and IC fab 1506 coexist in a common facility and use common resources.

[0092] Design studio (or design team) 1502 generates IC design layout 1510. IC design layout 1510 includes various geometric patterns, or IC layouts designed for IC 1508 to be manufactured. The geometric patterns correspond to patterns of metal, oxide, or semiconductor layers that constitute the various components of IC 1508 to be manufactured. The various layers are combined to form various IC features. For example, a portion of IC design layout 1510 includes various IC features, such as active diffusion regions, gate electrodes, source and drain electrodes, metal lines or partial vias, and openings for bonding pads, to be formed in a semiconductor substrate (e.g., a silicon wafer) and various material layers disposed on the semiconductor substrate.

[0093] Design studio 1502 implements the design process to form IC design layout 1510. The design process includes one or more of logic design, physical design, or placement and routing. IC design layout 1510 is presented in one or more data files containing geometric pattern information. For example, IC design layout 1510 can be expressed in GDS file format, GDSII file format, or DFII file format.

[0094] Mask chamber 1504 includes mask data preparation 1512 and mask fabrication 1514. Mask chamber 1504 uses an IC design layout 1510 to fabricate one or more masks 1516 for fabricating various layers of IC 1508 according to the IC design layout 1510. Mask chamber 1504 performs mask data preparation 1512, in which the IC design layout 1510 is converted into a representative data file (“RDF”). Mask data preparation 1512 provides the RDF to mask fabrication 1514. Mask fabrication 1514 includes a mask writer (not shown) that converts the RDF into an image on a substrate, such as a mask (mask) 1516 on a semiconductor wafer. The IC design layout 1510 is manipulated by mask data preparation 1512 to conform to the specific characteristics of the mask writer and / or the requirements of IC fab 1506. Figure 15 In this illustration, mask data preparation 1512 and mask manufacturing 1514 are shown as separate elements. In some embodiments, mask data preparation 1512 and mask manufacturing 1514 may be collectively referred to as mask data preparation.

[0095] In some embodiments, mask data preparation 1512 includes optical proximity correction (OPC), which uses lithographic enhancement techniques to compensate for image errors, such as those that may be caused by diffraction, interference, other process effects, etc. OPC adjusts the IC design layout (Figure 1510). In some embodiments, mask data preparation 1512 includes further resolution enhancement techniques (RET), such as off-axis illumination, subresolution auxiliary features, phase-shift masks, other suitable techniques, etc., or combinations thereof. In some embodiments, reverse lithography (ILT) is also used, where ILT treats OPC as an inverse imaging problem.

[0096] In some embodiments, mask data preparation 1512 includes a mask rule checker (MRC) (not shown). The MRC uses a set of mask creation rules to check the IC design layout 1510, which has undergone processes in the OPC, and these rules include certain geometric and / or connectivity constraints to ensure sufficient margins to address variability in semiconductor manufacturing processes, etc. In some embodiments, the MRC modifies the IC design layout 1510 to compensate for constraints during mask manufacturing, which can undo some modifications performed by the OPC to satisfy the mask creation rules.

[0097] In some embodiments, mask data preparation 1512 includes a lithography process check (LPC) (not shown), an LPC simulation performed by IC fab 1506 to manufacture IC 1508. The LPC simulates this process based on IC design layout 1510 to create a simulated manufactured device, such as IC 1508. Process parameters in the LPC simulation may include parameters associated with various processes in the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC considers various factors, such as spatial image contrast, depth of focus (“DOF”), mask error enhancement factor (“MEEF”), other suitable factors, and combinations thereof. In some embodiments, after the simulated manufactured device is created by the LPC, and if the shape of the simulated device is not close enough to meet design rules, OPC and / or MRC are repeated to further refine the IC design layout 1510.

[0098] It should be understood that the above description of mask data preparation 1512 has been simplified for clarity. In some embodiments, mask data preparation 1512 includes additional features, such as logic operations (LOPs) for modifying IC design layout 1510 according to manufacturing rules. Furthermore, the processes applied to IC design layout 1510 during mask data preparation 1512 can be performed in a variety of different sequences.

[0099] Following mask data preparation 1512 and during mask fabrication 1514, a mask 1516 or a set of masks 1516 is fabricated based on the IC design layout 1510. In some embodiments, mask fabrication 1514 includes performing one or more photolithographic exposures based on the IC design layout 1510. In some embodiments, a mechanism using an electron beam (e-beam) or multiple electron beams is used to form a pattern on one or more masks 1516 (photomasks or photomask templates) based on the IC design layout 1510. The one or more masks 1516 can be formed using various techniques. For example, in some embodiments, the one or more masks 1516 are formed using a binary technique. In some embodiments, the mask pattern includes opaque regions and transparent regions. Radiation beams (e.g., ultraviolet (UV) beams) used to expose an image-sensitive material layer (e.g., photoresist) coated on the wafer are blocked by the opaque regions and transmit through the transparent regions. In one example, one or more binary mask versions of mask 1516 include a transparent substrate (e.g., fused silica) and an opaque material (e.g., chromium) coated in the opaque regions of the binary mask.

[0100] In another example, one or more masks 1516 are formed using a phase-shifting technique. In the phase-shifting mask (PSM) version of one or more masks 1516, various features in the pattern formed on the phase-shifting mask are configured to have appropriate phase differences to improve resolution and imaging quality. In various examples, the phase-shifting mask can be attenuated PSM or alternating PSM. The one or more masks 1516 produced by mask fabrication 1514 are used for various processes. For example, the one or more masks 1516 are used in ion implantation processes to form various doped regions in semiconductor wafers, in etching processes to form various etched regions in semiconductor wafers, and / or in other suitable processes.

[0101] IC fab 1506 includes wafer fabrication 1518. IC fab 1506 is an IC manufacturing enterprise that includes one or more manufacturing facilities for manufacturing various different IC products. In some embodiments, IC fab 1506 is a semiconductor foundry. For example, there may be one manufacturing plant for front-end manufacturing (FEOL manufacturing) of multiple IC products, a second manufacturing plant for back-end manufacturing of IC products (BEOL manufacturing), and a third manufacturing plant for providing additional services for foundry operations.

[0102] IC fab 1506 uses one or more masks 1516 manufactured by mask chamber 1504 to fabricate IC 1508. Therefore, IC fab 1506 uses IC design layout 1510 at least indirectly to fabricate IC 1508. In some embodiments, semiconductor wafer 1520 is fabricated by IC fab 1506 using one or more masks 1516 to form IC 1508. In some embodiments, IC fab 1506 includes performing one or more photolithographic exposures based at least indirectly on IC design layout 1510. Semiconductor wafer 1520 includes a silicon substrate or other suitable substrate on which a material layer is formed. Semiconductor wafer 1520 also includes one or more of various doped regions, dielectric features, multilevel interconnects, etc. (formed in subsequent fabrication steps).

[0103] In one aspect, a 3D integrated circuit structure includes a first die layer and a second die layer disposed vertically above the first die layer. The first die layer includes one or more first devices and visual identity elements (VISs) formed in the first die layer and arranged around the one or more first devices in a first grid layout. The second die layer includes a plurality of second devices and a plurality of VISs formed in the second die layer and arranged around the second devices in a second grid layout. The first grid layout differs from the second grid layout. The density of VISs in the second die layer is greater than the density of VISs in the first die layer.

[0104] In another aspect, a system includes a 3D integrated circuit structure and a power supply operable to connect to the 3D integrated circuit structure. The 3D integrated circuit structure includes a first die layer and a second die layer. The first die layer includes devices and vertical interconnect structures (VISs) formed in the first die layer and arranged in a first grid layout. The second die layer is attached to the first die layer in a vertical direction and includes devices and VISs formed in the second die layer and arranged in a second grid layout. The arrangement of VISs in the first grid layout differs from the arrangement of VISs in the second grid layout. A first density of VISs in the first die layer differs from a second density of VISs in the second die layer.

[0105] In another aspect, a method for manufacturing a 3D integrated circuit structure includes: processing a first die layer to create devices and a first plurality of vertical interconnect structures (VISs) arranged in a first grid layout; processing an intermediate conductive layer on the first die layer; and processing a second die layer to create a plurality of devices and a second plurality of VISs arranged in a second grid layout. Signal lines in the intermediate conductive layer electrically connect corresponding VISs in the first plurality of VISs to corresponding VISs in the second plurality of VISs. The first grid layout on the first die layer differs from the second grid layout on the second die layer.

[0106] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and alterations thereto without departing from the spirit and scope of this disclosure.

[0107] Example 1 is a 3D integrated circuit structure, including: a first die layer including: one or more first devices; and a first plurality of vertical interconnect structures (VIS) formed in the first die layer and arranged in a first grid layout around the one or more first devices; and a second die layer disposed on the first die layer in a vertical direction and including: a plurality of second devices; and a second plurality of VIS formed in the second die layer and arranged in a second grid layout around the plurality of second devices, wherein: the first grid layout is different from the second grid layout; and the density of the second plurality of VIS is greater than the density of the first plurality of VIS.

[0108] Example 2 is the 3D integrated circuit structure described in Example 1, wherein the first spacing of the VIS in the first plurality of VISs is different from the second spacing of the VIS in the second plurality of VISs.

[0109] Example 3 is the 3D integrated circuit structure described in Example 1, wherein each of the one or more first devices and the plurality of second devices includes one of the following: a memory device, a logic circuit, an input / output device, a sensor, an RF circuit, an analog circuit, an analog-to-digital converter, or a computing unit.

[0110] Example 4 is the 3D integrated circuit structure described in Example 1, wherein at least one of the first plurality of VISs is configured to transmit a power signal.

[0111] Example 5 is the 3D integrated circuit structure described in Example 1, wherein at least one of the first plurality of VISs is configured to transmit data signals.

[0112] Example 6 is the 3D integrated circuit structure described in Example 1, wherein the first diameter of each of the first plurality of VISs is different from the second diameter of each of the second plurality of VISs.

[0113] Example 7 is the 3D integrated circuit structure described in Example 1, further comprising: an intermediate conductive layer disposed between the first die layer and the second die layer, and configured to transmit a power signal between the first die layer and the second die layer.

[0114] Example 8 is the 3D integrated circuit structure described in Example 1, wherein the 3D integrated circuit structure is a heterogeneous 3D integrated circuit structure.

[0115] Example 9 is an integrated circuit system comprising: a 3D integrated circuit structure; and a power supply operable to connect to the 3D integrated circuit structure, wherein the 3D integrated circuit structure comprises: a first die layer including: a first plurality of first devices; and a first plurality of vertical interconnect structures (VIS) formed in the first die layer and arranged in a first grid layout; a second die layer disposed on the first die layer in a vertical direction, the second die layer including: a second plurality of second devices; and a second plurality of VIS formed in the second die layer and arranged in a second grid layout, wherein: the arrangement of the first plurality of VIS in the first grid layout is different from the arrangement of the second plurality of VIS in the second grid layout; and a first density of the first plurality of VIS is different from a second density of the second plurality of VIS.

[0116] Example 10 is the system described in Example 9, wherein the first spacing of the VISs in the first plurality of VISs is different from the second spacing of the VISs in the second plurality of VISs.

[0117] Example 11 is the system described in Example 9, wherein the first diameter of the VIS in the first plurality of VISs is different from the second diameter of the VIS in the second plurality of VISs.

[0118] Example 12 is the system described in Example 9, wherein the 3D integrated circuit structure is a homogeneous 3D integrated circuit structure.

[0119] Example 13 is the system described in Example 9, wherein: at least one of the first devices in the plurality of first devices includes a computing unit; and at least one of the second devices in the plurality of second devices includes a memory device.

[0120] Example 14 is the system described in Example 13, wherein at least one of the second devices in the plurality of second devices includes at least one of the following: logic circuitry, input / output devices, RF circuitry, analog circuitry, or analog-to-digital converter.

[0121] Example 15 is the system described in Example 9, wherein: the power supply is operable to connect to the first die layer; and the first density is greater than the second density.

[0122] Example 16 is the system described in Example 9, wherein: the power supply is operable to connect to the second die layer; and the second density is greater than the first density.

[0123] Example 17 is the system described in Example 9, further comprising: an intermediate die layer disposed between and attached to the first die layer and the second die layer, the intermediate die layer comprising: a third plurality of third devices; and a third plurality of VISs, wherein the third density of the third plurality of VISs is less than the second density and greater than the first density.

[0124] Example 18 is the system described in Example 9, further comprising: an intermediate conductive layer disposed between the first die layer and the second die layer, the intermediate conductive layer including signal lines configured to transmit power signals between a corresponding VIS of a first plurality of VISs in the first die layer and a corresponding VIS of a second plurality of VISs in the second die layer.

[0125] Example 19 is a method for manufacturing a 3D integrated circuit structure, the method comprising: processing a first die layer to generate devices and a first plurality of vertical interconnect structures (VISs) on the first die layer, the first plurality of VISs being arranged in a first grid layout; processing an intermediate conductive layer above the first die layer to generate signal lines; processing a second die layer to generate a plurality of devices and a second plurality of VISs on the second die layer, the second plurality of VISs being arranged in a second grid layout; and attaching the second die layer to the first die layer, wherein: the arrangement of the first plurality of VISs in the first grid layout is different from the arrangement of the second plurality of VISs in the second grid layout; and the signal lines electrically connect corresponding VISs in the first plurality of VISs to corresponding VISs in the second plurality of VISs.

[0126] Example 20 is the method described in Example 19, wherein: the device on the first die layer is a computing unit; and each of the second plurality of devices includes one of the following: a memory device, a logic circuit, an input / output device, a sensor, an RF circuit, an analog circuit, or an analog-to-digital converter.

Claims

1. A 3D integrated circuit structure, comprising: The first die layer includes: One or more first devices; and A plurality of vertical interconnect structures (VIS) are formed in the first die layer and arranged in a first grid layout around the one or more first devices; and The second core layer is disposed vertically on top of the first core layer and includes: Multiple second devices; A second plurality of VISs are formed in the second die layer and arranged in a second grid layout around the plurality of second devices, wherein: The first grid layout is different from the second grid layout; and The density of the second plurality of VISs is greater than the density of the first plurality of VISs. The density of the first plurality of VISs is based on one or more of the following factors: the type of the one or more first devices, the power requirements of the one or more first devices, the power requirements of the plurality of second devices, and the IR voltage drop experienced by the signal at the second die layer, and the density of the second plurality of VISs is based on one or more of the following factors: the type of the plurality of second devices, and the power requirements of the plurality of second devices.

2. The 3D integrated circuit structure according to claim 1, wherein, The first spacing of the VIS in the first plurality of VISs is different from the second spacing of the VIS in the second plurality of VISs.

3. The 3D integrated circuit structure according to claim 1, wherein, Each of the one or more first devices and the plurality of second devices includes one of the following: a memory device, a logic circuit, an input / output device, a sensor, an RF circuit, an analog circuit, an analog-to-digital converter, or a computing unit.

4. The 3D integrated circuit structure according to claim 1, wherein, At least one of the first plurality of VISs is configured to transmit a power signal.

5. The 3D integrated circuit structure according to claim 1, wherein, At least one of the first plurality of VISs is configured to transmit data signals.

6. The 3D integrated circuit structure according to claim 1, wherein, The first diameter of each of the first plurality of VISs is different from the second diameter of each of the second plurality of VISs.

7. The 3D integrated circuit structure according to claim 1, further comprising: An intermediate conductive layer is disposed between the first die layer and the second die layer and is configured to transmit power signals between the first die layer and the second die layer.

8. The 3D integrated circuit structure according to claim 1, wherein, The 3D integrated circuit structure is a heterogeneous 3D integrated circuit structure.

9. An integrated circuit system, comprising: 3D integrated circuit structure; as well as A power supply, operable to be connected to the 3D integrated circuit structure, wherein the 3D integrated circuit structure includes: A first die layer, the first die layer comprising: The first plurality of first devices; and A plurality of vertical interconnect structures (VIS) are formed in the first die layer and arranged in a first grid layout; A second core layer is disposed vertically above the first core layer, and the second core layer comprises: The second and multiple second devices; and The second plurality of VISs are formed in the second core layer and arranged in a second grid layout, wherein: The arrangement of the first plurality of VISs in the first grid layout differs from the arrangement of the second plurality of VISs in the second grid layout; and The first density of the first plurality of VISs is different from the second density of the second plurality of VISs. The first density of the first plurality of VISs is based on one or more of the following factors: the type of the first plurality of first devices, the power requirements of the first plurality of first devices, the power requirements of the second plurality of second devices, and the IR voltage drop experienced by the signal at the second die layer, and the second density of the second plurality of VISs is based on one or more of the following factors: the type of the second plurality of second devices, and the power requirements of the second plurality of second devices.

10. The system according to claim 9, wherein, The first spacing of the VIS in the first plurality of VISs is different from the second spacing of the VIS in the second plurality of VISs.

11. The system according to claim 9, wherein, The first diameter of the VIS in the first plurality of VISs is different from the second diameter of the VIS in the second plurality of VISs.

12. The system according to claim 9, wherein, The 3D integrated circuit structure is a homogeneous 3D integrated circuit structure.

13. The system according to claim 9, wherein: At least one of the first devices in the plurality of first devices includes a computing unit; and At least one of the second devices in the plurality of second devices includes a memory device.

14. The system according to claim 13, wherein, At least one of the second devices in the plurality of second devices includes at least one of the following: logic circuits, input / output devices, RF circuits, analog circuits, or analog-to-digital converters.

15. The system according to claim 9, wherein: The power supply is operable to connect to the first die layer; and The first density is greater than the second density.

16. The system according to claim 9, wherein: The power supply is operable to connect to the second die layer; and The second density is greater than the first density.

17. The system according to claim 9, further comprising: An intermediate die layer, wherein the intermediate die layer is disposed between the first die layer and the second die layer and is attached to the first die layer and the second die layer, the intermediate die layer comprising: Third, multiple third devices; and A third plurality of VISs, wherein the third density of the third plurality of VISs is less than the second density and greater than the first density.

18. The system according to claim 9, further comprising: An intermediate conductive layer is disposed between the first die layer and the second die layer. The intermediate conductive layer includes signal lines configured to transmit power signals between a corresponding VIS in a first plurality of VISs in the first die layer and a corresponding VIS in a second plurality of VISs in the second die layer.

19. A method for manufacturing a 3D integrated circuit structure, the method comprising: The first die layer is processed to generate devices and a first plurality of vertical interconnect structures (VIS) on the first die layer, the first plurality of VIS being arranged in a first grid layout; The intermediate conductive layer above the first die layer is processed to generate signal lines; The second die layer is processed to generate multiple devices and a second plurality of VISs on the second die layer, the second plurality of VISs being arranged in a second grid layout; as well as The second die layer is attached to the first die layer, wherein: The arrangement of the first plurality of VISs in the first grid layout differs from the arrangement of the second plurality of VISs in the second grid layout; and The signal line electrically connects the corresponding VIS in the first plurality of VISs to the corresponding VIS in the second plurality of VISs. The density of the first plurality of VISs is based on one or more of the following factors: the type of device on the first die layer, the power requirements of the device on the first die layer, the power requirements of the device on the second die layer, and the IR voltage drop experienced by the signal at the second die layer, and the density of the second plurality of VISs is based on one or more of the following factors: the type of device on the second die layer, and the power requirements of the device on the second die layer.

20. The method of claim 19, wherein: The devices on the first die layer are computing units; and Each of the second plurality of devices includes one of the following: a memory device, a logic circuit, an input / output device, a sensor, an RF circuit, an analog circuit, or an analog-to-digital converter.

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