Microelectronic devices with doped extensions, and related methods and systems

Abstract

This application relates to microelectronic devices and related methods and systems having doped extensions near a GIDL region below a hierarchical stack. The microelectronic device includes a stacked structure comprising a vertically alternating sequence of insulating and conductive structures arranged in a hierarchical manner. At least one pillar comprising channel material extends through the stacked structure. A source region below the stacked structure comprises doped material. The vertical extension of the doped material protrudes upward at an elevation within the stacked structure (e.g., at an elevation close to or laterally overlapping at least one source-side GIDL region) to an interface with the channel material. The microelectronic device structure can be formed by a method comprising the steps of: forming a lateral opening in the unit material through the pillar; recessing the channel material to form a vertical recess; and forming the doped material in the vertical recess. Additional microelectronic devices, and related methods and electronic systems are also disclosed.

Description

[0001] Priority Claim

[0002] This application claims the benefit of U.S. Patent Application Serial No. 17 / 158,859, filed January 26, 2021, entitled “Microelectronic Devices with Dopant Extensions Near a GIDL Region Below a Tier Stack, and Relatted Methods and Systems”. Technical Field

[0003] Embodiments of this disclosure relate to the field of microelectronic device design and manufacturing. More specifically, this disclosure relates to methods, related systems, and methods for forming microelectronic devices (e.g., memory devices, such as 3D NAND memory devices) having a layered stacked structure comprising vertically alternating conductive and insulating structures. Background Technology

[0004] Memory devices provide data storage for electronic systems. Flash memory devices are one of various types of memory devices and have numerous uses in modern computers and other electronic devices. Conventional flash memory devices may comprise memory arrays having a large number of charge memory devices (e.g., memory cells, such as non-volatile memory cells) arranged in rows and columns. In NAND architecture type flash memory, memory cells arranged in columns are coupled in series, and the first memory cell of the column is coupled to a data line (e.g., a bit line). In “three-dimensional NAND” memory devices (which may also be referred to herein as “3D NAND” memory devices), a type of vertical memory device is not only memory cells arranged in rows and columns in a horizontal array, but also layers of the horizontal array are stacked on top of each other (e.g., as vertical memory cell strings) to provide a “three-dimensional array” of memory cells. The stacked layers contain conductive materials that alternate vertically with insulating (e.g., dielectric) materials. The conductive material serves as the control gate for, for example, access lines (e.g., word lines) of memory cells. Vertical structures (e.g., pillars including channel structures and tunneling structures) extend along the vertical strings of memory cells. The drain end of the string is adjacent to one of the top and bottom of a vertical structure (e.g., a pillar), while the source end of the string is adjacent to the other of the top and bottom of a pillar. The drain end is operatively connected to a bit line, and the source end is operatively connected to a source line. The 3D NAND memory device also includes electrical connections, such as access lines (e.g., word lines), to other conductive structures of the device, such that the memory cells of the vertical string can be selected for write, read, and erase operations.

[0005] The channel structure of a 3D NAND memory device can be configured as a so-called "hollow" channel structure having a channel material laterally surrounding a central or core of pillars. Block erasure of memory cells in such 3D NAND memory devices involves injecting holes (e.g., electron holes) into the channel material. For example, a gated conductive structure connected to the hollow channel structure can be used to provide gate-induced drain leakage (GIDL), generating holes that can be swept into other parts of the hollow channel structure by an electron field. This "GIDL" region may also be referred to herein or in the art as a "selection device". The gated connection between the GIDL region and the hollow channel structure can be facilitated by including a relatively higher doping level in the hollow channel structure near the GIDL region than in other parts of the hollow channel structure. Thus, the GIDL region can generate holes in the hollow channel region to achieve block erasure of the memory cell.

[0006] Conventional 3D NAND structures utilize holes injected using a GIDL region near the drain region at the top of the layered stack. However, as stacks scale up to add more levels and more memory cells, conventional one-sided (e.g., top-down) GIDL injection may be functionally insufficient to ensure complete block erasure of memory cell strings. Efforts have been made to include a bottom-up GIDL region near the source region in addition to an upper GIDL region near the drain region for top-down hole injection. However, designing and fabricating such structures continues to present challenges. Summary of the Invention

[0007] A microelectronic device comprising a stacked structure is disclosed. The stacked structure includes a vertically alternating sequence of insulating and conductive structures arranged in layers. At least one pillar extends through the stacked structure. The at least one pillar comprises a channel material. A source region is located below the stacked structure. The source region comprises a doped material. A vertical extension of the doped material projects upward to an interface with the channel material. The interface is located at an elevation within the stacked structure.

[0008] A method for forming a microelectronic device is also disclosed. The method includes forming a sacrificial material stack on a substrate structure. A layered stack structure is formed on the sacrificial material stack. The layered stack structure includes a vertically alternating sequence of insulating structures and other structures arranged in a hierarchical manner. A pillar opening is formed through the layered stack structure, through the sacrificial material, and into the substrate structure. Cell material, channel material, and insulating core material are formed in the pillar opening. A slit is formed through the layered stack structure and at least partially through the sacrificial material stack. At least one of the sacrificial material and the sacrificial material stack is selectively removed to expose at least one cell material formed in the pillar opening. A lateral opening is formed through the cell material to expose a portion of the channel material in the lateral opening. The channel material is recessed to form a vertical recess protruding into the stack structure at an elevation. A doped material is formed in the vertical recess.

[0009] Furthermore, an electronic system including an input device, an output device, a processor device, and a memory device is disclosed. The processor device is operatively coupled to the input device and the output device. The memory device is operatively coupled to the processor device. The memory device includes at least one microelectronic device structure. The at least one microelectronic device structure includes a stacked structure. The stacked structure includes insulating structures perpendicularly intersecting with conductive structures. Pillars extend through the stacked structure, through a region of doped material below the stacked structure, and to a substrate structure below the region of doped material. The doped material extends laterally into at least one of the pillars and upward within the at least one pillar to an interface with a channel material of the at least one of the pillars. The interface is at an elevation within the stacked structure and is close to at least one of the lowermost conductive structures of the stacked structure. Attached Figure Description

[0010] Figure 1 This is a schematic cross-sectional and elevation view of a microelectronic device structure according to an embodiment of the present disclosure, wherein the doped material of the source region includes a vertical extension protruding to an elevation at or near the elevation of at least one lower GIDL region.

[0011] Figure 2 This is a schematic cross-sectional and elevation view of a microelectronic device structure according to embodiments of the present disclosure, wherein the microelectronic device may include... Figure 1 The structure of microelectronic devices makes Figure 1 The explanation corresponds to Figure 2 A magnified view of box 102.

[0012] Figure 3 According to embodiments of this disclosure Figure 2 A schematic top-view diagram of the structure of a microelectronic device, in which... Figure 2 The view is along Figure 3 The section line AA is cut off.

[0013] Figure 4A and Figure 4B Each is a schematic cross-sectional and elevation view of a memory cell according to an embodiment of the present disclosure, wherein the illustrated areas correspond to... Figure 1 and / or Figure 2 Box 104.

[0014] Figures 5 to 15 It is for manufacturing according to embodiments of the present disclosure Figures 1 to 3 A schematic illustration of the cross-sections and elevations of the various stages of the processing of the microelectronic device structure.

[0015] Figures 16 to 26 Together Figure 5 and Figure 6It is for manufacturing according to embodiments of the present disclosure Figure 26 , Figure 27 and Figure 3 The diagram illustrates the cross-sections and elevations of various stages of the processing of the microelectronic device structure, including... Figure 16 The stage at Figure 6 After that stage.

[0016] Figure 26 This is a schematic cross-sectional and elevation view of a microelectronic device structure according to an embodiment of the present disclosure, wherein the doped material of the source region includes a vertical extension protruding to an elevation at or near the elevation of at least one lower GIDL region. Figure 4A and / or Figure 4B The memory cells and the described areas of any one or both of them may correspond, for example, to those indicated by box 104. Figure 26 The part.

[0017] Figure 27 This is a schematic cross-sectional and elevation view of a microelectronic device structure according to embodiments of the present disclosure, the microelectronic device structure may include... Figure 2 The structure of the microelectronic device (and therefore also includes) Figure 4A and / or Figure 4B (any or both of the memory cells 402) make Figure 26 The explanation can be corresponding to Figure 27 An enlarged view of box 102. Furthermore... Figure 27 A top-view schematic diagram of the structure of a microelectronic device can be used as... Figure 3 The schematic diagram of the top view shown in the figure, in which Figure 27 The explanation is along Figure 3 The view intercepted by section line AA.

[0018] Figure 28 This is a partial cross-sectional perspective schematic illustration of a microelectronic device according to embodiments of the present disclosure.

[0019] Figure 29 This is a block diagram of an electronic system according to an embodiment of the present disclosure.

[0020] Figure 30 This is a block diagram of a processor-based system according to an embodiment of the present disclosure. Detailed Implementation

[0021] Structures (e.g., microelectronic device structures), devices (e.g., microelectronic devices), and systems (e.g., electronic systems) according to embodiments of this disclosure include a stack of vertically alternating conductive and insulating structures arranged in a hierarchical manner with pillars extending vertically through them. A source region including a doped material (e.g., a doped semiconductor material) lies beneath the stack. Pillars extend through the doped material in the source region. The source region is formed such that vertical extensions of the doped material can protrude upwards from the source region at a lower elevation of the stack to approach a conductive structure configured as a gate-induced drain-leak (GIDL) region or an elevation containing said conductive structure. The vertical extensions of the doped material occupy vertical recesses formed in the channel material. The dopant (of the doped material) is thus positioned relatively close to the GIDL region(s) and facilitates a reliable gated connection between the GIDL region and the channel material on top of the doped material extension, thereby providing a more reliable block erase operation.

[0022] As used herein, the terms “gate-sensed drain leakage region” and “GIDL region” mean and include a conductive region (e.g., a conductive structure, a conductive layer) configured to generate holes (e.g., electron holes) in the adjacent channel material during a block erase operation such that the holes are swept into the channel material by an electron field, thereby erasing the memory cell associated with the pillar containing the channel material. This GIDL region may also be referred to herein or in the art as a “select gate” or a “select device.” When the GIDL region is adjacent to the source region, the GIDL region may also be referred to herein or in the art as a “source-side select device,” “source-gate select device,” or an SGS device. When the GIDL region is adjacent to the drain region, the GIDL region may also be referred to herein or in the art as a “drain-side select device,” “drain-gate select device,” or an SGD device.

[0023] As used herein, the terms “opening,” “groove,” “slit,” “recess,” and “void” mean and encompass a volume extending through or into at least one structure or at least one material, thereby leaving a gap in said at least one structure or at least one material, or a volume extending between structures or materials, thereby leaving a gap between the structures or materials. Unless otherwise described, an “opening,” “groove,” “slit,” and / or “recess” does not necessarily contain no material. That is, an “opening,” “groove,” “slit,” or “recess” is not necessarily an empty space. An “opening,” “groove,” “slit,” or “recess” formed in or between a structure or material may include a structure or material different from the structure or material in which or between the openings are formed. Furthermore, the structure or material(s) “exposed” within an opening, groove, slit, or recess is not necessarily in contact with the atmosphere or a non-solid environment. The structures or materials(s) "exposed" within openings, grooves, slits, or recesses may be adjacent to or in contact with other structures or materials(s) disposed within the openings, grooves, slits, or recesses. In contrast, unless otherwise described, a "void" may be substantially or entirely devoid of material. A "void" formed in or between structures or materials may not include structures or materials other than those forming the "void" therein or between. Furthermore, structures or materials "exposed" within "voids" may be in contact with the atmosphere or a non-solid environment.

[0024] As used herein, the terms “groove” and “slit” mean and include an elongated opening, while the terms “opening,” “recess,” and “gap” may include (respectively) an elongated opening, an elongated recess, or an elongated gap and / or (respectively) any or both of a non-elongated opening, a non-elongated recess, or a non-elongated gap.

[0025] As used herein, the terms “substrate” and “substrate structure” mean and include the substrate material or other construction on which components, such as those formed within a memory cell, are formed. A substrate or substrate structure may be a semiconductor substrate, a substrate semiconductor material on a support structure, a metal electrode, or a semiconductor substrate on which one or more materials, structures, or regions are formed. A substrate may be a conventional silicon substrate or other bulk substrate containing a semiconducting material. As used herein, the term “bulk substrate” means and includes not only silicon wafers, but also silicon-on-insulator (“SOI”) substrates (e.g., silicon-on-sapphire (“SOS”) or silicon-on-glass (“SOG”) substrates), silicon epitaxial layers on a substrate semiconductor substrate, or other semiconductor or optoelectronic materials, such as silicon-germanium (Si... 1-x Ge xWhere x is, for example, a mole fraction between 0.2 and 0.8), germanium (Ge), gallium arsenide (GaAs), gallium nitride (GaN), or indium phosphide (InP), etc. Furthermore, when referred to as “substrate” or “substrate structure” in the following description, the preceding process stages may have been used to form materials, structures, or junctions in a substrate semiconductor structure, substrate structure, or other substrate.

[0026] As used herein, when referring to materials or structures, the term "insulating" means and includes electrically insulating materials or structures. An "insulating" material or structure may be formed of and include one or more of the following: at least one dielectric oxide material (e.g., silicon oxide (SiO2)). x Phosphorus silicate glass, borosilicate glass, borosilicate-phosphorus silicate glass, fluorosilicate glass, alumina (AlO) x ), Hafnium oxide (HfO) x ), niobium oxide (NbO) x Titanium oxide (TiO) x Zirconium oxide (ZrO) x ), tantalum oxide (TaO) x ) and magnesium oxide (MgO) x One or more of the following), at least one dielectric nitride material (e.g., silicon nitride (SiN) y ()), at least one dielectric oxide material (e.g., silicon oxynitride (SiO) x N y ()), at least one dielectric carbon nitride material (e.g., silicon carbon nitride (SiO) x C z N y )) and / or air. This document contains the chemical formula of one or more of “x”, “y” and / or “z” (e.g., SiO2) x AlO x HfO x NbO x TiO x SiN y SiO x N y SiO x C z N yThe chemical formula represents a material in which each atom of another element (e.g., Si, Al, Hf, Nb, Ti) contains an average ratio of "x" atoms of one element, "y" atoms of the other element, and "z" atoms of an additional element (if present). Since a chemical formula represents a relative atomic ratio and does not limit the chemical structure, an insulating material or insulating structure may include one or more stoichiometric compounds and / or one or more non-stoichiometric compounds, and the values ​​of "x", "y", and "z" (if present) may be integers or non-integers. As used herein, the term "non-stoichiometric compound" means and includes chemical compounds having elemental compositions that cannot be expressed by a well-defined ratio of natural numbers and violate the law of definite proportions. Additionally, "insulating structure" means and includes structures formed of and containing one or more insulating materials.

[0027] As used herein, the term “sacrifice” as used with reference to materials or structures means and includes materials or structures that are formed during the manufacturing process but removed (e.g., substantially removed) before the completion of the manufacturing process.

[0028] As used herein, the term "horizontal" means and includes a direction parallel to the main surface of the substrate on which the referenced material or structure is positioned. The width and length of the corresponding material or structure can be defined as dimensions in the horizontal plane. Referring to the figures, the "horizontal" direction can be perpendicular to the indicated "Z" axis, parallel to the indicated "X" axis, and parallel to the indicated "Y" axis.

[0029] As used herein, the term "lateral" means and includes a direction in a horizontal plane parallel to the main surface of the substrate on which the referenced material or structure is positioned and generally perpendicular to the "longitudinal" direction. The width of the corresponding material or structure can be defined as its dimension in the lateral direction of the horizontal plane. Referring to the figures, the "lateral" direction may be parallel to the indicated "X" axis, perpendicular to the indicated "Y" axis, and perpendicular to the indicated "Z" axis.

[0030] As used herein, the term "longitudinal" means and encompasses a direction in a horizontal plane parallel to the main surface of the substrate on which the referenced material or structure is positioned and generally perpendicular to the "lateral" direction. The length of the corresponding material or structure can be defined as its dimension in the longitudinal direction of the horizontal plane. Referring to the figures, the "longitudinal" direction may be parallel to the indicated "Y" axis, perpendicular to the indicated "X" axis, and perpendicular to the indicated "Z" axis.

[0031] As used herein, the term "vertical" means and includes a direction perpendicular to the main surface of the substrate on which the referenced material or structure is positioned. The "height" of the corresponding material or structure can be defined as a dimension in the vertical plane. Referring to the figures, the "vertical" direction may be parallel to the indicated "Z" axis, perpendicular to the indicated "X" axis, and perpendicular to the indicated "Y" axis.

[0032] As used herein, the term “width” means and includes the dimension of the material or structure under discussion along the indicated “X” axis in a horizontal plane (e.g., at a particular elevation, if identified), defining the maximum distance along this “X” axis. For example, the “width” of a structure that is at least partially hollow or at least partially filled with one or more other materials is the horizontal dimension between the outermost edges or sidewalls of the structure, such as the outer diameter of the “X” axis of a hollow or filled cylindrical structure.

[0033] As used herein, the term "length" means and includes the dimension of the material or structure under discussion along the indicated "Y" axis in a horizontal plane (e.g., at a particular elevation, if identified), defining the maximum distance along this "Y" axis. For example, the "length" of a structure that is at least partially hollow or at least partially filled with one or more other materials is the horizontal dimension between the outermost edges or sidewalls of the structure, such as the outer diameter of the "Y" axis of a hollow or filled cylindrical structure.

[0034] As used herein, when referring to the relative arrangement of at least two materials or structures, the term "lateral overlap" is a spatial relative term meaning and encompassing at least a portion of at least one horizontal plane (e.g., elevation, step) occupied by one of the at least two materials or structures and also occupied by at least a portion of another of the at least two materials or structures. Thus, a structure of a "laterally overlapped" second structure comprises a first structure having at least a portion that overlaps with at least a portion of the second structure at elevation. Materials or structures described as "laterally overlapped" (without mention of "direct") may be directly or indirectly laterally overlapped. "Directly laterally overlapped" materials or structures are each physically in contact with one or more of the other directly laterally overlapped materials or structures in their respective directly laterally overlapped areas. Therefore, "directly laterally overlapped" materials or structures are directly physically in contact with each other at elevations within the directly laterally overlapped areas. "Indirectly laterally overlapped" materials or structures are physically spaced apart from each other in their respective indirectly laterally overlapped areas. Therefore, "indirectly laterally overlapped" materials or structures are not directly physically in contact with each other at elevations within the indirectly laterally overlapped areas.

[0035] As used herein, when referring to the relative arrangement of at least two materials or structures, the term "vertical overlap" is a spatial relative term meaning and encompassing at least a portion of at least one vertical plane occupied by one of the at least two materials or structures and also occupied by at least a portion of another of the at least two materials or structures. Materials or structures described as "vertically overlap" (without mention of "direct") may be directly vertically overlapped or indirectly vertically overlapped. "Directly vertically overlapped" materials or structures are each physically in contact with one or more of the other directly vertically overlapped materials or structures in their respective directly vertically overlapped areas. "Indirectly vertically overlapped" materials or structures are physically spaced apart from each other in their respective indirect vertical overlap areas.

[0036] As used herein, the terms “thickness” or “thinness” are spatially relative terms that refer to and encompass a dimension in a linear direction perpendicular to the nearest surface of an adjacent material or structure having a different composition or which may otherwise be distinguished from materials or structures that are discussed in terms of their thickness, thinness, or height.

[0037] As used herein, the term "between" is a spatially relative term used to describe the relative placement of a material, structure, or substructure with respect to at least two other materials, structures, or substructures. The term "between" can encompass placements where a material, structure, or substructure is directly adjacent to other materials, structures, or substructures, as well as placements where a material, structure, or substructure is indirectly adjacent to other materials, structures, or substructures.

[0038] As used herein, the term "proximity" is used to describe the placement of one material, structure, or substructure close to another material, structure, or substructure. The term "proximity" includes placement that is indirectly adjacent to, directly adjacent to, and internal to another material, structure, or substructure.

[0039] As used herein, when referring to materials or structures, the term "adjacent" is a spatially relative term meaning and referring to the next closest material or structure of the identified composition or property. Materials or structures of other compositions or properties besides the identified composition or property may be positioned between a material or structure and its "adjacent" material or structure of the identified composition or property. For example, the structure of material X "adjacent to" a structure of material Y is, for example, the first material X structure among a plurality of material X structures, which is next closest to a specific structure of material Y. "Adjacent" materials or structures may be directly or indirectly adjacent to the structure or material of the identified composition or property.

[0040] As used herein, when referring to the parameters, properties, or conditions of one structure, material, feature, or part thereof relative to the parameters, properties, or conditions of another such structure, material, feature, or part thereof, the term "consistent" means and encompasses relative terms in which the parameters, properties, or conditions of the two structures, materials, features, or parts are at least equal, substantially equal, or approximately equal according to their respective arrangements. For example, two structures having "consistent" thickness may each define the same, substantially equal, or approximately equal thickness at a lateral distance X from the feature, even though the two structures are at different elevations along the feature. As another example, a structure having "consistent" width may have two parts at elevation Y1 of this structure, each defining a width that is the same, substantially equal, or approximately equal at elevation Y2 of this structure.

[0041] As used herein, the terms “about” and “approximately” when used with reference to a numerical value of a particular parameter include the degree of deviation of the numerical value from the value, which will be understood by one of ordinary skill in the art as being within acceptable tolerances of the particular parameter. For example, “about” or “approximately” with respect to a numerical value may include additional values ​​within the range of 90.0% to 110.0% of the numerical value (e.g., within the range of 95.0% to 105.0%, 97.5% to 102.5%, 99.0% to 101.0%, 99.5% to 100.5%, or 99.9% to 100.1%).

[0042] As used herein, the term "substantially" when referring to a parameter, property, or condition means and includes that the parameter, property, or condition is equal to a given value or within a certain degree of difference from the given value, such that a person skilled in the art would understand that the given value is acceptablely satisfied, for example, within acceptable manufacturing tolerances. By way of example, depending on the specific parameter, property, or condition that is substantially satisfied, the parameter, property, or condition may be "substantially" the value when it is satisfied by at least 90.0%, at least 95.0%, at least 99.0%, or even at least 99.9%.

[0043] As used herein, when an element is referred to as being “on” or “above” another element, the term “on” or “above” is a spatially relative term meaning and encompassing that the element is directly on top of the other element, directly adjacent (e.g., laterally adjacent, horizontally adjacent, longitudinally adjacent, vertically adjacent) of the other element, directly below the other element, or directly in contact with the other element. It also encompasses an element being indirectly on top of, indirectly adjacent (e.g., laterally adjacent, horizontally adjacent, longitudinally adjacent, vertically adjacent) of, or indirectly below or near the other element, wherein other elements exist between them. Conversely, when an element is referred to as being “directly on” or “directly adjacent to” another element, no intermediate elements are present.

[0044] As used herein, for ease of description, other spatial relative terms such as “below,” “under,” “bottom,” “above,” “top,” and similar terms may be used to describe the relationship of one element or feature to another, as illustrated in the figures. Unless otherwise stated, any spatial relative terms used in this disclosure are intended to cover different orientations of material other than those depicted in the figures. For example, if the material in the figures were inverted, then an element described as “below” or “below” or “on the bottom” of another element or feature would then be oriented “above” or “on top” of that other element or feature. Thus, depending on the context in which the term is used, the term “below” can cover both above and below orientations, as will be apparent to one of ordinary skill in the art. Material may be oriented in other ways (rotated ninety degrees, inverted, etc.), and the spatial relative descriptions used herein shall be interpreted accordingly.

[0045] As used herein, the terms “step” and “elevation” are spatially relative terms used to describe the relationship of one material or feature to another, as illustrated in the figures, using—as a reference point—the lowest illustrated surface of the structure containing the material or feature. As used herein, “step” and “elevation” are each defined freely parallel to a horizontal plane on or within the main surface of the substrate or base structure on which the structure (containing the material or feature) is formed. “Lower step” and “lower elevation” are relatively closer to the lowest illustrated surface of the corresponding structure, while “higher step” and “higher elevation” are relatively farther from the lowest illustrated surface of the corresponding structure. Unless otherwise specified, any spatially relative terms used in this disclosure are intended to cover different orientations of the material other than those depicted in the figures. For example, the material in the figures may be inverted, rotated, etc., wherein the “upper” step and elevation described next are near the bottom of the page, and the “lower” step and elevation described next are near the top of the page.

[0046] As used herein, the terms “comprising,” “including,” “having,” and their grammatical equivalents are inclusive or open-ended terms that do not exclude additional, unreferenced elements or method steps, but also include the more restrictive terms “consisting of” and “substantially consisting of” and their grammatical equivalents. Thus, a structure described as “comprising,” “including,” and / or “having” materials may be a structure that also includes additional materials in some embodiments and / or does not include any other materials in some embodiments. Similarly, a composition (e.g., a gas) described as “comprising,” “including,” and / or “having” species may be a composition that also includes additional species in some embodiments and / or does not include any other species in some embodiments.

[0047] As used herein, the term “may” in relation to materials, structures, features, or methodological actions indicates consideration for their use in implementing embodiments of this disclosure, and this term is used preferentially over the more restrictive term “is” to avoid any implication that other, compatible materials, structures, features, and methods that may be used in combination with it should be excluded or must be excluded.

[0048] As used in this document, “and / or” means and includes any one or more of the associated items and all combinations thereof.

[0049] As used herein, the singular forms “a / an” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0050] As used herein, the “(s)” at the end of a term indicates and includes the singular and / or plural form of the term, unless the context clearly indicates otherwise.

[0051] As used herein, the terms “configured” and “configured” mean and refer to the size, shape, material composition, orientation, and arrangement of a reference material, structure, assembly, or device in order to facilitate the reference operation or properties of the reference material, structure, assembly, or device in a predetermined manner.

[0052] The description presented herein is not intended to be an actual view of any particular material, structure, substructure, region, subregion, device, system, or manufacturing stage, but is merely an idealized representation for describing embodiments of this disclosure.

[0053] This document describes embodiments with reference to cross-sectional views as schematic diagrams. Therefore, variations from the illustrated shapes are expected due to factors such as manufacturing techniques and / or tolerances. Consequently, the embodiments described herein should not be construed as limited to the specific shapes or structures illustrated, but may include shape deviations, for example, due to manufacturing techniques. For instance, a box-shaped structure illustrated or described may have rough and / or non-linear characteristics. Furthermore, the illustrated acute angles may be rounded. Therefore, the materials, features, and structures illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the materials, features, or structures, and do not limit the scope of the claims.

[0054] The following description provides specific details, such as material types and processing conditions, to provide a thorough description of embodiments of the disclosed apparatus (e.g., devices, systems) and methods. However, those skilled in the art will understand that embodiments of the apparatus and methods can be practiced without these specific details. In fact, embodiments of the apparatus and methods can be practiced in conjunction with conventional semiconductor manufacturing techniques used in industry.

[0055] The manufacturing processes described herein do not form a complete process flow for processing equipment (e.g., apparatus, system) or its structure. The remainder of the process flow is known to those skilled in the art. Therefore, only the methods and structures necessary for understanding embodiments of the equipment (e.g., apparatus, system) and methods of the present invention are described herein.

[0056] Unless the context otherwise indicates, the materials described herein may be formed by any suitable technique including (but not limited to) spin coating, blanket coating, chemical vapor deposition (“CVD”), atomic layer deposition (“ALD”), plasma-enhanced ALD, physical vapor deposition (“PVD”) (e.g., sputtering) or epitaxial growth. Depending on the specific material to be formed, the technique used for depositing or growing the material may be selected by one of ordinary skill in the art.

[0057] Unless the context otherwise indicates, the removal of the material described herein can be accomplished by any suitable technique that includes (but is not limited to) etching (e.g., dry etching, wet etching, vapor phase etching), ion milling, grinding planarization, or other known methods.

[0058] When referring to diagrams, similarity numbers always refer to similar components. Diagrams are not necessarily drawn to scale.

[0059] refer to Figure 1The microelectronic device structure 100 is illustrated in the elevation cross-sectional view, comprising a stacked structure 108 of vertically alternating (e.g., vertically staggered) insulating structures 110 and conductive structures 112 arranged in layers 114. Slit structures 116 extend through the stacked structure 108, through the doped material 118, and into or within the substrate structure 120 to divide the stacked structure 108 into blocks, as further discussed below. Pillars 122 containing channel material 106 also extend through the stacked structure 108, through the doped material 118, and into the substrate structure 120.

[0060] The substrate structure 120 may be formed of, for example, a semiconductor material (e.g., polysilicon) and may contain, for example, the semiconductor material. A doped material 118 inserted between the substrate structure 120 and the stacked structure 108 provides a source region 124 adjacent to the lower end of the pillar 122. The doped material 118 may be formed of, for example, a semiconductor material (e.g., the semiconductor material of the substrate structure 120) doped with either a P-type conductive material (e.g., polysilicon doped with at least one P-type dopant (e.g., one or more of boron, aluminum, and / or gallium)) or an N-type conductive material (e.g., polysilicon doped with at least one N-type dopant (e.g., one or more of arsenic, phosphorus, and / or antimony)).

[0061] The slit structure 116 extending through the stacked structure 108, through the doped material 118, and into the substrate structure 120 or into the substrate structure 120 may include an insulating liner 126 (e.g., formed of and comprising one or more insulating materials) and a non-conductive filler 128 (e.g., any or more of the aforementioned insulating materials and / or a semiconductive material such as polysilicon). In some embodiments, the sidewalls of the conductive structure 112 are laterally recessed relative to the insulating structure 110 along the slit structure 116. In such embodiments, the insulating liner 126 extends laterally corresponding to the laterally recessed portion of the conductive structure 112.

[0062] In the stacked structure 108, the insulating structure 110 may be formed of and contain at least one insulating material 130, for example, it may be formed of and contain any one or more of the insulating materials(s) discussed above (e.g., dielectric oxide materials, such as silicon dioxide). In this and other embodiments described herein, the insulating material 130 of the insulating structure 110 may be the same as or different from the other insulating materials(s) of the microelectronic device 100.

[0063] The conductive structure 112 of the stacked structure 108 may be formed of and contain one or more conductive materials 132, such as one or more of the following: at least one metal (e.g., one or more of tungsten, titanium, nickel, platinum, rhodium, ruthenium, iridium, aluminum, copper, molybdenum, silver, and gold), at least one alloy (e.g., an alloy of one or more of the aforementioned metals), or at least one metal-containing material containing one or more of the aforementioned metals (e.g., metal nitride, metal silicide, metal carbide, metal oxide, such as materials containing at least one of the following: titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), iridium oxide (IrO). x ), Ruthenium oxide (RuO) x The conductive structure 112 comprises at least one of the aforementioned conductive materials and at least one additional conductive material formed as a substrate. This includes at least one conductive doped semiconductor material (e.g., conductive doped silicon, conductive doped germanium, conductive doped silicon-germanium), polycrystalline silicon, and / or at least one other material exhibiting conductivity. In some embodiments, the conductive structure 112 comprises at least one of the aforementioned conductive materials and at least one additional conductive material formed as a substrate.

[0064] One or more of the conductive structures 112 adjacent to the source region 124 of the doped material 118 are configured as GIDL regions 134, such as source-gate select devices (e.g., SGS devices). In some embodiments, a single GIDL region (e.g., GIDL region 134) is present adjacent to the source region 124. In other embodiments, more than one GIDL region (e.g., GIDL region 134 and one or more additional GIDL regions 136) are present adjacent to the source region 124. One or more conductive structures 112 on top of the stacked structure 108 may also be configured as GIDL regions(s), such as drain-gate select devices (e.g., SGD devices).

[0065] At an elevation of the stacked structure 108 (e.g., above the source region 124), the strut 122 is laterally surrounded by the material of the layers 114 of the insulating structure 110 and the conductive structure 112. At an elevation of the stacked structure 108 at least above the GIDL region (e.g., GIDL region 134, and if included, an additional GIDL region 136), the channel material 106 may be horizontally inserted between the insulating material 138 forming the core of the strut 122 and the layers 114 of the stacked structure 108. At least a portion of the channel material 106 is vertically positioned below the insulating material 138.

[0066] The insulating material 138 may be formed of and comprise an electrically insulating material, such as (for example) phosphosilicate glass (PSG), borosilicate glass (BSG), fluorosilicone glass (FSG), borosilicate-phosphosilicate glass (BPSG), silicon dioxide, titanium dioxide, zirconium dioxide, hafnium dioxide, tantalum oxide, magnesium oxide, aluminum oxide, niobium oxide, molybdenum oxide, strontium oxide, barium oxide, yttrium oxide, nitride materials (e.g., silicon nitride (Si3N4)), oxynitrides (e.g., silicon oxynitride), dielectric carbonitride materials (e.g., silicon carbon nitride (SiCN)), dielectric carbonoxynitride materials (e.g., silicon carbonoxynitride (SiOCN)), or combinations thereof. In some embodiments, the insulating material 138 comprises silicon dioxide.

[0067] Channel material 106 may be formed from and include one or more of the following: semiconductor materials (at least one elemental semiconductor material, such as polycrystalline silicon; at least one group III-V compound semiconductor material, at least one group II-VI compound semiconductor material, at least one organic semiconductor material, GaAs, InPut, GaP, GaN, other semiconductor materials) and oxide semiconductor materials. Channel material 106 may be selectively or otherwise formulated to have high mobility (e.g., semiconductor materials comprising one or more of the following: doped polycrystalline silicon, germanium (Ge), silicon-germanium (SiGe), and / or gallium arsenide (GaAs)). In some embodiments, channel material 106 comprises doped semiconductor material. Channel material 106 may be configured as a so-called "doped hollow channel" (DHC) structure.

[0068] The pillar 122 also includes unit material horizontally inserted between the channel material 106 and the layer 114 of the stacked structure 108. The unit material may include: a tunneling dielectric material 140 (also referred to as "tunneling dielectric material") horizontally adjacent to the channel material 106; a memory material 142 horizontally adjacent to the tunneling dielectric material 140; and a dielectric barrier material 144 (also referred to as "charge barrier material") horizontally adjacent to the memory material 142. In some embodiments, the dielectric barrier material is also horizontally inserted (e.g., directly horizontally inserted) between the dielectric barrier material 144 and the layer 114 of the stacked structure 108. The unit material including the tunneling dielectric material 140, the memory material 142, the dielectric barrier material 144, and (if present) the dielectric barrier material 144, also extends into the substrate structure 120 and beneath the insulating material 138. However, the unit material does not extend continuously from the stacked structure 108 into the substrate structure 120.

[0069] The tunneling dielectric material 140 may be formed of and comprise a dielectric material, capable of performing charge tunneling through the dielectric material under suitable electrical bias conditions, for example, by hot carrier injection or by Fowler-Nordheim tunneling-induced charge transfer. The tunneling dielectric material 140 may be formed of and comprise one or more of the following: silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (e.g., aluminum oxide and hafnium oxide), dielectric metal oxynitrides, dielectric metal silicides, alloys thereof, and / or combinations thereof. In some embodiments, the tunneling dielectric material 140 comprises silicon dioxide or silicon oxynitride.

[0070] Memory material 142 may include charge-trapping materials or conductive materials. Memory material 142 may be formed from and include one or more of the following: silicon nitride, silicon oxynitride, polycrystalline silicon (e.g., doped polycrystalline silicon), conductive materials (e.g., tungsten, molybdenum, tantalum, titanium, platinum, ruthenium and their alloys, or metal silicides such as tungsten silicide, molybdenum silicide, tantalum silicide, titanium silicide, nickel silicide, cobalt silicide, or combinations thereof), semiconducting materials containing at least one elemental semiconductor element or at least one compound semiconductor material, polycrystalline silicon or amorphous semiconductor materials, conductive nanoparticles (e.g., ruthenium nanoparticles), and metal dots. In some embodiments, memory material 142 includes silicon nitride.

[0071] The dielectric barrier material 144 may be formed of and comprise one or more dielectric materials, such as (for example) one or more of the following: oxide (e.g., silicon dioxide), nitride (e.g., silicon nitride), oxynitride (e.g., silicon oxynitride), or another material. The dielectric barrier material(s) of the dielectric barrier material 144 may be formed as one or more distinct material regions (e.g., layers). In some embodiments, the dielectric barrier material 144 includes a single material region that may be formed of and comprise silicon oxynitride. In other embodiments, the dielectric barrier material 144 includes a structure configured as an oxide-nitride-oxide (ONO) structure having a series of material regions (e.g., layers) formed of oxide (e.g., silicon dioxide), nitride (e.g., silicon nitride), and re-oxide (e.g., silicon dioxide) and comprising oxide (e.g., silicon dioxide), nitride (e.g., silicon nitride), and re-oxide (e.g., silicon dioxide), respectively.

[0072] In some embodiments, the tunneling dielectric material 140, the memory material 142, and the dielectric barrier material 144 together may form a structure configured to trap charge, such as (for example) an oxide-nitride-oxide (ONO) structure. In some such embodiments, the tunneling dielectric material 140 comprises silicon dioxide, the memory material 142 comprises silicon nitride, and the dielectric barrier material 144 comprises silicon dioxide.

[0073] In embodiments incorporating a dielectric barrier material, it may be formed from and include one or more of the following: metal oxides (e.g., aluminum oxide, hafnium oxide, zirconium oxide, lanthanum oxide, yttrium oxide, tantalum oxide, gadolinium oxide, niobium oxide, titanium oxide), dielectric silicides (e.g., aluminum silicide, hafnium silicide, zirconium silicide, lanthanum silicide, yttrium silicide, tantalum silicide), and dielectric nitrides (e.g., aluminum nitride, hafnium nitride, lanthanum nitride, yttrium nitride, tantalum nitride).

[0074] The lateral opening 146 extends through the cell material (e.g., dielectric barrier material 144, memory material 142, tunneling dielectric material 140, and dielectric barrier material (if present)) and through the channel material 106. The doped material 118 of the source region 124 extends through the lateral opening 146; thus, the doped material 118 extends laterally through both the cell material and the channel material 106. The sidewalls of the doped material 118 may be in direct contact with the insulating material 138 at the core of the pillar 122. The insulating material 138 may form a monolithic structure, while the channel material 106 and the cell material are separated into upper and lower portions above and below the doped material 118 (e.g., above and below the lateral opening 146), respectively.

[0075] Channel material 106 is vertically recessed above and below lateral opening 146, and doped material 118 extends vertically upward and downward into the recess within the width (e.g., diameter) of pillar 122. These vertical extensions of doped material 118 form an upper vertical extension 148 (extending upward to an elevation within the elevation of stacked structure 108, for example, an elevation that overlaps or nearly overlaps with the elevation of at least one of GIDL regions (e.g., GIDL region 134 and / or additional GIDL region 136)) and a lower vertical extension 150 (extending downward to an elevation within the elevation of substrate structure 120). Both upper vertical extension 148 and lower vertical extension 150 are located near the substrate of pillar 122, adjacent to source region 124.

[0076] Channel material 106 is recessed above the lateral opening 146 at a vertical recess height 152, and doped material 118 is formed to fill the vertical recess height 152. Above the lateral opening 146, channel material 106 is mated to doped material 118 at a step within the elevation of stacked structure 108. Below the lateral opening 146, channel material 106 is mated to doped material 118 at a step within the elevation of substrate structure 120.

[0077] In embodiments where the dopant material 118 comprises doped polysilicon and the channel material 106 comprises doped polysilicon, the interface between the dopant material 118 and the channel material 106 may still be visually distinguishable, for example, via an electron microscope. In these or other embodiments, the dopant composition and / or dopant concentration in the dopant material 118 may differ from the dopant composition and / or dopant concentration in the channel material 106. For example, the dopant concentration in the dopant material 118 may be greater than the dopant concentration in the channel material 106.

[0078] The channel material 106 is vertically recessed, and the doped material 118 includes vertically extending portions (e.g., upper vertical extension 148, lower vertical extension 150) such that the doped material 118 extends vertically to a level (e.g., elevation) near or at least at a level (e.g., elevation) of at least one source-side GIDL region. The upper vertical extension 148 may extend to a level approximately 10 nm (e.g., approximately 5 nm below) below the lowermost surface of the lowest source-side GIDL region (e.g., GIDL region 134, which may be the lowest conductive structure 112 of the stacked structure 108) to approximately flush with the upper surface of the uppermost source-side GIDL region (e.g., additional GIDL region 136, or GIDL region 134 if only a single source-side GIDL region is included in the stacked structure 108). Therefore, in embodiments in which only a single GIDL region 134 (e.g., only a single source-side or lower GIDL region) is included in the stacked structure 108, the vertical recess height 152 can range from about 10 nm (e.g., within about 5 nm) smaller in vertical height than the thickness of the lowermost insulating structure 110 of the stacked structure 108 to about the combined thickness of the lowermost insulating structure 110 and the lowermost conductive structure 112 of the stacked structure 108. In embodiments that include multiple source-side GIDL regions, the vertical recess height 152 may not extend substantially above the upper surface of the uppermost source-side GIDL region.

[0079] In some embodiments, the upper vertical extension 148 of the doped material 118 laterally overlaps some or all of the elevations of the GIDL region 134 (e.g., at least the lowermost conductive structure 112 of the stacked structure 108). For example, according to Figure 1 In the embodiment described herein, the channel material 106 is vertically recessed into and the upper vertical extension 148 of the doped material 118 extends to approximately the height of the middle elevation of the GIDL region 134 (e.g., the lowermost conductive structure 112 of the stacked structure 108); thus, the doped material 118 laterally overlaps a portion of the GIDL region 134.

[0080] Below the lateral opening 146, the lower vertical extension 150 of the doped material 118 may have a height approximately equal to the vertical recess height 152 of the upper vertical extension 148. As discussed further below, the recess of the channel material 106 may be controlled such that at least some of the channel material 106 remains below (e.g., below) the insulating material 138 at the core of the pillar 122. The depth 154 of the unit material of the pillar 122 below the lateral opening 146 may also be controlled to ensure that at least some of the channel material 106 remains below the insulating material 138 at the core of the pillar 122. In some embodiments, the depth 154 (e.g., the pillar depth below the lateral opening 146) is in the range of approximately three times (3×) to approximately four times (4×) the vertical recess height 152. Below the lateral opening 146, the unit material and / or the channel material 106 may define a “U” shaped cross-section.

[0081] The upper vertical extension 148 of the doped material 118, adjacent to the GIDL regions(s), houses a dopant concentration in or from the doped material 118 that is relatively higher than that in or from the channel material 106, rather than being housed by the channel material 106 which remains adjacent to the GIDL regions(s). The upper vertical extension 148 of the doped material 118 also houses a relatively high concentration of dopant in the GIDL regions(s), such that in some embodiments, the dopant does not substantially diffuse outward from the doped material into the surrounding material. Therefore, the upper vertical extension 148 of the doped material 118 facilitates reliable functional (e.g., gating) communication between the adjacent GIDL regions(s)(s) (e.g., GIDL region 134, or, in embodiments having more than one source-side GIDL region, GIDL region 134 and additional GIDL region 136) and the channel material 106. During a block erase operation, (multiple) source-side GIDL regions (e.g., GIDL region 134 or GIDL region 134 plus additional GIDL region 136) induce the formation of holes (e.g., electron holes) in the channel material 106—and (multiple) drain-side GIDL regions do the same on top of the channel material 106—to reliably erase memory cells along pillars 122, even as such pillars 122 traverse numerous layers 114 of the stacked structure 108 (and thus numerous conductive structures 112 of the stacked structure 108).

[0082] Figure 1The plurality of (e.g., a certain number) layers 114 (and conductive structures 112 and insulating structures 110) described in the stacked structure 108 may constitute only the lower portion of a much taller stacked structure containing a number of additional layers 114 of conductive structures 112 and insulating structures 110. In some embodiments, the plurality of (e.g., a certain number) layers 114 of the stacked structure 108—and therefore the plurality of (e.g., a certain number) conductive structures 112 in the stacked structure 108—may range from thirty-two layers 114 (and thirty-two conductive structures 112) to three hundred or even more layers 114 (and three hundred or even more conductive structures 112). In some embodiments, the stacked structure 108 comprises one hundred and twenty-eight layers 114 (and one hundred and twenty-eight conductive structures 112). However, this disclosure is not limited thereto, and the stacked structure 108 may comprise a different number of layers 114 (and a different number of conductive structures 112).

[0083] The stacked structure 108 may be formed in one or more layers, each of which includes a vertically alternating sequence of insulating structures 110 and conductive structures 112 arranged in a hierarchy 114. For example, Figure 1 The microelectronic device structure 100 can be only Figure 2 The microelectronic device structure 200 described herein may be configured to form a stacked structure 108 in two parts (e.g., two layers): a lower layer 202 and an upper layer 204. In other embodiments, the stacked structure 108 may include more than two layers.

[0084] The strut 122 extends substantially vertically through each of the layers of the stacked structure 108 (e.g., lower layer 202 and upper layer 204), and also through the doped material 118 and into the substrate structure 120. In some embodiments, the materials of the strut 122 (e.g., the core insulating material 138, the channel material 106, and the material comprising the tunneling dielectric material 140, the memory material 142, and the dielectric barrier material 144) Figure 1 The unit material is formed as a continuous (e.g., seamless and / or indistinguishable portion) extending through the upper layer 204 and the lower layer 202 to the transverse opening 146. Figure 1 The material area of ​​the support column 122. In other embodiments, the material of the support column 122 is formed separately in the upper layer 204 and the lower layer 202 such that the interface of the separately formed material area is close to the interlayer portion 206. In some embodiments, the layer 114 ( Figure 1 The vertical alternating sequence of conductive structure 112 and insulating structure 110 of the interlayer portion 206 may be interrupted by one or more other structures, for example, the interlayer dielectric region of the insulating structure 110 which may be significantly thicker than any individual of the layer 114.

[0085] A slit structure 116 extending through the stacked structure 108 (e.g., through all layers, including the upper layer 204 and the lower layer 202) divides the pillars 122 into blocks 208. Each of the blocks 208 may contain an array of pillars 122, and the sequence of blocks 208 may form a pillar array portion 210 of the microelectronic device structure 200.

[0086] Laterally adjacent strut array portions 210, with or without intermediate features, may include at least some layers 114. Figure 1 The lateral ends of the stepped structure (multiple) of the stepped structure are defined by one or more stepped portions 212. Operable electrical contacts may be included in the stepped portions 212 to form various conductive structures 112 to the stacked structure 108. Figure 1 Electrical connections. The doped material 118 and the substrate structure 120 may extend from the strut array portion 210 to the stepped portion 212.

[0087] The microelectronic device structure 200 may further include additional features beneath or within the substrate structure 120. For example, bit lines and bit contacts may be formed in the substrate structure 120 (e.g., in the pillar array portion 210) to be operatively connected to pillar 122 and / or other electrical features of the microelectronic device structure 200. Additional conductive lines and contacts may also be included, for example, above the upper layer 204, for electrical connections to pillar 122 and / or other features of the microelectronic device structure 200. In some embodiments, a CMOS (Complementary Metal-Oxide-Semiconductor) circuit system is included in a CMOS region 214 beneath pillar 122 of the pillar array portion 210. In such embodiments, the microelectronic device structure 200 may be characterized to have a so-called “under-array CMOS” (“CuA”) region.

[0088] Figure 3 This is a top-down view illustrating one of the blocks 208 in an array containing pillars 122. A block 208 is bordered on its left and right sides by one of a pair of slit structures 116. Additional blocks 208 may be placed across the slit structures 116. (The last sentence appears to be incomplete and possibly refers to a different topic.) Figure 3 In the structure described in the text, Figure 2 The strut array section 210 can be along Figure 3 The cross-sectional view taken by the section line AA. Figure 2 Step section 212 (in Figure 3 The parts not described in the structural section described herein may be relative to... Figure 3 The horizontal arrangement is as described in the text.

[0089] In the discussion herein, the description of a pillar 122 is equally applicable to the microelectronic device structure of any embodiment of this disclosure (e.g., Figure 1 Microelectronic device structure 100 Figure 2Any or all of the pillars 122 of one or more blocks 208 (such as the microelectronic device structure 200). Therefore, some or all of the pillars 122 may have substantially the same material and structure.

[0090] Pillar 122 can implement a memory device (e.g., containing Figure 1 Microelectronic device structure 100 Figure 2 and Figure 3 The formation of a memory cell string of a microelectronic device structure 200 and / or any other microelectronic device structure memory device described or illustrated herein. Reference Figure 4A and Figure 4B The enlarged elevation cross-sectional view shows that it can be set at... Figure 1 Microelectronic device structure 100 Figure 2 The memory cell 402 in the microelectronic device structure 200 and / or any other microelectronic device structure including block 104 (e.g., Figure 4A The memory cell 402' and Figure 4B Memory cell 402”). Figure 4A and Figure 4B Each of the terms in the description can represent Figure 1 , Figure 2 And / or a simplified enlarged view of block 104 in other figures discussed below. References to "memory cell 402" or more "memory cells 402" herein also refer to... Figure 4A The memory cell 402' and / or described Figure 4B One or more of the memory cells 402 described herein.

[0091] Memory cell 402 is located near at least one of the layers 114, wherein at least one of the insulating structures 110 is perpendicularly adjacent to at least one of the conductive structures 112. In some embodiments (e.g.) Figure 4A In the embodiments described herein, the conductive materials 132 of the conductive structure 112 are substantially composed of or consist of a single conductive material or a homogeneous combination of conductive materials, wherein either of them is composed of... Figure 4A The conductive material 404 is shown in the description. The conductive material 404 may be directly adjacent to the insulating material 130 of the insulating structure 110, for example, without a distinguishing conductive liner.

[0092] In other embodiments, for example Figure 4B In the embodiments described herein, some or all of the conductive materials 132 of the conductive structures 112 may include conductive metal 406 at least partially surrounded by conductive liner material 408. The conductive liner material 408 may be directly adjacent to the upper and lower surfaces of the adjacent insulating structures 110, respectively. The conductive metal 406 may be directly perpendicular to portions of the conductive liner material 408.

[0093] have Figure 4B The memory cell 402 of the structure can be formed via a so-called "gate replacement" process, as discussed further below. The conductive liner material 408 may include, for example, a seed material capable of forming the conductive metal 406 during the gate replacement process. The conductive liner material 408 may be formed of and include, for example, a metal (e.g., titanium, tantalum), a metal nitride (e.g., tungsten nitride, titanium nitride, tantalum nitride), or another material. In some embodiments, the conductive liner material 408 comprises titanium nitride, and the conductive metal 406 comprises tungsten.

[0094] Continue to refer to Figure 4A and Figure 4B , pillar 122 (e.g., Figure 1 )(exist Figure 4A and Figure 4B In the description, a portion is referred to as pillar portion 410, which may be approximately half the lateral width (e.g., diameter) of one of the pillars 122, adjacent to a layer 114 having an insulating structure 110 and a conductive structure 112. As described in pillar portion 410, each of the pillars 122 is at least in the doped material 118 ( Figure 1 The upper vertical extension 148 includes a column 122 that can be laterally surrounded by each other. Figure 1 The channel material 106 and unit materials (e.g., tunneling dielectric material 140, memory material 142 and dielectric barrier material 144) of the insulating material 138 at the core (e.g., axial center) of the core.

[0095] In some embodiments of the memory cell (e.g., having Figure 4A The memory cell 402' and Figure 4B In the memory cell 402", channel material 106 can be horizontally inserted between insulating material 138 and tunneling dielectric material 140; tunneling dielectric material 140 can be horizontally inserted between channel material 106 and memory material 142; and memory material 142 can be horizontally inserted between tunneling dielectric material 140 and dielectric barrier material 144. In some such embodiments, dielectric barrier material 144 is horizontally inserted between memory material 142 and dielectric barrier material (not shown), and the dielectric barrier material can be directly adjacent to the conductive structure 112 and insulating structure 110 of layer 114. In other such embodiments, dielectric barrier material 144 is directly horizontally inserted between memory material 142 and layer 114.

[0096] In order to implement memory cell 402 (for example, Figure 4A Memory cell 402' Figure 4BThe memory cell 402”), one of the conductive structures 112 laterally surrounds (e.g., around) the pillar 122 (e.g., Figure 3 The material corresponding to ). Figure 4A In an embodiment of memory cell 402', conductive material 404 laterally surrounds pillar 122 (e.g., Figure 3 The material; while corresponding to Figure 4B In the embodiment of memory cell 402, both conductive metal 406 and conductive liner material 408 laterally surround the support column 122 (e.g., Figure 3 (materials).

[0097] Therefore, pillar 122 (for example, Figure 2 Each of the 124 (source poles) can provide from the source pole region 124 Figure 2 ) Vertically extending through or at least partially vertically extending through the stacked structure 108 ( Figure 2 The memory cell 402 is connected to the drain region above the stacked structure 108. At least one of the conductive structures 112 adjacent to the source region 124 and below the stacked structure 108 is configured as a GIDL region (e.g., a source-side select device), while at least one of the conductive structures 112 adjacent to the drain region and above the stacked structure is configured as another GIDL region (e.g., a drain-side select device).

[0098] Therefore, a microelectronic device including a stacked structure is disclosed. The stacked structure includes a vertically alternating sequence of insulating and conductive structures arranged in layers. At least one pillar extends through the stacked structure. The at least one pillar includes a channel material. A source region includes a doped material beneath the stacked structure. A vertical extension of the doped material protrudes upward at an elevation within the stacked structure to the interface with the channel material.

[0099] While forming a sufficient amount of dopant in the adjacent upper drain-side GIDL region is relatively easy, forming a sufficient amount of dopant in the adjacent (multiple) lower source-side GIDL regions is more challenging. Using the method described below, source region 124 ( Figure 1 , Figure 2 It is formed to include an upwardly extending vertical protrusion (e.g., upper vertical extension 148). Figure 1 This makes the doped material 118 ( Figure 1 It is placed near or laterally overlaps with at least one lower source-side GIDL region to facilitate a reliable gated connection between the GIDL region and the channel material 106 that is docked with the doped material 118.

[0100] refer to Figures 5 to 15 This describes the various stages used to form a microelectronic device, including... Figure 1Microelectronic device structure 100 and / or Figure 2 The microelectronic device structure 200.

[0101] refer to Figure 5 Sacrificial structures with different sacrificial material sequences (e.g., "clamped" structures) formed on substrate structure 120 will eventually become source region 124. Figure 1 The elevation of the first sacrificial material 502. A region (e.g., layer) of the first sacrificial material 502 may be formed (e.g., deposited) on the upper surface of the substrate structure 120, a region (e.g., layer) of the second sacrificial material 504 may be formed (e.g., deposited) on the first sacrificial material 502, and an additional region (e.g., layer) of the first sacrificial material 502 may be formed on the second sacrificial material 504.

[0102] Each of the regions in the first sacrificial material 502 can be formed to a thickness ranging from about 10 nm to about 40 nm. The regions in the second sacrificial material 504 can be formed to a thickness ranging from about 30 nm to about 60 nm. The thickness of the second sacrificial material 504 can then define the lateral opening 146. Figure 1 The height of the second sacrificial material 504 can be customized to facilitate the formation of a lateral opening 146 with a height sufficient to facilitate subsequent recess formation and recess filling operations. The thickness of the sacrificial clamping structure (e.g., the combined thickness of the lower region of the first sacrificial material 502, the region of the second sacrificial material 504, and the upper region of the first sacrificial material 502) can correspond to the source region 124 (e.g., the thickness of the source region formed on the substrate structure 120 and the stacked structure 108). Figure 1 The thickness of the doped material 118) between ) .

[0103] The first sacrificial material 502 and the second sacrificial material 504 may be selectively or otherwise formulated such that the second sacrificial material 504 can be selectively removed relative to the first sacrificial material 502 (e.g., selective etching). The second sacrificial material 504 may be further selectively or otherwise formulated to be selectively removed relative to the substrate structure 120 (e.g., relative to a semiconductor material such as polysilicon) and / or relative to insulating materials (e.g., oxides, nitrides, oxynitrides) in, for example, dielectric barrier material 144 (e.g., oxides, nitrides, oxynitrides). The first sacrificial material 502 may also be formulated or otherwise selected to be selectively removed (e.g., selective etching) relative to semiconductor materials (e.g., the semiconductor material 106 of the substrate structure 120) and / or relative to insulating materials (e.g., the insulating material 130, the dielectric barrier material 144, the tunneling dielectric material 140, and / or other insulating or dielectric structures) (e.g., selective etching). In some embodiments, the first sacrificial material 502 may be formed of and contain silicon carbon nitride (SiCN), and the second sacrificial material 504 may be formed of and contain silicon germanium (SiGe). The stoichiometric ratio of the elements in the first sacrificial material 502 in the upper region may be the same as or different from the stoichiometric ratio of the elements in the first sacrificial material 502 in the lower region.

[0104] A stacked structure 506 is formed on the upper region of the first sacrificial material 502. The stacked structure 506 is formed to include a vertically alternating sequence of insulating structures 110 and sacrificial structures 508 arranged in layers 510. The sacrificial structures 508 may be formed on the final conductive structure 112 (…). Figure 1 ) Replace or otherwise convert into a conductive structure 112 ( Figure 1 At the level of the stacked structure 506.

[0105] The sacrificial material 512 of the sacrificial structure 508 may be selectively or otherwise formulated to be selectively removed (e.g., selectively etched) relative to the insulating material 130 of the insulating structure 110. In some embodiments, the insulating material 130 comprises silicon dioxide, and the sacrificial material 512 comprises silicon nitride.

[0106] To form the stacked structure 506, the formation (e.g., deposition) of the insulating material 130 of the insulating structure 110 may alternate with the formation (e.g., deposition) of the sacrificial material 512 of the sacrificial structure 508. In some embodiments, the stacked structure 506 may be formed at this stage to include as many layers 510 as the sacrificial structure 508, because in the fabricated microelectronic device structure (e.g., Figure 2 All layers of the microelectronic device structure 200 (e.g., lower layer 202, upper layer 204) Figure 2 Conductive structures 112 will exist in all of them. Figure 1) level 114 ( Figure 1 In other embodiments, only the lower level 202's level 114 is formed at this stage, and in Figures 5 to 15 The subsequent stages described herein may be performed only in the lower layer 202 or only for the lower layer 202 before manufacturing the upper layer 204.

[0107] refer to Figure 6 The pillar openings can be formed (e.g., etched) through the stacked structure 506, through the clamping structure of the first sacrificial material 502 and the second sacrificial material 504, and into the substrate structure 120. The arrangement of the pillar openings can correspond to those formed in the pillar array portion 210. Figure 3 ) of the pillars 122 ( Figure 3 ) layout.

[0108] The strut opening can be formed to a depth, into the base structure 120, controlled or otherwise customized to define the area from the base of the strut opening to the upper surface of the lower region of the first sacrificial material 502 at the formation of the transverse opening 146. Figure 1 ), channel material 106 recess and doped material 118 ( Figure 1 The lower vertical extension 150 () Figure 1 After that, it remained on pillar 122 ( Figure 1 The depth 154 of the U-shaped unit material structure beneath the core of the insulating material 138. Therefore, the thickness of the first sacrificial material 502, at least the lower region of the first sacrificial material 502, can also be customized to facilitate the formation of a sufficiently deep U-shaped unit material structure to ensure that a sufficient amount of channel material 106 remains beneath the insulating material 138 after the channel material 106 is recessed, as further described below.

[0109] Within each of the pillar openings, unit materials (e.g., dielectric barrier materials, if present, dielectric barrier material 144, memory material 142, and tunneling dielectric material 140) may be sequentially formed (e.g., conformally deposited). Channel material 106 may be formed (e.g., conformally deposited) on the unit materials (e.g., on the tunneling dielectric material 140). Insulating material 138 may be formed (e.g., deposited) to fill the remaining space defined by the channel material 106.

[0110] refer to Figure 7 For structures to be formed in microelectronic devices (e.g., Figure 1 Microelectronic device structure 100 Figure 2 and / or Figure 3 Each slit structure 116 in the microelectronic device structure 200) Figure 1A slit 702 is formed (e.g., etched). The slit 702 is formed to extend through the stacked structure 506 and through the upper region of the first sacrificial material 502 to expose the second sacrificial material 504 (e.g., the upper surface of the second sacrificial material 504) at the base of the slit 702. A portion of the second sacrificial material 504 may or may not be removed to form the slit 702. However, at least a portion of the second sacrificial material 504 is retained such that the lower region of the first sacrificial material 502 is not exposed in the slit 702.

[0111] A sacrificial liner 704 is formed (e.g., conformal forming, deposition) to add a liner to the slot 702, thereby forming a lined slot 706. The sacrificial liner 704 may be formed of and contain a nitride material (e.g., silicon nitride). The substrate portion 708 may be removed (e.g., etched) without substantially removing the sidewall portions of the sacrificial liner 704, such as... Figure 8 The description states that the sacrificial liner 704 is maintained to cover the sidewalls of the layer 510 of the stacked structure 506.

[0112] In some embodiments, when or after etching through the substrate of the sacrificial liner 704, the etching continues (e.g., by dry etching) to or completely through the second sacrificial material 504. In some such embodiments, the lower region of the first sacrificial material 502 and optionally a portion of the substrate structure 120 may also be removed, such as Figure 8 The extension slit 802 exposes the second sacrificial material 504 and the lower region of the first sacrificial material 502 in the extension slit 802, but does not expose the layer 510 of the stacked structure 506.

[0113] In other embodiments, the extension slit 802 may be formed to a depth that terminates or partially extends into the second sacrificial material 504 such that the lower region of the first sacrificial material 502 is not exposed in the extension slit 802.

[0114] The second sacrificial material 504 can be removed (e.g., exposed) via the extended slit 802 without substantially removing the sacrificial liner 704, the first sacrificial material 502, and the outer material of the unit material (e.g., dielectric barrier material 144). Figure 9 The description states that the second sacrificial material 504 ( Figure 8In embodiments formed of and containing SiGe, the second sacrificial material 504 may be selectively removed, for example, by a "wet" etchant chemical comprising, substantially comprising, or consisting of a mixture of, for example, hydrogen fluoride (HF), hydrogen peroxide (H2O2), and acetic acid (CH3COOH), or, for another example, by a "dry" etchant chemical comprising, substantially comprising, or consisting of a mixture of, for example, gaseous hydrochloric acid (HCl(g)) in an epitaxial reactor. In other embodiments, other etch chemistry or selective material removal techniques may be used.

[0115] Selective removal of the second sacrificial material 504 ( Figure 8 A gap 902 is formed between the regions of the first sacrificial material 502 and exposes the outer sidewall of the outer unit material (e.g., dielectric barrier material 144). In embodiments in which the extending slit 802 is formed to extend completely through the first sacrificial material 502, the gap 902 also exposes a portion of the substrate structure 120.

[0116] refer to Figure 10 The unit materials (e.g., dielectric barrier material 144, memory material 142, and tunneling dielectric material 140) are etched via the void 902 (e.g., by wet etching, by dry etching) to form the lateral extension 1002. In some embodiments, removal of the unit materials (e.g., etching) may be the removal of the second sacrificial material 504. Figure 8 The etching process continues. The lateral extension 1002 exposes the outer sidewall of the channel material 106.

[0117] In some embodiments, the cell material may have lateral etching selectivity for the material of the substrate structure 120 and the channel material 106 (e.g., polysilicon). The lateral extension 1002 may be formed by performing a sequence of etching actions, including an oxide removal action (e.g., for etching the dielectric barrier material 144), a nitride removal action (e.g., for etching the memory material 142), and another oxide removal action (e.g., for etching the tunneling dielectric material 140).

[0118] The formation of the lateral extension 1002 allows one, more, or all of the unit materials to be vertically recessed relative to the other unit materials, relative to the first sacrificial material 502, relative to the lowermost insulating structure 110 of the stacked structure 506, and / or relative to the substrate structure 120. Therefore—although Figure 10The lower surface of the cell material (e.g., dielectric barrier material 144, memory material 142, tunneling dielectric material 140) is described as being substantially coplanar with the upper and lower surfaces of the lower and upper regions of the first sacrificial material 502, respectively—but this disclosure is not limited thereto. The thickness of the upper region of the first sacrificial material 502 can be customized to ensure that etching of the cell material does not expose the sacrificial material 512 of the lowermost sacrificial structure 508 to the etchant. The thickness of the upper region of the first sacrificial material 502 can also be customized to ensure that the insulating material 130 of the insulating structure 110 is not exposed to the etchant.

[0119] In some embodiments, in the region adjacent to the lateral extension 1002, one, more, or all of the unit material may be thinned relative to its corresponding lateral thickness level before the lateral extension 1002 is formed. Therefore - although Figure 10 The horizontal thickness of the unit material is described as roughly similar to Figure 9 The corresponding horizontal thickness is described in the description - but this disclosure is not limited thereto.

[0120] The etching process that forms the lateral extension 1002 can also thin the sacrificial liner 704. Figure 9 The material of the sacrificial liner 704. However, the thickness of the sacrificial liner 704 may have been customized to ensure that at least some of the sacrificial liner 704, for example as a thinner sacrificial liner 1004, remains above the gap 902 along the sidewall of the wider slot 1006, so that the layers 510 of the stacked structure 506 are not exposed to the etchant(s) used to form the lateral extension 1002.

[0121] After the lateral extension 1002 is formed, the first sacrificial material 502 may be selectively removed (e.g., exposed) to form the source region void 1102. As discussed above, the first sacrificial material 502 may have been selected or formulated so that the first sacrificial material 502 can be selectively removed without substantially removing, for example, oxide insulating material (e.g., insulating material 130 of insulating structure 110) exposed in the source region void 1102.

[0122] In embodiments where the first sacrificial material 502 is formed of SiCN and contains SiCN, and where one or more of the unit materials (e.g., memory material 142) contain nitride material, the first sacrificial material 502 can be removed, while the nitride material of the unit material is removed laterally. In other embodiments, the first sacrificial material 502 can be removed after the laterally extended portion 1002 is formed.

[0123] As described above, the first sacrificial material 502 ( Figure 8 ) and the second sacrificial material 504 ( Figure 8The second sacrificial material 504 can be selectively removed relative to the first sacrificial material 502, and the first sacrificial material 502 can be selectively removed relative to oxide materials (e.g., the insulating structure 110 and the unit material). Therefore, both the second sacrificial material 504 and the first sacrificial material 502 can be selectively removed, at least in some embodiments, without the need for a conversion process (e.g., an oxidation process) to adjust the etch selectivity of the material. Avoiding such a conversion process in these embodiments simplifies the manufacturing process.

[0124] After removing the first sacrificial material 502 ( Figure 10 At or after this time, remove the portion of the channel material 106 exposed in the lateral extension 1002 - such as Figure 12 The description states that a portion is both horizontal and vertical to form an upper vertical recess 1202 with a vertical recess height of 152 and a lower vertical recess 1204 with a substantially the same vertical recess height of 152.

[0125] In some embodiments, the channel material 106 may be recessed by a wet etching process and / or a dry etching process, for example, targeting the etching of semiconductor material (e.g., polysilicon), such that portions of the channel material 106 above and below the lateral extension 1002 are removed, without substantially removing the insulating material 138 at the core of the pillar 122, the cell material of the pillar 122 (e.g., dielectric barrier material 144, memory material 142, and tunneling dielectric material 140), the thinner sacrificial liner 1004 in the wider slit 1006, and the insulating material 130 of the insulating structure 110 exposed in the source region void 1102. Etching the channel material 106 may also remove some of the substrate structure 120, although at least a U-shaped portion of the cell material may remain below the lateral extension 1002, at least partially within the substrate structure 120.

[0126] As discussed above, the material of the pillar 122, in which the pillar opening is formed, may have been etched to a depth in the substrate structure 120 to provide a depth 154 for the unit material (e.g., dielectric barrier material 144, memory material 142, and tunneling dielectric material 140) in the U-shaped structure below the lateral opening 146 (formed by the lateral extension 1002) after the channel material 106 is recessed. The depth 154 may be such that not all of the channel material 106 is removed from below the insulating material 138 at the core of the pillar 122. Therefore, in some embodiments, the depth 154 may be approximately three times (3×) to approximately four times (4×) the vertical recess height 152 such that a portion of the channel material 106 remains below and supports the insulating material 138 at the core of the pillar 122. The remaining material of the U-shaped structure can thus provide structural support to maintain the physical integrity of the support column 122 after the formation of the lateral extension 1002 (e.g., lateral opening 146), the upper vertical recess 1202 and the lower vertical recess 1204.

[0127] The channel material 106 is recessed by a height (e.g., a vertical recess height 152), said height being tailored such that the upper vertical recess 1202 at least approaches (or does not overlap with) the extension of at least one of the GIDL regions in the lower sacrificial structure 508 that will eventually become the source-side GIDL region. For example, the channel material 106 may be recessed such that the upper vertical recess 1202 extends at least into the GIDL region 1206 (which will eventually become the source-side GIDL region). Figure 1 The GIDL region 134) within the layer (e.g., at least within about 5 nm) to approximately flush with the upper surface of the additional GIDL region 1208 (within the layer containing Figure 1 In the embodiment of the additional GIDL region 136). That is, the upper elevation of the upper vertical recess 1202 may be located within approximately 10 nm (e.g., within approximately 5 nm below) below the lower surface of the lowermost sacrificial structure 508 of the stacked structure 506 and approximately equal to the GIDL region intended to become the highest source side (e.g., Figure 1 The elevation of the upper surface of the sacrificial structure 508 in the additional GIDL area 136).

[0128] refer to Figure 13 Source region 124 ( Figure 1 The doped material 118 is formed (e.g., deposited) to fill or substantially fill the upper vertical recess 1202, the lower vertical recess 1204, and the source region void 1102. The doped material 118 may also be formed on a thinner sacrificial substrate 1004 to form a substrate-lined slit 1302. In other embodiments, the doped material 118 may be formed to substantially fill the volume within the thinner sacrificial substrate 1004.

[0129] In the upper vertical recess 1202, a doped material 118 is formed closely adjacent to the elevation of the stacked structure 506 that will become the source-side GIDL regions(e.g., depending on the vertical recess height 152, closely adjacent to at least one level of GIDL region 1206, and in some embodiments, also closely adjacent to the level of an additional GIDL region 1208). The doped material 118 and its relatively high dopant concentration (e.g., relative to the relatively low dopant concentration in the channel material 106) are positioned. This close proximity of the dopant to the elevation of the (multiple) GIDL regions(e.g.,) can be achieved without requiring, for example, thermally driven outward diffusion of the dopant from the doped material 118. In other embodiments, thermally driven outward diffusion of the dopant may also be performed. In some such embodiments, if thermally driven outward diffusion alone is relied upon to ensure sufficient dopant concentration in the (multiple) levels of the GIDL regions(e.g., the levels of GIDL region 1206, and in some embodiments, the levels of the additional GIDL region 1208), then a relatively low temperature and / or a relatively short temperature exposure duration may also be utilized.

[0130] Forming the dopant material 118 in the space created by vertically recessing the channel material 106 also facilitates the placement of the dopant material 118 at a target elevation (e.g., the elevation of the interface between the dopant material 118 and the channel material 106 in the stacked structure 506) close to the GIDL region(s) without necessitating material at the substrate of a so-called “through” (e.g., vertical etching) high aspect ratio opening. That is, the disclosed method can, at least in some embodiments, avoid the stage of vertically etching the material (e.g., channel material 106, unit material) at the substrate of the pillar opening before forming the dopant material 118 in the area occupied by the horizontal axis of the pillar 122. Avoiding vertical etching at a high aspect ratio substrate simplifies the manufacturing process and avoids potential process failures, specifically because the number of layers 510 of the stacked structure 506 can be scaled up to a larger number. For example, if vertical etching of the cell material at the base of the pillar opening is not utilized during the manufacturing process, the width of the pillar opening (e.g., at the base of pillar 122) may not need to be formed as extensively as it would originally be required to achieve a vertical through-hole. Where the fabrication criticality of the pillar base width is lower, pillar 122 itself can be formed narrower than it would originally be, allowing the pillar 122 array to be scaled to include a higher density of pillars 122 per unit microelectronic device structure cross-sectional area.

[0131] After the doped material 118 is formed in the source region voids and extends laterally and vertically into the substrate of the pillar 122, the doped material 118 and the thinner sacrificial liner 1004 can be selectively removed from the sidewalls of the layers 510 along the stacked structure 506, such as Figure 14The doped material 118 and the thinner sacrificial substrate 1004 can be removed, while material of layer 510 (e.g., sacrificial material 512 of sacrificial structure 508 and insulating material 130 of insulating structure 110) is generally not removed. For example, the doped material 118 and the thinner sacrificial substrate 1004 can be isotropically etched, for example, by an etchant comprising tetramethylammonium hydroxide (TMAH). In the resulting slit 1402, the ends of sacrificial structure 508 and insulating structure 110 of stacked structure 506 are exposed. (e.g., from source region void 1102) A portion of the doped material 118 in slit 1402 exposed at the elevation of source region 124 can also be removed, thereby causing the doped material 118 to be laterally recessed relative to the sidewalls of stacked structure 506 defining slit 1402.

[0132] The "replacement gate" process can be performed via slit 1402 to expose sacrificial material 512—and thus sacrificial structure 508—and as Figure 15 The description states that conductive materials 132 are formed in such a way (e.g., Figure 4A Conductive material 404 and / or Figure 4B The conductive liner material 408 and the conductive metal 406 are used to replace the sacrificial structure 508. Figure 14 The replacement gate process forms the conductive structure 112 of the layer 114 of the stacked structure 108.

[0133] In slit 1402, insulating liner 126 ( Figure 1 ) can be formed (e.g., deposited) on the sidewalls of layer 114 of the stacked structure 108. Non-conductive filler material 128 ( Figure 1 The remaining volume between the insulating liner 126 can be formed (e.g., deposited) to fill or substantially fill the slit structure 116. Figure 1 Complete (e.g., for) Figure 2 and Figure 3 Each of the slit structures 116 in the microelectronic device structure 200).

[0134] In some embodiments, the microelectronic device structure 200 may be preformed before the upper layer 204 of the microelectronic device structure 200 is formed. Figure 2 The lower level of 202 execution Figures 5 to 15 And then Figure 1 The stage. For example, in completing Figure 1 The microelectronic device structure 100 is formed to form the lower layer 202. Figure 2 Following this, as discussed above, the additional layer 510 of the sacrificial structure 508, which is perpendicular to the insulating structure 110, is... Figure 5 Formed on the lower level 202; a portion of the support 122 of the upper level 204 is formed through the additional level 510; the upper slit (e.g., as if passing through) Figure 14 The slit 1402 of the stacked structure 506 is formed through the additional layer 510; a gate replacement process is performed to replace the sacrificial structure 508 with the conductive structure 112 of the upper layer 204; and the material of the slit structure 116 is formed in the slit of the upper layer 204 to form Figure 2 and Figure 3 The microelectronic device structure 200 includes the lower layer 202. Figure 1 The structure of the microelectronic device 100.

[0135] In some embodiments, the lower layer 202 ( Figure 2 The layers 510 and pillars 122 of the upper layer 204 are formed in a separate stage prior to the gate replacement process. For example, in Figure 14 Before that stage, Figures 5 to 13 The phase was carried out to manufacture microelectronic device structures 200 ( Figure 2 The lower layer 202 of the microelectronic device structure 200. Next, the upper layer 204 of the microelectronic device structure 200 is a stacked structure 506 including the sacrificial structure 508. Figure 13 The formation of the next layer is then carried out. Next, in the case of forming a stacked structure 506 comprising layers 510 for both the lower layer 202 and the upper layer 204, the slit 1402 ( Figure 14 The gate replacement process can be performed by forming a structure that passes through both the upper layer 204 and the lower layer 202. Figure 5 The sacrificial structure 508 is replaced by a conductive structure 112 from either the upper layer 204 or the lower layer 202 of the stacked structure 108, and the slit structure 116 is fabricated (e.g., Figure 1 ) to form in the lower level 202 Figure 1 Microelectronic device structure 100 Microelectronic device structure 200 ( Figure 2 , Figure 3 ).

[0136] In other embodiments, as discussed above, the lower layer 202 ( Figure 2 ) and the upper level 204 ( Figure 2 Both are executed together. Figures 5 to 15 And then Figure 1 The stage that makes Figures 5 to 14 The stacked structure 506 and then Figure 15 and Figure 1 The stacking structure 108 represents the stacking structure 506 of level 510 (in Figures 5 to 14 The stacked structure 108 of level 114 (in the middle) and level 114 Figure 15 and Figure 1 (middle), thus forming both the lower level 202 and the upper level 204.

[0137] Therefore, a method for forming a microelectronic device is disclosed. The method includes forming a sacrificial material stack on a substrate structure. A layered stack structure is formed on the sacrificial material stack. The layered stack structure includes a vertically alternating sequence of insulating structures and other structures arranged in a hierarchical manner. A pillar opening is formed through the layered stack structure, through the sacrificial material stack, and into the substrate structure. Cell material, channel material, and insulating core material are formed in the pillar opening. A slit is formed through the layered stack structure and at least partially through the sacrificial material stack. At least one of the sacrificial material and the sacrificial material stack is selectively removed to expose at least one cell material formed in the pillar opening. A lateral opening is formed through the cell material to expose a portion of the channel material in the lateral opening. The channel material is recessed to form a vertical recess protruding into the stack structure at an elevation. A doped material is formed in the vertical recess.

[0138] Figures 5 to 15 and Figure 1 The stage description describes a method in which the gate replacement process is performed after the formation of the pillar 122, which has a vertical recess of channel material 106 and a vertical extension of doped material 118 of source region 124, is completed. In other embodiments (e.g., by...) Figures 16 to 27 In the embodiments described in the various stages, the gate replacement process is performed before the channel material 106 is vertically recessed and the vertical extension of the doped material 118 is formed.

[0139] refer to Figure 16 The stages described can be found at Figure 5 (forming a sacrificial clamping structure of the first sacrificial material 502 and the second sacrificial material 504 and forming a stacked structure 506 with sacrificial structure 508) and Figure 6 Following the stages described in (forming insulating material 138, channel material 106, and unit material in the support opening). The slit 702 is described above in the relevant text. Figure 7 The structures are formed in a generally similar manner (e.g., for each slit structure 116 to be manufactured). Figure 3 The slit 702 passes through the stacked structure 506. However, in some embodiments, the slit 702 is formed to a depth that does not extend completely through the upper region of the first sacrificial material 502. Therefore, the slit 702 exposes the sidewalls of the sacrificial structure 508 and the insulating structure 110 of the layer 510 of the stacked structure 108 and exposes a portion of the first sacrificial material 502.

[0140] The gate replacement process is performed via slit 702 to replace the conductive structure 112 of the layer 114 of the stacked structure 108 formed by the sacrificial structure 508, such as Figure 17 The process is explained in the text. This gate replacement process can be broadly similar to the above description. Figure 15The alternative gate process is described.

[0141] refer to Figure 18 , for example, in a manner roughly similar to the above regarding Figure 7 The described method involves forming a sacrificial liner 704 in slit 702, thereby forming a lined slit 706. However, in this embodiment, the sacrificial liner 704 is disposed on the sidewalls of the conductive structure 112 and the insulating structure 110 of the layer 114 of the stacked structure 108. The sacrificial liner 704 may also be formed on a portion of the first sacrificial material 502. Then, similar to the above description... Figure 8 The method described is to remove (e.g., etch) the substrate portion 708.

[0142] refer to Figure 19 In the base portion 708 where the sacrificial liner 704 is removed ( Figure 18 Afterwards, or when removing the base portion 708 of the sacrificial liner 704, it is also removed (e.g., in a manner similar to etching as described above). Figure 8 (Description of the upper region of the first sacrificial material 502) A portion of the upper region of the first sacrificial material 502. In some embodiments, some of the second sacrificial material 504 is non-removable or only removable, such that the extended slit 802 formed by removing the base portion 708 of the sacrificial liner 704 and the exposed portion of the upper region of the first sacrificial material 502 exposes the upper surface of the second sacrificial material 504 without exposing any portion of the lower region of the first sacrificial material 502. (As discussed above, regarding the formation of...) Figure 8 The extended slit 802 (rather than being etched through the second sacrificial material 504 and into or through the first sacrificial material 502) takes this same approach. Alternatively, it is generally similar to... Figure 8 As described herein, the extended slit 802 may be formed to extend completely through the second sacrificial material 504 and into or through the lower region of the first sacrificial material 502, and in some embodiments, partially extend into the substrate structure 120.

[0143] like Figure 20 The description above explains how to remove the second sacrificial material 504 in a manner largely similar to the above description. Figure 9 The described manner forms the void 902. In embodiments in which the extending slit 802 is formed by not extending through the lower region of the first sacrificial material 502, the substrate structure 120 may not be exposed in the void 902.

[0144] refer to Figure 21 Then, (for example, in a manner roughly similar to the above regarding...) Figure 10The described method (of forming a lateral extension 1002) exposes the channel material 106 in the vicinity of the U-shaped structure between the stacked structure 108 and the unit material below the lateral extension 1002. Laterally etching the unit material to form the lateral extension 1002 may also thin the sacrificial liner 704. Figure 20 A thinner sacrificial liner 1004 is formed along the sidewalls defining the wider slit 1006. In embodiments where the lower region of the first sacrificial material 502 has not yet been etched through, at this stage, portions of the substrate structure 120 are still not exposed.

[0145] After laterally etching the unit material to form the lateral extension 1002, in a manner generally similar to that described above... Figure 11 The described method involves selectively removing (e.g., exposing) the first sacrificial material 502 (as described). Figure 22 (See explanation below) to form source region void 1102.

[0146] refer to Figure 23 This causes the channel material 106 to be vertically recessed (thus forming an upper vertical recess 1202 and a lower vertical recess 1204), and is generally similar to the above description regarding Figure 12 and Figure 13 The method described is to form the doped material 118 in the recess. However, since the gate replacement process has already been performed, the formation of the doped material 118 in the upper vertical recess 1202 is close to the conductive structure 112 that houses the dopant of the doped material 118 in the GIDL region 134 (or the GIDL region(s) containing optional additional GIDL regions 136), without the need for the dopant to diffuse outward from the doped material 118 to the target elevation in some regions.

[0147] refer to Figure 24 The wider slit 2402 can be formed, for example, by isotropically etching the doped material 118 and using a thinner sacrificial liner 1004 as a protective sidewall for the layers 114 of the stacked structure 108 (e.g., for each slit structure 116 to be formed). Figure 3 The wider slit 2402 extends vertically through the doped material 118, thereby exposing a portion of the substrate structure 120 at the substrate of each of the wider slits 2402.

[0148] The remaining portion of the thinner sacrificial liner 1004 can be as follows Figure 25The process involves removing (e.g., selective etching) material to form a slit 1402 extending through the stacked structure 108, through the doped material 118, and to or partially reaching the substrate structure 120. For example, in embodiments where the thinner sacrificial liner 1004 (e.g., formed from sacrificial liner 704) is formed of and contains nitride material, a selective material removal process for the nitride material can be used to remove the thinner sacrificial liner 1004 without removing the insulating material 130 of the insulating structure 110 and without removing the conductive material(s) 132 of the conductive structure(s) 112 in the stacked structure 108.

[0149] refer to Figure 26 The insulating liner 126 and the non-conductive filler material 128 can be formed to fill or substantially fill the slit 1402. Figure 25 And similar to the above regarding making Figure 1 The microelectronic device structure 100 in Figure 15 The slit structure 116 is formed in the manner described after the phase is completed. Thus, a microelectronic device structure 2600 is formed, which includes a vertical extension of the doped material 118 of the source region 124 such that the doped material 118 extends into or near at least one of the source-side GIDL regions (e.g., one or both of GIDL region 134 and / or additional GIDL region 136), thereby facilitating a reliable gated connection between the channel material 106 and the source-side GIDL region.

[0150] Figure 26 The microelectronic device structure 2600 described in block 102 can be used as Figure 27 The larger microelectronic device structure 2700 described herein includes, for example, Figure 1 The microelectronic device structure 100 may be included in Figure 2 The microelectronic device structure 200 is as described above. Figure 3 The top-view diagram described in the text can be used to illustrate the same point. Figure 27 A top plan view of the pillar array portion 210 of the microelectronic device structure 2700, wherein... Figure 27 The view of the pillar array section 210 can be seen along Figure 3 The section line AA is cut off.

[0151] In addition, as mentioned above... Figure 2 The structure of the microelectronic device is described in 200. Figure 27 The multiple layers of the microelectronic device structure 2700 (e.g., lower layer 202 and upper layer 204) can be determined according to Figures 16 to 27 The microelectronic device structure 2600 is formed together with the upper layer 204 of the microelectronic device structure 2700 in a separate stage. Figures 16 to 26 The stage is aimed at Figure 27 The lower layer 202 of the microelectronic device structure 2700 is formed.

[0152] By the aforementioned methods (e.g., through) Figures 5 to 15 and Figure 1 The method described in the text; through Figure 5 , Figure 6 and Figures 16 to 27 The method described herein involves placing the doped material 118 of the source region 124 close to and nearly laterally overlapping with at least one source-side GIDL region(s). The doped material 118 and the source-side GIDL regions(s) (e.g., GIDL region 134) Figure 1 , Figure 26 The proximity of the multiple source-side GIDL regions allows for a relatively high doping gradient to enhance hole (e.g., electron-hole) formation from the lower source side of the pillar 122 (and channel material 106) during block erase operations. Therefore, the gated connection between the multiple source-side GIDL regions and the channel structure (of channel material 106) in the pillar 122 is more reliable and allows the microelectronic device to be formed with a greater number of layers 114 (and thus a greater number of conductive structures 112 and memory cells 402) than conventional devices.

[0153] Furthermore, the proximity of the dopant to the source-side GIDL regions(multiple) can be achieved without performing a process for driving the dopant diffusion from the source regions (e.g., without performing a rapid thermal processing (RTP) operation) or by performing a thermal diffusion process at a lower temperature and / or for a shorter duration. Therefore, the thermally driven diffusion process can be avoided in some embodiments, or in other embodiments, it can be performed at a lower temperature (e.g., about 700°C or about 600°C or less, rather than about 900°C or greater) and / or for a shorter duration. This eliminates the use of temperature and / or timing conditions that would otherwise impair material or device characteristics (e.g., material degradation (e.g., bending of pillar 122) and slow down operation (e.g., in the CMOS region 214 below the array of pillar 122)).

[0154] Moreover, as described above, the method avoids using vertical "perforations" at the substrate of pillar 122 (e.g., to remove a substrate portion of channel material 106 and / or unit material, where dopants can then be implanted or otherwise formed). Therefore, the critical dimension ("CD") of pillar 122 itself can be relatively narrow, and the pillar array portion 210 ( Figure 3 The fabrication process can be made to form a relatively larger pillar density than the case where vertical etching at the substrate with a high aspect ratio opening is required, so as to ensure that a sufficient concentration of dopant is placed in the adjacent (multiple) source-side GIDL regions.

[0155] refer to Figure 28 This is a schematic cross-sectional perspective illustration of a portion of a microelectronic device 2800 (e.g., a memory device, such as a 3D NAND flash memory device) including a microelectronic device structure 2802. The microelectronic device structure 2802 may be substantially similar to, for example... Figure 2 Microelectronic device structure 200 (e.g., containing Figure 1 Microelectronic device structure 100) and / or Figure 27 Microelectronic device structure 2700 (e.g., containing Figure 26 Microelectronic device structure 2600).

[0156] like Figure 28 The description indicates that the microelectronic device structure 2802 may include a stepped structure 2804 (which may correspond to, for example...) Figure 2 Microelectronic device structure 200 and / or Figure 27 The stepped portion 212 of the microelectronic device structure 2700. The stepped structure 2804 may define a contact area to connect the access line 2806 to a layer of the microelectronic device structure 2802 (e.g., the lower layer 202). Figure 2 , Figure 27 ) and / or the upper layer 204 ( Figure 2 , Figure 27 Stacking structures in any one or both of the following (e.g., stacking structure 108, e.g., Figure 1 , Figure 26 The conductive layer 2808 (e.g., conductive layer, conductive plate, for example, conductive structure 112) Figure 1 , Figure 26 )).

[0157] Microelectronic device structure 2802 may include memory cells 2812 (e.g., Figure 4A memory cell 402' and / or Figure 4B The struts of string 2810 (e.g., one or more of the memory cells 402) Figure 2 and / or Figure 27 The pillars 122). The pillars forming the strings 2810 of the memory cells 2812 may be relative to the conductive layer 2808, relative to the data line 2814, and relative to the source layer 2816 (e.g., Figure 2 and / or Figure 27The source region 124), relative to access line 2806, relative to first select gate 2818 (e.g., upper select gate, such as drain select gate (SGD), which may include one or more regions configured as drain-side GIDL regions), relative to select line 2820, and / or relative to one or more second select gates 2822 (e.g., lower select gates, such as source select gates (SGS), which may include source-side GIDL regions configured as...). Figure 1 and Figure 26 The GIDL region 134 and additional GIDL regions 136 (if present) extend at least slightly perpendicularly (e.g., in the Z direction) and orthogonally. As described above, source hierarchy 2816 (e.g., source region 124) Figure 2 , Figure 27 The portion extends vertically to the vicinity of the (multiple) source-side GIDL regions (e.g., by the second select gate 2822) of the second select gate 2822. Figure 1 and Figure 26 The elevation occupied by at least one of the GIDL area 134 and the additional GIDL area 136.

[0158] The first selection gate 2818, the conductive layer 2808, and the second selection gate 2822 may be horizontally divided (e.g., in the X-axis direction) to pass through a slit 2826 (e.g., slit structure 116). Figures 2 to 1 , Figure 3 , Figure 26 , Figure 27 Multiple blocks 2824 spaced apart from each other (e.g., in the X-axis direction) (e.g., block 208) Figure 2 , Figure 3 , Figure 27 )).

[0159] Vertical conductive contacts 2828 can electrically couple components to each other as described. For example, select line 2820 can be electrically coupled to first select gate 2818, and access line 2806 can be electrically coupled to conductive layer 2808.

[0160] The microelectronic device 2800 may also include a memory array (e.g., a strut array portion 210) located within the memory array. Figure 2 , Figure 27 The control unit 2830 below. The control unit 2830 may include control logic configured to control the operation of various features of the microelectronic device 2800 (e.g., memory string 2810, memory cell 2812). By non-limiting example, the control unit 2830 may include one or more of the following (e.g., each): a charge pump (e.g., V... CCP Charge pump, V NEGWLCharge pumps, DVC2 charge pumps), delay-locked loop (DLL) circuit systems (e.g., ring oscillators), V dd Regulators, drivers (e.g., serial drivers), decoders (e.g., local layer decoders, column decoders, row decoders), sense amplifiers (e.g., equalization (EQ) amplifiers, isolation (ISO) amplifiers, NMOS sense amplifiers (NSA), PMOS sense amplifiers (PSA)), repair circuitry systems (e.g., column repair circuitry systems, row repair circuitry systems), I / O devices (e.g., local I / O devices), memory test devices, MUX, error checking and correction (ECC) devices, self-refresh / wear equalization devices, and / or other chip / layer control circuitry systems. For example, control unit 2830 may be electrically coupled to data line 2814, source layer 2816, access line 2806, first select gate 2818, and / or second select gate 2822. In some embodiments, control unit 2830 may be configured to and / or include a CMOS (complementary metal-oxide-semiconductor) circuitry system. In such embodiments, control unit 2830 may be characterized to have an "array-under CMOS" ("CuA") configuration. Therefore, control unit 2830 may be included in... Figure 2 and / or Figure 27 In the CMOS region 214.

[0161] The first select gate 2818 may extend horizontally in a first direction (e.g., the Y-axis direction) and may be coupled at a first end (e.g., the upper end) of the string 2810 to a corresponding first group of strings 2810 of the memory cell 2812. The second select gate 2822 may be formed in a generally planar configuration and may be coupled to the string 2810 at a second opposite end (e.g., the lower end) of the string 2810 of the memory cell 2812. As discussed above, a portion of the source hierarchy 2816 extends vertically upwards to at least one lower GIDL region (e.g., adjacent to or laterally overlapping the second select gate 2822) Figure 1 and Figure 26 The elevation of GIDL area 134 and additional GIDL area 136.

[0162] Data lines 2814 (e.g., bit lines) may extend horizontally in a second direction (e.g., in the X-axis direction) at an angle (e.g., vertical) to a first direction extending from the first select gate 2818. Data lines 2814 may be coupled at a first end (e.g., the upper end) of a string 2810 to a corresponding second group of strings 2810. Strings 2810 coupled to the first group of corresponding first select gates 2818 may share a specific string 2810 with strings 2810 coupled to the second group of corresponding data lines 2814. Therefore, a specific string 2810 at the intersection of a specific first select gate 2818 and a specific data line 2814 can be selected. Thus, the first select gate 2818 can be used to select memory cells 2812 of the string 2810 of memory cells 2812.

[0163] Conductive layers 2808 (e.g., word lines, word line boards) may extend in a corresponding horizontal plane. Conductive layers 2808 may be vertically stacked such that each conductive layer 2808 is coupled to all strings 2810 of memory cells 2812 in a corresponding block 2824, and the strings 2810 of memory cells 2812 extend vertically through the stack(s) of conductive layers 2808 in the corresponding block 2824 (e.g., layers, etc.). Figure 2 , Figure 27 (Lower layer 202 and upper layer 204). Conductive layer 2808 may be coupled to a memory cell 2812 coupled to the conductive layer 2808 or may form a control gate of the memory cell 2812. Each conductive layer 2808 may be coupled to a memory cell 2812 of a specific string 2810 of memory cells 2812.

[0164] The first select gate 2818 and the second select gate 2822 are operable to select a specific string 2810 of memory cells 2812 between a specific data line 2814 and the source level 2816. Therefore, a specific memory cell 2812 can be selected and electrically coupled to one of the data lines 2814 by (e.g., by selecting) the appropriate first select gate 2818, second select gate 2822, and conductive level 2808 coupled to the specific memory cell 2812.

[0165] The stepped structure 2804 can be configured to provide an electrical connection between the access line 2806 and the conductive level 2808 via a vertical conductive contact 2828. In other words, a particular step of the conductive level 2808 can be selected via one of the access lines 2806 that are electrically connected to a corresponding conductive contact 2828 that is electrically connected to the particular conductive level 2808.

[0166] Data line 2814 can be electrically coupled to string 2810 of memory cell 2812 via conductive structure 2832.

[0167] Includes microelectronic device structures (e.g., Figure 1 Microelectronic device structure 100 Figure 2 Microelectronic device structure 200 Figure 26 Microelectronic device structure 2600 and / or Figure 27 Microelectronic devices (e.g., microelectronic device 2800) with microelectronic device structure 2700 can be used in embodiments of the electronic systems disclosed herein. For example, Figure 29 This is a block diagram of an electronic system 2900 according to an embodiment of the present disclosure. The electronic system 2900 may include, for example, a computer or computer hardware component, a server or other networking hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a Wi-Fi or cellular-enabled tablet computer (e.g., or Tablet computers, e-books, navigation devices, etc.

[0168] Electronic system 2900 includes at least one memory device 2902. Memory device 2902 may include one or more embodiments of, for example, microelectronic devices and / or structures previously described herein (e.g., Figure 28 Microelectronic devices 2800, Figure 1 Microelectronic device structure 100 Figure 2 Microelectronic device structure 200 Figure 26 Microelectronic device structure 2600 and / or Figure 27 The microelectronic device structure 2700, for example, is formed according to the embodiments previously described herein.

[0169] The electronic system 2900 may further include at least one electronic signal processor device 2904 (generally referred to as a “microprocessor”). The processor device 2904 may optionally include embodiments of the microelectronic devices and / or microelectronic device architectures previously described herein (e.g., Figure 28 Microelectronic devices 2800, Figure 1 Microelectronic device structure 100 Figure 2 Microelectronic device structure 200 Figure 26 Microelectronic device structure 2600 and / or Figure 27The microelectronic device architecture 2700 is described. The electronic system 2900 may further include one or more input devices 2906 for users to input information into the electronic system 2900, such as (for example) a mouse or other pointing device, keyboard, touchpad, button, or control panel. The electronic system 2900 may further include one or more output devices 2908 for outputting information (e.g., visual or audio output) to the user, such as (for example) a monitor, display, printer, audio output jack, speaker, etc. In some embodiments, the input device 2906 and output device 2908 may include a single touchscreen device that can be used both to input information into the electronic system 2900 and to output visual information to the user. The input device 2906 and output device 2908 may be in electrical communication with one or more of the memory device 2902 and the electronic signal processor device 2904.

[0170] Therefore, an electronic system including an input device, an output device, a processor device, and a memory device is disclosed. The processor device is operatively coupled to the input device and the output device. The memory device is operatively coupled to the processor device. The memory device includes at least one microelectronic device structure. The at least one microelectronic device structure includes a stacked structure. The stacked structure includes insulating structures perpendicularly intersecting with conductive structures. Pillars extend through the stacked structure, through a region of doped material below the stacked structure, and into a substrate structure below the region of doped material. The doped material extends laterally into at least one of the pillars and upward within the at least one pillar to an interface with a channel material of the at least one of the pillars. The interface is at an elevation within the stacked structure. The elevation of the interface is also close to the elevation of at least one of the lowest conductive structures in the stacked structure.

[0171] refer to Figure 30 A block diagram of a processor-based system 3000 is shown. The processor-based system 3000 may include various microelectronic devices manufactured according to embodiments of this disclosure (e.g., Figure 28 Microelectronic device 2800) and microelectronic device structure (e.g., Figure 1 Microelectronic device structure 100 Figure 2 Microelectronic device structure 200 Figure 26 Microelectronic device structure 2600 and / or Figure 27The microelectronic device structure 2700). The processor-based system 3000 can be any of various types, such as a computer, pager, cellular phone, personal memo, control circuitry, or other electronic device. The processor-based system 3000 may include one or more processors 3002, such as microprocessors, for controlling system functions and processing requests in the processor-based system 3000. The processor 3002 and other sub-components of the processor-based system 3000 may include microelectronic devices manufactured according to embodiments of this disclosure (e.g., Figure 28 Microelectronic device 2800) and microelectronic device structure (e.g., Figure 1 Microelectronic device structure 100 Figure 2 Microelectronic device structure 200 Figure 26 Microelectronic device structure 2600 and / or Figure 27 Microelectronic device structure 2700).

[0172] The processor-based system 3000 may include a power supply 3004 operatively communicating with the processor 3002. For example, if the processor-based system 3000 is a portable system, the power supply 3004 may include one or more of a fuel cell, a power harvesting device, a permanent battery, a replaceable battery, and / or a rechargeable battery. The power supply 3004 may also include an AC adapter; thus, for example, the processor-based system 3000 can be plugged into a wall socket. The power supply 3004 may also include a DC adapter, allowing the processor-based system 3000 to be plugged into, for example, a vehicle cigarette lighter or a vehicle power port.

[0173] Various other devices may be coupled to processor 3002 depending on the functions performed by processor-based system 3000. For example, user interface 3006 may be coupled to processor 3002. User interface 3006 may include one or more input devices, such as buttons, switches, keyboards, light pens, mice, digitizers and light pens, touch screens, voice recognition systems, microphones, or combinations thereof. Display 3008 may also be coupled to processor 3002. Display 3008 may include LCD displays, SED displays, CRT displays, DLP displays, plasma displays, OLED displays, LED displays, 3D projections, audio displays, or combinations thereof. Furthermore, RF subsystem / baseband processor 3010 may also be coupled to processor 3002. RF subsystem / baseband processor 3010 may include antennas coupled to RF receivers and RF transmitters. Communication port 3012 or more may also be coupled to processor 3002. The communication port 3012 may be adapted to couple to one or more peripheral devices 3014 (e.g., modem, printer, computer, scanner, or camera) or to a network (e.g., local area network (LAN), remote local area network, internal network, or Internet).

[0174] Processor 3002 can control processor-based system 3000 by implementing software programs stored in memory (e.g., system memory 3016). The software programs may include, for example, operating systems, database software, graphics software, word processing software, media editing software, and / or media playback software. Memory (e.g., system memory 3016) is operatively coupled to processor 3002 to store various programs and facilitate their execution. For example, processor 3002 may be coupled to system memory 3016, which may include one or more of spin torque transfer magnetic random access memory (STT-MRAM), magnetic random access memory (MRAM), dynamic random access memory (DRAM), static random access memory (SRAM), race memory, and / or other known memory types. System memory 3016 may include volatile memory, non-volatile memory, or combinations thereof. System memory 3016 is typically large enough to dynamically store loaded applications and data. In some embodiments, system memory 3016 may include the semiconductor devices described above (e.g., Figure 28 Microelectronic devices 2800) and structures (e.g., Figure 1 Microelectronic device structure 100 Figure 2 Microelectronic device structure 200 Figure 26 Microelectronic device structure 2600 and / or Figure 27 Microelectronic device structure 2700 or a combination thereof.

[0175] Processor 3002 may also be coupled to non-volatile memory 3018, which does not imply that system memory 3016 must be volatile. Non-volatile memory 3018 may include one or more of STT-MRAM, MRAM, read-only memory (ROM) (e.g., EPROM, resistive read-only memory (RROM)), and flash memory used together with system memory 3016. The size of non-volatile memory 3018 is typically selected to be large enough to store only the necessary operating system, applications, and fixed data. Additionally, non-volatile memory 3018 may include high-capacity memory (e.g., disk-driven memory, such as (for example) a hybrid drive containing resistive memory or other types of non-volatile solid-state memory). Non-volatile memory 3018 may include the microelectronic devices described above (e.g., Figure 28 Microelectronic devices 2800) and structures (e.g., Figure 1 Microelectronic device structure 100 Figure 2 Microelectronic device structure 200 Figure 26 Microelectronic device structure 2600 and / or Figure 27 Microelectronic device structure 2700 or a combination thereof.

[0176] Non-limiting examples may include the following, either individually or in combination:

[0177] Example 1: A microelectronic device comprising: a stacked structure including a vertically alternating sequence of insulating and conductive structures arranged in layers; at least one pillar extending through the stacked structure, the at least one pillar including a channel material; and a source region below the stacked structure, the source region including a doped material, the vertical extension of the doped material protruding upward at an elevation within the stacked structure to an interface with the channel material.

[0178] Example 2: The microelectronic device according to Example 1, wherein the vertical extension of the doped material laterally overlaps at least a portion of the lowest conductive structure of the conductive structure of the stacked structure in terms of elevation.

[0179] Example 3: A microelectronic device according to any one of Examples 1 and 2, wherein the vertical extension of the doped material protrudes to an elevation that is approximately 10 nm below the lowest surface of the lowest conductive structure of the stacked structure.

[0180] Example 4: A microelectronic device according to any one of Examples 1 to 3, wherein the at least one pillar further includes an insulating material at the core of the at least one pillar, and the channel material laterally surrounds the insulating material above the elevation to which the vertical extension of the doped material protrudes.

[0181] Example 5: A microelectronic device according to any one of Examples 1 to 4, wherein the at least one pillar further comprises a unit material that laterally surrounds the channel material above the elevation to which the vertical extension of the doped material protrudes.

[0182] Example 6: The microelectronic device according to Example 5, wherein the channel material is perpendicularly recessed relative to at least one of the unit materials.

[0183] Example 7: A microelectronic device according to any one of Examples 5 and 6, wherein the doped material of the source region extends laterally through the cell material and the channel material.

[0184] Example 8: A microelectronic device according to any one of Examples 1 to 7, wherein the channel material includes a lower portion below the insulating core of the at least one pillar.

[0185] Example 9: The microelectronic device according to Example 8, wherein the channel material of the at least one pillar further includes an upper portion that is perpendicularly spaced from the lower portion by the doped material.

[0186] Example 10: A microelectronic device according to any one of Examples 1 to 9, wherein the doped material in the source region further includes a downwardly projecting lower vertical extension of the doped material.

[0187] Example 11: A microelectronic device according to any one of Examples 1 to 10, wherein the height of the vertical extension of the doped material is greater than the thickness of the lowest insulating structure of the insulating structure of the stacked structure.

[0188] Example 12: A microelectronic device according to any one of Examples 1 to 11, wherein the elevation to which the vertical extension of the doped material protrudes is approximately equal to the elevation of the upper surface of the lowermost conductive structure of the conductive structure of the stacked structure.

[0189] Example 13: A microelectronic device according to any one of Examples 1 to 12, wherein the vertical extension of the doped material laterally overlaps at least a portion of another conductive structure of the lowermost conductive structure and the conductive structure of the stacked structure.

[0190] Example 14: A method of forming a microelectronic device, the method comprising: forming a sacrificial material stack on a substrate structure; forming a layered stack structure on the sacrificial material stack comprising a vertically alternating sequence of insulating structures and other structures arranged in a hierarchical manner; forming a pillar opening through the layered stack structure, through the sacrificial material stack, and into the substrate structure; forming a cell material, a channel material, and an insulating core material in the pillar opening; forming a slit through the layered stack structure and at least partially through the sacrificial material stack; selectively removing at least one of the sacrificial material and the sacrificial material stack to expose at least one cell material formed in the pillar opening; forming a lateral opening through the cell material to expose a portion of the channel material in the lateral opening; recessing the channel material to form a vertical recess protruding into the stack structure; and forming a doped material in the vertical recess.

[0191] Example 15: According to the method of Example 14, forming the sacrificial material stack on the substrate structure includes: forming a lower region of a first sacrificial material on the substrate structure; forming a region of a second sacrificial material on the lower region of the first sacrificial material; and forming an upper region of the first sacrificial material on the region of the second sacrificial material.

[0192] Example 16: According to the method of Example 15, forming a slit through the layered stack structure and at least partially through the sacrificial material stack includes forming the slit through at least the upper region of the layered stack structure and the first sacrificial material.

[0193] Example 17: The method according to any of Examples 15 and 16, wherein selectively removing the sacrificial material, the at least one of the sacrificial material stack to expose the at least one unit material includes selectively removing the region of the second sacrificial material without removing the lower region and the upper region of the first sacrificial material.

[0194] Example 18: According to the method of Example 14, the formation of the sacrificial material stack on the substrate structure includes: forming a SiCN lower region on the substrate structure; forming a SiGe region on the SiCN lower region; and forming a SiCN upper region on the SiGe region.

[0195] Example 19: The method according to any of Examples 14 to 18 further includes replacing other structures of the layered stacked structure with a conductive structure after forming the doped material in the vertical recess.

[0196] Example 20: The method according to any of Examples 14 to 18 further includes replacing the other structures of the layered stacked structure with a conductive structure after the slit is formed and before selectively removing at least one of the sacrificial materials to expose the at least one unit material.

[0197] Example 21: The method according to any of Examples 14 to 20, wherein forming the slit includes forming the slit through the layered stack structure and only partially through the sacrificial material stack.

[0198] Example 22: The method according to any of Examples 14 to 20, wherein forming the slit includes forming the slit through the layered stack structure and through the sacrificial material stack.

[0199] Example 23: The method according to any of Examples 14 to 22, wherein recessing the channel material further includes forming a lower vertical recess protruding downward into the substrate structure.

[0200] Example 24: The method according to any of Examples 14 to 23, wherein recessing the channel material includes leaving at least a portion of the channel material below the insulating core material.

[0201] Example 25: An electronic system comprising: an input device; an output device; a processor device operatively coupled to the input device and the output device; and a memory device operatively coupled to the processor device and including at least one microelectronic device structure, the at least one microelectronic device structure including: a stacked structure including insulating structures perpendicularly intersecting with conductive structures; and pillars extending through the stacked structure, through a doped material region below the stacked structure, and into a substrate structure below the doped material region; the doped material extending laterally into at least one of the pillars and upward within the at least one of the pillars to an interface with a channel material of the at least one of the pillars, the interface being at an elevation within the stacked structure and close to at least one of the lowermost conductive structures of the stacked structure.

[0202] While the disclosed structures, devices (e.g., apparatus), systems, and methods are readily available in various modifications and alternatives in their implementations, specific embodiments have been shown by way of example in the drawings and described in detail herein. However, this disclosure is not intended to be limited to the specific forms disclosed. Rather, this disclosure covers all modifications, combinations, equivalents, variations, and alternatives falling within the scope of this disclosure as defined by the appended claims and their legal equivalents.

Claims

1. A microelectronic device comprising: A stacked structure comprising a vertically alternating sequence of insulating and conductive structures arranged in layers; At least one pillar extending through the stacked structure, the at least one pillar comprising unit material laterally surrounding channel material, the channel material being perpendicularly recessed relative to at least one of the unit materials; and A source region, located below the stacked structure, includes a doped material, a vertical extension of which protrudes upward at an elevation within the stacked structure to the interface with the channel material, and the vertical extension of which laterally overlaps at an elevation at at least a portion of the lowest conductive structure of the conductive structure of the stacked structure.

2. The microelectronic device of claim 1, wherein the vertical extension of the doped material protrudes to an elevation approximately 10 nm below the lowest surface of the lowest conductive structure of the stacked structure.

3. The microelectronic device according to any one of claims 1 to 2, wherein the at least one pillar further comprises an insulating material at the core of the at least one pillar, the channel material laterally surrounding the insulating material above the elevation to which the vertical extension of the doped material protrudes.

4. The microelectronic device according to any one of claims 1 to 2, wherein the cell material laterally surrounds the channel material above the elevation to which the vertical extension of the doped material protrudes.

5. The microelectronic device of claim 4, wherein the channel material is recessed perpendicularly relative to all the unit materials.

6. The microelectronic device of claim 4, wherein the doped material of the source region extends laterally through the cell material and the channel material.

7. The microelectronic device according to any one of claims 1 to 2, wherein the channel material comprises a lower portion below the insulating core of the at least one pillar.

8. The microelectronic device of claim 7, wherein the channel material of the at least one pillar further comprises an upper portion perpendicularly spaced from the lower portion by the doped material.

9. The microelectronic device according to any one of claims 1 to 2, wherein the doped material in the source region further comprises a downwardly projecting lower vertical extension of the doped material.

10. The microelectronic device according to any one of claims 1 to 2, wherein the height of the vertical extension of the doped material is greater than the thickness of the lowest insulating structure of the insulating structure of the stacked structure.

11. The microelectronic device of claim 1, wherein the vertical extension of the doped material protrudes to an elevation approximately equal to the elevation of the upper surface of the lowermost conductive structure of the conductive structure of the stacked structure.

12. The microelectronic device of claim 1, wherein the vertical extension of the doped material laterally overlaps at least a portion of another conductive structure of the lowermost conductive structure and the conductive structure of the stacked structure.

13. A method of forming a microelectronic device, the method comprising: A stack of sacrificial material is formed on the substrate structure; A layered stacking structure comprising a vertically alternating sequence of insulating structures and other structures arranged in a hierarchical manner is formed on the sacrificial material stack; Forming a strut opening that passes through the layered stacked structure, through the sacrificial material stack, and into the base structure; Unit material, channel material, and insulating core material are formed in the opening of the support column; Forming a slit that passes through the layered stacked structure and at least partially through the sacrificial material stack; Selectively remove at least one sacrificial material from the sacrificial material stack to expose at least one unit material formed in the pillar opening; A transverse opening is formed through the unit material to expose a portion of the channel material within the transverse opening; The channel material is recessed to form an elevation that protrudes into the layered stacking structure and laterally covers at least a portion of the lowest other structure of the layered stacking structure at the elevation; and Doped material is formed in the vertical recess.

14. The method of claim 13, wherein forming the sacrificial material stack on the substrate structure comprises: A lower region of the first sacrificial material is formed on the substrate structure; A region of the second sacrificial material is formed on the lower region of the first sacrificial material; and The upper region of the first sacrificial material is formed on the region of the second sacrificial material.

15. The method of claim 14, wherein forming a slit through the layered stack structure and at least partially through the sacrificial material stack comprises forming the slit through at least the upper region of the layered stack structure and the first sacrificial material.

16. The method of claim 15, wherein selectively removing the at least one sacrificial material in the sacrificial material stack to expose the at least one unit material comprises selectively removing the region of the second sacrificial material without removing the lower region and the upper region of the first sacrificial material.

17. The method of claim 13, wherein forming the sacrificial material stack on the substrate structure comprises: A SiCN lower region is formed on the substrate structure; A SiGe region is formed on the lower SiCN region; and A SiCN upper region is formed on the SiGe region.

18. The method of claim 13, further comprising replacing the layered stacked structure with a conductive structure after forming the doped material within the vertical recess.

19. The method of claim 13, further comprising replacing the other structures of the layered stacked structure with a conductive structure after the slit is formed and before selectively removing at least one of the sacrificial materials to expose the at least one unit material.

20. The method according to any one of claims 13 to 19, wherein forming the slit comprises forming the slit through the layered stack structure and only partially through the sacrificial material stack.

21. The method according to any one of claims 13 to 19, wherein forming the slit comprises forming the slit through the layered stack structure and through the sacrificial material stack.

22. The method according to any one of claims 13 to 19, wherein recessing the channel material further comprises forming a lower vertical recess projecting downward into the substrate structure.

23. The method according to any one of claims 13 to 19, wherein recessing the channel material includes leaving at least a portion of the channel material beneath the insulating core material.

24. An electronic system comprising: Input device; Output device; A processor device operatively coupled to the input device and the output device; and A memory device operatively coupled to the processor device and including at least one microelectronic device structure, the at least one microelectronic device structure comprising: A stacked structure, comprising insulating structures perpendicularly intersecting with conductive structures; and A pillar extends through the stacked structure, through the doped material region beneath the stacked structure, and into the substrate structure beneath the doped material region. The doped material extends laterally into at least one of the pillars and upward within the at least one of the pillars to an interface with the channel material of the at least one of the pillars, the interface being at an elevation that laterally covers at least a portion of the lowest conductive structure of the stacked structure.

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