Semiconductor structure and method for forming the same

CN114792729BActive Publication Date: 2025-09-23SEMICON MFG INT (SHANGHAI) CORP +1
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Patent Information

Application Number
CN202110099857.3
Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
Filing Date
2021-01-25
Publication Date
2025-09-23
Estimated Expiration
2041-01-25

AI Technical Summary

Technical Problem

In existing MOS transistors, the parasitic capacitance between the gate and the source and drain regions is large, resulting in increased device delay and switching power consumption. In addition, the dielectric constant of existing sidewall materials is large, making it difficult to effectively reduce the parasitic capacitance.

Method used

An air sidewall is formed between the gate structure and the sidewall. Multiple openings are formed by etching the gate structure and the sidewall, and the isolation structure is filled to enclose the holes, thereby reducing the parasitic capacitance by utilizing the low dielectric constant of air.

Benefits of technology

It effectively reduces the parasitic capacitance of the semiconductor structure, reduces the delay and switching power consumption of the device, and improves the response speed and switching power consumption performance.

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Abstract

A semiconductor structure and a method for forming the same, wherein the semiconductor structure comprises: a substrate; a fin on the substrate; a gate structure spanning the fin; a sidewall disposed on a portion of the sidewall of the gate structure, with a top surface lower than the top surface of the gate structure; a dielectric layer disposed on the substrate and fin exposed by the gate structure; a first opening extending through the gate structure in a direction perpendicular to the extension direction of the gate structure; a second opening disposed on either side of the gate structure and connected to the first opening; a third opening disposed on either side of the gate structure, with the bottom exposing the top surface of the sidewall, connected to the second opening, the second opening being disposed between the third opening and the first opening and having a depth greater than that of the third opening; and an isolation structure filling a portion of the first, second, and third openings, forming a cavity within the first, second, and third openings. The semiconductor structure provided by embodiments of the present invention is advantageous in reducing parasitic capacitance and improving the performance of the semiconductor structure.
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Citation Information

Patent Citations

  • Integrated circuit device

    US10283600B2

  • Transistor with airgap spacer and tight gate pitch

    US20200219989A1