A method for verifying the SFDR of a large-signal input to an analog-to-digital converter.

Abstract

This invention discloses an SFDR verification method for large-signal input analog-to-digital converters (ADCs). The platform network includes a signal source, a power amplifier, a bandpass filter (BPF), an RC network, and a verification board connected sequentially. The power amplifier's supply voltage is adjustable. By setting the supply voltage, a corresponding gain and the lowest possible signal source output power are obtained, thereby reducing the amount and amplitude of spurious signals at the ADC output and preventing aliasing into the signal band after sampling. Simultaneously, the link gain compensation function of the power amplifier is utilized to push the signal power to the required amplitude, ultimately ensuring successful SFDR verification. This invention inserts a high-gain power amplifier in the measured analog frequency band at the large-signal source output. To adapt to the power amplifier output capability under different signal source inputs, a power amplifier with an adjustable supply voltage is selected. Furthermore, a dedicated power amplifier enable control module is set up to protect the high-gain power amplifier device when there is no signal input.

Description

Technical Field

[0001] This invention relates to analog-to-digital converters, and particularly to an SFDR verification method for large-signal inputs of analog-to-digital converters. Background Technology

[0002] In the verification of analog-to-digital converters (ADCs), especially in scenarios with high sampling rates, certain users have specific requirements for signal performance exceeding the sampling rate within its design bandwidth. For example, an ADC with a sampling rate of 1.5 GHz and a design bandwidth of 2.8 GHz requires a typical SFDR (Signal Flow Rate) better than 55 dBFs @ -6 dBFs for a 2.5 GHz input signal. Therefore, for these special scenarios, attention must be paid to the impedance matching and power loss of the input link; otherwise, excessive link loss will lead to severe distortion of the signal source output signal, and the link bandpass filter will be unable to filter out in-band signals. Therefore, there is an urgent need to explore a verification method for large-signal SFDR that reduces the requirements for input link impedance matching and power loss.

[0003] For large-signal SFDR verification of analog-to-digital converters, the current method is consistent with that used for normal low-frequency signals, such as platform networking. Figure 1 L1, L2 and L3 are the losses of connecting cables or PCB traces.

[0004] To measure SFDR of large signals, in order to meet the high signal amplitude and overcome the attenuation of analog signals in the link, the output power of the signal source must be maximized. This will bring two problems: first, the spurious components of the instrument's output signal will increase, especially when the critical maximum output capability is reached, where spurious components increase rapidly; second, when the instrument outputs large signals, the maximum output power is limited, and the maximum capability will decrease compared to outputting low-frequency small signals.

[0005] When attempting to test SFDR using this approach, due to the aforementioned shortcomings, the test results clearly did not meet expectations, such as... Figure 2 When there is a bandpass filter in the link, the signal power can only be pushed up to -11dBFs, the sampled spectrum has many spurious signals, and the SFDR is -51dBFs; for example Figure 3 To reduce link insertion loss, the bandpass filter was removed. While this allowed the signal power to exceed -6 dBFs, spurious emissions significantly increased and amplified, deteriorating the SFDR to -42 dBFs, thus failing to meet verification requirements. Large-signal SFDR verification based on this scheme is not feasible. Therefore, the following aspects must be addressed: excessive instrument output power leading to distortion, excessive signal link attenuation, and excessively large filter bandwidth. Summary of the Invention

[0006] To address the problems of the prior art, this invention provides a method for verifying the SFDR of a large signal input of an analog-to-digital converter.

[0007] To overcome the problems of existing solutions, mainly the limited output power of the signal source and signal distortion, this invention proposes a large-signal SFDR verification method that reduces instrument output power. Specifically, a power amplifier for the measured frequency band is added to the signal output link. By setting an appropriate power amplifier supply voltage, corresponding gain and the lowest possible signal source output power are achieved. This reduces the amount and amplitude of spurious signals in the instrument output, preventing aliasing into the signal band after sampling. Simultaneously, the power amplifier compensates for link gain, pushing the signal power to the required amplitude, ultimately ensuring successful SFDR verification.

[0008] The technical solution of this invention is:

[0009] A method for verifying the SFDR of a large signal input analog-to-digital converter, wherein the SFDR verification platform network includes a signal source, a power amplifier, a bandpass filter (BPF), an RC network, and a verification board connected in sequence;

[0010] The power amplifier has an adjustable supply voltage. By setting the supply voltage, the corresponding gain and the lowest possible signal source output power can be obtained, thereby reducing the amount and amplitude of spurious signals output by the analog-to-digital converter and avoiding aliasing into the signal band after sampling. At the same time, the link gain compensation function of the power amplifier is used to push the signal power to the required amplitude, ultimately ensuring that the SFDR verification is passed.

[0011] The losses of the connecting cables or PCB traces between the various components of the platform network are L1, L2, L3, and L4, respectively; the signal source output amplitude PIN is adjusted according to the sampling output POUT, and the power amplifier supply voltage is adjusted to obtain different power amplifier gains GxxV; the bandpass filter loss is L5, and the RC network loss is L6; therefore, the power relationship of the entire link is:

[0012] POUT = PIN - L1 + G XX V - L2 - L5 - L3 - L6 - L4.

[0013] Preferably, the SFDR verification method includes the following steps:

[0014] S1. Set the signal source output frequency to F0 and the output amplitude POUT to 0dBm. Start the test with low power and then adjust according to the sampled output. Set the test board clock FS to the sampling clock of the analog-to-digital converter. The test board power supply is normal. Select the low voltage V1 for the power amplifier power supply first, and then decide whether to increase the power amplifier power supply to obtain additional gain according to the sampled output.

[0015] S2. Assuming the product requires a typical SFDR better than 55dBFs @ -6dBFs signal input, SFDR and POUT are obtained based on the output spectrum analysis. If POUT is less than the target power, the power amplifier supply voltage is adjusted to the medium voltage V2 until POUT meets the requirement. At the same time, it is noted whether the SFDR deteriorates to the target value. If it is greater than -55dBFs, it proves that this solution still cannot meet the verification. If the power amplifier is adjusted to the maximum POUT and still cannot reach the target power, and the SFDR still has a margin, then the signal source output power is increased until both POUT and SFDR meet the requirements.

[0016] S3. After continuous adjustments in step 2, the power amplifier is finally powered by a high voltage V3. With BPF in the link, the output POUT and SFDR are sampled. After removing BPF, the output POUT and SFDR are sampled and tested, thus meeting the verification requirements.

[0017] The advantages of this invention are:

[0018] The SFDR verification method for large-signal input analog-to-digital converters of this invention adds a power amplifier for the measured frequency band to the signal output link. By setting an appropriate power amplifier supply voltage, corresponding gain and the lowest possible signal source output power are obtained. This reduces the amount and amplitude of spurious signals output by the instrument, preventing aliasing into the signal band after sampling. Simultaneously, the power amplifier compensates for link gain, pushing the signal power to the required amplitude, ultimately ensuring successful SFDR verification. Attached Figure Description

[0019] The present invention will be further described below with reference to the accompanying drawings and embodiments:

[0020] Figure 1 The signal input link diagram for traditional SFDR testing;

[0021] Figure 2 The input signal for the traditional SFDR test is 2.5GHz, Fs=1.5GHz, and the BPF test results are available.

[0022] Figure 3 The test results are for a traditional SFDR test with an input signal of 2.5GHz, Fs=1.5GHz, and no BPF.

[0023] Figure 4 This is a diagram of the SFDR test signal input link for this invention.

[0024] Figure 5 The SFDR test input signal for this invention is 2.5GHz, Fs=1.5GHz, and the BPF test results are available.

[0025] Figure 6The test results for the SFDR of this invention are as follows: input signal 2.5GHz, Fs=1.5GHz, without BPF. Detailed Implementation

[0026] like Figure 4 As shown, the SFDR verification platform of this invention includes a signal source, a power amplifier, a bandpass filter (BPF), an RC network, and a verification board connected in sequence. At the output of the large signal source, a power amplifier with a high gain (around 30dB) in the measured analog frequency band is inserted. To adapt to the power amplifier output capability under different signal source inputs, a power amplifier with an adjustable power supply voltage is selected. At the same time, in order to protect the high-gain power amplifier device when there is no signal input, a dedicated power amplifier enable control module is set up.

[0027] Figure 4 In this diagram, assuming the losses of the link connecting cable and PCB traces are L1, L2, L3, and L4 respectively, the signal source output frequency is 2.5GHz, the amplitude pin is adjusted according to the sampling output POUT, the power amplifier supply voltages are 3.3V, 4.2V, and 5V respectively (adjusting the voltage can obtain different power amplifier gains GxxV), the bandpass filter loss is L5, and the RC network loss of the verification board input link at 2.5GHz is L6, then the power relationship of the entire link is as follows:

[0028] POUT = PIN - L1 + G XX V-L2-L5-L3-L6-L4

[0029] Step 1: Set the signal source output frequency to 2.5GHz and the output amplitude POUT to 0dBm. Initially, set the power to a low level and adjust it based on the sampled output. Set the test board clock to 1.5GHz, which is the sampling clock for the analog-to-digital converter. Ensure the test board power supply is normal. Initially, select a low voltage of 3.3V for the power amplifier supply. Later, determine whether to increase the power amplifier supply to obtain additional gain based on the sampled output. Ensure the power amplifier's enable signal is normal and begin sampling and analyzing the output signal spectrum.

[0030] Step 2: Assuming the product requires a typical SFDR better than 55dBFs@-6dBFs input signal, analyze the output spectrum to determine SFDR and POUT. If POUT is less than the target power, first adjust the power amplifier supply voltage to 4.2V until POUT meets the requirement. At the same time, pay attention to whether SFDR deteriorates to the target value. If it is greater than -55dBFs, it proves that this solution still cannot meet the verification. If the power amplifier is adjusted to the maximum POUT and still cannot reach the target power, but SFDR still has a margin, then increase the signal source output power until both POUT and SFDR meet the requirements.

[0031] Step 3: After continuous adjustments in Step 2, when the power amplifier is powered by 5V and the signal source output is 10dBm, with BPF in the link, the sampling output POUT is -13dBFs and SFDR is -65dBFs. Figure 5 Since the signal source output power is relatively low and spurious components are relatively few at this time, we can try removing the BPF and then testing. The results are as follows. Figure 6 The sampling output POUT is -7dBFs and SFDR is -56dBFs, which meets the verification requirements. To further improve the POUT value, you can try replacing the connection cable with one that has lower loss and return loss, which can further improve the test performance.

[0032] The above embodiments are only for illustrating the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be construed as limiting the scope of protection of the present invention. All modifications made according to the spirit and essence of the main technical solution of the present invention should be covered within the scope of protection of the present invention.

Claims

1. A method for verifying SFDR of a large signal input of an analog-to-digital converter, the method comprising: The SFDR verification platform network consists of a signal source, a power amplifier, a bandpass filter (BPF), an RC network, and a verification board connected in sequence. The power amplifier has an adjustable supply voltage. By setting the supply voltage, the corresponding gain and the lowest possible signal source output power can be obtained, thereby reducing the amount and amplitude of spurious signals output by the analog-to-digital converter and avoiding aliasing into the signal band after sampling. At the same time, the link gain compensation function of the power amplifier is used to push the signal power to the required amplitude, ultimately ensuring that the SFDR verification is passed. The SFDR verification method includes the following steps: S1. Set the signal source output frequency to F0 and the output amplitude POUT to 0dBm. Start the test with low power and then adjust according to the sampled output. Set the test board clock FS to the sampling clock of the analog-to-digital converter. The test board power supply is normal. Select the low voltage V1 for the power amplifier power supply first, and then decide whether to increase the power amplifier power supply to obtain additional gain according to the sampled output. S2. Assuming the product requires a typical SFDR better than 55dBFs @ -6dBFs signal input, SFDR and POUT are obtained based on the output spectrum analysis. If POUT is less than the target power, the power amplifier supply voltage is adjusted to the medium voltage V2 until POUT meets the requirement. At the same time, it is noted whether the SFDR deteriorates to the target value. If it is greater than -55dBFs, it proves that this solution still cannot meet the verification. If the power amplifier is adjusted to the maximum POUT and still cannot reach the target power, and the SFDR still has a margin, then the signal source output power is increased until both POUT and SFDR meet the requirements. S3. After continuous adjustments in step 2, the power amplifier is finally powered by a high voltage V3. With BPF in the link, the output POUT and SFDR are sampled. After removing BPF, the output POUT and SFDR are sampled and tested, thus meeting the verification requirements.

2. The method of claim 1, wherein, The losses of the connecting cables or PCB traces between the various components of the platform network are L1, L2, L3, and L4, respectively; the signal source output amplitude PIN is adjusted according to the sampling output POUT, and the power amplifier supply voltage is adjusted to obtain different power amplifier gains GxxV; the bandpass filter loss is L5, and the RC network loss is L6; therefore, the power relationship of the entire link is: POUT = PIN - L1 + GXXV - L2 - L5 - L3 - L6 - L4.

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