Block grouping based on power cycles and power-on time

Abstract

The present application relates to block grouping based on power cycles and power-on time. Initializing a block cluster associated with a memory device. Storing an initial value of a power cycle count associated with the memory device. Responsive to programming a block resident on the memory device, associating the block with the block cluster. Responsive to determining that a current value of the power cycle count exceeds the initial value of the power cycle count, shutting down the block cluster. Responsive to determining that a time period that has elapsed since the block cluster was initialized exceeds a threshold period, shutting down the block cluster.

Description

Technical Field

[0001] Embodiments of the present disclosure relate generally to memory subsystems, and more particularly, to block grouping based on power cycling and power-on time. Background Art

[0002] The memory subsystem may include one or more memory devices that store data. The memory devices may be, for example, non-volatile memory devices and volatile memory devices. In general, the host system may utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the invention

[0003] One aspect of the present disclosure provides a method comprising: initializing a block cluster associated with a memory device; storing an initial value of a power cycle count associated with the memory device; in response to programming a block resident on the memory device, associating the block with the block cluster; in response to determining that a current value of the power cycle count exceeds the initial value of the power cycle count, shutting down the block cluster; and in response to determining that a time period that has elapsed since the block cluster was initialized exceeds a threshold period, shutting down the block cluster.

[0004] Another aspect of the present disclosure provides a system comprising: a memory device; and a processing device operatively coupled to the memory device to perform operations including: identifying multiple blocks of the memory device that share a common power cycle time interval, a common programming time interval, and a common programming temperature range; performing a scanning operation with respect to a subset of the multiple blocks; and associating the multiple blocks with threshold voltage shift intervals based on the scanning operation.

[0005] Another aspect of the present disclosure provides a non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: initializing a block cluster associated with a memory device; storing an initial value of a power cycle count associated with the memory device; in response to programming a block resident on the memory device, associating the block with the block cluster; in response to determining that a current value of the power cycle count exceeds the initial value of the power cycle count, shutting down the block cluster; and in response to determining that a time period that has elapsed since the block cluster was initialized exceeds a threshold period, shutting down the block cluster. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] The present disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the present disclosure. However, the drawings should not be considered to limit the present disclosure to specific embodiments, but are only for explanation and understanding.

[0007] Figure 1An example computing system including a memory subsystem according to some embodiments of the present disclosure is described.

[0008] Figure 2 The temporal voltage shift caused by the slow charge loss exhibited by a tri-level memory cell according to some embodiments of the present disclosure is schematically illustrated.

[0009] Figure 3 Depicted is an example graph illustrating the dependence of threshold voltage shift on post-programming time (ie, the period of time elapsed since a block has been programmed) in accordance with an embodiment of the present disclosure.

[0010] Figure 4 A set of predefined threshold voltage shift intervals according to an embodiment of the present disclosure is schematically illustrated.

[0011] Figure 5 The block family management operations performed by the block family manager component of the memory subsystem controller operating according to an embodiment of the present disclosure are schematically illustrated.

[0012] Figure 6 The selection of a block family for calibration according to an embodiment of the present disclosure is schematically illustrated.

[0013] Figure 7 Schematically illustrates instance metadata maintained by a memory subsystem controller for associating blocks and / or partitions with block families according to an embodiment of the present disclosure.

[0014] Figure 8 Block grouping based on both power cycle count and accumulated power-on time according to an embodiment of the present disclosure is schematically illustrated.

[0015] Fig. 9 is a flow chart of an example method of grouping blocks based on power cycle count and accumulated power-on time according to some embodiments of the present disclosure.

[0016] Fig.10 is a flow chart for associating a block family with a specific threshold voltage shift interval based on a calibration scan according to some embodiments of the present disclosure.

[0017] Fig.11 is a block diagram of an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0018] Aspects of the present disclosure are directed to block grouping based on power cycles and power-on time. The memory subsystem may be a storage device, a memory module, or a combination of a storage device and a memory module. Figure 1Examples of storage devices and memory modules are described. In general, a host system may utilize a memory subsystem that includes one or more components, such as memory devices that store data. The host system may provide data for storage at the memory subsystem and may request retrieval of data from the memory subsystem.

[0019] The memory subsystem may utilize one or more memory devices (including any combination of different types of non-volatile memory devices and / or volatile memory devices) to store data provided by the host system. An example of a non-volatile memory device is a NAND memory device. Figure 1 Other examples of non-volatile memory devices are described. Each of the memory devices may include one or more memory cell arrays. A memory cell ("cell") is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more binary bits of information and have various logical states associated with the number of bits stored. The logical states may be represented by binary values ​​such as "0" and "1" or combinations of such values.

[0020] Various data operations may be performed by the memory subsystem. The data operation may be an operation initiated by the host. For example, the host system may initiate a data operation (e.g., write, read, erase, etc.) on the memory subsystem. The host system may send an access request (e.g., a write command, a read command) to the memory subsystem to store data on a memory device at the memory subsystem and read data from a memory device on the memory subsystem. The data to be read or written as specified by the host request is referred to as "host data" hereinafter. The host request may include logical address information (e.g., logical block address (LBA), name space) for the host data, which is the location associated with the host data by the host system. The logical address information (e.g., LBA, name space) may be part of the metadata of the host data. The metadata may also include error handling data (e.g., error correction code (ECC) codeword, parity check code), data version (e.g., for distinguishing the new and old of the written data), valid bitmap (whose LBA or logical transfer unit contains valid data), etc.

[0021] A memory device includes a plurality of memory cells capable of storing one or more bits of information, depending on the memory cell type. A memory cell can be programmed (written to) by applying a certain voltage to the memory cell, which causes the charge to be increased by a voltage called the "threshold voltage" and denoted as V T The memory cell is retained.

[0022] A high quality memory device may have a distribution that is narrower than the operating range of control voltages allowed by the device's cells. Thus, multiple distributions (with "valleys" between them) may fit into an operating voltage window that allows multiple bits per cell to be stored and reliably detected, such as 2 for a triple level cell (TLC). 3 = 8 distributions (7 valleys), 2 for multi-level cells (MLC) 2 = 4 distributions (3 valleys), etc. The distributions are interspersed with voltage intervals ("valley margins") where no (or very few) memory cells in the device have their threshold voltage. Thus, such valley margins can be used to separate the various charge states by applying a read voltage corresponding to each valley, and the logical state of the cell can be determined by detection during a read operation. This effectively allows a single memory cell to store multiple bits of information: N A memory cell operating in a distribution (also called a hierarchy) is capable of storing N bits of information. During a read operation, 2 N -1 read voltage to differentiate 2 N Specifically, the measured threshold voltage V exhibited by the memory cell can be T The read operation is performed by comparing to one or more reference read voltage levels corresponding to known valleys (eg, valley centers) of the memory device.

[0023] As the charge in the cell decreases, the threshold voltage V of the memory cell decreases due to a phenomenon known as slow charge loss (SCL). T Can vary over time, a process sometimes referred to as "time voltage shift" (TVS). TVS can contain different components, such as intrinsic charge loss, system charge loss, fast charge loss, etc. TVS typically increases with increasing number of program erase cycles (PEC), increasing temperature, and increasing programming voltage. TVS can exhibit significant die-to-die variation.

[0024] Since a typical cell stores negatively charged particles (electrons), the loss of electrons causes the voltage threshold to move along the voltage axis toward the lower threshold voltage V T The threshold voltage may change rapidly at first (immediately after the memory cell is programmed), while more often in a roughly log-linear or power-law fashion (ΔV ) with respect to the time t elapsed from the cell programming event (referred to herein as the time after programming (TAP)). T (t)=-C*t b) slowed down. TAP can be estimated (e.g., inferred from data state metrics) or directly measured (e.g., from a controller clock). A cell, block, page, block family (block group), etc. is new (or relatively new) with a (relatively) small TAP and old (or relatively old) with a (relatively) large TAP. A time slice is the duration between two TAP points during which measurements can be made (e.g., referenced 8 to 12 minutes after programming). A time slice can be referenced by its center point (e.g., 10 minutes). In some embodiments of the present disclosure, this can be accomplished by keeping track of the time elapsed since the programming event and environmental conditions such as temperature for a particular memory partition (block, plane, etc.), and offsetting the voltage per valley to be used during a read operation by ΔV T is associated with TVS mitigation, where the standard “base read level” threshold voltage V T The change (exhibited by the cell immediately after programming) is the voltage offset: V T →V T +ΔV T , where ΔV T It is negative due to charge loss. Although TVS is a continuous process and has no effect on ΔV T The compensation of (t) may vary over time, but in some embodiments, a discrete number of threshold voltage shift "intervals" may be utilized to adequately achieve the accuracy of the shift. A "family" of blocks (or any other memory partitions) programmed within a specified time window and / or under similar environmental (e.g., temperature) conditions may be associated with one of the threshold voltage shift intervals. Under the condition that wear leveling remains programmed with similar program-erase cycles (PEC), the time and temperature conditions that have passed since programming are among the major factors affecting the amount of TVS, and it can be inferred that different partitions within a single family of blocks exhibit similar distributions of the threshold voltages of their memory cells, and therefore require the same voltage shift to be applied to the base read level for read operations.

[0025] Block families may be created asynchronously with respect to block programming events. In an illustrative example, a new block family may be created ("opened") whenever a specified time period Δt (e.g., a predetermined number of minutes) has passed since the last block family was created or whenever the reference temperature of the memory cells has changed by more than a specified threshold ΔΘ (e.g., 10C, 20C, or any other value). Similarly, a family may be "closed" (and a new family may be created) after a time Δt has passed since the family was created or when the reference temperature has changed (in either direction) by more than ΔΘ. The memory subsystem controller may maintain identifiers of active block families that are associated with one or more blocks being programmed.

[0026] The memory subsystem controller may periodically perform a calibration process to associate the partitions of each family with one of the threshold voltage offset intervals. Each threshold voltage offset interval may in turn be associated with a set of voltage offsets to be applied for read operations. The association of partitions with families and families with threshold voltage offset intervals is referred to herein as auxiliary read metadata (ARM), which represents part of a broader state metric of a memory device. The state metric may also include the number of abandoned physical memory blocks (or other partitions), the number of times various physical blocks have been erased, the configuration type of cells of various memory partitions (e.g., single-level cells vs. multi-level cells), or any other type of information representing the state of a memory device. The ARM may be stored in a metadata table maintained by the memory subsystem controller.

[0027] The calibration scan (also referred to as the calibration process) may evaluate the data state metric (e.g., voltage shift or bit error rate) of each die of each block family, for example, by measuring the value of the data state metric of the block (of the block family) stored on the die in one of a set of predefined threshold voltage shift intervals for each die of each block family. The calibration scan may then update the interval pointer associated with the die and the block family to point to the threshold voltage shift interval corresponding to the measured value of the data state metric. Each threshold voltage shift interval is in turn associated with a voltage shift to be applied for a read operation. For example, TLC has 8 distributions (levels) and 7 valleys. Therefore, for a given threshold voltage shift interval associated with TLC, there are 7 offsets (i.e., one offset for each valley). For example, the interval pointer may remain the same if the data state metric is within the range associated with the existing interval pointer, or may be changed to point to an older threshold voltage shift interval if the data state metric is within the range associated with the older threshold voltage shift interval. Although a block family may be associated (via an interval pointer) with a plurality of different threshold voltage offset intervals, a block family is referred to herein as being associated with ("being in") a particular one of the threshold voltage offset intervals. More specifically, a block family is associated with (or is in) the oldest threshold voltage offset interval with which the dies of the block family are associated.

[0028] According to an embodiment of the present disclosure, the TVS of the grouped programmed partitions can be selectively tracked. Based on the grouping of the partitions into families, appropriate interval-specific read (voltage) offsets are applied to the base read (voltage) level in the read operation. The base read level can also be stored in the metadata of the memory device. Upon receiving a read command, the memory subsystem controller can identify the family associated with the memory partition identified by the logical address specified in the read command, identify the current threshold voltage offset interval associated with the identified family, determine the read offset set of the identified threshold voltage offset interval, calculate a new read voltage by superimposing the read offset associated with the identified threshold voltage offset interval to the base read level, and perform a read operation using the new read voltage, as described in more detail below.

[0029] Power events such as surges, power down (smooth or asynchronous) and subsequent power up of a memory subsystem can significantly disrupt TVS dynamics. As a result, the association of a memory partition with a particular threshold voltage shift interval (as determined prior to the power event and stored in a metadata table) may no longer adequately identify a read voltage shift (as specified by the corresponding threshold voltage shift interval) for reliable post-event read operations.

[0030] In some implementations, the memory subsystem controller may group blocks into block clusters based on their respective timestamps, which are recorded using a cumulative power-on clock that tracks the time the memory subsystem was powered on and pauses when the memory subsystem is powered off. However, because the cumulative power-on clock does not track the time the memory subsystem was powered off, two blocks that appear to have been programmed within a short period of time based on the cumulative power-on timestamps may be grouped in a common block cluster when in fact a significant period of time (e.g., hours or days) has passed between programming of the blocks while the memory subsystem was powered off.

[0031] Aspects and embodiments of the present disclosure address the above-mentioned deficiencies and others by implementing a memory subsystem controller that groups blocks (or other memory partitions) based on a combination of a power cycle count and a power-on time of the memory subsystem. Upon detecting a power-on event, a power cycle count maintained by the memory subsystem controller is incremented. Thus, upon detecting an increment in the power cycle count, the memory subsystem controller immediately shuts down the current block family and initializes a new block family for the newly programmed block.

[0032] In some embodiments, the memory subsystem may selectively scan memory device blocks based on their respective programming times and power cycle counts. In some implementations, the memory subsystem controller may identify a subset of blocks that share the same programming time interval and the same power cycle count. The memory subsystem controller may associate the identified subset of blocks with a threshold voltage shift interval determined based on one or more scan operations performed on one or more blocks of the subset.

[0033] Advantages of the present disclosure include, but are not limited to, improving the performance of the memory subsystem by grouping blocks based on power cycles and power-on time, thereby reducing the error rate in read operations of blocks programmed within a time frame that includes power-off time. In addition, by performing scans in response to power events, the memory subsystem can avoid performing scans during performance benchmarks, because performance benchmarks are usually completed within the same power cycle. Therefore, aspects of the present disclosure reduce or eliminate scans performed during performance benchmarks.

[0034] Figure 1 An example computing system 100 is illustrated that includes a memory subsystem 110 in accordance with some embodiments of the present disclosure. Memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or a combination of the like.

[0035] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash storage (UFS) drives, secure digital (SD) cards, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small outline DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0036] The computing system 100 can be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, a vehicle (e.g., an airplane, a drone, a train, a car, or other transportation), a device supporting the Internet of Things (IoT), an embedded computer (e.g., a computer included in a vehicle, industrial equipment, or a networked commercial device), or such a computing device that includes a memory and a processing device (e.g., a processor).

[0037] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to multiple memory subsystems 110 of different types. Figure 1 An example of a host system 120 coupled to one memory subsystem 110 is illustrated. As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which may be an indirect communication connection or a direct communication connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0038] The host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller). The host system 120 uses the memory subsystem 110, for example, to write data to the memory subsystem 110 and read data from the memory subsystem 110.

[0039] The host system 120 may be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fibre Channel, a Serial Attached SCSI (SAS), a Double Data Rate (DDR) memory bus, a Small Computer System Interface (SCSI), a Dual In-line Memory Module (DIMM) interface (e.g., a DIMM socket interface supporting Double Data Rate (DDR)), etc. The physical host interface may be used to transmit data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 through a physical host interface (e.g., a PCIe bus), the host system 120 may further utilize an NVM Express (NVMe) interface to access memory components (e.g., the memory device 130). The physical host interface may provide an interface for transferring control, address, data, and other signals between the memory subsystem 110 and the host system 120. Figure 1 Memory subsystem 110 is illustrated as an example. In general, host system 120 can access multiple memory subsystems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0040] The memory devices 130, 140 may include any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (e.g., memory device 140) may be, but are not limited to, random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0041] Some examples of non-volatile memory devices (e.g., memory device 130) include "NAND" type flash memory and write-in-place memory, such as a three-dimensional cross-point ("3D cross-point") memory device, which is a cross-point array of non-volatile memory cells. The cross-point array of non-volatile memory cells can be combined with a stackable cross-grid data access array to perform bit storage based on changes in body resistance. In addition, in contrast to many flash-based memories, cross-point non-volatile memories can perform write-in-place operations, where non-volatile memory cells can be programmed without pre-erasing the non-volatile memory cells. NAND-type flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0042] Each of the memory devices 130 may include one or more memory cell arrays. One type of memory cell (e.g., a single-level cell (SLC)) may store one bit per cell. Other types of memory cells (e.g., multi-level cells (MLC), three-level cells (TLC), four-level cells (QLC), and five-level cells (PLC)) may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more memory cell arrays, such as SLC, MLC, TLC, QLC, PLC, or any combination of the like. In some embodiments, a particular memory device may include an SLC portion of a memory cell, as well as an MLC portion, a TLC portion, a QLC portion, or a PLC portion. The memory cells of the memory device 130 may be grouped into pages, which may refer to a logical unit of a memory device for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0043] Although nonvolatile memory components such as a 3D cross-point nonvolatile memory cell array and NAND-type flash memory (e.g., 2D NAND, 3D NAND) are described, the memory device 130 may be based on any other type of nonvolatile memory, such as read-only memory (ROM), phase change memory (PCM), self-selected memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin transfer torque (STT)-MRAM, conductive bridging RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), "NOR" (NOR) flash memory, or electrically erasable programmable read-only memory (EEPROM).

[0044] The memory subsystem controller 115 (for simplicity, controller 115) can communicate with the memory device 130 to perform operations, such as reading data, writing data, or erasing data and other such operations at the memory device 130. The memory subsystem controller 115 can include hardware, such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The hardware can include digital circuits with dedicated (i.e., hard-coded) logic to perform the operations described herein. The memory subsystem controller 115 can be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or other suitable processor.

[0045] The memory subsystem controller 115 may include a processing device including one or more processors (e.g., processor 117) configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory subsystem 110, including handling communications between the memory subsystem 110 and the host system 120.

[0046] In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, etc. Local memory 119 may also include a read-only memory (ROM) for storing microcode. Figure 1 The example memory subsystem 110 in FIG. 1 has been illustrated as including a memory subsystem controller 115, but in another embodiment of the present disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0047] Typically, the memory subsystem controller 115 may receive commands or operations from the host system 120, and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation between logical addresses (e.g., logical block addresses (LBA), name spaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuit system to communicate with the host system 120 via a physical host interface. The host interface circuit system may convert commands received from the host system into command instructions to access the memory device 130, and convert responses associated with the memory device 130 into information for the host system 120.

[0048] The memory subsystem 110 may also include additional circuitry or components not illustrated. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that may receive addresses from the memory subsystem controller 115 and decode the addresses to access the memory device 130.

[0049] In some embodiments, the memory device 130 includes a local media controller 135 that operates in conjunction with the memory subsystem controller 115 to perform operations on one or more memory cells of the memory device 130. An external controller (e.g., the memory subsystem controller 115) can manage the memory device 130 externally (e.g., perform media management operations on the memory device 130). In some embodiments, the memory subsystem 110 is a managed memory device, which is a raw memory device 130 with control logic on the die (e.g., the local controller 132) and a controller for media management within the same memory device package (e.g., the memory subsystem controller 115). An example of a managed memory device is a managed NAND (MNAND) device.

[0050] The memory subsystem 110 includes a block family manager component 113 that can group blocks based on power cycle counts and cumulative power-on timestamps. In some embodiments, the memory subsystem controller 115 includes at least a portion of the block family manager component 113. In some embodiments, the block family manager component 113 is part of the host system 110, an application, or an operating system. In other embodiments, the local media controller 135 includes at least a portion of the block family manager component 113 and is configured to perform the functions described herein.

[0051] The block family manager component 113 may determine the power cycle count and the length of the accumulated power-on time when grouping blocks in a block family. The memory subsystem controller 115 may maintain an accumulated power-on clock that may be stored in the non-volatile memory device 140. The accumulated power-on clock tracks the power-on time of the memory subsystem and saves the clock setting when the memory subsystem is powered off. When the memory subsystem is powered on, the accumulated power-on clock restarts from the saved clock setting. For example, if the memory subsystem is powered off at 2:45pm, the memory subsystem controller 115 saves the accumulated power-on clock setting to the memory device 140 (e.g., the accumulated power-on clock setting may store 240 minutes of accumulated power-on time). When the memory subsystem is subsequently powered on at, for example, 7:50pm on the same day, the accumulated power-on clock will restart at the saved setting (240 minutes in this example). Based on the accumulated power-on clock, the block programmed at 7:51pm appears to have been programmed within 2 minutes of the block programmed at 2:44pm. However, the blocks were actually programmed more than 5 hours apart.

[0052] Therefore, the block family manager component 113 may also consider the power cycle count when grouping blocks.The memory subsystem controller 115 may store the power cycle count, for example, in the non-volatile memory device 140. The power cycle count is incremented upon detection of a power-on event of the memory subsystem.

[0053] The block family manager component 113 may initialize a block family associated with a memory device, such as the memory device 140. The block family manager component 113 may store a current power cycle count at the time the block family is initialized. When programming a block associated with the memory device, the block family manager component 113 associates the block with the block family. The block family manager component 113 may shut down the block family upon detecting an increment in the power cycle count (i.e., indicating that the memory subsystem has been powered off and powered on again), or upon determining that the time that has elapsed since the block family was initialized exceeds a threshold time period. Continuing with the above example, the block family manager component 113 may group blocks in different block families based on different power cycle counts, even though the block programmed at 2:44 just before the memory subsystem was powered off and the block programmed at 7:51 just after the memory subsystem was powered on may have been programmed within a specified threshold time period based on the cumulative power-on clock.

[0054] In some embodiments, the block family manager component 113 may identify blocks associated with a memory device (e.g., memory device 140) that shares a power cycle count and is programmed within a threshold time interval. The block family manager component 113 may scan a subset of the identified blocks. It should be noted that in some embodiments, the subset may include a single identified block, all identified blocks, or any number between a single identified block and all identified blocks. The subset may be a randomly selected identified block, or may be certain blocks within the identified blocks (e.g., may include the earliest programmed block, the most recently programmed block, and / or a block programmed in the middle of a threshold time interval). The subset may be selected in a manner not described herein.

[0055] Based on the scan of the identified block subset, the block family manager component 113 may determine which threshold voltage offset interval the identified block is associated with. In an embodiment, the scan may measure a data state metric (e.g., a voltage shift or a bit error rate) of the identified block subset. Based on the data state metric, the block family manager component 113 may associate the identified block with an appropriate threshold voltage offset interval. That is, the block family manager component 113 may associate the identified block with an appropriate threshold voltage offset interval to offset the measured voltage shift or correct the measured bit error rate.

[0056] Additional details regarding the operation of the block family manager component 113 are described below.

[0057] Figure 2 Schematically illustrates the time voltage shift caused by the slow charge loss exhibited by a three-level memory cell according to some embodiments of the present disclosure. Figure 2 The illustrative example of utilizes a three-level cell, but the same observations can be made, and thus the same remedies apply to single-level cells and multi-level cells, as well as any other fractional or integer number of bits per cell (e.g., 3.5 bits per cell, etc.) to compensate for slow charge loss.

[0058] A memory cell can be programmed (written to) by applying a certain voltage (e.g., a programming voltage) to the memory cell, thereby generating a charge stored by the memory cell. Precisely controlling the amount of charge stored by a memory cell allows the memory cell to have multiple threshold voltage levels corresponding to different logic levels, thereby effectively allowing a single memory cell to store multiple bits of information. n A memory cell operated at n different threshold voltage levels is capable of storing n bits of information.

[0059] Each of the graphs 210 and 230 illustrates programming voltage distributions 220A-220N (also referred to herein as "programming distributions" or "voltage distributions" or "distributions" or "tiers") of memory cells programmed with respective write levels (which may be assumed to be at the midpoint of the programming distributions) to encode corresponding logic levels ("000" to "111" in the case of TLC). The programming distributions 220A-220N may illustrate a range of threshold voltages (e.g., a normal distribution of threshold voltages) for memory cells programmed with respective write levels (e.g., programming voltages). To distinguish adjacent program distributions (corresponding to two different logic levels), a read threshold voltage level (shown by a vertical dashed line) is defined such that any measured voltage below the read threshold level is associated with one program distribution in a pair of adjacent program distributions, while any measured voltage greater than or equal to the read threshold level is associated with the other program distribution in the pair of adjacent distributions.

[0060] In chart 210, eight states of the memory cell are shown below the corresponding program distribution (except for the state labeled ER which is the erased state, the distribution of states is not shown). Each state corresponds to a logic level. The read threshold voltage levels are labeled Va-Vh. As shown, any measured voltage below Va is associated with the ER state. The states labeled P1, P2, P3, P4, P5, P6, and P7 correspond to distributions 220A-220N, respectively.

[0061] Time after programming (TAP) shall refer to the time elapsed since the cell was written in this article and is the main driver of time voltage shift (TVS) together with temperature. TVS captures SCL and other charge loss mechanisms. TAP can be estimated (e.g., inferred from data state metrics) or directly measured (e.g., from controller clock). Cells, blocks, pages, block families, etc. are new (or relatively new) with (relatively) small TAPs and old (or relatively old) with (relatively) large TAPs. A time slice is the duration between two TAP points during which measurements can be made (e.g., performing a reference calibration at X to Y minutes or hours after programming). A time slice can be referenced by its center point.

[0062] As can be seen from example graphs 210 and 230 that compare a time after programming (TAP) of 0 (immediately after programming) and a TAP of T hours (where T is the number of hours), respectively, the program distribution varies over time primarily due to slow charge loss. In order to reduce the read bit error rate, the corresponding read threshold voltage needs to be adjusted to compensate for the program distribution shift shown by the vertical dashed line. In various embodiments of the present disclosure, the temporal voltage shift is selectively tracked for a die group based on measurements made at one or more representative die of the die group. Based on measurements of the temporal voltage shift and operating temperature of the die in the die group characterized by the representative die in the die group, the read threshold voltage offset used to read the memory cells for the die in the die group is updated and applied to the base read threshold level to perform a read operation.

[0063] Figure 3 An example graph 300 illustrating the dependence of a threshold voltage shift 310 on a post-programming time 320 (ie, the period of time that has elapsed since a block has been programmed) according to an embodiment of the present disclosure is depicted. Figure 3 Schematically illustrated, the block families of the memory device are grouped into threshold voltage shift intervals 330A-330N, such that each block family includes one or more blocks that have been programmed in a specified time window, a specified temperature window, and during the same power cycle. As noted above, since the time and temperature that have passed after programming are the primary factors that affect the temporal voltage shift, it is presumed that all blocks and / or partitions within a block family 310 exhibit similar threshold voltage distributions in the memory cells, and therefore will need to have the same voltage shift applied to the base read level for a read operation.

[0064] Block clusters may be created asynchronously with respect to page programming events. In an illustrative example, each time a specified period of time (e.g., a predetermined number of minutes) has passed since the last block cluster was created, each time a power cycle count is incremented, or each time a memory cell reference temperature updated at a specified time interval has changed by more than a specified threshold since the current block cluster was created, Figure 1 The memory subsystem controller 115 may create new block families.

[0065] The newly created block family may be associated with interval 0. The memory subsystem controller may then periodically perform a foreground or background calibration process to align each die of each block family with a predefined threshold voltage offset interval (in Figure 3 The association of blocks to block families, and block families and die to threshold voltage offset block groups, may be stored in corresponding metadata tables maintained by the memory subsystem controller.

[0066] Figure 4Schematically illustrates a set of placed threshold voltage shift intervals (interval 0 to interval 9) according to an embodiment of the present disclosure. Figure 4 Schematically, the threshold voltage shift chart can be subdivided into a plurality of intervals, so that each interval corresponds to a threshold voltage shift range. Figure 4 The illustrative example of defines ten intervals, but in other embodiments, various other numbers of intervals (e.g., 64 intervals) may be used.

[0067] The memory subsystem controller may associate each die of each block family with a threshold voltage offset interval based on a calibration process that is performed periodically. The calibration process selects a set of threshold voltage offsets to be applied to a base voltage read level in order to perform a read operation. The calibration process involves performing read operations with different threshold voltage offsets for a specified number of randomly selected pages or blocks within the block family being calibrated, and selecting the threshold voltage offset that minimizes the error rate (e.g., bit error rate) of the read operation. Additionally or alternatively, to compensate for the SCL, the calibration process may make measurements on data state metrics (e.g., voltage shifts for specific valleys) to assign the block family to an interval of corresponding offsets.

[0068] Figure 5 The block family management operation implemented by the block family manager component of the memory subsystem controller operating according to the embodiment of the present disclosure is schematically illustrated. Figure 5 Schematically illustrated, block family manager 510 may maintain in a memory variable an identifier 520 of the active block family associated with one or more blocks being programmed of cursors 530A-530K. "Cursor" will broadly refer herein to a location on a memory device to which data is written.

[0069] The memory subsystem controller may utilize a power-on minute (POM) clock to track the creation time of a block family. In some embodiments, in addition to the POM clock, a less accurate clock may be utilized that continues to run when the controller is in various low power states, such that upon waking up from a low power state, the POM clock is updated based on the less accurate clock. Typically, neither the POM clock nor the less accurate clock continues to run when the controller is powered off.

[0070] The memory subsystem controller may utilize a power cycle counter 572 for tracking power cycles of the memory subsystem. The power cycle counter 572 may maintain a count representing the number of times the memory subsystem has been powered on; that is, the power cycle counter 572 increments upon detecting a power-on event.

[0071] Immediately after each block family is initialized, the current time 540 and the power cycle count 572 are stored in memory variables as the block family start time 550 and the block family start power cycle (PC) count 552. When a page or block is programmed, the current time 540 is compared to the block family start time 550, and the power cycle counter 572 is compared to the block family start power cycle count 552. In response to detecting that the difference between the current time 540 and the block family start time 550 is greater than or equal to a specified time period (e.g., a predetermined number of minutes), and / or in response to detecting that the difference between the power cycle counter 572 and the block family start power cycle count 552 does not match, the memory variable storing the active block family identifier 520 is updated to store the next block family number (e.g., the next consecutive integer), the memory variable storing the block family start time 550 is updated to store the current time 540, and the memory variable storing the block family start power cycle count 552 is updated to store the power cycle counter 572.

[0072] The block family manager 510 may also maintain two memory variables for storing the high and low reference temperatures of the selected die of each memory device. After initialization of each block family, the high temperature 560 and low temperature 570 variables store the values ​​of the current temperature of the selected die of the memory device. In operation, while the active block family identifier 520 remains the same, temperature measurements are periodically obtained and compared with the correspondingly updated stored high temperature 560 and low temperature 570 values: if the temperature measurement is found to be greater than or equal to the value stored by the high temperature variable 560, the value stored by the high temperature variable 560 is updated to store the temperature measurement; conversely, if the temperature measurement is found to drop below the value stored by the low temperature variable 570, the value stored by the low temperature variable 570 is updated to store the temperature measurement.

[0073] The block family manager 510 may further periodically calculate the difference between the high temperature 560 and the low temperature 570. In response to determining that the difference between the high temperature 560 and the low temperature 570 is greater than or equal to the specified temperature threshold, the block family manager 510 may close the existing block family and may create a new active block family by updating the memory variable storing the active block family identifier 520 to store the next block family number (e.g., the next sequential integer number), updating the memory variable storing the block family start time 550 to store the current time 540, and updating the high temperature 560 and low temperature 570 variables to store the value of the current temperature of the selected die of the memory device.

[0074] When programming a block, the memory subsystem controller associates the block with the currently active block family. The association of each block with the corresponding block family is reflected by the block family metadata 580, as described below with reference to Figure 7 Describe in more detail.

[0075] As mentioned herein above, based on a calibration scan (i.e., a calibration process) that is performed periodically, the memory subsystem controller associates each die of each block family with a threshold voltage offset interval that defines a set of threshold voltage offsets to be applied to the base voltage read level in order to perform a read operation. In some embodiments, the scan is performed in response to detecting a power-on event. The scan may involve performing read operations with different threshold voltage offsets with respect to a subset of the identified plurality of blocks, and selecting a threshold voltage offset interval that causes a defined error rate for the read operation. The identified plurality of blocks may include blocks that share a common power cycle time interval and a common programming time interval. The identified subset of blocks may be selected randomly, or selected based on satisfying a specific criterion (e.g., being the earliest programmed block of the identified plurality of blocks).

[0076] Figure 6 Schematically illustrating the selection of a block family for calibration according to an embodiment of the present disclosure. Figure 6 Schematically, the memory subsystem controller may limit calibration operations to the oldest block cluster in each threshold voltage shift interval (e.g., block cluster 610 in interval 0 and block cluster 620 in interval 1) because the oldest block cluster is the oldest block cluster that migrates to the next threshold voltage shift interval before any other block cluster in the current threshold voltage shift interval due to slow charge loss.

[0077] Figure 7 Schematically illustrates instance metadata maintained by a memory subsystem controller for associating blocks and / or partitions with block families according to an embodiment of the present disclosure. Figure 7 Schematically illustrated, the memory subsystem controller may maintain a superblock table 710 , a family table 720 , and an offset table 730 .

[0078] Each record of SuperBlock Table 710 specifies a Block Family associated with a specified SuperBlock and Partition combination. In some implementations, a SuperBlock Table record may additionally include a Time, Power Cycle Count, and Temperature value associated with a specified SuperBlock and Partition combination.

[0079] The family table 720 is indexed by the block family number, so that each record of the family table 720 specifies a set of threshold voltage offset intervals associated with the corresponding die of the block family for the block family referenced by the index of the record. In other words, each record of the family table 720 contains a vector, each element of which specifies a threshold voltage offset interval associated with the die referenced by the index of the vector element. The set of threshold voltage offset blocks to be associated with the block family die can be determined by a calibration process, as described in more detail above.

[0080] Finally, the offset table 730 is indexed by the threshold voltage offset bin number. Each record of the offset table 730 specifies a set of threshold voltage offsets associated with a threshold voltage offset block group (eg, for TLC, MLC, and / or SLC).

[0081] Metadata tables 710-730 may be stored in Figure 1 In some implementations, at least a portion of the metadata table may be cached in one or more memory devices 130. Figure 1 In the local memory 119 of the memory subsystem controller 115.

[0082] In operation, upon receiving a read command, the memory subsystem controller determines the physical address corresponding to the logical block address (LBA) specified by the read command. The components of the physical address (e.g., physical block number and die identifier) ​​are used to perform a metadata table traversal: first, the superblock table 710 is used to identify the block family identifier corresponding to the physical block number; then, the block family identifier is used as an index into the family table 720 to determine the threshold voltage offset interval associated with the block family and die; finally, the identified threshold voltage offset interval is used as an index into the offset table 730 to determine the threshold voltage offset corresponding to the threshold voltage offset interval. The memory subsystem controller may then apply the identified threshold voltage offset additively to the base voltage read level in order to perform the requested read operation.

[0083] exist Figure 7 In the illustrative example of , Super Block Table 710 maps Partition 0 of Super Block 0 to Block Family 4, which is used as an index into Family Table 720 to determine that Die 0 is mapped to Interval 2. The latter value is used as an index into the Offset Table to determine the threshold voltage offset value for Interval 2.

[0084] Figure 8 Schematically illustrates an example of block grouping based on a combination of power cycle count and accumulated power-on time of a memory subsystem according to some embodiments of the present disclosure. Figure 8 As illustrated in FIG. 1 , blocks 1 and 2 are opened and closed during power cycle (PC) 1. Block 2 is opened during power cycle 1 and closed during power cycle 2. Block 4 is opened and closed during power cycle 2. Block 5 is opened during power cycle 2 and closed during power cycle 3. Block 6 is opened and closed during power cycle 3.

[0085] The power cycle count 810 is incremented each time the drive state is powered on. Figure 8 , the drive state is "ON" at time t0 and is powered off at time t1. At time t2, the drive state is "ON" and the power cycle count 810 is incremented. The drive is powered off at time t3. At time t4, the drive is powered on and the power cycle count 810 is incremented.

[0086] Still Figure 8 820 and the cumulative power-on timestamp 822. The real timestamp 820 may represent the real progress of time. The cumulative power-on timestamp 822 may represent the power-on minute (POM) clock maintained by the memory subsystem controller. The cumulative power-on timestamp 822 does not track the time when the drive state is not "on".

[0087] In an embodiment, the memory subsystem controller may group blocks based on both the cumulative power-on timestamp 822 and the power cycle count 810. For example, the memory subsystem controller may determine that blocks 1 and 2 are opened and closed within a specified time window, and may determine that blocks 1 and 2 are opened and closed during the same power cycle (i.e., power cycle count 1). Therefore, the memory subsystem controller may group blocks 1 and 2 in the same block cluster.

[0088] The memory subsystem controller may determine that blocks 3 and 4 are opened and closed within a specified time window based on the cumulative power-on timestamp 822. However, blocks 3 and 4 are opened and closed in different power cycles (i.e., block 3 is opened in power cycle count 1 and closed in power cycle count 2, and block 4 is opened and closed in power cycle count 2). Thus, the memory subsystem controller may determine not to group blocks 3 and 4 in the same block cluster.

[0089] The memory subsystem controller may determine that blocks 6 and 7 are opened and closed in the same power cycle (i.e., power cycle count 3). However, the memory subsystem controller may determine that blocks 6 and 7 are not opened and closed within a specified time period window. That is, the difference between the accumulated power-on timestamp 822 at the time when block 7 is closed and the accumulated power-on timestamp 822 at the time when block 6 is opened exceeds a threshold time period. Therefore, the memory subsystem controller may determine not to group blocks 6 and 7 in the same block cluster.

[0090] Fig. 9 900 is a flowchart of an example method for grouping blocks based on power cycle count and accumulated power-on time according to an embodiment of the present disclosure. The method 900 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, a dedicated logic, a programmable logic, a microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, the method 900 is performed by Figure 1The block family manager component 113 of the embodiment of the present invention is executed. Although shown in a specific order or sequence, the order of the process can be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are only examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible.

[0091] At operation 910, processing logic initializes a block family associated with a memory device. Processing logic may additionally associate the block family with a threshold voltage shift interval, as described herein below with reference to Figure 7 Describe in more detail.

[0092] At operation 920, processing logic stores an initial value of a power cycle associated with the memory device. In an embodiment, the power cycle value may be stored in a non-volatile memory associated with the memory device. The power cycle value may be incremented in response to detecting that the memory device is powered on, and thus may track the number of times the memory device has been powered on.

[0093] At operation 930, in response to programming a block resident on a memory device, processing logic associates the block with a block family. In an embodiment, processing logic associates the block with a block family by updating block family metadata associated with the memory device. The block family metadata includes a table having a plurality of records, and each record associates a block with a block family.

[0094] At operation 940, in response to determining that the current value of the power cycle count exceeds the initial value of the power cycle count, the processing logic shuts down the block family. In an embodiment, the processing logic may allow the counter to reset. That is, once the counter has reached its maximum value, the counter may be reset and the processing logic may accurately identify that the current value of the power cycle exceeds the initial value of the power cycle count.

[0095] At operation 950, in response to determining that the time period that has passed since the block cluster was initialized exceeds the threshold period, processing logic shuts down the block cluster. The time period that has passed since the block cluster was initialized can be based on a cumulative power-on clock associated with the memory device. In response to shutting down the block cluster, processing logic initializes a new block cluster.

[0096] In an embodiment, processing logic may initialize the low and high temperatures based on a reference temperature of the memory device. Subsequently, in response to determining that the difference between the high and low temperatures is greater than or equal to a specified threshold temperature value, processing logic shuts down the block cluster.

[0097] In an embodiment, the processing logic may receive a second reference temperature of the memory device. In response to determining that the second reference temperature is greater than or equal to the high temperature, the processing logic may update the high temperature to store the second reference temperature. Alternatively, in response to determining that the second reference temperature is lower than the low temperature, the processing logic may update the low temperature to store the second reference temperature.

[0098] Fig.10 is a flowchart of associating a block family with a specific threshold voltage offset interval based on a calibration scan according to an embodiment of the present disclosure. According to an embodiment of the present disclosure, the block family is one or more blocks grouped based on power cycles and cumulative power-on time. Method 1000 may be performed by processing logic, which may include hardware (e.g., a processing device, a circuit system, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executed on a processing device), or a combination thereof. In some embodiments, method 1000 is performed by Figure 1 The block family manager component 113 of the embodiment of the present invention is executed. Although shown in a specific order or sequence, the order of the processes can be modified unless otherwise specified. Therefore, it should be understood that the illustrated embodiments are only examples, and the illustrated processes can be performed in a different order, and some processes can be performed in parallel. In addition, one or more processes can be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are also possible. In an embodiment, the process can be executed in response to detecting a power-on event of the memory subsystem. Fig.10 operation.

[0099] At operation 1010, processing logic identifies a plurality of blocks of a memory device that share a common power cycle time interval, a common programming time interval, and a common programming temperature range. Processing logic may examine programmed blocks associated with the memory device and identify blocks that are programmed within a specified time interval (e.g., within a certain predetermined number of minutes), programmed in the same power cycle, and programmed within a specified temperature range. The time interval is specified by a first timestamp value reflecting a time when the block is opened based on a cumulative power-on clock, and a second timestamp value reflecting a time when the block is closed based on the cumulative power-on clock. The temperature range is determined by a low temperature and a high temperature based on a reference temperature of the memory device. The power cycle time interval is specified by a first power cycle count representing a power cycle count when the block is opened, and a second power cycle count representing a power cycle count when the block is closed.

[0100] At operation 1020, processing logic performs a scan operation with respect to a subset of the plurality of blocks. The subset may be randomly selected, or may include a predetermined block (e.g., the earliest programmed block within the plurality of blocks). The subset may include a single block, more than one block, or all of the identified blocks. The scan operation may include measuring a data state metric of memory cells in the subset of the plurality of blocks. The data state metric may be, for example, a voltage shift or a bit error rate. Processing logic may identify a threshold voltage shift interval corresponding to the measured data state metric value. That is, processing logic may identify a threshold voltage shift interval to offset the measured voltage shift or to correct the measured bit error rate.

[0101] At operation 1030, processing logic may associate a plurality of blocks with threshold voltage shift intervals based on the scanning operation. At operation 1040, processing logic updates block family metadata associated with the memory device. The block family metadata includes a table of records, and each record associates each block subset with a corresponding threshold voltage shift interval. Figure 7 Further describes the block family metadata.

[0102] Fig.11 An example machine of a computer system 1100 is illustrated, within which a set of instructions for causing the machine to perform any one or more of the methods discussed herein may be executed. In some embodiments, the computer system 1100 corresponds to a host system (e.g., Figure 1 ) that includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 The memory subsystem 110 of the controller may be used to execute the operation of the controller (for example, to execute the operating system to execute the corresponding Figure 1 In some embodiments, the machine may be connected (e.g., using a network) to other machines in a peer-to-peer (or distributed) network environment, or in the capacity of a server or a client machine in a client-server network environment.

[0103] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or a bridge, or any machine capable of executing (sequentially or otherwise) a set of instructions that specify actions to be taken by the machine. In addition, while a single machine is described, the term "machine" should also be construed to include any collection of machines that individually or collectively execute one (or more) sets of instructions to perform any one or more of the methodologies discussed herein.

[0104] The example computer system 1100 includes a processing device 1102, a main memory 1104 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM), such as synchronous DRAM (SDRAM) or RDRAM, etc.), a static memory 1106 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 1118, which communicate with each other via a bus 1130.

[0105] The processing device 1102 represents one or more general processing devices, such as a microprocessor, a central processing unit, etc. More specifically, the processing device can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. The processing device 1102 can also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), a network processor, etc. The processing device 1102 is configured to execute instructions 1126 for performing the operations and steps discussed herein. The computer system 1100 may additionally include a network interface device 1108 to communicate on a network 1120.

[0106] The data storage system 1118 may include a machine-readable storage medium 1124 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 1126 or software embodying any one or more of the methods or functions described herein. The instructions 1126 may also reside, completely or at least partially, within the main memory 1104 and / or within the processing device 1102 during execution by the computer system 1100, with the main memory 1104 and the processing device 1102 also constituting machine-readable storage media. The machine-readable storage medium 1124, the data storage system 1118, and / or the main memory 1104 may correspond to Figure 1 Memory subsystem 110.

[0107] In one embodiment, instructions 1126 include instructions for implementing a command corresponding to a block family manager component (e.g., Figure 1 The block family manager component 113 of the present invention may be a block family manager component 113 of the present invention. Although the machine-readable storage medium 1124 is shown as a single medium in the example embodiment, the term "machine-readable storage medium" should be considered to include a single medium or multiple media storing one or more sets of instructions. The term "machine-readable storage medium" should also be considered to include any medium that is capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methods of the present disclosure. The term "machine-readable storage medium" should therefore be considered to include, but not be limited to, solid-state memory, optical media, and magnetic media.

[0108] Some portions of the previous detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing can most effectively convey the substance of their work to others skilled in the art. In this article, and generally, an algorithm is conceived to be a self-consistent sequence of operations that produce a desired result. An operation is one that requires physical manipulation of physical quantities. Typically (but not necessarily), these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has proven to be convenient at times, primarily for common reasons, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, and the like.

[0109] It should be borne in mind, however, that all of these and similar terms will be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may refer to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage systems.

[0110] The present disclosure also relates to an apparatus for performing the operations described herein. This apparatus may be specially constructed for the desired purpose, or it may comprise a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but not limited to, any type of disk, including a floppy disk, an optical disk, a CD-ROM, and a magnetic optical disk, a read-only memory (ROM), a random access memory (RAM), an EPROM, an EEPROM, a magnetic card or an optical card, or any type of medium suitable for storing electronic instructions, each of which is connected to a computer system bus.

[0111] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general purpose systems may be used in conjunction with the programs according to the teachings herein, or it may prove convenient to construct a more specialized device to perform the method. The structures of various such systems will be presented as set forth in the description below. In addition, the present disclosure is not described with reference to any particular programming language. It should be appreciated that the teachings of the present disclosure as described herein may be implemented using various programming languages.

[0112] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having stored thereon instructions that can be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium, such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory component, etc.

[0113] In the foregoing description, embodiments of the present disclosure have been described with reference to specific example embodiments thereof. It will be apparent that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure as set forth in the appended claims. Therefore, the description and drawings should be viewed in an illustrative sense rather than a restrictive sense.

Claims

1. A method performed by a memory system, wherein the method comprises: Initializing a cluster of blocks associated with a memory device; storing an initial value of a power cycle count associated with the memory device; responsive to programming a block residing on the memory device, associating the block with the block family; determining a current value of the power cycle count; determining a period of time that has elapsed since the block family was initialized; and The block cluster is shut down based on at least one of: a difference between the initial value of the power cycle count and the current value of the power cycle count, or the time period that has elapsed since the block cluster was initialized. 2 . The method of claim 1 , wherein the time period is determined based on a cumulative power-on clock associated with the memory device.

3. The method of claim 1 , wherein associating the block with the block family further comprises: Block family metadata associated with the memory device is updated, wherein the block family metadata comprises a table including a plurality of records, and wherein a record in the plurality of records associates the block with the block family.

4. The method of claim 1, further comprising: In response to closing the block cluster, a new block cluster is initialized.

5. The method of claim 1, further comprising: In response to initializing the block family, the block family is associated with a threshold voltage shift interval. The method of claim 1 , wherein the power cycle count is incremented in response to detecting that the memory device is powered on.

7. The method of claim 1, further comprising: initializing a low temperature and a high temperature based on a reference temperature of the memory device; and In response to determining that a difference between the high temperature and the low temperature is greater than or equal to a specified threshold temperature value, the block family is shut down.

8. The method of claim 7, further comprising: receiving a second reference temperature of the memory device; in response to determining that the second reference temperature is greater than or equal to the high temperature, updating the high temperature to store the second reference temperature; and In response to determining that the second reference temperature is lower than the low temperature, the low temperature is updated to store the second reference temperature.

9. A memory system comprising: Memory device; and a processing device operatively coupled to the memory device to perform operations comprising: identifying a plurality of blocks of the memory device that share a common power cycling time interval, a common programming time interval, and a common programming temperature range; performing a scan operation with respect to a subset of the plurality of blocks; and Based on the scanning operation, the plurality of blocks are associated with threshold voltage shift intervals.

10. The memory system of claim 9, wherein a programming time interval of a block is specified by a first timestamp value reflecting a time when the block is opened based on a cumulative power-on clock and a second timestamp value reflecting a time when the block is closed based on the cumulative power-on clock, and wherein a power cycle time interval of the block is specified by a first power cycle count representing a first power cycle count value when the block is opened and a second power cycle count representing a second power cycle count when the block is closed.

11. The memory system of claim 9, wherein the operation is performed in response to detecting that the memory system is powered on.

12. The memory system of claim 9, wherein performing the scan operation with respect to the subset of the plurality of blocks comprises: measuring a data state metric within memory cells of the subset of the plurality of blocks; and The threshold voltage shift interval corresponding to the measured value of the data state metric is identified.

13. The memory system of claim 9, wherein associating each subset of blocks with the threshold voltage shift interval comprises: Block family metadata associated with the memory device is updated, wherein the block family metadata comprises a table including a plurality of records, and wherein a record in the plurality of records associates the subset of the plurality of blocks with the threshold voltage shift interval.

14. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: Initializing a cluster of blocks associated with a memory device; storing an initial value of a power cycle count associated with the memory device; responsive to programming a block residing on the memory device, associating the block with the block family; in response to determining that the current value of the power cycle count exceeds the initial value of the power cycle count, shutting down the block cluster; and In response to determining that a time period that has elapsed since the cluster of blocks was initialized exceeds a threshold period, the cluster of blocks is closed.

15. The non-transitory computer-readable storage medium of claim 14, wherein the time period is determined based on a cumulative power-on clock associated with the memory device.

16. The non-transitory computer-readable storage medium of claim 14, wherein associating the block with the block family further comprises: Block family metadata associated with the memory device is updated, wherein the block family metadata comprises a table including a plurality of records, and wherein a record in the plurality of records associates the block with the block family.

17. The non-transitory computer-readable storage medium of claim 14, further comprising: In response to closing the block cluster, a new block cluster is initialized.

18. The non-transitory computer-readable storage medium of claim 14, further comprising: In response to initializing the block family, the block family is associated with a threshold voltage shift interval.

19. The non-transitory computer-readable storage medium of claim 14, wherein the power cycle count is incremented in response to detecting that the memory device is powered on.

20. The non-transitory computer-readable storage medium of claim 14, further comprising: initializing a low temperature and a high temperature based on a reference temperature of the memory device; in response to determining that a difference between the high temperature and the low temperature is greater than or equal to a specified threshold temperature value, shutting down the block family; receiving a second reference temperature of the memory device; in response to determining that the second reference temperature is greater than or equal to the high temperature, updating the high temperature to store the second reference temperature; and In response to determining that the second reference temperature is lower than the low temperature, the low temperature is updated to store the second reference temperature.

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