Apparatus, method and storage medium for graphics processing

Abstract

The present disclosure relates to apparatuses, methods and storage media for graphics processing. Techniques related to memory allocation for graphics surfaces are disclosed. In embodiments, graphics processing circuitry is configured to access a graphics surface based on an address allocated to the graphics surface in a surface space. First translation circuitry is configured to access one or more entries of a set of multiple translation entries for a page of the surface space (wherein the translation entries are stored using addresses in a virtual space and map pages of the surface space to the virtual space), to translate address information of the surface space to address information in the virtual space based on the one or more entries of the translation entries. The graphics processing circuitry is configured to provide an address for accessing the graphics surface based on the translation by the first translation circuitry, and second translation circuitry is configured to translate the address in the virtual space to an address in a physical space of a memory configured to store the graphics surface. The present techniques allow sparse allocation of larger graphics surfaces.

Description

[0001] This application is a divisional application of the invention patent application filed on September 4, 2020, with application number 202010923482.3, entitled "Apparatus, Method and Storage Medium for Graphics Processing". Technical Field

[0002] This disclosure relates generally to memory allocation, and more specifically to multi-level address translation of graphics surfaces. Background Technology

[0003] Graphics processors typically use surfaces, such as textures, to determine the pixel attributes of a scene being rendered. Surfaces often contain a large amount of data (e.g., for high-resolution images), so allocating memory space for surfaces in some scenes can negatively impact other processing. Attached Figure Description

[0004] Figure 1 This is a block diagram illustrating an exemplary multilayer conversion circuit configured to process addresses in surface space according to some embodiments.

[0005] Figure 2A This is an illustration showing exemplary surfaces, virtual and physical spaces according to some implementation schemes.

[0006] Figure 2B This is a diagram illustrating an exemplary surface space transformation table according to some embodiments.

[0007] Figure 3 This is a block diagram illustrating a more detailed example of a conversion circuit according to some implementation schemes.

[0008] Figure 4 This is a flowchart illustrating an exemplary method for accessing a surface using surface space according to some implementation schemes.

[0009] Figure 5 This is a block diagram illustrating an exemplary computing device that may include one or more graphics processors according to some embodiments.

[0010] Figure 6 This is a block diagram illustrating an exemplary computer-readable medium for storing circuit design information according to some embodiments. Detailed Implementation

[0011] This specification includes references to various embodiments to indicate that this disclosure is not intended to refer to a particular specific embodiment, but rather to a range of embodiments falling within the spirit of this disclosure, including the appended claims. Specific features, structures, or characteristics may be combined in any suitable manner consistent with this disclosure.

[0012] Within this disclosure, different entities (which may be referred to differently as “cells,” “circuits,” other components, etc.) may be described or claimed to be “configured to” perform one or more tasks or operations. This expression—an [entity] configured to [perform one or more tasks]—is used herein to refer to a structure (i.e., a physical thing, such as an electronic circuit). More specifically, this expression is used to indicate that the structure is arranged to perform one or more tasks during operation. A structure may be described as “configured to” perform a task even if the structure is not currently being operated. “Translation circuit configured to translate addresses” is intended to cover, for example, a circuit that performs this function during operation, even if the circuit in question is not currently being used (e.g., the circuit is not connected to electricity). Therefore, an entity described or stated as “configured to” perform a task refers to a physical thing, such as a device, circuit, memory storing program instructions executable to perform that task, etc. This phrase is not used herein to refer to intangible things.

[0013] The term "configured as" is not intended to mean "can be configured as". For example, an unprogrammed FPGA is not considered "configured as" to perform a particular function, although it may "be configurable as" to perform that function. After proper programming, the FPGA can then be configured to perform that function.

[0014] The formulation structure in the appended claims, “configured to” perform one or more tasks, is explicitly intended not to invoke 35 U.S.SC § 112(±) for that claim element. Therefore, none of the claims in this application are intended to be interpreted as having a means-plus-function element. If the applicant wishes to invoke section 112(±) during the application process, they will use the “means for” [performing a function] structure to formulate the claim element.

[0015] As used herein, the term "based on" describes one or more factors that influence the determination. This term does not exclude the possibility that additional factors may influence the determination. That is, the determination may be based solely on the specified factors or on the specified factors and other unspecified factors. Consider the phrase "A is determined based on B." This phrase specifies that B is a factor used to determine A or that B influences the determination of A. This phrase does not exclude the possibility that the determination of A may also be based on another factor such as C. This phrase is also intended to cover implementations where A is determined solely based on B. As used herein, the phrase "based on" is synonymous with the phrase "at least partially based on."

[0016] Furthermore, as used herein, the terms “first,” “second,” “third,” etc., do not necessarily imply an order of elements (e.g., chronological order). For example, references to a “first” graphic operation and a “second” graphic operation do not imply an order of graphic operations, and there is a lack of additional language to restrict the temporal relationship between these operations. In short, references such as “first,” “second,” etc., are used as designations to facilitate reference in the specification and appended claims.

[0017] Graphical surfaces, such as textures, are typically used to determine the pixel attributes of a rendered scene. For example, a graphics processor may map scene coordinates to texture coordinates and sample texels near those texture coordinates using various techniques or filters to determine pixel attributes. Some textures can include large amounts of data, such as for high-resolution textures. In the disclosed embodiments, the system is configured to use a graphics surface without allocating memory space for the entire surface. It should be noted that, for example, the surface may have three (or more) dimensions, for example, when multiple mipmaps are generated to represent different levels of detail in the texture, as is well known to those skilled in the art.

[0018] In some implementations, surfaces with sparse allocations may have their own surface spaces instead of being directly mapped to a virtual space. This surface space can be unique for a given surface, and multiple surface spaces for different surfaces can be mapped to the virtual space. In some implementations, a translation table for each sparse surface is used to map the surface space to the virtual space within sparse page particles. In some implementations, pages of the surface space are mapped to consecutive pages in the virtual space, which allows for translations using base addresses and offsets. Accesses utilizing addresses in the surface space can result in multiple translations, such as a first translation to the virtual space and a second translation to the physical space (where the second translation can be similar to other accesses starting with addresses in the virtual space). Exemplary surfaces, virtual spaces, and physical spaces will be referenced below. Figure 2A and Figure 2B A detailed discussion follows. It should be noted that in various implementations, when the surface is sparsely allocated, certain pages of the surface space may not be allocated, and accesses to those pages can be detected and appropriately handled. In various implementations, these techniques can allow the use of larger surfaces without allocating memory space for the entire surface. In some implementations, accesses to unmapped pages of a sparse surface can be detected by a first set of conversion circuitry, and the bandwidth or allocation impact on the shared data cache from these accesses can be avoided.

[0019] Figure 1This is a block diagram illustrating an example multilayer translation circuit configured to process addresses in surface space according to some embodiments. In the illustrated embodiment, the device includes processing circuitry 110, a first translation circuit 120, a second translation circuit 130, and a memory 140. In the illustrated embodiment, the first translation circuit 120 is configured to translate between addresses in surface space and addresses in virtual space, while the second translation circuit 130 is configured to translate between addresses in virtual space and addresses in physical space.

[0020] In some embodiments, processing circuitry 110 is configured to access sparsely allocated surfaces in memory 140. It should be noted that memory 140 may be part of a cache / memory hierarchy. As is well known in the art, a device can implement a virtual space larger than the actual physical space provided by memory 140. Non-limiting examples of processing circuitry 110 include a texture processing unit (TPU) or a pixel back-end (PBE). In some embodiments, sparse addressing may be available only to a portion of the processing circuitry included in the device (e.g., the functionality may be available to both the TPU and PBE, but not to other circuitry such as programmable shader pipelines). In an illustrated embodiment, processing circuitry 110 is configured to provide address information of the surface space to first translation circuitry 120 when accessing a sparsely allocated surface. This address information may, for example, include the address of a translation table for the surface space.

[0021] In the illustrated implementation, the first conversion circuit 120 is configured to receive address information in the surface space and provide the corresponding address information in the virtual space to the processing circuit 110. In some implementations, the first conversion circuit 120 is configured to provide this conversion based on a surface space conversion table 165 stored in memory 140, which can be stored using addresses in the virtual space and therefore needs to be converted to addresses in the physical space before being accessed. In some implementations, the conversion table 165 is populated by the executing graphics program. In some implementations, the first conversion circuit 120 is configured to cache the conversion table data, as referenced below. Figure 3 This will be discussed in further detail. In the illustrated embodiment, the first conversion circuit 120 is configured to issue a request and receive a response related to conversion information via the second conversion circuit 130 (e.g., based on an address accessed in the surface space conversion table 165 in virtual space). It should be noted that if a page in the surface space is not mapped, the first conversion circuit 120 may indicate this to the processing circuit 110 instead of providing address information.

[0022] In the illustrated embodiment, processing circuit 110 receives address information in the virtual space from first conversion circuit 120 and provides the address in the virtual space to second conversion circuit 130 based on the address information. For example, if the address information in the virtual space from conversion circuit 120 is an address in the virtual space for sparse pages in surface space, processing circuit 110 can generate the access address in the virtual space based on the calculated offset within surface space and the virtual address of the sparse page. In other embodiments, the address information generated by first conversion circuit 120 may specifically include the address in the virtual space to be provided to second conversion circuit 130 (e.g., in an embodiment where processing circuit 110 sends the calculated offset to conversion circuit 120).

[0023] In the illustrated embodiment, the second translation circuit 130 is configured to receive an address in virtual space and translate it into a physical address, for example, a physical address for storing data to be accessed in the graphics surface portion 155 (stored in memory 140). In some embodiments, the second translation circuit 130 is included in a memory management unit (MMU). The second translation circuit 130 can use any of a variety of suitable translation techniques to translate the address in virtual space into an address in physical space. In some embodiments, the second translation circuit 130 can implement conventional paging techniques, which can allow the use of the first translation circuit 120 in existing MMU designs. The second translation circuit 130 can store a page table in memory 140 that can be initially addressed using an address in physical space (unlike the surface space translation table 165 which is initially addressed using an address in virtual space). In the illustrated embodiment, the second translation circuit 130 provides a physical address to memory 140, which uses the physical address to read or write data (in the case of reading, in the illustrated example, the second translation circuit 130 provides the read data to processing circuit 110 and can provide a completion signal for writing).

[0024] In some implementations, processing circuitry 110 is also configured to access conventionally allocated surfaces within the virtual space. A surface may not be allocated its own surface space, but rather allocated directly within the virtual space. For example, control information may indicate whether a surface is sparsely allocated. When accessing a surface that is not sparsely allocated, processing circuitry 110 can directly provide the address in the virtual space to second translation circuitry 130 without using first translation circuitry 120.

[0025] Given that the graphics program can sparsely allocate surfaces (e.g., providing mapping only for a portion of the pages in surface space), the address information from processing circuitry 110 to first conversion circuitry 120 can correspond to pages not mapped by surface space conversion table 165. In this case, first conversion circuitry 120 can provide processing circuitry 110 with a signal indicating a lack of mapping. Other circuitry or the executing graphics program can then take various actions based on this indication. For example, if processing circuitry 110 is a texture processing unit, it can filter unmapped texels with a constant color and send a negative acknowledgment (NACK) to the programmable shader executing the graphics program. The shader can then take various actions, such as mapping the requested page (e.g., when the activity count indicates that the page has been accessed frequently, as discussed in detail below), accessing a lower-resolution portion of the surface (e.g., another mipmap level), etc. In some embodiments, the pixel backend can terminate writing to unmapped addresses.

[0026] It should be noted that although the various embodiments disclosed herein involve the allocation of graphics surfaces, the disclosed techniques can be used for a variety of other data structures, whether or not related to graphics; graphics surfaces are included for illustrative purposes and are not intended to limit the scope of this disclosure. Furthermore, in addition to or instead of a graphics processor, the disclosed techniques can be implemented by other types of processors such as a central processing unit.

[0027] Figure 2A This is an illustration of an exemplary address space according to some embodiments. In the illustrated embodiment, the system implements a virtual space 210, multiple surface spaces 220A to 220N, and a physical space 230. In some embodiments, mapping surface spaces 220 within the virtual space 210 can provide the benefits of the virtual space (e.g., physical space cannot be accessed outside of the virtual-to-physical mapping) while allowing for less trusted sparse surface allocations. Note that the system can use addresses in the virtual space 210 to store translation tables for each surface space 220 (and these addresses are translated into addresses in the physical space 230 for actual storage), and the system can use addresses in the physical space 230 to store page tables for the virtual space 210.

[0028] Figure 2BThis is an illustration of an exemplary surface space conversion table according to some embodiments. In the illustrated embodiment, table 165 includes multiple entries 250A to 250N and corresponding activity count fields 260A to 260N. In some embodiments, an entry 250 exists for each page of surface space 220. In some embodiments, each entry 250 provides an indication of a mapping between surface space pages and virtual space pages, or the absence of a mapping for surface space pages. Note that in embodiments where surface space and virtual space have different page sizes, the entry may indicate a mapping between multiple surface space pages and one virtual space page, or vice versa. In some embodiments, each entry 250 includes a field indicating whether a page is mapped. Conversion circuitry can access the appropriate entry in table 165 based on a requested address in surface space 220 (e.g., based on the base address field of the surface space and a determined offset within the space).

[0029] In some implementations, the activity count field 260 is configured to store an activity count indicating the number of attempts to access a corresponding page in the surface space. In some implementations, the graphics program can use these counts to make decisions about which pages in the surface space are mapped or unmapped. It should be noted that the activity count may be updated based on requests to access a page, even if that page is not mapped. Furthermore, the activity count can be maintained based on accesses of various granularities. For example, accesses of a threshold number of bytes can be guaranteed to increment the corresponding activity count, but smaller accesses can also cause increments, for example, based on caching behavior in a particular implementation.

[0030] In some implementations, the data stored in translation table 165 is interleaved, such as the address of the first part of the mapping following the base address of the table, followed by the address of the corresponding activity count, and then the address of another part of the mapping. As mentioned above, the base address of table 165 may be an address in virtual space 21O.

[0031] Figure 3 This is a block diagram illustrating a more detailed example of a conversion circuit according to some embodiments. Note that it has... Figure 1 Components with the same number can be referenced as above. Figure 1 The configuration is as discussed. In the example shown, the device includes processing circuitry 110, other processing circuitry 322, sparse level 1 (L1) cache 320, sparse level 2 (L2) cache 325, L2 data cache 380, second conversion circuitry 130, and memory 140.

[0032] Other processing circuitry 322 is shown to illustrate that the sparse conversion circuitry can be shared by multiple processing circuits, such as a texture processing unit, a pixel backend, etc. In various embodiments, the sparse conversion circuitry can be configured to translate the address of any client circuit in a suitable number of client circuits.

[0033] In the illustrated implementation, the translation circuitry configured to translate addresses from surface space to virtual space includes multiple cache levels 320 and 325. In some implementations, both the sparse L1 cache 320 and the sparse L2 cache 325 are configured to store entries from the surface space translation table 365. The sparse L2 cache 325 may be a larger cache configured to cache more translation entries than the sparse L1 cache 320.

[0034] In some implementations, the address in the surface space includes the page base address, offset, and page size. In some implementations, processing circuitry 110 sends the page address in the surface space to sparse L1 cache 320 to determine whether the page is mapped. In other implementations, processing circuitry 110 determines the translation table entry for the accessed page and sends the address of the translation table entry in the virtual space to sparse L1 cache 320. In some implementations, the L1 cache includes control circuitry configured to determine the address in the virtual space based on page table entry 250. In some implementations, this includes first determining the virtual space address of the corresponding page table entry 250, determining whether the entry is cached (e.g., using a portion of the virtual space address as a tag), and if the entry is cached, determining the address of the sparse page in the virtual space based on the content of page table entry 250. If page table entry 250 is not cached in sparse L1 cache 320, the control circuitry can send a request to sparse L2 cache 325. If a hit occurs, the sparse L2 cache can return the entry; otherwise, if a miss occurs, the surface space translation table 365 is accessed to attempt to retrieve the page table entry. In the illustrated embodiment, if a mapping exists, cache 320 returns the page address in virtual space, which processing circuitry 110 can use to generate an address in virtual space (e.g., based on a calculated offset and the received address). In other embodiments, L1 cache 320 can send and receive address information at other granularities, such as including a specific address for the request from processing circuitry 110.

[0035] In some implementations, accesses to the sparse L2 cache 325 rarely miss, for example, due to its size and prefetching technique. For instance, the system can prefetch nearby page table entries 250 within the 2D range of the surface into the sparse L2 cache 325 before requesting the corresponding address. Therefore, the translation circuitry can generate addresses in virtual space even without accessing the translation table in memory 140, even for the first access to a page in the surface space. In some implementations, this can advantageously allow sparse translations with low latency, e.g., misses only on the first access to the 2D range of the surface.

[0036] In the illustrated implementation, the system includes an L2 data cache 380 that operates based on addresses in virtual space. The L2 data cache 380 can be a cache shared by multiple blocks, such as a programmable shader, texture processing unit, etc. A sparse L2 cache 325 can access the surface space translation table 365 directly via the second translation circuit 130 or via the L2 data cache 380, as shown in the illustrated example. Generally, using sideband sparse translation circuitry (e.g., caches 320 and 325) to map pages in surface space avoids interference with the L2 data cache 380 used for other operations.

[0037] In the illustrated implementation, the control circuitry in the sparse L1 cache 320 is also configured to maintain an activity counter 310 for the cached translation entries. The activity counter can be maintained at any of a variety of suitable data granularities. In some implementations, for each request in the surface space, the sparse L1 cache 320 increments one or more corresponding activity counters. When the system evicts an entry from the sparse L1 cache 320, the system can store the corresponding activity counter in the sparse L2 cache 325 or the surface space translation table 365. It should be noted that the various caches discussed herein can be implemented using various cache implementation methods, including using different associativity, write-back or write-through techniques, different replacement strategies, etc.

[0038] In the illustrated embodiment, memory 140 also stores page table 385, which can be addressed in physical space and is used by second translation circuit 130 to translate addresses in virtual space into addresses in physical space.

[0039] Exemplary methods

[0040] Figure 4 This is a flowchart illustrating an exemplary method for accessing a surface using surface space according to some implementation schemes. Figure 4The methods shown can be used in conjunction with any of the computer circuits, systems, devices, components, or parts disclosed herein. In various embodiments, some of the method elements shown may be executed concurrently in a different order than that shown, or may be omitted. Additional method elements may also be executed as needed.

[0041] At 410, in the illustrated embodiment, the graphics processing circuitry accesses the graphics surface based on an address allocated to the graphics surface in surface space. In some embodiments, a portion of the surface space is mapped to a virtual space, which can advantageously provide security for the virtual space while allowing for sparse allocation of surfaces. In some embodiments, the surface space is dedicated to the graphics surface, such that other surfaces do not use the surface space. In some embodiments, the graphics surface comprises elements of two or more dimensions. For example, a surface may be a set of mipmaps for textures, representing textures at different levels of detail. In other cases or embodiments, the surface may be one-dimensional or two-dimensional.

[0042] At 420, in the illustrated embodiment, the first translation circuit accesses one or more entries from a set of multiple translation entries for pages in the surface space, wherein these translation entries are stored using addresses in the virtual space, and maps pages in the surface space to the virtual space. It should be noted that the first translation circuit may maintain all or part of the entries in this set internally (e.g., using one or more dedicated caches), or it may maintain these entries externally (e.g., in memory 140 or some other memory). Figure 2B Page table entry 250 is an example of a transformation entry. In some embodiments, this set of transformation entries can be configured by graphical instructions executed by the device. For example, a graphical program can assign or modify page table entry 250. In some embodiments, page table entries include information indicating that pages in surface space are not mapped, such as whether the surface is sparsely allocated.

[0043] At 430, in the illustrated embodiment, the first conversion circuit converts the address information of the surface space into address information in the virtual space based on one or more entries in the conversion entries. For example, the address information of the surface space may specify: (1) the base address of the conversion table for the surface space in the virtual space, and (2) the calculated offset within the surface space. This can be used to generate the address of the appropriate conversion entry in the table in the virtual space. The conversion entry may provide the address of a sparse page in the virtual space, which can be combined with the calculated offset within the surface space to generate a virtual address for accessing the surface. It should be noted that in different embodiments, different parts of the calculation in this example may be divided between the processing circuit 110 and the conversion circuit 120. For example, in one embodiment, the processing circuit 110 may send address information having both the calculated offset and the base address in the virtual space of the conversion table, or in another embodiment, the address of the conversion entry in the virtual space may be calculated and sent.

[0044] At 440, in the illustrated embodiment, the graphics processing circuitry provides an address for accessing the graphics surface based on the conversion performed by the first conversion circuitry. For example, the graphics processing circuitry may provide an address for access in virtual space to the second conversion circuitry 130.

[0045] At 450, in the illustrated embodiment, the second conversion circuit translates the address in the virtual space into an address in the physical space of the memory configured to store the graphics surface. The system can then use the address in the physical space to access the data of the graphics surface.

[0046] In some embodiments, the first translation circuitry is configured to maintain the set of multiple translation entries in memory (e.g., memory implementing physical space) and to cache at least a portion of the set of multiple translation entries in a cache. In some embodiments, the first translation circuitry uses multiple cache levels for the translation entries, such as a first-level cache and a second-level cache, wherein the second-level cache is configured to cache data for a larger number of translation entries than the first-level cache. In some embodiments, the system is configured to prefetch data for said one or more translation entries into the second-level cache before receiving an access request corresponding to said one or more translation entries.

[0047] In some implementations, graphics circuitry 1 is configured to access other graphics surfaces that do not require multi-layer translation. For example, graphics processing circuitry can access another graphics surface stored in memory using an address in virtual space without using a first conversion circuit, and a second conversion circuit can translate an address in virtual space into an address in physical space.

[0048] Exemplary device

[0049] Now for reference Figure 5 A block diagram illustrating an exemplary embodiment of device 500 is shown. In some embodiments, the components of device 500 may be included within a system-on-a-chip. In some embodiments, device 500 may be included in a mobile device that may be battery-powered. Therefore, the power consumption of device 500 may be an important design consideration. In the illustrated embodiment, device 500 includes a structure 510, a computing complex 520, an input / output (I / O) bridge 550, a cache / memory controller 545, a graphics unit 570, and a display unit 565. In some embodiments, in addition to and / or replacing the components shown, device 500 may include other components (not shown), such as video processor encoders and decoders, image processing or recognition elements, computer vision elements, etc.

[0050] Structure 510 may include various interconnects, buses, MUXs, controllers, etc., and may be configured to facilitate communication between various components of device 500. In some embodiments, portions of structure 510 may be configured to implement various different communication protocols. In other embodiments, structure 510 may implement a single communication protocol, and components coupled to structure 510 may internally switch from a single communication protocol to other communication protocols.

[0051] In the illustrated embodiments, computing complex 520 includes a bus interface unit (BIU) 525, a cache 530, and cores 535 and 540. In various embodiments, computing complex 520 may include a variety of numbers of processors, processor cores, and / or caches. For example, computing complex 520 may include one, two, or four processor cores, or any other suitable number. In one embodiment, cache 530 is a set-associative L2 cache. In some embodiments, cores 535 and / or 540 may include internal instruction and / or data caches. In some embodiments, coherence units (not shown) in architecture 510, cache 530, or elsewhere in device 500 may be configured to maintain coherence between the various caches of device 500. BIU 525 may be configured to manage communication between computing complex 520 and other elements of device 500. Processor cores (such as cores 535 and 540) may be configured to execute instructions of a specific instruction set architecture (ISA) that may include operating system instructions and user application instructions.

[0052] The cache / memory controller 545 can be configured to manage data transfer between the structure 510 and one or more caches and / or memories. For example, the cache / memory controller 545 can be coupled to an L3 cache, which in turn can be coupled to system memory. In other embodiments, the cache / memory controller 545 can be directly coupled to memory. In some embodiments, the cache / memory controller 545 may include one or more internal caches.

[0053] As used herein, the term "coupled to" can indicate one or more connections between elements, and coupling can include intermediate elements. For example, in Figure 5 In this context, the graphics unit 570 can be described as being "coupled" to memory via structure 510 and cache / memory controller 545. In contrast, in... Figure 5 In the exemplary implementation, the graphics unit 570 is "directly coupled" to the structure 510 because there are no intermediate elements.

[0054] The graphics unit 570 may include one or more processors and / or one or more graphics processing units (GPUs). For example, the graphics unit 570 may receive graphics-oriented instructions, such as... Metal or Instructions. The graphics unit 570 can execute dedicated GPU instructions or perform other operations based on received graphics-oriented instructions. The graphics unit 570 is typically configured to process large blocks of data in parallel and can build an image in a frame buffer for output to a display. The graphics unit 570 may include transformation, lighting, triangle, and / or rendering engines in one or more graphics processing pipelines. The graphics unit 570 can output pixel information for displaying the image. In various embodiments, the programmable shader 575 may include highly parallel execution cores configured to execute graphics programs, which may include pixel tasks, vertex tasks, and computation tasks (which may be graphics-dependent or not).

[0055] In some implementation schemes, the above references Figures 1 to 4 The various circuits discussed are included in the graphic unit 570.

[0056] Display unit 565 can be configured to read data from a frame buffer and provide a stream of pixel values ​​for display. In some embodiments, display unit 565 can be configured to display a pipeline. Additionally, display unit 565 can be configured to blend multiple frames to produce an output frame. Furthermore, display unit 565 may include one or more interfaces for coupling to a user display (e.g., a touchscreen or an external display). Or embedded display port (eDP)).

[0057] I / O bridge 550 may include various components configured to implement, for example, Universal Serial Bus (USB) communication, security, audio, and / or low-power always-on functionality. For example, I / O bridge 550 may also include interfaces such as pulse-width modulation (PWM), general-purpose input / output (GPIO), serial peripheral interface (SPI), and / or internal integrated circuit (I2C). Various types of peripheral devices and equipment can be coupled to device 500 via I / O bridge 550.

[0058] Exemplary computer-readable media

[0059] Various exemplary circuits have been described in detail above in this disclosure. It is intended that this disclosure cover not only embodiments including such circuit systems, but also computer-readable storage media including design information specifying such circuit systems. Therefore, this disclosure is intended to support claims that cover not only means including the disclosed circuit systems, but also storage media specifying circuit systems in a format recognized by a manufacturing system configured to generate hardware (e.g., integrated circuits) including the disclosed circuit systems. Claims regarding such storage media are intended to cover entities that, for example, generate circuit designs but do not themselves manufacture such designs.

[0060] Figure 6 This is a block diagram illustrating an exemplary non-transitory computer-readable storage medium for storing circuit design information according to some embodiments. In the illustrated embodiment, a semiconductor manufacturing system 620 is configured to process design information 615 stored on a non-transitory computer-readable medium 610 and manufacture an integrated circuit 630 based on the design information 615.

[0061] The nontransitory computer-readable storage medium 610 may include any device of a variety of suitable types of memory devices or storage devices. The nontransitory computer-readable storage medium 610 may be an installation medium, such as a CD-ROM, floppy disk, or magnetic tape device; computer system memory or random access memory such as DRAM, DDR RAM, SRAM, EDO RAM, Rambus RAM, etc.; non-volatile memory such as flash memory, magnetic media, such as hard disk drives or optical storage devices; registers, or other similar types of memory elements. The nontransitory computer-readable storage medium 610 may also include other types of nontransitory memory or combinations thereof. The nontransitory computer-readable storage medium 610 may include two or more memory media that may reside in different locations, such as different computer systems connected via a network.

[0062] Design information 615 can be specified using any of a variety of suitable computer languages, including hardware description languages ​​such as, but not limited to, VHDL, Verilog, SystemC, SystemVerilog, RHDL, M, MyHDL, etc. Design information 615 can be used by semiconductor manufacturing system 620 to manufacture at least a portion of integrated circuit 630. The format of design information 615 can be recognized by at least one semiconductor manufacturing system 620. In some embodiments, design information 615 may also include one or more cell libraries specifying the synthesis and / or layout of integrated circuit 630. In some embodiments, the design information is specified wholly or partially in the form of a netlist specifying cell library elements and their connectivity. Design information 615 acquired separately may or may not include sufficient information for manufacturing the corresponding integrated circuit. For example, design information 615 may specify circuit elements to be manufactured but not their physical layout. In this case, design information 615 may need to be combined with layout information to actually manufacture the specified circuit.

[0063] In various implementations, integrated circuit 630 may include one or more custom macrocells, such as memory, analog or mixed-signal circuitry, etc. In this case, design information 615 may include information associated with the included macrocells. Such information may include, but is not limited to, a circuit diagram capture database, mask design data, behavioral models, and device or transistor-level netlists. As used herein, mask design data may be formatted according to a Graphical Data System (GDSII) or any other suitable format.

[0064] The semiconductor manufacturing system 620 may include any of the various suitable elements configured to manufacture integrated circuits. This may include, for example, elements for depositing semiconductor material (e.g., on a wafer that may include a mask), removing material, changing the shape of the deposited material, modifying the material (e.g., by doping the material or modifying the dielectric constant using ultraviolet treatment), and so on. The semiconductor manufacturing system 620 may also be configured to perform various tests on the manufactured circuits for proper operation.

[0065] In various embodiments, integrated circuit 630 is configured to operate according to a circuit design specified in design information 615, which may include performing any of the functionalities described herein. For example, integrated circuit 630 may include Figure 1 , Figure 3 and Figure 5 Any of the various components shown herein. Additionally, integrated circuit 630 can be configured to perform the various functions described herein in conjunction with other components. Furthermore, the functionality described herein can be performed by multiple interconnected integrated circuits.

[0066] As used herein, the phrase “design information specifying the design of a circuit configured to…” does not imply that the circuit under consideration must be manufactured to meet the elements. Rather, the phrase indicates that the design information describes a circuit that, when manufactured, will be configured to perform the indicated action or will include the specified components.

[0067] ***

[0068] Although specific embodiments have been described above, these embodiments are not intended to limit the scope of this disclosure, even where only a single embodiment is described with respect to a particular feature. The examples of features provided in this disclosure are intended to be illustrative and not limiting, unless otherwise stated. The foregoing description is intended to cover such alternatives, modifications, and equivalents, which will be apparent to those skilled in the art to the effectiveness of this disclosure.

[0069] The scope of this disclosure includes any feature or combination of features, or any generalization thereof, disclosed herein (expressly or implicitly), whether or not it alleviates any or all the problems addressed herein. Therefore, new claims may be made for any such combination of features during the proceedings of this patent application (or a patent application claiming priority thereto). Specifically, referring to the appended claims, features of dependent claims may be combined with features of independent claims, and features from the respective independent claims may be combined in any suitable manner rather than solely by the specific combinations listed in the appended claims.

Claims

1. An apparatus comprising: The graphics processing circuitry is configured to access the graphics surface using an address in the surface space allocated to the graphics surface. A first conversion circuit is configured to convert an address in the surface space to an address in the virtual space based on one or more conversion entries in a conversion table that maps pages in the surface space to pages in the virtual space, wherein the conversion table is configured to initially map only a portion of the surface space to the virtual space. as well as The second conversion circuit is configured to convert the address in the virtual space into an address in the physical space of the memory configured to store the graphics surface.

2. The apparatus of claim 1, wherein the first conversion circuit is configured to provide the address in the virtual space to the graphics processing circuit, and the graphics processing circuit is configured to use the address in the virtual space to access a data cache; and The second conversion circuit is configured to convert the address in the virtual space to the address in the physical space in response to a miss in the data cache.

3. The apparatus of claim 1, wherein the conversion table is configurable by graphics instructions executed by the graphics processing circuitry.

4. The apparatus of claim 1, wherein the graphics processing circuitry is configured to maintain activity count information based on access to portions of the surface space; and The graphics processing circuitry is configured to map previously unmapped pages of the surface space to the virtual space based on activity count information associated with the pages of the surface space.

5. The apparatus of claim 1, wherein the graphics processing circuitry is configured to store the translation table in the memory.

6. The apparatus of claim 5, wherein the first conversion circuit is configured to cache at least a portion of the conversion table in a cache dedicated to caching conversion information for surface space.

7. The apparatus of claim 6, wherein the graphics processing circuitry is configured to prefetch data for the one or more transformation entries into the cache before receiving an access request corresponding to one or more transformation entries.

8. The apparatus of claim 1, wherein the graphics processing circuitry is configured to assign different surface spaces to different graphic surfaces and store conversion entries for corresponding groups of the different surface spaces.

9. The apparatus of claim 1, wherein the graphics processing circuitry is further configured to use an address in the virtual space to access another graphics surface stored in the memory, without using the first conversion circuitry.

10. The apparatus of claim 1, wherein the apparatus is a computing device, the computing device further comprising: Central processing unit; and monitor.

11. A non-transitory computer-readable medium having instructions stored thereon, the instructions being executable by a computing device to perform operations, the operations including: Provide the graphics processing circuitry of the computing device with addresses in the surface space allocated to the graphics surface; Configure one or more conversion entries in a conversion table that maps pages in the surface space to virtual space, wherein the initial configuration maps only a portion of the surface space to the virtual space; as well as Access addresses in the physical space of a memory configured to store the graphic surface, wherein the addresses in the physical space are generated by the computing device by translating addresses in the virtual space, and wherein the addresses in the virtual space are generated by the computing device by translating addresses in the surface space based on one or more translation entries.

12. The non-transitory computer-readable medium of claim 11, wherein the operation further comprises: Access is based on activity count information related to accesses to portions of the surface space; as well as Based on the activity count information associated with the pages in the surface space, previously unmapped pages in the surface space are mapped to the virtual space.

13. The non-transitory computer-readable medium of claim 11, wherein the operation further comprises: Different surface spaces are assigned to different graphic surfaces, and conversion entries for the corresponding groups of said different surface spaces are stored.

14. A non-transitory computer-readable storage medium storing design information thereon, the design information specifying at least a portion of a design of a hardware integrated circuit in a format recognizable by a semiconductor manufacturing system, the semiconductor manufacturing system being configured to use the design information to manufacture the circuit according to the design, wherein the design information specifying the circuit includes: The graphics processing circuitry is configured to access the graphics surface using an address in the surface space allocated to the graphics surface. A first conversion circuit is configured to convert the address in the surface space to an address in the virtual space based on one or more conversion entries in a conversion table that maps pages in the surface space to pages in the virtual space, wherein the conversion table is configured to initially map only a portion of the surface space to the virtual space. as well as The second conversion circuit is configured to convert the address in the virtual space into an address in the physical space of the memory configured to store the graphics surface.

15. The non-transitory computer-readable storage medium of claim 14, wherein the first translation circuit is configured to provide the address in the virtual space to the graphics processing circuit, and the graphics processing circuit is configured to use the address in the virtual space to access a data cache; and The second conversion circuit is configured to convert the address in the virtual space to the address in the physical space in response to a miss in the data cache.

16. The non-transitory computer-readable storage medium of claim 14, wherein the translation table is configurable by graphics instructions executed by the graphics processing circuitry.

17. The non-transitory computer-readable storage medium of claim 14, wherein the graphics processing circuitry is configured to maintain activity count information based on access to portions of the surface space; and The graphics processing circuitry is configured to map previously unmapped pages of the surface space to the virtual space based on activity count information associated with the pages of the surface space.

18. The non-transitory computer-readable storage medium of claim 14, wherein the graphics processing circuitry is configured to store the translation table in the memory.

19. The non-transitory computer-readable storage medium of claim 18, wherein the first conversion circuit is configured to cache at least a portion of the conversion table in a cache dedicated to caching conversion information for surface space; and The graphics processing circuitry is configured to prefetch data for one or more transformation entries into the cache before receiving an access request corresponding to one or more transformation entries.

20. The non-transitory computer-readable storage medium of claim 18, wherein the graphics processing circuitry is configured to assign different surface spaces to different graphics surfaces and store conversion entries for corresponding groups of the different surface spaces.

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