Display device and method of driving a display device

Abstract

A display device and a method of driving the display device are provided. The display device includes a display panel including a first display area and a second display area surrounding the first display area, wherein first pixels having a first size are disposed in the first display area and second pixels having a second size are disposed in the second display area, a gate driver applying a gate signal to a gate line, a data driver applying a data voltage to a data line, and a timing controller controlling the gate driver and the data driver. The gate line includes a first gate line and a second gate line, the first gate line being connected to both the first pixels and the second pixels, and the second gate line being connected only to the second pixels. The data line includes a first data line and a second data line, the first data line not transmitting the data voltage to the second pixels connected with the second gate line, and the second data line transmitting the data voltage to the second pixels connected with the second gate line.

Description

Technical Field

[0001] Embodiments of the invention relate to a display device and a method of driving the display device. More specifically, embodiments of the invention relate to a display device configured to expand the display area while maintaining a bezel portion on a display panel, and a method of driving the display device. Background Technology

[0002] Typically, a display device may include a display panel and a display panel driver. The display panel may include pixels and can display an image corresponding to input image data using these pixels. The display panel may be connected to the display panel driver via gate lines and data lines. The display panel driver may include a gate driver, a data driver, and a timing controller. The gate driver provides gate signals to the display panel via gate lines, the data driver provides data voltages to the display panel via data lines, and the timing controller controls the gate driver and the data driver.

[0003] In display devices, the area occupied by the drive circuitry, including in the display panel driver, is typically located within the bezel portion, thus limiting the size of the display area on the display panel where images are displayed. However, in such display devices, the drive circuitry is an essential component, making it impossible to completely eliminate the bezel portion. Summary of the Invention

[0004] Recently, pixel-on-driver (POD) technology has been proposed to expand the display area while maintaining the bezel portion by adding a peripheral display area on top of the driver circuit. However, in this case, coupling occurs between the data voltages because separate data voltages are applied to the peripheral display area of ​​the display device, and vertical crosstalk occurs due to electrical interference between the data voltages.

[0005] Embodiments of the invention provide a display device that improves display quality by minimizing electrical interference between data voltages applied to a main display area and a peripheral display area, respectively.

[0006] Embodiments of the invention also provide a method for driving a display device that improves display quality by minimizing electrical interference between data voltages.

[0007] In an embodiment of the display device according to the invention, the display device includes: a display panel including a first display area and a second display area surrounding the first display area, wherein a first pixel having a first size is disposed in the first display area, and a second pixel having a second size different from the first size is disposed in the second display area; a gate driver for applying gate signals to gate lines of the display panel; a data driver for applying data voltages to data lines of the display panel; and a timing controller for controlling the gate driver and the data driver. In such an embodiment, the gate lines include a first gate line and a second gate line, the first gate line being connected to both the first pixel and the second pixel, and the second gate line being connected only to the second pixel. In such an embodiment, the data lines include a first data line and a second data line, the first data line not transmitting data voltages to the second pixel connected to the second gate line, and the second data line transmitting data voltages to the second pixel connected to the second gate line. In such an embodiment, when a gate signal is applied to the second gate line, a pseudo-data voltage is applied to the first data line.

[0008] In one embodiment, the display device may further include a data corrector that generates correction data based on input image data and a lookup table.

[0009] In an embodiment, the data corrector may include: a display area determiner that identifies first image data to be displayed on a first display area and second image data to be displayed on a second display area based on input image data; a lookup table that stores arrangement information of the first gate line and the second gate line; and a correction data generator that generates correction data by using the lookup table.

[0010] In one embodiment, the timing controller can receive correction data from the data corrector and generate a pseudo data signal based on the correction data.

[0011] In one embodiment, when a gate signal is applied to the second gate line, the data driver can apply a pseudo-data voltage generated based on the pseudo-data signal to the first data line.

[0012] In an embodiment, multiple second data lines may be provided, and the pseudo data voltage may be the same as the data voltage applied to the second data line closest to the first data line.

[0013] In an embodiment, the pseudo data voltage may be the same as the data voltage applied to the first data line in the previous frame.

[0014] In an embodiment, the pseudo data voltage may have a voltage level corresponding to the intermediate value of the data voltage applied to the second data line.

[0015] In an embodiment, the pseudo data voltage may have a voltage level between the voltage level of the data voltage corresponding to the black image and the voltage level of the data voltage corresponding to the white image.

[0016] In an embodiment, the second display area may include: a corner display area extending from the corner of the second display area; and a middle display area located between the first display area and the corner display area.

[0017] In an embodiment of the method for driving a display device according to the invention, the method includes the steps of: applying a gate signal to a first gate line connected to both a first pixel and a second pixel; applying a gate signal to a second gate line connected only to the second pixel; and applying a data voltage to a data line. The first pixel may have a first size and be disposed in a first display area. In such an embodiment, the second pixel has a second size different from the first size and is disposed in a second display area surrounding the first display area. In such an embodiment, the data line includes a first data line and a second data line, the first data line not transmitting a data voltage to the second pixel connected to the second gate line, and the second data line transmitting a data voltage to the second pixel connected to the second gate line. In such an embodiment, the step of applying a data voltage to the data line includes: applying a dummy data voltage to the first data line when the gate signal is applied to the second gate line.

[0018] In an embodiment, the method may further include the following step: generating correction data based on input image data and a lookup table.

[0019] In an embodiment, the step of generating correction data may include: identifying first image data to be displayed on a first display area and second image data to be displayed on a second display area based on input image data; and generating correction data by using a lookup table, in which arrangement information of the first gate line and the second gate line is stored.

[0020] In an embodiment, the method may further include the step of generating a pseudo-data signal based on the correction data.

[0021] In an embodiment, the step of applying a data voltage to a data line may further include: generating a pseudo data voltage based on a pseudo data signal.

[0022] In an embodiment, multiple second data lines may be provided, and the pseudo data voltage may be the same as the data voltage applied to the second data line closest to the first data line.

[0023] In an embodiment, the pseudo data voltage may be the same as the data voltage applied to the first data line in the previous frame.

[0024] In an embodiment, the pseudo data voltage may have a voltage level corresponding to the intermediate value of the data voltage applied to the second data line.

[0025] In an embodiment, the pseudo data voltage may have a voltage level between the voltage level of the data voltage corresponding to the black image and the voltage level of the data voltage corresponding to the white image.

[0026] In an embodiment, the second display area may include: a corner display area extending from the corner of the second display area; and a middle display area located between the first display area and the corner display area.

[0027] In an embodiment of the invention, the display device may apply a dummy data voltage to the first data line to minimize electrical interference between data voltages.

[0028] Therefore, in such an embodiment, the display device can reduce coupling between data voltages and prevent vertical crosstalk caused by electrical interference. As a result, the display device can improve the reliability of display quality by minimizing the degradation of the image quality displayed on the display panel. Attached Figure Description

[0029] Figure 1 This is a block diagram illustrating a display device according to an embodiment of the invention.

[0030] Figure 2 It is shown that it includes Figure 1 A diagram illustrating an embodiment of a display panel in a display device.

[0031] Figure 3 yes Figure 2 An enlarged view of a corner section of the display panel.

[0032] Figure 4 It is shown that it includes Figure 1 A block diagram of an embodiment of a data corrector in a display device.

[0033] Figure 5 This illustrates an embodiment. Figure 1 A flowchart of the operation of the display device.

[0034] Figure 6 This illustrates an alternative embodiment. Figure 1 A flowchart of the operation of the display device.

[0035] Figure 7 This is a block diagram illustrating an electronic device according to an embodiment of the invention.

[0036] Figure 8 It is shown that Figure 7 The diagram shows an embodiment of an electronic device implemented as a smartphone. Detailed Implementation

[0037] The invention will now be described more fully below with reference to the accompanying drawings, in which various embodiments are illustrated. However, the invention may be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Similar reference numerals throughout denote similar elements.

[0038] It will be understood that when an element is referred to as being "on" another element, the element may be directly on the other element, or an intermediary element may exist between the element and the other element. Conversely, when an element is referred to as being "directly on" another element, there is no intermediary element.

[0039] It will be understood that although the terms “first,” “second,” “third,” etc., may be used herein to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Therefore, without departing from the teaching herein, “first element,” “first component,” “first region,” “first layer,” or “first part” discussed below may be referred to as a second element, second component, second region, second layer, or second part.

[0040] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, unless the context clearly indicates otherwise, “a,” “an,” “the,” and “at least one” do not indicate a limitation of quantity but are intended to include both the singular and the plural. For example, unless the context clearly indicates otherwise, “element” has the same meaning as “at least one element.” “At least one” will not be construed as limited to “a” or “an.” “Or” means “and / or.” As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items. It will also be understood that when the terms “comprising” and / or variations thereof or “including” and / or variations thereof are used in this specification, they indicate the presence of the stated features, areas, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, areas, integrals, steps, operations, elements, components, and / or groups thereof.

[0041] Furthermore, relative terms (such as "below" or "bottom" and "above" or "top") may be used here to describe the relationship between one element and another shown in the figure. It will be understood that relative terms are intended to encompass different orientations of the device besides those depicted in the figure. For example, if a device in a figure is flipped, an element described as being "below" the other element will subsequently be oriented to be "above" the other element. Thus, depending on the specific orientation in the figure, the term "below" can encompass both "above" and "below". Similarly, if a device in a figure is flipped, an element described as being "below" or "under" the other element will subsequently be oriented "above" the other element. Thus, the terms "below" or "under" can encompass both "above" and "below".

[0042] Unless otherwise defined, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in a general dictionary) shall be interpreted as having the same meaning as they have in the relevant field and in the context of this disclosure, and shall not be interpreted in an idealized or overly formal sense, unless expressly defined herein.

[0043] The embodiments described herein should not be construed as being limited to the specific shapes of the regions shown herein, but will include, for example, shape deviations caused by manufacturing processes. For instance, regions shown or described as flat may generally have rough and / or non-linear characteristics. Furthermore, the sharp corners shown may be rounded (rounded). Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to show the precise shapes of the regions, nor are they intended to limit the scope of the present claims.

[0044] In the following description, embodiments of the invention will be described in detail with reference to the accompanying drawings.

[0045] Figure 1 This is a block diagram illustrating a display device 10 according to an embodiment. Figure 2 It is shown that it includes Figure 1 A diagram of an embodiment of the display panel 100 in the display device 10. Figure 3 yes Figure 2 An enlarged view of a corner portion 110 of the display panel 100.

[0046] Reference Figures 1 to 3 An embodiment of the display device 10 may include a display panel 100 and a display panel driver 120. The display panel driver 120 may include a timing controller 200, a data corrector 210, a gate driver 300, a gamma reference voltage generator 400, and a data driver 500.

[0047] The display panel 100 may include a display portion for displaying images and a peripheral portion disposed adjacent to the display portion.

[0048] The display panel 100 may include pixels P to display an image corresponding to the input image data IMG. Gate lines GL may extend along a first direction D1, and data lines DL may extend along a second direction D2 that intersects the first direction D1.

[0049] In an embodiment, such as Figure 2 As shown, the display portion of the display panel 100 for displaying images may include a main display area MA and a peripheral display area SA. The main display area MA may be surrounded by the peripheral display area SA. A first pixel PX1 having a first size may be disposed in the main display area MA, and a second pixel PX2 having a second size different from the first size may be disposed in the peripheral display area SA. In such an embodiment, the number of pixels per unit inch (ppi) in the peripheral display area SA may be different from the number of pixels per unit inch in the main display area MA.

[0050] At least one panel driving circuit may be disposed in the lower circuitry layer of the peripheral display area SA. The panel driving circuit disposed in the lower circuitry layer of the peripheral display area SA may include a timing controller 200. The panel driving circuit disposed in the lower circuitry layer of the peripheral display area SA may include a gate driver 300. The panel driving circuit disposed in the lower circuitry layer of the peripheral display area SA may include a data driver 500. The panel driving circuit disposed in the lower circuitry layer of the peripheral display area SA may include a gamma reference voltage generator 400. Therefore, in such an embodiment, compared to a conventional display panel, the display panel 100 can provide a wider display area by displaying an image on the peripheral display area SA while maintaining the bezel portion.

[0051] The timing controller 200 can receive input image data IMG and input control signal CONT from an external device (not shown). In one embodiment, for example, the input image data IMG received from the external device may include red image data, green image data, and blue image data. According to an embodiment, the input image data IMG may also include white image data. In an alternative embodiment, for example, the input image data IMG may include magenta image data, yellow image data, and cyan image data. In an embodiment, the input control signal CONT received from the external device may include a master clock signal, a data enable signal, a vertical synchronization signal, a horizontal synchronization signal, etc.

[0052] In this embodiment, the timing controller 200 can generate a first control signal CONT1, a second control signal CONT2, a third control signal CONT3, and a data signal DATA based on the input image data IMG and the input control signal CONT. In such an embodiment, the timing controller 200 can also generate a dummy (or "virtual") data signal DATA_D.

[0053] The timing controller 200 can generate a first control signal CONT1 for controlling the operation of the gate driver 300 based on the input control signal CONT, and output the first control signal CONT1 to the gate driver 300. The first control signal CONT1 may include a vertical start signal and a gate clock signal.

[0054] The timing controller 200 can generate a second control signal CONT2 based on the input control signal CONT for controlling the operation of the data driver 500, and output the second control signal CONT2 to the data driver 500. The second control signal CONT2 may include a horizontal start signal and a load signal.

[0055] In one embodiment, the timing controller 200 can generate a data signal DATA based on the input image data IMG. In such an embodiment, the timing controller 200 can generate a pseudo-data signal DATA_D based on the correction data CD. The timing controller 200 can output the data signal DATA and the pseudo-data signal DATA_D to the data driver 500.

[0056] The timing controller 200 can generate a third control signal CONT3 based on the input control signal CONT for controlling the operation of the gamma reference voltage generator 400. The timing controller 200 can output the third control signal CONT3 to the gamma reference voltage generator 400.

[0057] Data corrector 210 can be based on input image data IMG and lookup table 230 (shown in...). Figure 4 The data corrector 210 generates correction data CD. It can receive input image data IMG and identify the image data to be displayed on the display area. The data corrector 210 can generate correction data CD for generating pseudo-data voltages by using the arrangement information of gate lines GL previously stored in lookup table 230. The data corrector 210 can transmit the correction data CD to timing controller 200. In one embodiment, for example, as... Figure 1As shown, the data corrector 210 may be located outside the timing controller 200 to transmit or receive signals associated with the timing controller 200. In an alternative embodiment, for example, the data corrector 210 may be located inside the timing controller 200 as part of the timing controller 200, but is not limited thereto.

[0058] The gate driver 300 can generate a gate signal for driving the gate line GL in response to a first control signal CONT1 received from the timing controller 200. The gate driver 300 can output the gate signal to the gate line GL. In one embodiment, for example, the gate driver 300 can sequentially output the gate signal to the gate line GL. In one embodiment, for example, the gate driver 300 can be mounted on a peripheral portion of the display panel 100, but is not limited thereto.

[0059] The gamma reference voltage generator 400 can generate a gamma reference voltage VGREF in response to a third control signal CONT3 received from the timing controller 200. The gamma reference voltage generator 400 can provide the gamma reference voltage VGREF to the data driver 500. The gamma reference voltage VGREF provided to the data driver 500 can have a value corresponding to the corresponding data signal DATA. In one embodiment, for example, the gamma reference voltage generator 400 can be disposed within the timing controller 200 or the data driver 500, but is not limited thereto.

[0060] In one embodiment, the data driver 500 can receive a second control signal CONT2, a data signal DATA, and a pseudo-data signal DATA_D from the timing controller 200, and can receive a gamma reference voltage VGREF from the gamma reference voltage generator 400. The data driver 500 can convert the digital data signal DATA into an analog data voltage using the gamma reference voltage VGREF. In another embodiment, the data driver 500 can convert the digital pseudo-data signal DATA_D into an analog pseudo-data voltage using the gamma reference voltage VGREF. The data driver 500 can output the data voltage to the data line DL.

[0061] Reference Figure 2 and Figure 3The display portion of the display panel 100 for displaying images may include a peripheral display area SA and a main display area MA. The main display area MA may be surrounded by the peripheral display area SA. According to an embodiment, a first image may be displayed on the main display area MA, and a second image may be displayed on the peripheral display area SA. At least one panel driving circuit may be disposed in the lower circuit layer of the peripheral display area SA. Therefore, in such an embodiment, compared to a conventional display panel, the display panel 100 can provide a wider display area by displaying an image on the peripheral display area SA while maintaining the bezel portion.

[0062] In one embodiment, a first pixel PX1 having a first size can be disposed in the main display area MA. In such an embodiment, a second pixel PX2 having a second size can be disposed in the peripheral display area SA. In one embodiment, the first size of the first pixel PX1 can be smaller than the second size of the second pixel PX2. In such an embodiment, the number of pixels per inch in the main display area MA can be larger than the number of pixels per inch in the peripheral display area SA. In such an embodiment, the second size of the second pixel PX2 can be larger than the first size of the first pixel PX1. In such an embodiment, the number of pixels per inch in the peripheral display area SA can be smaller than the number of pixels per inch in the main display area MA. In one embodiment, as... Figure 3 As shown, the peripheral display area SA may include a corner display area SCA extending from the corner of the peripheral display area SA, and an intermediate display area SMA between the main display area MA and the corner display area SCA. The corner display area SCA and the intermediate display area SMA may be formed using different processes. Each of the corner display area SCA and the intermediate display area SMA may include a second pixel PX2.

[0063] In an embodiment, the gate line GL applied to the display panel 100 (see...) Figure 1The gate line GL can include a first gate line GL1 connected to both a first pixel PX1 and a second pixel PX2, and a second gate line GL2 connected only to the second pixel PX2. In such an embodiment, the gate line GL can include a first gate line GL1 electrically connected to both the main display area MA and the peripheral display area SA. The first gate line GL1 can transmit gate signals to both the first pixel PX1 and the second pixel PX2. The gate line GL can include a second gate line GL2 electrically connected only to the peripheral display area SA. The second gate line GL2 can transmit gate signals only to the second pixel PX2. In one embodiment, for example, the second gate line GL2 can be connected to the second pixel PX2 in a corner display area SCA of the peripheral display area SA. In an alternative embodiment, for example, the second gate line GL2 can be connected to the second pixel PX2 in a central display area SMA of the peripheral display area SA.

[0064] The data cable DL for display panel 100 (see...) Figure 1 The identification can be based on whether or not data voltage is transmitted to the second pixel PX2 connected to the second gate line GL2. In an embodiment, the data line DL may include a first data line DL1 and a second data line DL2, wherein the first data line DL1 does not transmit data voltage to the second pixel PX2 connected to the second gate line GL2, and the second data line DL2 transmits data voltage to the second pixel PX2 connected to the second gate line GL2. In an embodiment, as... Figure 2 As shown, the first data line DL1 may not transmit data voltage to the second pixel PX2 connected to the second gate line GL2. In such an embodiment, the second data line DL2 may transmit data voltage to the second pixel PX2 connected to the second gate line GL2. In one embodiment, when a gate signal is applied to the second gate line GL2, the second data line DL2 may transmit valid data voltage to the second pixel PX2. In another embodiment, when a gate signal is applied to the second gate line GL2, since there is no target pixel to which data voltage is transmitted, the first data line DL1 will not transmit valid data voltage to that pixel regardless of the applied data voltage.

[0065] When the data driver 500 applies a data voltage corresponding to a black image to the first data line DL1, the data voltage corresponding to the black image and applied to the first data line DL1 will couple with the effective data voltage applied to the first data line DL1, resulting in electrical interference. In one embodiment, for example, the electrical interference may be vertical crosstalk. Such electrical interference can degrade the image quality of the image displayed on the display panel 100 and cause display quality defects. In an embodiment of the invention, when the gate signal is applied to the second gate line GL2, the display device 10 can apply a pseudo-data voltage that minimizes electrical interference to the first data line DL1, thereby effectively preventing display quality defects caused by electrical interference.

[0066] Figure 4 It is shown that it includes Figure 1 A block diagram of an embodiment of the data corrector 210 in the display device 10.

[0067] Reference Figures 1 to 4 The embodiment of data corrector 210 can be based on input image data IMG and a lookup table ( Figure 4 The LUT 230 generates correction data CD. The data corrector 210 can receive input image data IMG and identify the display area. The data corrector 210 can generate correction data CD for generating pseudo-data voltages by using the arrangement information of gate lines GL previously stored in the lookup table 230. The data corrector 210 can transmit the correction data CD to the timing controller 200. In an embodiment, the data corrector 210 may include a display area determiner 220, a lookup table 230, and a correction data generator 240 to perform such operations.

[0068] In an embodiment, the display area determiner 220 can identify first image data to be displayed on the main display area MA and second image data to be displayed on the peripheral display area SA based on the input image data IMG. The display area determiner 220 can identify the input image data IMG as first image data and second image data using a data table input during the manufacturing process of the display device 10. The display area determiner 220 can transmit the first image data and second image data to the correction data generator 240. The lookup table 230 can store arrangement information of the first gate line GL1 and the second gate line GL2. In an embodiment, the lookup table 230 can store arrangement information of the first gate line GL1 connected to both the first pixel PX1 and the second pixel PX2, and the second gate line GL2 connected only to the second pixel PX2, and transmit the arrangement information of the gate lines GL to the correction data generator 240. The correction data generator 240 can generate correction data CD using the lookup table 230. In one embodiment, the correction data generator 240 can receive, from the display area determiner 220, first image data to be displayed on the main display area MA and second image data to be displayed on the peripheral display area SA. In such an embodiment, the correction data generator 240 can receive arrangement information of the first gate line GL1 and the second gate line GL2 from a lookup table 230. The correction data generator 240 can generate correction data CD for determining the pseudo data voltage applied to the first data line DL1. In one embodiment, for example, when a gate signal is applied to the second gate line GL2, the correction data CD can determine the voltage level of the pseudo data voltage applied to the first data line DL1. The correction data generator 240 can identify, from the second image data to be displayed on the peripheral display area SA, the second image data to be displayed on the second pixel PX2 connected to the second gate line GL2. The correction data CD can correct the second image data to determine the voltage level of the pseudo data voltage in a manner that effectively reduces or substantially minimizes electrical interference between data voltages.

[0069] In the embodiment, referencing is returned. Figure 1The data corrector 210 can generate a correction data CD and transmit the correction data CD to the timing controller 200. The timing controller 200 can receive the correction data CD from the data corrector 210. The timing controller 200 can generate a pseudo data signal DATA_D based on the correction data CD. The timing controller 200 can transmit the data signal DATA and the pseudo data signal DATA_D to the data driver 500. The data driver 500 can receive the data signal DATA and the pseudo data signal DATA_D from the timing controller 200. The data driver 500 can convert the digital data signal DATA into an analog data voltage using a gamma reference voltage VGREF, and the data driver 500 can convert the digital pseudo data signal DATA_D into an analog pseudo data voltage using a gamma reference voltage VGREF. The data driver 500 can output the data voltage to the data line DL.

[0070] The gate line GL applied to the display panel 100 may include a first gate line GL1 connected to both a first pixel PX1 and a second pixel PX2, and a second gate line GL2 connected only to the second pixel PX2. In such an embodiment, the gate line GL may include a first gate line GL1 electrically connected to both a main display area MA and a peripheral display area SA. The first gate line GL1 may transmit gate signals to both the first pixel PX1 and the second pixel PX2. The gate line GL may include a second gate line GL2 electrically connected only to the peripheral display area SA. The second gate line GL2 may transmit gate signals only to the second pixel PX2. In one embodiment, for example, the second gate line GL2 may be connected to the second pixel PX2 in a corner display area SCA within the peripheral display area SA. In an alternative embodiment, for example, the second gate line GL2 may be connected to the second pixel PX2 in a central display area SMA within the peripheral display area SA. In an embodiment, the data line DL of the display panel 100 may be identified based on whether data voltage is transmitted to the second pixel PX2 connected to the second gate line GL2. In one embodiment, the data line DL may include a first data line DL1 and a second data line DL2. The first data line DL1 does not transmit data voltage to the second pixel PX2 connected to the second gate line GL2, while the second data line DL2 transmits data voltage to the second pixel PX2 connected to the second gate line GL2. In such an embodiment, when a gate signal is applied to the second gate line GL2, the data driver 500 may apply a pseudo-data voltage generated based on the pseudo-data signal DATA_D to the first data line DL1. In one embodiment, for example, the pseudo-data voltage may have a voltage level other than (or different from) the voltage level of the data voltage corresponding to a black image. When the pseudo-data voltage has such a voltage level, the display device 10 can reduce coupling between data voltages and prevent vertical crosstalk caused by electrical interference.

[0071] Figure 5 This illustrates an embodiment. Figure 1 A flowchart of the operation of the display device 10.

[0072] Reference Figure 5According to an embodiment of the display device 10 of the invention, a gate signal can be applied to a first gate line GL1 connected to both the first pixel PX1 and the second pixel PX2 (S110), a gate signal can be applied to a second gate line GL2 connected only to the second pixel PX2 (S120), and a data voltage can be applied to the first data line DL1 and the second data line DL2 (S130). When the gate signal is applied to the second gate line GL2, the display device 10 can apply a pseudo data voltage to the first data line DL1 other than (or different from) the data voltage corresponding to a black image (S140).

[0073] In one embodiment, the display device 10 may apply a gate signal to a first gate line GL1 connected to both the first pixel PX1 and the second pixel PX2 (S110), and apply a gate signal to a second gate line GL2 connected only to the second pixel PX2 (S120). In such an embodiment, the gate line GL (see...) Figure 1 The display area (MA) may include a first gate line GL1 electrically connected to both the main display area (MA) and the peripheral display area (SA). The first gate line GL1 can transmit gate signals to both the first pixel PX1 and the second pixel PX2. The gate line GL may also include a second gate line GL2 electrically connected only to the peripheral display area (SA). The second gate line GL2 can transmit gate signals only to the second pixel PX2. In one embodiment, for example, the second gate line GL2 may be connected to the second pixel PX2 in a corner display area (SCA) within the peripheral display area (SA). In an alternative embodiment, for example, the second gate line GL2 may be connected to the second pixel PX2 in a central display area (SMA) within the peripheral display area (SA).

[0074] In one embodiment, the display device 10 can apply a data voltage to the first data line DL1 and the second data line DL2 (S130). In such an embodiment, the data line DL (see...) Figure 1The system may include a first data line DL1 and a second data line DL2. The first data line DL1 does not transmit data voltage to the second pixel PX2 connected to the second gate line GL2, while the second data line DL2 transmits data voltage to the second pixel PX2 connected to the second gate line GL2. The first data line DL1 may not transmit data voltage to the second pixel PX2 connected to the second gate line GL2. The second data line DL2 may transmit data voltage to the second pixel PX2 connected to the second gate line GL2. When a gate signal is applied to the second gate line GL2, the second data line DL2 may transmit valid data voltage to the second pixel PX2. In such an embodiment, when a gate signal is applied to the second gate line GL2, since there is no target pixel to which data voltage is transmitted, the first data line DL1 will not transmit valid data voltage to that pixel regardless of the applied data voltage.

[0075] In an embodiment, when a gate signal is applied to the second gate line GL2, the display device 10 may apply a pseudo-data voltage to the first data line DL1 (S140) other than (or different from) the data voltage corresponding to a black image. When the data voltage corresponding to a black image is applied to the first data line DL1, this data voltage couples with the valid data voltage applied to the first data line DL1, resulting in electrical interference. Such electrical interference degrades the image quality of the image displayed on the display panel 100 and causes display quality defects. In an embodiment of the invention, when a gate signal is applied to the second gate line GL2, the display device 10 may apply a pseudo-data voltage to the first data line DL1 that minimizes electrical interference to prevent such display quality defects caused by electrical interference. In one embodiment, for example, the pseudo-data voltage may be the same as the data voltage applied to the second data line DL2 closest to the first data line DL1. In an alternative embodiment, for example, the pseudo-data voltage may be the same as the data voltage applied to the first data line DL1 in the previous frame. In one alternative embodiment, for example, the dummy data voltage may have a voltage level corresponding to the intermediate value of the data voltage applied to the second data line DL2. However, the invention is not limited to such a dummy data voltage. In one alternative embodiment, for example, the dummy data voltage may be set to have a voltage level between the voltage level of the data voltage corresponding to the black image and the voltage level of the data voltage corresponding to the white image. In such an embodiment, when the dummy data voltage is changed, the display device 10 can reduce coupling between data voltages and prevent vertical crosstalk caused by electrical interference.

[0076] Figure 6 This illustrates an alternative embodiment. Figure 1A flowchart of the operation of the display device 10.

[0077] Reference Figures 1 to 6 According to an embodiment of the display device 10 of the invention, a gate signal can be applied to a first gate line GL1 connected to both the first pixel PX1 and the second pixel PX2 (S210), and a gate signal can be applied to a second gate line GL2 connected only to the second pixel PX2 (S220). In such an embodiment, the display device 10 can generate correction data CD based on input image data IMG and lookup table 230 (S230), generate a pseudo data signal DATA_D based on the correction data CD (S240), and apply a data voltage to the first data line DL1 and the second data line DL2 (S250). When the gate signal is applied to the second gate line GL2, the display device 10 can apply a pseudo data voltage other than (or different from) the data voltage corresponding to a black image to the first data line DL1 (S260).

[0078] In one embodiment, the display device 10 may apply a gate signal to a first gate line GL1 connected to both the first pixel PX1 and the second pixel PX2 (S210), and apply a gate signal to a second gate line GL2 connected only to the second pixel PX2 (S220). In such an embodiment, the gate driver 300 may generate a gate signal for driving the gate line GL in response to a first control signal CONT1 received from the timing controller 200. The gate driver 300 may output the gate signal to the gate line GL. In one embodiment, for example, the gate driver 300 may sequentially output the gate signal to the gate line GL. In such an embodiment, the gate line GL may include a first gate line GL1 electrically connected to both the main display area MA and the peripheral display area SA. The first gate line GL1 may transmit the gate signal to both the first pixel PX1 and the second pixel PX2. The gate line GL may include a second gate line GL2 electrically connected only to the peripheral display area SA. The second gate line GL2 may transmit the gate signal only to the second pixel PX2. In one embodiment, for example, the second gate line GL2 may be connected to a second pixel PX2 in a corner display area SCA within a peripheral display area SA. In an alternative embodiment, for example, the second gate line GL2 may be connected to a second pixel PX2 in a central display area SMA within a peripheral display area SA. In an embodiment, the data lines DL of the display panel 100 may be identified based on whether data voltage is transmitted to the second pixel PX2 connected to the second gate line GL2. In such an embodiment, the data lines DL may include a first data line DL1 and a second data line DL2, wherein the first data line DL1 does not transmit data voltage to the second pixel PX2 connected to the second gate line GL2, and the second data line DL2 transmits data voltage to the second pixel PX2 connected to the second gate line GL2.

[0079] In one embodiment, the display device 10 can generate correction data CD based on the input image data IMG and lookup table 230 (S230), generate a pseudo data signal DATA_D based on the correction data CD (S240), and apply a data voltage to the first data line DL1 and the second data line DL2 (S250). In such an embodiment, the data corrector 210 can generate correction data CD based on the input image data IMG and lookup table 230 (S230). Figure 4The LUT 230 generates correction data CD. The data corrector 210 can receive input image data IMG and identify the display area. The data corrector 210 can generate correction data CD for generating pseudo-data voltages by using the arrangement information of gate lines GL previously stored in the lookup table 230. The data corrector 210 can transmit the correction data CD to the timing controller 200. In such an embodiment, the data corrector 210 may include a display area determiner 220, a lookup table 230, and a correction data generator 240 to perform such operations. The display area determiner 220 can identify first image data to be displayed on the main display area MA and second image data to be displayed on the peripheral display area SA based on the input image data IMG. The display area determiner 220 can identify the input image data IMG as first image data and second image data by using a data table entered in the manufacturing process of the display device 10. The display area determiner 220 can transmit the first image data and second image data to the correction data generator 240. Lookup table 230 can store arrangement information of the first gate line GL1 and the second gate line GL2. In such an embodiment, lookup table 230 may include arrangement information of the first gate line GL1 connected to both the first pixel PX1 and the second pixel PX2, and the second gate line GL2 connected only to the second pixel PX2, and transmit the arrangement information of the gate lines GL to the correction data generator 240. The correction data generator 240 can generate correction data CD by using lookup table 230. In such an embodiment, the correction data generator 240 can receive first image data to be displayed on the main display area MA and second image data to be displayed on the peripheral display area SA from the display area determiner 220. In an embodiment, the correction data generator 240 can receive the arrangement information of the first gate line GL1 and the second gate line GL2 from lookup table 230. The correction data generator 240 can generate correction data CD for determining the pseudo data voltage applied to the first data line DL1. In one embodiment, for example, when a gate signal is applied to the second gate line GL2, the correction data CD can determine the voltage level of the pseudo data voltage applied to the first data line DL1. The correction data generator 240 can identify the second image data to be displayed on the second pixel PX2 connected to the second gate line GL2 from the second image data to be displayed on the peripheral display area SA. The correction data CD can correct the second image data to determine the voltage level of the dummy data voltage that minimizes electrical interference between data voltages.

[0080] In one embodiment, the data corrector 210 can generate corrected data CD and transmit the corrected data CD to the timing controller 200. The timing controller 200 can receive the corrected data CD from the data corrector 210. The timing controller 200 can generate a pseudo-data signal DATA_D based on the corrected data CD. The timing controller 200 can transmit the data signal DATA and the pseudo-data signal DATA_D to the data driver 500. The data driver 500 can receive the data signal DATA and the pseudo-data signal DATA_D from the timing controller 200. The data driver 500 can convert the digital data signal DATA into an analog data voltage using a gamma reference voltage VGREF. In such an embodiment, the data driver 500 can convert the digital pseudo-data signal DATA_D into an analog pseudo-data voltage using a gamma reference voltage VGREF. The data driver 500 can output the data voltage to the data line DL. In such an embodiment, when a gate signal is applied to the second gate line GL2, the data driver 500 can apply the pseudo-data voltage generated based on the pseudo-data signal DATA_D to the first data line DL1. In one embodiment, for example, the pseudo data voltage may have a voltage level other than (or different from) the voltage level of the data voltage corresponding to the black image.

[0081] In one embodiment, when a gate signal is applied to the second gate line GL2, the display device 10 may apply a pseudo-data voltage to the first data line DL1, other than (or different from) the data voltage corresponding to a black image. In this embodiment, when a gate signal is applied to the second gate line GL2, the display device 10 may apply a pseudo-data voltage to the first data line DL1 that minimizes electrical interference, thereby preventing display quality defects caused by electrical interference.

[0082] In such an embodiment, the pseudo data voltage can be generated based on the pseudo data signal DATA_D generated from the timing controller 200. In one embodiment, for example, the pseudo data voltage can be the same as the data voltage applied to the second data line DL2 closest to the first data line DL1. In another embodiment, for example, the pseudo data voltage can be the same as the data voltage applied to the first data line DL1 in the previous frame. In an alternative embodiment, for example, the pseudo data voltage can have a voltage level corresponding to an intermediate value of the data voltage applied to the second data line DL2. However, the invention is not limited to such a pseudo data voltage. In an alternative embodiment, for example, the pseudo data voltage can be set between the data voltage corresponding to a black image and the data voltage corresponding to a white image.

[0083] In this embodiment, as described above, the display device 10 can reduce coupling between data voltages and prevent vertical crosstalk caused by electrical interference. As a result, the display device 10 can improve the reliability of display quality by minimizing defects in the image quality of the image displayed on the display panel 100.

[0084] Figure 7 This is a block diagram illustrating an electronic device 1000 according to an embodiment of the invention. Figure 8 It is shown that Figure 7 The diagram shows an embodiment of the electronic device 1000 implemented as a smartphone.

[0085] Reference Figure 7 and Figure 8 Embodiments of electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, an input / output (“I / O”) device 1040, a power supply 1050, and a display device 1060. In such an embodiment, the display device 1060 may be… Figure 1 The display device 10. In an embodiment, the electronic device 1000 may further include multiple ports for communicating with video cards, sound cards, memory cards, universal serial bus (“USB”) devices, other electronic devices, etc. In an embodiment, such as Figure 8 As shown, electronic device 1000 can be implemented as a smartphone. However, electronic device 1000 is not limited to this. In an alternative embodiment, for example, electronic device 1000 can be implemented as a cellular phone, video phone, smart tablet, smartwatch, tablet personal computer (“PC”), car navigation system, computer monitor, laptop computer, head-mounted display (“HMD”) device, etc.

[0086] Processor 1010 can perform various computing functions. Processor 1010 may be a microprocessor, a central processing unit (“CPU”), an application processor (“AP”), etc. Processor 1010 may be connected to other components via address buses, control buses, data buses, etc. In embodiments, processor 1010 may be connected to an expansion bus such as a peripheral component interconnect (“PCI”) bus. Memory device 1020 may store data for the operation of electronic device 1000. In one embodiment, for example, memory device 1020 may include at least one non-volatile memory device (such as an erasable programmable read-only memory (“EPROM”) device, an electrically erasable programmable read-only memory (“EEPROM”) device, a flash memory device, a phase-change random access memory (“PRAM”) device, a resistive random access memory (“RRAM”) device, a nano-floating gate memory (“NFGM”) device, a polymer random access memory (“PoRAM”) device, a magnetic random access memory (“MRAM”) device, a ferroelectric random access memory (“FRAM”) device, etc.) and / or at least one volatile memory device (such as a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a mobile DRAM device, etc.). Storage device 1030 may include a solid-state drive (“SSD”) device, a hard disk drive (“HDD”) device, a CD-ROM device, etc. I / O device 1040 may include input devices (such as a keyboard, keypad, mouse, touchpad, touchscreen, etc.) and output devices (such as a printer, speaker, etc.). In an embodiment, I / O device 1040 may be included in display device 1060. Power supply 1050 provides power for the operation of electronic device 1000.

[0087] Display device 1060 can display an image corresponding to the visual information of electronic device 1000. In such an embodiment, display device 1060 may include: a display panel including a first display area having a first pixel with a first size and a second display area surrounding the first display area, wherein a second pixel having a second size different from the first size is disposed in the second display area; a gate driver for applying gate signals to gate lines of the display panel; a data driver for applying data voltages to data lines of the display panel; and a timing controller for controlling the gate driver and the data driver. In such an embodiment, the gate lines may include a first gate line and a second gate line, the first gate line being connected to both the first pixel and the second pixel, and the second gate line being connected only to the second pixel. In such an embodiment, the data lines may include a first data line and a second data line, the first data line not transmitting data voltages to the second pixel connected to the second gate line, and the second data line transmitting data voltages to the second pixel connected to the second gate line. In such an embodiment, when a gate signal is applied to the second gate line, a dummy data voltage may be applied to the first data line. In such an embodiment, display device 1060 can reduce coupling between data voltages and prevent vertical crosstalk caused by electrical interference. As a result, the display device 1060 can improve the reliability of display quality by minimizing defects in the image quality of the image displayed on the display panel. For ease of description, any repeated detailed descriptions of the same or similar components of the display device 1060 as described above will be omitted.

[0088] Embodiments of the invention can be applied to any display device and electronic device including the display device. In one embodiment, for example, the invention can be applied to digital televisions (“TV”), three-dimensional (“3D”) TVs, mobile phones, smartphones, tablet computers, virtual reality (“VR”) devices, PCs, home electronic devices, laptop computers, personal digital assistants (“PDAs”), portable media players (“PMPs”), digital cameras, music players, portable game consoles, navigators, etc.

[0089] The invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the inventive concept to those skilled in the art.

[0090] Although the invention has been specifically shown and described with reference to embodiments thereof, those skilled in the art will understand that various changes in form and detail may be made therein without departing from the spirit or scope of the invention as defined by the claims.

Claims

1. A display device, the display device comprising: The display panel includes a first display area and a second display area surrounding the first display area and disposed on top of a driving circuit, wherein a first pixel having a first size is disposed in the first display area, and a second pixel having a second size different from the first size is disposed in the second display area; A gate driver applies gate signals to the gate lines of the display panel; A data driver applies data voltage to the data lines of the display panel; and The timing controller controls the gate driver and the data driver. The gate line includes a first gate line and a second gate line. The first gate line is connected to both the first pixel and the second pixel, and the second gate line is connected only to the second pixel. The data lines include a first data line and a second data line. The first data line does not transmit the data voltage to the second pixel connected to the second gate line, while the second data line transmits the data voltage to the second pixel connected to the second gate line. When the gate signal is applied to the second gate line, a pseudo data voltage is applied to the first data line.

2. The display device according to claim 1, further comprising: The data corrector generates corrected data based on the input image data and a lookup table.

3. The display device according to claim 2, wherein, The data corrector includes: Display area determiner, based on the input image data, identifies first image data to be displayed on the first display area and second image data to be displayed on the second display area; The lookup table stores arrangement information of the first gate line and the second gate line; and A correction data generator generates the correction data using the lookup table.

4. The display device according to claim 3, wherein, The timing controller receives the correction data from the data corrector and generates a pseudo data signal based on the correction data.

5. The display device according to claim 4, wherein, When the gate signal is applied to the second gate line, the data driver applies the pseudo data voltage generated based on the pseudo data signal to the first data line.

6. The display device according to claim 1, wherein, The second data line is configured to have multiple lines, and The pseudo-data voltage is the same as the data voltage applied to the second data line closest to the first data line.

7. The display device according to claim 1, wherein, The pseudo data voltage is the same as the data voltage applied to the first data line in the previous frame.

8. The display device according to claim 1, wherein, The pseudo-data voltage has a voltage level corresponding to the intermediate value of the data voltage applied to the second data line.

9. The display device according to claim 1, wherein, The pseudo data voltage has a voltage level between the voltage level of the data voltage corresponding to the black image and the voltage level of the data voltage corresponding to the white image.

10. The display device according to claim 1, wherein, The second display area includes: a corner display area extending from the corner of the second display area; and a middle display area located between the first display area and the corner display area.

11. A method for driving a display device, the method comprising the following steps: A gate signal is applied to a first gate line that connects both the first pixel and the second pixel. Apply the gate signal to the second gate line that is only connected to the second pixel; and Apply the data voltage to the data line. The first pixel has a first size and is disposed in the first display area. The second pixel has a second size different from the first size and is disposed in a second display area surrounding the first display area and disposed on top of the driving circuit. The data lines include a first data line and a second data line. The first data line does not transmit the data voltage to the second pixel connected to the second gate line, while the second data line transmits the data voltage to the second pixel connected to the second gate line. The step of applying the data voltage to the data line includes: applying a dummy data voltage to the first data line when the gate signal is applied to the second gate line.

12. The method according to claim 11, further comprising the following step: Correction data is generated based on the input image data and a lookup table.

13. The method according to claim 12, wherein, The steps for generating the correction data include: Based on the input image data, first image data to be displayed in the first display area and second image data to be displayed in the second display area are identified; and The correction data is generated by using the lookup table, which stores the arrangement information of the first gate line and the second gate line.

14. The method of claim 13, further comprising the step of: A pseudo-data signal is generated based on the correction data.

15. The method according to claim 14, wherein, The step of applying the data voltage to the data line further includes: The pseudo data voltage is generated based on the pseudo data signal.

16. The method according to claim 11, wherein, The second data line is configured to have multiple lines, and The pseudo-data voltage is the same as the data voltage applied to the second data line closest to the first data line.

17. The method according to claim 11, wherein, The pseudo data voltage is the same as the data voltage applied to the first data line in the previous frame.

18. The method according to claim 11, wherein, The pseudo-data voltage has a voltage level corresponding to the intermediate value of the data voltage applied to the second data line.

19. The method according to claim 11, wherein, The pseudo data voltage has a voltage level between the voltage level of the data voltage corresponding to the black image and the voltage level of the data voltage corresponding to the white image.

20. The method according to claim 11, wherein, The second display area includes: a corner display area extending from the corner of the second display area; and a middle display area located between the first display area and the corner display area.

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