sensitive amplifier

Abstract

The application provides a sensitive amplifier, comprising a control module provided with an input end and an output end, which is used for pulse width adjustment of a first offset cancellation signal received by the input end according to a transistor process angle, and generates and outputs a second offset cancellation signal; and an amplification module connected with the output end of the control module, which is used for offset noise cancellation of the amplification module under the control of the second offset cancellation signal. The above scheme can form a compensation voltage with appropriate size on a read bit line and a complementary read bit line, accurately cancels noise caused by manufacturing differences of a transistor, and improves the accuracy of the sensitive amplifier.

Description

Technical Field

[0001] This application relates to, but is not limited to, a sensitive amplifier. Background Technology

[0002] As the linewidth of semiconductor memory shrinks, the capacitance of the memory cells within the semiconductor memory decreases, making noise have a greater impact on the normal operation of the semiconductor memory.

[0003] Sensitive amplifiers can eliminate noise caused by manufacturing variations in transistors within semiconductor memory, enabling accurate data storage. When the sensitive amplifier operates in the offset cancellation phase, a compensation voltage is generated on the read bit line and the complementary read bit line; the magnitude of this compensation voltage affects the noise cancellation effect.

[0004] Therefore, generating appropriate compensation voltages on the bit lines and complementary bit lines is crucial for semi-cancelling noise within semiconductor memories. Summary of the Invention

[0005] One embodiment of this application provides a sensitive amplifier, comprising:

[0006] The control module includes an input terminal and an output terminal, and is used to adjust the pulse width of the first offset cancellation signal received at its input terminal according to the transistor process corner, and generate and output a second offset cancellation signal through its output terminal.

[0007] The amplification module, connected to the output of the control module, is used to eliminate the offset noise of the amplification module under the control of the second offset cancellation signal.

[0008] In one embodiment, the control module includes:

[0009] The parameter generation circuit is used to generate a pulse width adjustment signal based on the transistor process corner of the parameter generation circuit.

[0010] The adjustment circuit has its control terminal connected to the output terminal of the parameter generation circuit, its input terminal receiving the first offset cancellation signal, adjusting the pulse width of the first offset cancellation signal according to the pulse width adjustment signal, and outputting the second offset cancellation signal.

[0011] In one embodiment, the parameter generation circuit includes:

[0012] Oscillation control unit, used to generate an oscillation enable signal with a fixed time width;

[0013] A ring oscillator, whose control terminal is connected to the output terminal of an oscillation control unit, is used to generate an oscillation signal when an oscillation enable signal is received;

[0014] An oscillation counter, whose input is connected to the output of a ring oscillator, is used to count the number of oscillation signals within a fixed time width and output a pulse width adjustment signal.

[0015] In one embodiment, the transistor process angle of the ring oscillator is the same as that of the amplification module, and the number of oscillation signals generated within a fixed time width is determined by the transistor process angle of the ring oscillator.

[0016] In one embodiment, the ring oscillator includes an odd number of first NAND gates;

[0017] For each first NAND gate, its first input is connected to the output of the first NAND gate in the previous stage, and its output is connected to the first input of the first NAND gate in the next stage. The first input of the first stage first NAND gate is connected to the output of the last stage first NAND gate.

[0018] An odd number of first NAND gates have their second inputs connected to the same node, which serves as the control terminal of the ring oscillator; the output of any one of the first NAND gates serves as the output of the ring oscillator.

[0019] In one embodiment, the oscillation control unit is configured to output a valid oscillation enable signal after the arrival of the oscillation start signal and an invalid oscillation enable signal after the arrival of the oscillation stop signal.

[0020] In one embodiment, the oscillation control unit includes:

[0021] The second NAND gate circuit receives the oscillation start signal at its first input terminal.

[0022] The first NOT gate circuit receives the oscillation termination signal at its input terminal; its output terminal is connected to the second input terminal of the second NAND gate circuit.

[0023] The second NOT gate circuit has its input terminal connected to the output terminal of the second NAND gate circuit, and its output terminal serves as the output terminal of the oscillation control unit.

[0024] In one embodiment, the parameter generation circuit includes multiple output terminals, and the pulse width adjustment signal includes multiple pulse width adjustment sub-signals. The output terminals of the parameter generation circuit output the pulse width adjustment sub-signals respectively.

[0025] The adjustment circuit includes multiple adjustment sub-modules connected in sequence; the control terminal of each adjustment sub-module is connected to an output terminal of the parameter generation circuit.

[0026] The first-level adjustment submodule receives the first offset cancellation signal and adjusts the pulse of the first offset cancellation signal according to the pulse width adjustment sub-signal it receives;

[0027] Each of the remaining adjustment submodules receives the output signal from the previous adjustment submodule and adjusts the pulse of the output signal of the previous adjustment submodule according to the pulse width adjustment sub-signal received at its control terminal; the output signal of the last adjustment submodule is the second offset cancellation signal.

[0028] In one embodiment, each adjustment submodule includes:

[0029] The delay unit's input terminal serves as the input terminal of the adjustment submodule;

[0030] An OR gate circuit, whose first input is connected to the output of the delay unit, and whose second input serves as the control terminal of the adjustment submodule;

[0031] An AND gate circuit, whose first input is connected to the input of a delay unit, whose second input is connected to the output of an OR gate circuit, and whose output serves as the output of an adjustment submodule.

[0032] In one embodiment, if the first offset cancellation signal is a high-level active signal, the oscillation counter is a down counter;

[0033] If the first offset cancellation signal is a low-level active signal, the oscillation counter is an adder counter.

[0034] In one embodiment, the amplification module includes:

[0035] The first P-type transistor has its source coupled to the first power supply terminal and its gate connected to the drain of the second P-type transistor.

[0036] The source of the second P-type transistor is connected to the source of the first P-type transistor, and its gate is connected to the drain of the first P-type transistor.

[0037] The first N-type transistor has its drain connected to the drain of the first P-type transistor, its gate connected to the bit line, and its source coupled to the second power supply terminal.

[0038] The second N-type transistor has its drain connected to the drain of the second P-type transistor, its gate connected to the complementary bit line, and its source connected to the source of the first N-type transistor.

[0039] The third N-type transistor has its drain connected to the drain of the first N-type transistor and its source connected to the bit line; its gate is turned on when it receives the second offset cancellation signal.

[0040] The fourth N-type transistor has its drain connected to the drain of the second N-type transistor and its source connected to the complementary bit line; its gate is turned on when it receives the second offset cancellation signal.

[0041] In one embodiment, the process angles of the third N-type transistor, the fourth N-type transistor, and the ring oscillator are the same.

[0042] In one embodiment, the amplification module further includes:

[0043] The fifth N-type transistor has its drain connected to the drain of the second N-type transistor and then connected to the read bit line. Its source is connected to the bit line, and its gate is used to receive the precharge signal and is used to turn on under the control of the precharge signal.

[0044] The sixth N-type transistor has its drain connected to the drain of the first N-type transistor and then connected to the complementary readout bit line, and its source connected to the complementary bit line; its gate is used to receive the precharge signal and is used to turn on under the control of the precharge signal.

[0045] In one embodiment, the signal delay between the first offset cancellation signal and the precharge signal is preset.

[0046] In one embodiment, the amplification module further includes:

[0047] The third P-type transistor has its source connected to the first power supply terminal and its drain connected to the source of the first P-type transistor.

[0048] The seventh N-type transistor has its source connected to the second power supply terminal and its drain connected to the source of the first N-type transistor.

[0049] This application provides a sensitive amplifier, which includes a control module and an amplification module. The control module adjusts the pulse width of a first offset cancellation signal based on the transistor process angle to obtain a second offset cancellation signal, and controls the amplification module to form a compensation voltage on the readout bit line and the complementary readout bit line based on the second offset cancellation signal, so as to form a compensation voltage of appropriate magnitude on the readout bit line and the complementary readout bit line, accurately eliminate noise caused by transistor manufacturing differences, and improve the accuracy of the sensitive amplifier. Attached Figure Description

[0050] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0051] Figure 1 This is a circuit diagram of a sensitive amplifier;

[0052] Figure 2 This is a schematic diagram of the structure of a sensitive amplifier provided in an embodiment of this application;

[0053] Figure 3 This is a schematic diagram of the structure of a control module provided in one embodiment of this application;

[0054] Figure 4 This is a schematic diagram of the structure of an adjustment submodule provided in an embodiment of this application;

[0055] Figure 5A A schematic diagram illustrating the working principle of an adjustment submodule provided in an embodiment of this application;

[0056] Figure 5B A schematic diagram illustrating another working principle of the adjustment submodule provided in one embodiment of this application;

[0057] Figure 6 This is a schematic diagram of the parameter generation circuit provided in one embodiment of this application;

[0058] Figure 7 This is a schematic diagram of the structure of an oscillation control unit provided in an embodiment of this application;

[0059] Figure 8 This is a schematic diagram illustrating the working principle of an oscillation control unit provided in an embodiment of this application;

[0060] Figure 9 A timing diagram of a sensitive amplifier provided in one embodiment of this application.

[0061] Figure label:

[0062] 100. Control module; 110. Adjustment submodule; 111. Delay unit; 112. OR gate; 113. AND gate; 120. Parameter generation circuit; 200. Amplification module; 210. Oscillation control unit; 211. First NOT gate; 212. Second NAND gate; 213. Second NOT gate; 220. Ring oscillator; 221. First NAND gate; 230. Oscillation counter.

[0063] The accompanying drawings illustrate specific embodiments of this application, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concept of this application to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0064] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.

[0065] like Figure 1 As shown, a sensitive amplifier includes a first P-type transistor P1, a second P-type transistor P2, a first N-type transistor N1, and a second N-type transistor N2.

[0066] In this configuration, the gate of the first P-type transistor P1 is connected to the drain of the second P-type transistor P2, and the gate of the second P-type transistor P2 is connected to the drain of the first P-type transistor P1.

[0067] The sensitive amplifier also includes a third N-type transistor N3 and a fourth N-type transistor N4. The drain of the first N-type transistor N1 is connected to its gate via the third N-type transistor N3, and the gate of the first N-type transistor N1 is connected to bit line BL. The gate of the second N-type transistor N2 is connected to its drain via the fourth N-type transistor N4, and the gate of the second N-type transistor N2 is connected to complementary bit line BLB.

[0068] The sensitive amplifier also includes a fifth N-type transistor N5 and a sixth N-type transistor N6. The gate of the first N-type transistor N1 is connected to the drain of the second N-type transistor N2 via the fifth N-type transistor N5. The drain of the second N-type transistor N2 is then connected to the drain of the second P-type transistor P2, and subsequently to the readout bit line SABL. The gate of the second N-type transistor N2 is connected to the drain of the first N-type transistor N1 via the sixth N-type transistor N6. The drain of the first N-type transistor N1 is then connected to the drain of the first P-type transistor P1, and subsequently to the complementary readout bit line SABLB.

[0069] During the offset elimination phase, both the third N-type transistor N3 and the fourth N-type transistor N4 are turned on, and both the first N-type transistor N1 and the second N-type transistor N2 operate in diode mode, generating compensation voltages on bit line BL and complementary bit line BLB, as well as on read bit line SABL and complementary read bit line SABLB.

[0070] Since there is already a compensation voltage on the readout bit line SABL and the complementary readout bit line SABLB, during the pre-readout stage, the compensation voltage can cancel out the noise caused by the manufacturing difference between the first N-type transistor N1 and the second N-type transistor N2 in the elimination sensitive amplifier, and accurately present the data on the bit line BL and the complementary bit line BLB.

[0071] During the recovery phase, both the fifth N-type transistor N5 and the sixth N-type transistor N6 are turned on, the bit line BL and the read bit line SABL are connected, and the complementary bit line BLB and the complementary read bit line SABLB are connected, thereby realizing the recovery of data in the memory cell.

[0072] The magnitude of the compensation voltage affects the noise cancellation effect. Both excessively large and insufficient compensation voltages cannot accurately eliminate the manufacturing differences between the first N-type transistor N1 and the second N-type transistor N2. The magnitude of the compensation voltage is related to the driving capability of the transistors in the sensitive amplifier. A stronger driving capability allows for a larger compensation voltage to be formed on the read bit line SABL and the complementary read bit line SABLB. Conversely, a weaker driving capability results in a smaller compensation voltage on these two lines.

[0073] In order to more accurately generate a compensation voltage of appropriate magnitude on the readout bit line SABL and the complementary readout bit line SABLB, this application adjusts the width of the offset cancellation signal based on the driving capability of the transistors of the sensitive amplifier, so that the sensitive amplifier generates a compensation voltage of appropriate magnitude under the control of the adjusted offset cancellation signal, accurately eliminates the noise caused by the manufacturing difference between the first N-type transistor N1 and the second N-type transistor N2, and improves the accuracy of the sensitive amplifier.

[0074] like Figure 2 As shown, one embodiment of this application provides a sensitive amplifier, which includes a control module 100 and an amplification module 200.

[0075] The control module 100 has an input terminal and an output terminal. The input terminal of the control module 100 receives a first offset cancellation signal OC. The control module 100 adjusts the pulse width of the first offset cancellation signal OC according to the transistor process corner, and generates and outputs a second offset cancellation signal OC'. The output terminal of the control module 100 is connected to the control terminal of the amplification module 200. Under the control of the second offset cancellation signal OC', the amplification module 200 generates a compensation voltage on the readout bit line SABL and the complementary readout bit line SABLB, so as to eliminate the offset noise of the amplification module 200 under the control of the second offset cancellation signal OC'.

[0076] The first offset cancellation signal OC is a pulse signal, and the pulse width of the first offset cancellation signal OC is determined according to the design parameters of each transistor in the amplification module 200.

[0077] In one embodiment, since the transistors of the sensitive amplifier have the same process angle during manufacturing, the pulse width of the first offset cancellation signal OC can be adjusted according to the process angle of the transistors of the amplification module 200, or the pulse width of the first offset cancellation signal OC can be adjusted according to the process angle of the transistors of the control module 100.

[0078] In one embodiment, if the transistor process corner is FF (NEFT-FAST corner & PEFT-FAST corner), the pulse width of the second offset cancellation signal OC' is smaller. If the transistor process corner is SS (NEFT-SLOW corner & PEFT-SLOW corner), the pulse width of the second offset cancellation signal OC' is larger.

[0079] When the aforementioned sensitive amplifier is operating, if the transistor process angle is SS, the weaker the driving capability of the transistor in the amplification module 200, the slower the rate at which the transistor pulls the voltage of the read bit line SABL and the complementary read bit line SABLB. Furthermore, the pulse width of the second offset cancellation signal OC' is relatively large, resulting in a longer offset cancellation phase. This provides sufficient time to form a suitable compensation voltage on the read bit line BL and the complementary read bit line SABLB. Conversely, if the transistor process angle is FF, the stronger the driving capability of the transistor in the amplification module 200, the faster the rate at which the transistor pulls the voltage of the read bit line SABL and the complementary read bit line SABLB. Furthermore, the pulse width of the second offset cancellation signal OC' is relatively small, resulting in a shorter offset cancellation phase. This avoids excessively long offset cancellation times and ensures that a suitable compensation voltage is formed on the read bit line SABL and the complementary read bit line SABLB. After a suitable compensation voltage is formed on the readout bit line SABL and the complementary readout bit line SABLB, the compensation voltage can cancel the noise caused by manufacturing differences in the transistors in the sensitive amplifier during the pre-readout stage. This can accurately amplify the data on the readout bit line SABL and the complementary readout bit line SABLB, thereby improving the accuracy of the sensitive amplifier.

[0080] In the above technical solution, the sensitive amplifier includes a control module 100 and an amplification module 200. The control module 100 adjusts the pulse width of the first offset cancellation signal OC based on the transistor process angle to obtain a second offset cancellation signal OC', and controls the amplification module 200 to form a compensation voltage on the read bit line SABL and the complementary read bit line SABLB based on the second offset cancellation signal OC', so as to form a compensation voltage of appropriate magnitude on the read bit line SABL and the complementary read bit line SABLB, accurately eliminate noise caused by transistor manufacturing differences, and improve the accuracy of the sensitive amplifier.

[0081] In one embodiment, the control module 100 includes a parameter generation circuit 120 and an adjustment circuit. The adjustment circuit has an input terminal, an output terminal, and a control terminal. The parameter generation circuit 120 has an output terminal, and the control terminal of the adjustment circuit is connected to the output terminal of the parameter generation circuit 120. The parameter generation circuit 120 generates a pulse width adjustment signal according to the transistor process corner of the parameter generation circuit and inputs the pulse width adjustment signal to the control terminal of the adjustment circuit. The input terminal of the adjustment circuit receives a first offset cancellation signal OC. The adjustment circuit is used to adjust the pulse width of the first offset cancellation signal OC according to the pulse width adjustment signal and output a second offset cancellation signal OC'.

[0082] In one embodiment, such as Figure 3 As shown, the adjustment circuit includes multiple cascaded adjustment submodules 110, each adjustment submodule 110 having an input terminal a1, an output terminal a2, and a control terminal a3. The cascading of multiple adjustment submodules 110 means that the output terminal a2 of the previous adjustment submodule 110 is connected to the input terminal a1 of the next adjustment submodule 110.

[0083] The parameter generation circuit 120 includes multiple output terminals, the number of which is the same as the number of adjustment sub-modules 110, such that the control terminal a3 of each adjustment sub-module 110 is connected to one output terminal of the parameter generation circuit 120. The pulse width adjustment signal includes multiple pulse width adjustment sub-signals, the number of which is the same as the number of output terminals of the parameter generation circuit 120; one output terminal of the parameter generation circuit 120 outputs one pulse width adjustment sub-signal.

[0084] The input terminal a1 of the first-level adjustment submodule 110 receives the first offset cancellation signal OC. The parameter generation circuit 120 inputs a corresponding pulse width adjustment sub-signal to the control terminal a3 of the first-level adjustment submodule 110. The first-level adjustment submodule 110 adjusts the pulse width of the first offset cancellation signal OC according to the received pulse width adjustment sub-signal. For each of the remaining adjustment submodules 110, the parameter generation circuit 120 inputs a corresponding pulse width adjustment sub-signal to the control terminal a3 of the corresponding adjustment submodule 110. Each adjustment submodule 110 receives the output signal of the previous adjustment submodule 110 and adjusts the pulse width of the output signal of the previous adjustment submodule 110 according to the received pulse width adjustment sub-signal. The output terminal a2 of the last-level adjustment submodule 110 outputs the second offset cancellation signal OC'.

[0085] For example, the adjustment circuit includes n adjustment sub-modules 110, which are sequentially labeled as first-level adjustment sub-module 110, second-level adjustment sub-module 110, ..., nth-level adjustment sub-module 110. The parameter generation circuit 120 includes n output terminals, which are sequentially labeled as first output terminal Q1, second output terminal Q2, ..., nth output terminal Q(n).

[0086] The control terminal a3 of the first-level adjustment submodule 110 is connected to the first output terminal Q1 of the parameter generation circuit 120, and the output terminal a2 of the first-level adjustment submodule 110 is connected to the input terminal a1 of the second-level adjustment submodule 110; the control terminal a3 of the second-level adjustment submodule 110 is connected to the second output terminal Q2 of the parameter generation circuit 120, and the output terminal a2 of the second-level adjustment submodule 110 is connected to the input terminal a1 of the third-level adjustment submodule 110; and so on; the control terminal a3 of the nth-level adjustment submodule 110 is connected to the nth output terminal Q(n) of the parameter generation circuit 120, and the output terminal a2 of the (n-1)th-level adjustment submodule 110 is connected to the input terminal a1 of the nth-level adjustment submodule 110.

[0087] The input terminal a1 of the first-level adjustment submodule 110 is used to receive the first offset cancellation signal OC. The first-level adjustment submodule 110 is used to perform pulse width adjustment processing on the first offset cancellation signal OC according to the pulse width adjustment sub-signal received by its control terminal a3. The second-level adjustment submodule 110 is used to perform pulse width adjustment processing on the output signal of the first-level adjustment submodule 110 according to the pulse width adjustment sub-signal received by its control terminal a3. The third-level adjustment submodule 110 is used to perform pulse width adjustment processing on the output signal of the second-level adjustment submodule 110 according to the pulse width adjustment sub-signal received by its control terminal a3. And so on, the nth-level adjustment submodule 110 is used to perform pulse width adjustment processing on the output signal of the (n-1)th-level adjustment submodule 110 according to the pulse width adjustment sub-signal received by its control terminal a3.

[0088] In one embodiment, if a certain pulse width adjustment sub-signal is active, the adjustment submodule 110 performs pulse width adjustment processing on the output signal of the previous-level adjustment submodule 110. If a certain pulse width adjustment sub-signal is inactive, the adjustment submodule 110 directly outputs the output signal of the previous-level adjustment submodule 110.

[0089] In the above technical solution, the pulse width adjustment signal is determined based on the transistor process angle, and the number of adjustment sub-modules 110 used for pulse width adjustment is adjusted, thereby adjusting the pulse width of the second offset cancellation signal OC' output by the last stage adjustment sub-module 110.

[0090] In one embodiment, each adjustment submodule 110 is used to perform pulse width reduction processing on the output signal of the previous adjustment submodule 110 or the first offset cancellation signal OC, so that the pulse width of the output second offset cancellation signal OC' is smaller than the pulse width of the first offset cancellation signal OC.

[0091] In one embodiment, each adjustment submodule 110 is used to perform pulse width increase processing on the output signal of the previous adjustment submodule 110 or the first offset cancellation signal OC, so that the pulse width of the output second offset cancellation signal OC' is greater than the pulse width of the first offset cancellation signal OC.

[0092] In one embodiment, such as Figure 4 As shown, each adjustment submodule 110 includes a delay unit 111, an OR gate circuit 112, and an AND gate circuit 113. The delay unit 111 has an input terminal and an output terminal. The input terminal of the delay unit 111 serves as the input terminal a1 of the adjustment submodule 110, and is used to receive the first offset cancellation signal OC or the output signal of the previous-level adjustment submodule 110. The OR gate circuit 112 has a first input terminal, a second input terminal, and an output terminal. The first input terminal of the OR gate circuit 112 is connected to the output terminal of the delay unit 111, and the second input terminal of the OR gate circuit 112 serves as the control terminal a3 of the adjustment submodule 110, used to connect to a corresponding output terminal of the parameter generation circuit 120. The AND gate circuit 113 has a first input terminal, a second input terminal, and an output terminal. The first input terminal of AND gate 113 is connected to the input terminal of delay unit 111. The first input terminal of AND gate 113 is used to receive the first offset cancellation signal OC or the output signal of the previous level adjustment submodule 110. The second input terminal of AND gate 113 is connected to the output terminal of OR gate 112. The output terminal of AND gate 113 serves as the output terminal a2 of adjustment submodule 110 and is used to connect to the input terminal a1 of the next level adjustment submodule 110.

[0093] For the first-level adjustment submodule 110, the input terminal of the delay unit 111 receives the first offset cancellation signal OC. For adjustment submodules 110 other than the first-level adjustment submodule 110, the input terminal of the delay unit 111 receives the output signal of the previous-level adjustment submodule 110. For ease of description, the output signal of the previous-level adjustment submodule 110 or the first offset cancellation signal OC are collectively referred to as the signal to be processed S1.

[0094] like Figure 5AAs shown, when the signal to be processed S1 is a high-level active signal, the delay unit 111 delays the signal to be processed S1 to generate a delayed signal to be processed S2. When the pulse width adjustment sub-signal received at the second input terminal of the OR gate circuit 112 is low, the OR gate circuit 112 outputs the delayed signal to be processed S2. After the AND gate circuit 113 performs an AND operation on the signal to be processed S1 and the delayed signal to be processed S2, an output signal S3 with a pulse width of ΔT2 can be obtained, which is shorter than the pulse width ΔT1 of the signal to be processed.

[0095] like Figure 5B As shown, when the pulse width adjustment sub-signal received at the second input terminal of the OR gate circuit 112 is high, the OR gate circuit 112 outputs a high level S4. After the AND gate circuit 113 ANDs the high level S4 with the signal to be processed S1, the pulse width of the output signal S5 is the same as the width of the signal to be processed S1.

[0096] In the above technical solution, the adjustment submodule 110 includes a delay unit 111, an AND gate circuit 113, and an OR gate circuit 112. When the pulse width adjustment sub-signal received at the second input terminal of the OR gate circuit 112 is at a high level, the AND gate circuit 113 directly outputs the output signal of the previous adjustment submodule 110. When the pulse width adjustment sub-signal received at the second input terminal of the OR gate circuit 112 is at a low level, the AND gate circuit 113 outputs an output signal with a smaller pulse width. This enables the adjustment submodule 110 to perform pulse width adjustment processing on the output signal of the previous adjustment submodule 110 based on the pulse width adjustment sub-signal.

[0097] In one embodiment, such as Figure 6 As shown, the parameter generation circuit 120 includes an oscillation control unit 210, a ring oscillator 220, and an oscillation counter 230. The oscillation control unit 210 generates an oscillation enable signal with a fixed time width. The oscillation control unit 210 has an output terminal. The ring oscillator 220 has a control terminal and an output terminal. The output terminal of the oscillation control unit 210 is connected to the control terminal of the ring oscillator 220. The ring oscillator 220 generates at least one oscillation signal within a fixed time width. The number of oscillation signals generated by the ring oscillator 220 within the fixed time width is determined by the transistor process corner of the ring oscillator 220. The oscillation counter 230 has an input terminal and an output terminal. The input terminal of the oscillation counter 230 is connected to the output terminal of the ring oscillator 220. The oscillation counter 230 counts the number of oscillation signals within the fixed time width and outputs a pulse width adjustment signal via its output terminal.

[0098] In one embodiment, the oscillation control unit 210 is used to output a valid oscillation enable signal after the arrival of the oscillation start signal and an invalid oscillation enable signal after the arrival of the oscillation end signal. By controlling the interval between the arrival time of the oscillation start signal and the arrival time of the oscillation end signal, the time for outputting the valid oscillation enable signal can be controlled. If the interval between the arrival time of the oscillation start signal and the arrival time of the oscillation end signal is a fixed time width, then the effective time of the output oscillation enable signal can be a fixed time width.

[0099] In the above technical solution, since the transistor process angle of the ring oscillator 220 and the transistor process angle of the amplification module 200 are the same, the number of oscillation signals generated by the ring oscillator 220 within a fixed time width is related to the process angle of the amplification module 200. By counting the number of oscillation signals through the oscillation counter 230 to generate a pulse width adjustment signal, the pulse width adjustment signal can be generated based on the transistor process angle, so that the adjustment circuit can adjust the width of the first offset cancellation signal OC based on the pulse width adjustment signal.

[0100] In one embodiment, such as Figure 6 As shown, the ring oscillator 220 includes an odd number of first NAND gate circuits 221. Each first NAND gate circuit 221 has a first input terminal, a second input terminal, and an output terminal.

[0101] For each first NAND gate 221, its first input terminal is connected to the output terminal of the first NAND gate 221 in the previous stage, and its output terminal is connected to the first input terminal of the first NAND gate 221 in the next stage. The first input terminal of the first-stage first NAND gate 221 is connected to the output terminal of the last-stage first NAND gate 221, thus forming a ring oscillator 220. The second input terminals of an odd number of first NAND gates 221 are connected to the same node and serve as the control terminal of the ring oscillator 220. The output terminal of any one of the odd number of first NAND gates 221 serves as the output terminal of the ring oscillator 220.

[0102] In the aforementioned ring oscillator 220, when the oscillation enable signal is high, the ring oscillator 220 outputs an oscillation signal; that is, it is effective when the oscillation enable signal is high. When the oscillation enable signal is low, the ring oscillator 220 stops outputting the oscillation signal; that is, it is effective when the oscillation enable signal is low.

[0103] When the time for the ring oscillator 220 to generate oscillation signals is fixed, the number of oscillation signals generated by the ring oscillator 220 is only related to the transistor process angle of the ring oscillator 220. When the transistor process angle of the ring oscillator 220 is FF, the ring oscillator 220 generates more oscillation signals. When the transistor process angle of the ring oscillator 220 is SS, the ring oscillator 220 generates fewer oscillation signals.

[0104] In the above technical solution, the time width for the oscillation enable signal to be high is fixed, so the time for the ring oscillator 220 to generate oscillation signals is fixed, making the number of oscillation signals generated by the ring oscillator 220 only related to the transistor process angle. By counting the number of oscillation signals and using the counting result as a pulse width adjustment signal, the pulse width adjustment of the first offset cancellation signal OC based on the transistor process angle can be realized.

[0105] In one embodiment, such as Figure 7 As shown, the oscillation control unit 210 includes a first NOT gate 211, a second NAND gate 212, and a second NOT gate 213. Both the first NOT gate 211 and the second NOT gate 213 have input and output terminals, while the second NAND gate 212 has a first input, a second input, and an output terminal. The first input terminal of the second NAND gate 212 receives the oscillation start signal Rin1, the input terminal of the first NOT gate 211 receives the oscillation stop signal Rin2, the second input terminal of the second NAND gate 212 is connected to the output terminal of the first NOT gate 211, the input terminal of the second NOT gate 213 is connected to the output terminal of the second NAND gate 212, and the output terminal of the second NOT gate 213 serves as the output terminal of the oscillation control unit 210.

[0106] like Figure 8As shown, both the oscillation start signal Rin1 and the oscillation stop signal Rin2 are active high-level pulse signals, and the rising edge of the oscillation start signal Rin1 is earlier than the rising edge of the oscillation stop signal Rin2. When the oscillation start signal Rin1 is high, the first input of the second NAND gate 212 is high, and the oscillation stop signal Rin2 is low. After the first NOT gate 211 performs an inversion operation, the output is high. The second input of the second NAND gate 212 is high, and the output of the second NAND gate 212 is low. After the second NOT gate 213 performs an inversion operation, the output is high, which is the output of the active oscillation enable signal Ro. When the oscillation start signal Rin1 is still high, the first input of the second NAND gate 212 is still high, the oscillation termination signal Rin2 becomes high, and after the first NOT gate 211 performs an inversion operation, it outputs a low level. The second input of the second NAND gate 212 is low, and the second NAND gate 212 outputs a high level. After the second NOT gate 213 passes through it, it outputs a low level, which means it outputs an invalid oscillation enable signal Ro.

[0107] The second NAND gate 212 outputs a valid oscillation enable signal Ro between the rising edge of the oscillation start signal Rin1 and the rising edge of the oscillation stop signal Rin2, and an invalid oscillation enable signal Ro at other times. By making the interval between the rising edge of the oscillation start signal Rin1 and the rising edge of the oscillation stop signal Rin2 a fixed time width, the effective time of the output oscillation enable signal Ro can be made to be a fixed time width.

[0108] In one embodiment, the pulse width adjustment amount of the first-level adjustment submodule 110, the pulse width adjustment amount of the second-level adjustment submodule 110, ..., the pulse width adjustment amount of the nth-level adjustment submodule 110 increase or decrease in a geometric sequence. Then, by counting the oscillation signal generated by the ring oscillator 220, a pulse width adjustment signal is output. This enables the output pulse width adjustment signal to make the pulse width of the second offset cancellation signal OC' smaller when the transistor process corner is FF.

[0109] In one embodiment, the oscillation counter 230 has n output terminals, and the n output terminals of the oscillation counter 230 are labeled as first output terminal, second output terminal, ..., nth output terminal in order from the least significant bit to the most significant bit.

[0110] The first output terminal of the oscillation counter 230 is connected to the control terminal of the first-stage adjustment submodule 110, the second output terminal of the oscillation counter 230 is connected to the control terminal of the second-stage adjustment submodule 110, and so on, with the nth output terminal of the oscillation counter 230 connected to the control terminal of the nth-stage adjustment submodule 110.

[0111] If the first offset cancellation signal OC is a high-level active signal, the pulse width reduction of the first-level adjustment submodule 110, the pulse width reduction of the second-level adjustment submodule 110, ..., the pulse width reduction of the nth-level adjustment submodule 110 increase in a geometric progression, and the oscillation counter 230 is a subtraction counter.

[0112] For example: the first offset cancellation signal OC is a high-level active signal, and the adjustment circuit includes three adjustment sub-modules 110. The pulse width reduction of the first-level adjustment sub-module 110, the pulse width reduction of the second-level adjustment sub-module 110, and the pulse width reduction of the third-level adjustment sub-module 110 are Δt, 2Δt, and 4Δt, respectively.

[0113] Different transistor process corners result in different numbers of oscillation signals generated within a fixed time width. As shown in Table 1, if the number of oscillation signals generated within a fixed time width is 0, then the pulse width adjustment signal is 111, and the three adjustment submodules 110 do not perform pulse width adjustment, so the total pulse adjustment amount of the adjustment circuit is 0.

[0114] If the number of oscillation signals generated within a fixed time width is 7, then the pulse width adjustment signal is 000. The first-level adjustment submodule 110 performs pulse width reduction processing on the first offset elimination signal OC, with a reduction amount of -Δt. The second-level adjustment submodule 110 performs pulse width reduction processing on the output signal of the first-level adjustment submodule 110, with a reduction amount of -2Δt. The third-level adjustment submodule 110 performs pulse width reduction processing on the output signal of the second-level adjustment submodule 110, with a reduction amount of -4Δt. Therefore, the total pulse adjustment amount of the adjustment circuit is -7Δt.

[0115] Table 1 First Relationship Table

[0116] 0 111 0 1 110 -△t 2 101 -2△t 3 100 -3△t 4 011 -4△t 5 010 -5△t 6 001 -6△t 7 000 -7△t

[0117] If the first offset cancellation signal OC is a low-level active signal, the pulse width increase of the first-level adjustment submodule 110, the pulse width increase of the second-level adjustment submodule 110, ..., the pulse width increase of the nth-level adjustment submodule 110 increases in a geometric progression, and the oscillation counter 230 is an adder counter.

[0118] For example, the first offset cancellation signal OC is a low-level active signal, and the adjustment circuit includes three adjustment sub-modules 110. The pulse width increase of the first-level adjustment sub-module 110, the pulse width increase of the second-level adjustment sub-module 110, and the pulse width increase of the third-level adjustment sub-module 110 are Δt, 2Δt, and 4Δt, respectively.

[0119] As shown in Table 2, if the number of oscillation signals generated within a fixed time width is 0, then the pulse width adjustment signal is 000. The first-level adjustment submodule 110 increases the pulse width of the output first offset cancellation signal OC by Δt. The second-level adjustment submodule 110 increases the pulse width of the output signal of the first-level adjustment submodule 110 by 2Δt. The third-level adjustment submodule 110 increases the pulse width of the output signal of the second-level adjustment submodule 110 by 4Δt. Therefore, the total pulse adjustment amount of the adjustment circuit is 7Δt.

[0120] Table 2 Second Relationship Table

[0121] 0 000 +7△t 1 001 +6△t 2 010 +5△t 3 011 +4△t 4 100 +3△t 5 101 +2△t 6 110 +△t 7 111 +0

[0122] In the above technical solution, if the first offset cancellation signal is a high-level active signal and the oscillation counter is a subtraction counter, and if the first offset cancellation signal is a low-level active signal and the oscillation counter is an addition counter, it can be realized that when the transistor process corner is FF, the more oscillation signals there are, the smaller the pulse width of the output pulse width adjustment signal can be made to the second offset cancellation signal OC'.

[0123] Continue to refer to Figure 2 Another embodiment of this application provides a sensitive amplifier, which includes a control module 100 and an amplification module 200. The amplification module 200 includes a first P-type transistor P1, a second P-type transistor P2, a first N-type transistor N1, and a second N-type transistor N2.

[0124] In this configuration, the source of the first P-type transistor P1 is coupled to the first power supply terminal VCC, the gate of the first P-type transistor P1 is connected to the drain of the second P-type transistor P2, the source of the second P-type transistor P2 is connected to the source of the first P-type transistor P1, and the gate of the second P-type transistor P2 is connected to the drain of the first P-type transistor P1.

[0125] The drain of the first N-type transistor N1 is connected to the drain of the first P-type transistor P1 and then to the complementary readout bit line SABLB. The gate of the first N-type transistor N1 is connected to the bit line BL. The source of the first N-type transistor N1 is coupled to the second power supply terminal VSS. The drain of the second N-type transistor N2 is connected to the drain of the second P-type transistor P2 and then to the readout bit line SABLB. The gate of the second N-type transistor N2 is connected to the complementary bit line BLB. The source of the second N-type transistor N2 is connected to the source of the first N-type transistor N1.

[0126] In one embodiment, the amplification module 200 further includes a third N-type transistor N3 and a fourth N-type transistor N4. The drain of the third N-type transistor N3 is connected to the drain of the first N-type transistor N1, the source of the third N-type transistor N3 is connected to the gate of the first N-type transistor N1, and the gate of the third N-type transistor N3 is used to connect to the output terminal of the control module 100. The drain of the fourth N-type transistor N4 is connected to the drain of the second N-type transistor N2, the source of the fourth N-type transistor N4 is connected to the gate of the second N-type transistor N2, and the gate of the fourth N-type transistor N4 is used to connect to the output terminal of the control module 100.

[0127] In one embodiment, the amplification module 200 further includes a fifth N-type transistor N5 and a sixth N-type transistor N6. The drain of the fifth N-type transistor N5 is connected to the drain of the second N-type transistor N2, and the source of the fifth N-type transistor N5 is connected to the gate of the first N-type transistor N1. The gate of the fifth N-type transistor N5 is used to receive the pre-charge signal ISO. The drain of the sixth N-type transistor N6 is connected to the drain of the first N-type transistor N1, and the source of the sixth N-type transistor N6 is connected to the gate of the second N-type transistor N2. The gate of the sixth N-type transistor N6 is used to receive the pre-charge signal ISO.

[0128] In one embodiment, the source of the first P-type transistor P1 is coupled to the first power supply terminal VCC. Alternatively, the source of the first P-type transistor P1 can be directly connected to the first power supply terminal VCC, and the power supply module can control whether the first power supply terminal VCC supplies power to the sensitive amplifier.

[0129] In one embodiment, the amplification module 200 further includes a third P-type transistor P3. The source of the first P-type transistor P1 is coupled to the first power supply terminal VCC. Alternatively, the source of the first P-type transistor P1 can be connected to the first power supply terminal VCC through the third P-type transistor P3. The source of the third P-type transistor P3 is connected to the first power supply terminal VCC, and the drain of the third P-type transistor P3 is connected to the source of the first P-type transistor P1. The third P-type transistor P3 controls the first power supply terminal VCC to supply power to the sensitive amplifier.

[0130] In one embodiment, the source of the first N-type transistor N1 is coupled to the second power supply terminal VSS. Alternatively, the source of the first N-type transistor N1 can be directly connected to the second power supply terminal VSS, and the power supply module can control whether the second power supply terminal VSS supplies power to the sensitive amplifier.

[0131] In one embodiment, the amplification module 200 further includes a seventh N-type transistor N7. The source of the first N-type transistor N1 is coupled to the second power supply terminal VSS. Alternatively, the source of the first N-type transistor N1 can be connected to the second power supply terminal VSS through the seventh N-type transistor N7. The source of the seventh N-type transistor N7 is connected to the second power supply terminal VSS, and the drain of the seventh N-type transistor N7 is connected to the source of the first N-type transistor N1. The seventh N-type transistor N7 controls the second power supply terminal VSS to supply power to the sensitive amplifier.

[0132] like Figure 9 As shown, during the pre-charging phase from time t0 to t1, the pre-charging signal ISO and the second offset cancellation signal OC' are both active. The fifth N-type transistor N5 and the sixth N-type transistor N6 are both turned on, connecting bit line BL and the read bit line SABL, as well as the complementary bit line BLB and the complementary read bit line SABLB. The third N-type transistor N3 and the fourth N-type transistor N4 are also active, connecting bit line BL, read bit line SABL, complementary bit line BLB, and complementary read bit line SABLB. The first power signal SAP and the second power signal SAN are inactive. The third P-type transistor P3 and the seventh N-type transistor N7 are disconnected, and the first power supply terminal VCC and the second power supply terminal VSS are disconnected from the sensitive amplifier. The charging module pulls the voltages of bit line BL, complementary bit line BLB, read bit line SABL, and complementary read bit line SABLB to the charging value.

[0133] During the offset cancellation phase from time t1 to t2, the precharge signal ISO is inactive, the second offset cancellation signal OC' is active, the third N-type transistor N3 and the fourth N-type transistor N4 are turned on, and the first N-type transistor N1 and the second N-type transistor N2 are connected as diodes. The first power supply signal SAP and the second power supply signal SAN are active, the third P-type transistor P3 and the seventh N-type transistor N7 are turned on, and the first power supply terminal VCC and the second power supply terminal VSS are connected to the sensitive amplifier. Compensation voltage Vos is generated on bit line BL and complementary bit line BLB, and compensation voltage Vos is also generated on readout bit line SABL and complementary readout bit line SABLB.

[0134] During the voltage sharing phase from time t2 to t3, the precharge signal ISO and the second offset cancellation signal OC' are both inactive. The third N-type transistor N3 and the fourth N-type transistor N4 are off, the fifth N-type transistor N5 and the sixth N-type transistor N6 are off, the first power signal SAP and the second power signal SAN are inactive, and the third P-type transistor P3 and the seventh N-type transistor N7 are off. The word line signal WL is active, and the memory cell shares charge with the bit line BL or the complementary bit line BLB, presenting a data voltage difference on the bit line BL and the complementary bit line BLB.

[0135] During the pre-read phase (t3 to t4), the pre-charge signal ISO and the second offset cancellation signal OC' are both inactive. The third N-type transistor N3 and the fourth N-type transistor N4 are off, as are the fifth N-type transistor N5 and the sixth N-type transistor N6. The first power supply signal SAP and the second power supply signal SAN are active, while the third P-type transistor P3 and the seventh N-type transistor N7 are on. The first power supply terminal VCC pulls the voltage of the read bit line SABL and the complementary read bit line SABLB based on the data voltage difference on bit line BL and the complementary read bit line BLB. Since a compensation voltage Vos is already present on the read bit line SABL and the complementary read bit line SABLB, during the t3 to t4 phase, the compensation voltage Vos can cancel out the noise caused by the manufacturing difference between the first N-type transistor N1 and the second N-type transistor N2 in the cancellation sensitivity amplifier, accurately presenting the data on the read bit line SABL and the complementary read bit line SABLB.

[0136] During the recovery phase from time t4 to t5, the precharge signal ISO is active, the second offset cancellation signal OC' is inactive, the third N-type transistor N3 and the fourth N-type transistor N4 are off, and the fifth N-type transistor N5 and the sixth N-type transistor N6 are on. The read bit line SABL pulls the bit line BL voltage, and the complementary read bit line SABLB pulls the complementary bit line BLB voltage to restore the stored charge in the memory cell.

[0137] The time interval between the falling edge of the first offset cancellation signal and the falling edge of the precharge signal is determined according to the design parameters of each transistor in the amplification module 200. The pulse width of the second offset cancellation signal OC' is obtained by adjusting the pulse width of the first offset cancellation signal OC based on the transistor process angle. The time interval between the falling edge of the precharge signal ISO and the falling edge of the second offset cancellation signal OC' is the time tOC' during which the compensation voltage Vos is generated on the readout bit line SABL and the complementary readout bit line SABLB. Therefore, the time tOC' during which the compensation voltage Vos is generated is adaptively adjusted based on the speed of the transistor process angle.

[0138] With a transistor process angle of FF, the smaller the pulse width of the second offset cancellation signal OC', the shorter the time tOC' to generate the compensation voltage Vos, and the shorter the conduction time of the third N-type transistor N3 and the fourth N-type transistor N4. At this time, the driving capability of the third N-type transistor N3 and the fourth N-type transistor N4 is stronger. By shortening the conduction time of the third N-type transistor N3 and the fourth N-type transistor N4, it is possible to avoid the first N-type transistor N1 and the second N-type transistor N2 generating excessive compensation voltage Vos on the readout bit line SABL and the readout complementary bit line BLB.

[0139] The transistor process angle is SS. The larger the pulse width of the second offset cancellation signal OC', the longer the time tOC' to generate the compensation voltage Vos, and the longer the conduction time of the third N-type transistor N3 and the fourth N-type transistor N4. At this time, the driving capability of the third N-type transistor N3 and the fourth N-type transistor N4 is weaker. By extending the conduction time of the third N-type transistor N3 and the fourth N-type transistor N4, the first N-type transistor N1 and the second N-type transistor N2 can generate a suitable compensation voltage Vos on the read bit line SABL and the complementary read bit line SABLB.

[0140] In the above technical solution, by adjusting the pulse width of the second offset cancellation signal OC' received by the gates of the third N-type transistor N3 and the fourth N-type transistor N4, the conduction time of the third N-type transistor N3 and the fourth N-type transistor N4 can be adjusted. This can compensate for the different driving capabilities of transistors caused by the transistor process angle, so that a suitable compensation voltage Vos is generated on the readout bit line SABL and the complementary readout bit line SABLB, effectively eliminating the noise introduced by the transistor manufacturing difference and avoiding the introduction of new noise.

[0141] Other embodiments of this application will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.

[0142] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.

Claims

1. A sensitive amplifier, characterized in that, include: The control module includes an input terminal and an output terminal, and is used to adjust the pulse width of the first offset cancellation signal received at its input terminal according to the transistor process corner, and generate and output a second offset cancellation signal through its output terminal. An amplification module, connected to the output of the control module, is used to eliminate the offset noise of the amplification module under the control of the second offset cancellation signal; The control module includes: A parameter generation circuit is used to generate a pulse width adjustment signal based on the transistor process angle of the parameter generation circuit. The adjustment circuit has its control terminal connected to the output terminal of the parameter generation circuit, its input terminal receiving the first offset cancellation signal, and adjusting the pulse width of the first offset cancellation signal according to the pulse width adjustment signal received by its control terminal, and outputting the second offset cancellation signal. The parameter generation circuit includes: Oscillation control unit, used to generate an oscillation enable signal with a fixed time width; A ring oscillator, the control terminal of which is connected to the output terminal of the oscillation control unit, is used to generate an oscillation signal when the oscillation enable signal is received; An oscillation counter, whose input is connected to the output of a ring oscillator, is used to count the number of oscillation signals within the fixed time width and output the pulse width adjustment signal.

2. The sensitive amplifier according to claim 1, characterized in that, The transistor process angle of the ring oscillator is the same as that of the amplification module, and the number of oscillation signals generated within the fixed time width is determined by the transistor process angle of the ring oscillator.

3. The sensitive amplifier according to claim 1 or 2, characterized in that, The ring oscillator includes an odd number of first NAND gates; For each of the first NAND gates, its first input is connected to the output of the first NAND gate in the previous stage, its output is connected to the first input of the first NAND gate in the next stage, and the first input of the first stage first NAND gate is connected to the output of the last stage first NAND gate. The second input terminals of the odd number of first NAND gates are connected to the same node, which serves as the control terminal of the ring oscillator; the output terminal of any one of the first NAND gates serves as the output terminal of the ring oscillator.

4. The sensitive amplifier according to claim 1 or 2, characterized in that, The oscillation control unit is used to output a valid oscillation enable signal after the oscillation start signal arrives, and to output an invalid oscillation enable signal after the oscillation end signal arrives.

5. The sensitive amplifier according to claim 4, characterized in that, The oscillation control unit includes: The second NAND gate circuit receives the oscillation start signal at its first input terminal; The first NOT gate circuit receives the oscillation termination signal at its input terminal; its output terminal is connected to the second input terminal of the second NAND gate circuit. The second NOT gate circuit has its input terminal connected to the output terminal of the second NAND gate circuit, and its output terminal serves as the output terminal of the oscillation control unit.

6. The sensitive amplifier according to claim 1 or 2, characterized in that, The parameter generation circuit includes multiple output terminals, and the pulse width adjustment signal includes multiple pulse width adjustment sub-signals. The output terminals of the parameter generation circuit output the pulse width adjustment sub-signals respectively. The adjustment circuit includes multiple adjustment sub-modules connected in cascade. The control terminal of each adjustment submodule is connected to one output terminal of the parameter generation circuit; The first-level adjustment submodule receives the first offset cancellation signal and is used to adjust the pulse of the first offset cancellation signal according to the received pulse width adjustment sub-signal; Each of the remaining adjustment submodules receives the output signal of the previous adjustment submodule and adjusts the pulse of the output signal of the previous adjustment submodule according to the pulse width adjustment sub-signal received at its control terminal; the output signal of the last adjustment submodule is the second offset cancellation signal.

7. The sensitive amplifier according to claim 6, characterized in that, Each of the aforementioned adjustment submodules includes: The delay unit has its input terminal serving as the input terminal of the adjustment submodule; An OR gate circuit, whose first input is connected to the output of the delay unit, and whose second input serves as the control terminal of the adjustment submodule; An AND gate circuit, whose first input is connected to the input of the delay unit, whose second input is connected to the output of the OR gate circuit, and whose output serves as the output of the adjustment submodule.

8. The sensitive amplifier according to claim 6, characterized in that... ； If the first offset cancellation signal is a high-level active signal, the oscillation counter is a down counter; If the first offset cancellation signal is a low-level active signal, the oscillation counter is an adder counter.

9. The sensitive amplifier according to claim 1 or 2, characterized in that, The amplification module includes: The first P-type transistor has its source coupled to the first power supply terminal and its gate connected to the drain of the second P-type transistor. The second P-type transistor has its source connected to the source of the first P-type transistor and its gate connected to the drain of the first P-type transistor. The first N-type transistor has its drain connected to the drain of the first P-type transistor and then connected to the complementary readout bit line, its gate connected to the bit line, and its source coupled to the second power supply terminal. The second N-type transistor has its drain connected to the drain of the second P-type transistor and then connected to the readout bit line, its gate connected to the complementary bit line, and its source connected to the source of the first N-type transistor. The third N-type transistor has its drain connected to the drain of the first N-type transistor and its source connected to the bit line; its gate is turned on when the second offset cancellation signal is received. The fourth N-type transistor has its drain connected to the drain of the second N-type transistor and its source connected to the complementary bit line; its gate is turned on when the second offset cancellation signal is received.

10. The sensitive amplifier according to claim 9, characterized in that, The process angles of the third N-type transistor, the fourth N-type transistor, and the ring oscillator are the same.

11. The sensitive amplifier according to claim 9, characterized in that, The amplification module also includes: The fifth N-type transistor has its drain connected to the drain of the second N-type transistor, its source connected to the bit line, and its gate used to receive a pre-charge signal and to be turned on under the control of the pre-charge signal. The sixth N-type transistor has its drain connected to the drain of the first N-type transistor and its source connected to the complementary bit line; its gate is used to receive a pre-charge signal and is used to turn on under the control of the pre-charge signal.

12. The sensitive amplifier according to claim 11, characterized in that, The time interval between the falling edge of the first offset cancellation signal and the falling edge of the precharge signal is preset.

13. The sensitive amplifier according to claim 9, characterized in that, The amplification module also includes: The third P-type transistor has its source connected to the first power supply terminal and its drain connected to the source of the first P-type transistor. The seventh N-type transistor has its source connected to the second power supply terminal and its drain connected to the source of the first N-type transistor.

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