Signal receiving circuit, memory and control method

Abstract

The present disclosure provides a signal receiving circuit, a memory and a control method. The circuit comprises a receiving unit and a bypass unit. The receiving unit is configured to transmit an input signal to the bypass unit in an open state. The bypass unit is coupled to the receiving unit and an internal circuit. When the receiving unit is open, the bypass unit is configured to output a final signal consistent with the input signal and the bypass signal to the internal circuit. When the receiving unit is closed, the bypass unit is configured to output a final signal consistent with the input signal and the bypass signal to the internal circuit. The present scheme can avoid affecting the receiving unit during the aging test.

Description

Technical Field

[0001] This disclosure relates to memory technology, and more particularly to a signal receiving circuit, a memory, and a control method. Background Technology

[0002] With the development of memory technology, memory has been widely used in many fields. For example, Dynamic Random Access Memory (DRAM) is widely used.

[0003] In related technologies, considering the reliability of memory, aging tests, also known as burn-in tests, are performed on the memory. However, prolonged high-temperature and high-pressure testing may affect the signal receiving unit of the memory. Summary of the Invention

[0004] Embodiments of this disclosure provide a signal receiving circuit, a memory, and a control method.

[0005] According to some embodiments, a first aspect of this disclosure provides a signal receiving circuit, including: a receiving unit and a bypass unit; the receiving unit is configured to transmit an input signal to the bypass unit in an on state; the bypass unit is coupled to the receiving unit and an internal circuit, and is configured to, when the receiving unit is on, output a final signal consistent with the input signal to the internal circuit based on the input signal and a bypass signal; and, when the receiving unit is off, output a final signal consistent with the input signal to the internal circuit based on the bypass signal.

[0006] In some embodiments, the bypass unit includes: a logic gate; the input of the logic gate is connected to the output of the receiving unit and the bypass signal, and the output of the logic gate is connected to the internal circuit; the logic gate is configured to perform logical operations on the input signal output by the receiving unit and the bypass signal when the receiving unit is turned on, and output a signal consistent with the input signal; and to perform logical operations on the bypass signal when the receiving unit is turned off, and output a signal consistent with the current input signal.

[0007] In some embodiments, the logic gate includes an OR gate; the first input of the OR gate is connected to the output of the receiving unit, the second input of the OR gate is connected to the bypass signal, and the output of the OR gate is connected to the internal circuit; wherein, when the receiving unit is turned on, the bypass signal is fixed at a low level; when the receiving unit is turned off, the bypass signal is consistent with the input signal.

[0008] In some embodiments, the logic gate includes an XOR gate; the first input terminal of the XOR gate is connected to the output terminal of the receiving unit, the second input terminal of the XOR gate is connected to the bypass signal, and the output terminal of the XOR gate is connected to the internal circuit; wherein, when the receiving unit is turned on, the bypass signal is fixed at a high level; when the receiving unit is turned off, the bypass signal is the inverted signal of the input signal.

[0009] In some embodiments, the logic gate further includes a NOT gate; the input terminal of the NOT gate is connected to the input signal, and the NOT gate is used to generate the bypass signal when the receiving unit is turned off.

[0010] In some embodiments, the bypass unit includes: a data selector; the input terminal of the data selector is connected to the output terminal of the receiving unit and the bypass signal, and the output terminal of the data selector is connected to the internal circuit; the data selector is used to select to output the signal output by the receiving unit or the bypass signal according to a control signal; wherein, when the receiving unit is turned off, the bypass signal is consistent with the input signal.

[0011] In some embodiments, the circuit further includes: a control module; the control module, connected to the data selector, is configured to output a control signal of a first level state to the data selector when the receiving unit is turned on; and to output a control signal of a second level state to the data selector when the receiving unit is turned off; the data selector is configured to select the signal output by the receiving unit according to the control signal of the first level state; and to select the bypass signal according to the control signal of the second level state.

[0012] In some embodiments, the input signal includes a clock signal or a chip select signal.

[0013] In some embodiments, the circuit further includes: a signal generation module; the signal generation module is connected to the bypass unit and is used to output the bypass signal according to the bypass control signal.

[0014] In some embodiments, the signal generation module includes a register.

[0015] According to some embodiments, a second aspect of this disclosure provides a memory, including: a signal receiving circuit and an internal circuit as described in any of the foregoing descriptions; wherein the signal receiving circuit is configured to receive an input signal and output a final signal consistent with the input signal; and the internal circuit, connected to the signal receiving circuit, is configured to perform a corresponding operation based on the final signal and an operation instruction.

[0016] In some embodiments, the number of signal receiving circuits is multiple, and the multiple signal receiving circuits are configured to correspond to multiple input signals.

[0017] According to some embodiments, a third aspect of this disclosure provides a control method for a signal receiving circuit, applied to any of the signal receiving circuits described above. The method includes: determining the current state of a receiving unit, the state including an on state or an off state; and controlling the level state of a bypass signal according to the current state of the receiving unit, so that the final signal output by the bypass unit to the internal circuit is consistent with the input signal.

[0018] In some embodiments, the bypass unit includes an OR gate; the first input of the OR gate is connected to the output of the receiving unit, the second input of the OR gate is connected to the bypass signal, and the output of the OR gate is connected to the internal circuit; controlling the level of the bypass signal according to the current state of the receiving unit includes: if the receiving unit is in an on state, controlling the bypass signal to be fixed at a low level; if the receiving unit is in a off state, controlling the bypass signal to be consistent with the input signal.

[0019] In some embodiments, the bypass unit includes: an XOR gate; the first input terminal of the XOR gate is connected to the output terminal of the receiving unit, the second input terminal of the XOR gate is connected to the bypass signal, and the output terminal of the XOR gate is connected to the internal circuit; controlling the level state of the bypass signal according to the current state of the receiving unit includes: if the receiving unit is in the on state, controlling the bypass signal to be fixed at a high level; if the receiving unit is in the off state, controlling the bypass signal to be the inverted signal of the input signal.

[0020] In some embodiments, the bypass unit includes: a data selector; the input terminal of the data selector is connected to the output terminal of the receiving unit and the bypass signal, and the output terminal of the data selector is connected to the internal circuit; controlling the level state of the bypass signal according to the current state of the receiving unit includes: if the receiving unit is in a closed state, controlling the bypass signal to be consistent with the input signal.

[0021] In some embodiments, the signal receiving circuit further includes: a signal generation module; the signal generation module is connected to the bypass unit and is used to output the bypass signal according to a bypass control signal; the step of controlling the level state of the bypass signal according to the current state of the receiving unit includes: controlling the level state of the bypass signal output by the signal generation module by outputting a corresponding bypass control signal according to the current state of the receiving unit.

[0022] The signal receiving circuit, memory, and control method provided in this disclosure include a receiving unit and a bypass unit. When the receiving unit is turned on, the input signal can be transmitted to the bypass unit through the receiving unit. The bypass unit outputs a signal consistent with the input signal to the internal circuit based on the input signal and a bypass signal. When the receiving unit is turned off, the bypass unit outputs a signal consistent with the input signal to the internal circuit based on the bypass signal. In this solution, the receiving unit can be turned off as needed, such as during aging tests. Even when the receiving unit is turned off, it can still output a signal consistent with the original input signal to the internal circuit, thereby supporting the normal operation of the memory. This solution is well-suited for aging test scenarios and avoids affecting the receiving unit during the aging test process. Attached Figure Description

[0023] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of the embodiments of this disclosure.

[0024] Figure 1 This is an example diagram of the architecture of a memory shown in one embodiment of this disclosure;

[0025] Figure 2 This is a structural example diagram of a storage cell shown in one embodiment of the present disclosure;

[0026] Figure 3 A flowchart illustrating the aging test process;

[0027] Figure 4 A structural example diagram of a signal receiving circuit provided in one embodiment;

[0028] Figure 5 This is an example diagram of a signal receiving unit in related technologies;

[0029] Figure 6 A structural example diagram of a signal receiving circuit provided in one embodiment;

[0030] Figure 7a Example diagram of a signal state when the receiving unit is turned on;

[0031] Figure 7b This is an example diagram of another signal state when the receiving unit is turned on;

[0032] Figure 7c Example diagram of a signal state when the receiving unit is turned off;

[0033] Figure 7d This is an example diagram of another signal state when the receiving unit is turned off;

[0034] Figure 8A structural example diagram of a signal receiving circuit provided in one embodiment;

[0035] Figure 9a Example diagram of a signal state when the receiving unit is turned on;

[0036] Figure 9b This is an example diagram of another signal state when the receiving unit is turned on;

[0037] Figure 9c Example diagram of a signal state when the receiving unit is turned off;

[0038] Figure 9d This is an example diagram of another signal state when the receiving unit is turned off;

[0039] Figure 10 A structural example diagram of a signal receiving circuit provided in one embodiment;

[0040] Figure 11 A structural example diagram of a signal receiving circuit provided in one embodiment;

[0041] Figure 12 An example structural diagram of a memory provided in an embodiment of this disclosure;

[0042] Figure 13 This is a flowchart illustrating a control method for a signal receiving circuit provided in an embodiment of the present disclosure.

[0043] The accompanying drawings have illustrated specific embodiments of this disclosure, which will be described in more detail below. These drawings and descriptions are not intended to limit the scope of the concept in any way, but rather to illustrate the concepts of this disclosure to those skilled in the art through reference to particular embodiments. Detailed Implementation

[0044] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numerals in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this disclosure. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this disclosure as detailed in the appended claims.

[0045] The terms “comprising” and “having” in this disclosure are used to indicate an open-ended inclusion, meaning that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms “first” and “second”, etc., are used only as illustrative marks and are not intended to limit the number of objects. Furthermore, the different elements and areas in the accompanying drawings are only schematic, and therefore this disclosure is not limited to the dimensions or distances shown in the drawings.

[0046] The technical solutions of this disclosure will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of this disclosure will now be described with reference to the accompanying drawings.

[0047] Figure 1 This is an example diagram of the memory architecture shown in one embodiment of this disclosure, such as... Figure 1 As shown, taking DRAM as an example, it includes data input / output buffers, row decoders, column decoders, sense amplifiers, and a memory array. The memory array mainly consists of rows and columns. The memory cells of the memory array are located where a row intersects with a bit line along the row direction of the array.

[0048] Each storage unit is used to store one bit of data. For example... Figure 2 As shown, Figure 2 This is a structural example diagram of a memory cell according to an embodiment of the present disclosure. The memory cell mainly consists of a transistor switch M and a capacitor C. The capacitor is used to store bit data, and the transistor switch is used to turn off or on depending on the selected state.

[0049] Access to a memory cell can be achieved by controlling rows and columns. Taking a read scenario as an example: when bit data needs to be read from a memory cell, the row decoder selects the row (word line) containing that memory cell. Correspondingly, transistor switch M in the diagram turns on, and the state of capacitor C is detected by sensing and amplifying the column (bit line) signal. For example, if the bit data stored in the memory cell is 1, then after transistor switch M turns on, 1 will be read from the bit line of the memory cell, and vice versa. Furthermore, taking a write scenario as an example: when bit data needs to be written to a memory cell, such as writing 1, the row decoder selects the row (word line) containing that memory cell, and the corresponding transistor switch M in the diagram turns on. By setting the logic level of the column (bit line) to 1, capacitor C is charged, thus writing 1 to the memory cell. Conversely, to write 0, the logic level of the bit line is set to 0, causing capacitor C to discharge, thus writing 0 to the memory cell.

[0050] In practical applications, to ensure the reliability of memory, various tests are conducted, such as aging tests. Specifically, during the manufacturing process of electronic products, especially highly integrated devices like memory, multiple processes can introduce various defects, such as obvious defects and potential defects. Obvious defects mainly refer to defects that cause the product to malfunction, such as short circuits / open circuits. Potential defects mainly refer to defects that allow the product to be used temporarily but may quickly become apparent during use, ultimately leading to the product's malfunction, such as insufficient solder.

[0051] Obvious defects can be detected through conventional inspection methods, while potential defects can be identified using aging tests. Furthermore, aging tests can be applied to product improvement; for example, if an aging test reveals that a component frequently fails, the easily damaged component can be replaced or improved, thereby improving product quality. As an example, the aging test procedure can be found in [link to aging test procedure]. Figure 3 , Figure 3 The flowchart for aging testing can be roughly divided into three stages: initialization, inputting test signals to execute parallel tests (PARA Mode Entry), and reading test results. In this process, the input test signals are received through the memory's signal receiving unit. Correspondingly, the memory's internal circuitry receives the test signals and performs the corresponding operations. The actual execution results are then used to determine whether the memory is functioning correctly, thus achieving the aging test.

[0052] However, this approach reveals that aging tests can impact the signal receiving unit of the memory. Specifically, since aging tests are typically conducted under high temperature and high pressure conditions, prolonged exposure to these conditions can damage the structure of the memory's signal receiving unit. To protect the signal receiving unit, the approach considers disabling it during aging tests. However, once the signal receiving unit is disabled, it cannot receive test signals, rendering the test impossible.

[0053] Some aspects of the embodiments of this disclosure relate to the above considerations. The following describes the solutions by way of example with reference to some embodiments of this disclosure.

[0054] Example 1

[0055] Figure 4 A structural example diagram of a signal receiving circuit provided in one embodiment is shown below. Figure 4 As shown, the signal receiving circuit includes a receiving unit 41 and a bypass unit 42;

[0056] The receiving unit 41 is used to transmit the input signal to the bypass unit when it is in the enabled state;

[0057] The bypass unit 42, coupled to the receiving unit 41 and the internal circuit 43, is used to output a final signal consistent with the input signal to the internal circuit 43 based on the input signal and the bypass signal when the receiving unit 41 is turned on; and to output a final signal consistent with the input signal to the internal circuit 43 based on the bypass signal when the receiving unit 41 is turned off.

[0058] In practical applications, the signal receiving circuit provided in this embodiment can be used in various memories. As an example, the power mapping detection method can be applied to Double Data Rage RAM (DDR), including but not limited to Double Data Rage RAM.

[0059] The internal circuitry includes the module circuits that perform processing within the memory. For example, the signal receiving circuit, belonging to the peripheral area circuitry, is used to receive external signals. The signal receiving unit transmits the received signals to the corresponding internal circuitry in the memory, where the internal circuitry performs processing based on the received signals. In a practical scenario, in a DRAM system, commands, addresses, and data issued by the memory controller all need to be received by a specific receiver unit to convert the received signals into a full-swing signal more suitable for processing by the internal circuitry. This signal can be a full-swing digital logic signal. Figure 5 Example Figure 5 This is an example diagram of a signal receiving unit in related technologies. Based on the example in the diagram, it can be understood that the signal receiving unit can be understood as the external receiving module of the memory, used to receive external signals and transmit them to the internal circuitry. In practical applications, the signal receiving unit can be located between the memory pins and the internal circuitry.

[0060] In practical applications, due to the diverse operating environments of memory, such as the need for a series of processes including fabrication, simulation testing, and aging testing before normal use, this embodiment found that during these processes, such as aging testing, the signal receiving unit may be damaged, thus affecting the normal operation of the memory after the aging test. Considering this, an attempt was made to disable the memory's signal receiving unit in the early stages, such as during aging testing, to avoid damage. However, it is also necessary to consider how to ensure normal signal input to the memory's internal circuitry during the testing phase.

[0061] As an example, the signal receiving circuit in this embodiment includes a receiving unit and a bypass unit. The receiving unit can perform functions similar to those of signal receiving units in related technologies, such as performing the aforementioned full-swing signal processing on the input signal. Specific methods can be found in related technologies and will not be detailed here. The characteristic of the signal receiving circuit in this embodiment is that, in addition to the receiving unit, a bypass circuit is also provided. Through the cooperative operation of the receiving unit and the bypass unit, the signal receiving circuit can output a final signal consistent with the original input signal that needs to be input to the internal circuit, regardless of whether the receiving unit is on or off. This is also referred to as the new output signal in this document. Here, "input signal" refers to the signal that needs to be input to the memory, such as instructions and data sent by the memory controller to the memory. In one example, the input signal includes, but is not limited to, a clock signal or a chip select signal.

[0062] To illustrate with a practical example: Under normal conditions, the memory can normally power on the receiving unit 41. Once powered on, the receiving unit 41 transmits the received input signal normally to the bypass unit 42. Correspondingly, one input of the bypass unit 42 is the input signal transmitted from the receiving unit 41 to the bypass unit 42. Additionally, the bypass unit 42 has another input, a bypass signal. Based on these two inputs—the input signal and the bypass signal—the bypass unit 42 outputs a final signal consistent with the input signal, which is then provided to the internal circuit 43. The internal circuit 43 performs relevant processing based on the signal provided by the bypass unit 42. Furthermore, under testing conditions, such as aging tests, the receiving unit 41 can be powered off to avoid damaging the receiving unit. When the receiving unit 41 is powered off, it cannot transmit input signals to the bypass unit 42. Correspondingly, the bypass unit 42 outputs a final signal consistent with the input signal based on the received bypass signal, which is then provided to the internal circuit 43. The internal circuit 43 performs relevant processing based on the signal provided by the bypass unit 42. Figure 4 The dashed line between the receiving unit 41 and the bypass unit 42 indicates that when the receiving unit 41 is turned on, it can transmit signals to the bypass unit 42, and when the receiving unit 41 is turned off, it stops transmitting signals to the bypass unit 42.

[0063] Because the bypass circuit outputs a signal identical to the input signal, it can support the normal processing and operation of the memory's internal circuitry. Here, "identical" means that the logic state is the same. For example, if the input signal is a high-level signal, the final signal output by the bypass circuit will also be a high-level signal; however, the voltage value or swing of the two signals may be the same or different. One scenario is that, in aging test scenarios, the signal provided to the internal circuitry can accurately characterize the signal's logic state to support memory testing. Since the test scenario is not the memory's typical operating environment, when the receiving unit is off, the bypass unit can output a signal with a different voltage value or swing than the input signal. This allows for testing of the memory's internal circuitry without the need for additional signal swing processing circuitry, thus simplifying the circuit structure.

[0064] It is understood that in the signal receiving circuit of this embodiment, when the receiving unit is turned on, the bypass unit outputs the final signal to the internal circuit based on the input signal provided by the receiving unit and the received bypass signal; when the receiving unit is turned off, the receiving unit cannot transmit the received input signal to the bypass unit, and the bypass unit outputs the final signal to the internal circuit based on the received bypass signal. The final signal is consistent with the current input signal.

[0065] The following examples illustrate the specific structure of the bypass unit:

[0066] In some examples, the bypass unit 42 can be implemented by logic gates. Therefore, based on the aforementioned examples, the bypass unit 42 includes: logic gates;

[0067] The input terminal of the logic gate is connected to the output terminal of the receiving unit 41 and the bypass signal, and the output terminal of the logic gate is connected to the internal circuit 43.

[0068] The logic gate is used to perform logical operations on the input signal and the bypass signal output by the receiving unit 41 when the receiving unit 41 is turned on, and output a signal consistent with the input signal; and to perform logical operations on the bypass signal when the receiving unit 41 is turned off, and output a signal consistent with the current input signal.

[0069] Logic gates are fundamental components of integrated circuits. Simple logic gates can be composed of transistors. Combinations of these transistors can perform logical operations on input signals, generating high-level or low-level signals. For example, high and low levels can represent logical "true" and "false" or binary 1 and 0, respectively, thus implementing logical operations. In practical applications, logic gates in memory can have all components and connecting wires fabricated on a semiconductor substrate, forming integrated logic gate circuits to reduce product size.

[0070] In this example, the bypass unit 42 is implemented using logic gates. Specifically, when the receiving unit 41 is on, the logic gate performs logical operations on the input signal output by the receiving unit 41 and the received bypass signal based on the input signal provided by the receiving unit 41 and the received bypass signal, outputting a signal consistent with the input signal. When the receiving unit 41 is off, the receiving unit 41 cannot transmit the received input signal to the logic gate, and the logic gate then performs logical operations on the bypass signal, outputting the final signal to the internal circuitry. The aforementioned logic gate can output a signal consistent with the input signal through logical operations based on the on or off state of the receiving unit, providing it to the internal circuitry of the memory. Constructing the bypass unit using logic gates can improve circuit integration, simplify the circuit, and reduce its size.

[0071] The logic gates include, but are not limited to, gate circuits used to implement the above-described logical operations. As one implementation method, such as... Figure 6 As shown, Figure 6 This is a structural example diagram of a signal receiving circuit provided in one embodiment, wherein the logic gate includes: OR gate 61;

[0072] The first input terminal of OR gate 61 is connected to the output terminal of receiving unit 41, the second input terminal of OR gate 61 is connected to the bypass signal, and the output terminal of OR gate is connected to internal circuit 43.

[0073] Specifically, when the receiving unit 41 is turned on, the bypass signal is fixed at a low level; when the receiving unit 41 is turned off, the bypass signal is consistent with the input signal.

[0074] Let's illustrate this with a real-world example: In one scenario, such as when the memory is operating normally, the receiving unit can be in the ON state. When the receiving unit is ON, one possibility is that the input signal is high-level. Accordingly, considering... Figure 7a Example Figure 7a This is an example diagram showing a signal state when the receiving unit is turned on. The receiving unit 41 receives a high-level input signal (e.g., represented by "1" in the diagram) and transmits the high-level input signal to the OR gate 61. Since the receiving unit 41 is turned on at this time, the bypass signal is fixed to a low-level signal (e.g., represented by "0" in the diagram). Accordingly, for the OR gate 61, the input signal "1" provided by the receiving unit 41 and the received bypass signal "0" are ORed logically, and the output is a final signal of "1", which is consistent with the logical state of the input signal.

[0075] When the receiving unit is enabled, another scenario is that the input signal is low, and correspondingly, combined with... Figure 7b Example Figure 7bThis is an example diagram of another signal state when the receiving unit is turned on. The receiving unit 41 receives a low-level input signal (e.g., represented by "0" in the diagram) and transmits the low-level input signal to the OR gate 61. Since the receiving unit 41 is turned on at this time, the bypass signal is fixed to a low-level signal (e.g., represented by "0" in the diagram). Accordingly, for the OR gate 61, the input signal "0" provided by the receiving unit 41 and the received bypass signal "0" are subjected to an OR logic operation, and the output is a final signal of "0", which is consistent with the logic state of the input signal.

[0076] In another scenario, such as when the memory is undergoing aging testing, the receiving unit is turned off. When the receiving unit is off, one possibility is that the input signal is high-level, and correspondingly, combined with... Figure 7c Example Figure 7c This is an example diagram of a signal state when the receiving unit is off. The receiving unit 41 does not transmit the high-level input signal to the OR gate 61. Since the receiving unit 41 is off at this time, the bypass signal is consistent with the input signal. Accordingly, for the OR gate 61, receiving the bypass signal "1" results in a final signal with an output of "1", which is consistent with the logic state of the input signal.

[0077] In the case where the receiving unit is off, another scenario is that the input signal is low-level, and correspondingly, combined with... Figure 7d Example Figure 7d This is an example diagram of another signal state when the receiving unit is off. The receiving unit 41 does not transmit the low-level input signal to the OR gate 61. Since the receiving unit 41 is off at this time, the bypass signal is consistent with the input signal. Accordingly, for the OR gate 61, receiving the bypass signal "0" results in a final signal with an output of "0", which is consistent with the logic state of the input signal.

[0078] In the signal receiving circuit of this example, the bypass unit includes an OR gate. When the receiving unit is on, the bypass signal is fixed at a low level. When the receiving unit is off, the bypass signal is consistent with the input signal. This allows the OR gate to output a final signal consistent with the input signal to the internal circuit regardless of whether the receiving unit is on or off. This enables the circuit to adapt to signal input in different scenarios, avoids damage to the receiving unit, and simplifies the circuit structure and reduces product size by implementing the bypass unit through the OR gate.

[0079] An example of implementing a bypass unit based on logic gates, as another implementation method, is as follows: Figure 8 As shown, Figure 8 The diagram shows a structural example of a signal receiving circuit provided in one embodiment, wherein the logic gate includes: an XOR NOT gate 62;

[0080] The first input terminal of the XOR gate 62 is connected to the output terminal of the receiving unit 41, the second input terminal of the XOR gate 62 is connected to the bypass signal, and the output terminal of the XOR gate 62 is connected to the internal circuit 43.

[0081] When the receiving unit 41 is turned on, the bypass signal is fixed at a high level; when the receiving unit 41 is turned off, the bypass signal is the inverted signal of the input signal.

[0082] Let's illustrate this with a real-world example: In one scenario, such as when the memory is operating normally, the receiving unit can be in the ON state. When the receiving unit is ON, one possibility is that the input signal is high-level. Accordingly, considering... Figure 9a Example Figure 9a This is an example diagram showing a signal state when the receiving unit is turned on. The receiving unit 41 receives a high-level input signal (e.g., represented by "1" in the diagram) and transmits the high-level input signal to the XOR gate 62. Since the receiving unit 41 is turned on at this time, the bypass signal is fixed as a high-level signal (e.g., represented by "1" in the diagram). Correspondingly, for the XOR gate 62, the input signal "1" provided by the receiving unit 41 and the received bypass signal "1" are subjected to an XOR NOT logical operation, and the output is a final signal of "1". This final signal is consistent with the logical state of the input signal.

[0083] When the receiving unit is enabled, another scenario is that the input signal is low, and correspondingly, combined with... Figure 9b Example Figure 9b This is an example diagram of another signal state when the receiving unit is turned on. The receiving unit 41 receives a low-level input signal (e.g., represented by "0" in the diagram) and transmits the low-level input signal to the XOR gate 62. Since the receiving unit 41 is turned on at this time, the bypass signal is fixed to a high-level signal (e.g., represented by "1" in the diagram). Correspondingly, for the XOR gate 62, the input signal "0" provided by the receiving unit 41 and the received bypass signal "1" are subjected to an XOR NOT logical operation, and the output is a final signal of "0", which is consistent with the logical state of the input signal.

[0084] In another scenario, such as when the memory is undergoing aging testing, the receiving unit is turned off. When the receiving unit is off, one possibility is that the input signal is high-level, and correspondingly, combined with... Figure 9c Example Figure 9cThis is an example diagram of a signal state when the receiving unit is off. The receiving unit 41 does not transmit a high-level input signal (e.g., represented by "1" in the diagram) to the XOR gate 62. Since the receiving unit 41 is off at this time, the bypass signal is opposite to the input signal. Accordingly, for the XOR gate 62, receiving the bypass signal "0" results in a final signal with an output of "1", which is consistent with the logic state of the input signal.

[0085] In the case where the receiving unit is off, another scenario is that the input signal is low-level, and correspondingly, combined with... Figure 9d Example Figure 9d This is an example diagram of another signal state when the receiving unit is off. The receiving unit 41 does not transmit a low-level input signal (e.g., represented by "0" in the diagram) to the XOR gate 62. Since the receiving unit 41 is off at this time, the bypass signal is opposite to the input signal. Accordingly, for the XOR gate 62, receiving the bypass signal "1" results in a final signal with an output of "0", which is consistent with the logic state of the input signal.

[0086] In practical applications, in order to generate a bypass signal opposite to the input signal, in one example, the logic gate further includes a NOT gate;

[0087] The input terminal of the NOT gate is connected to the input signal, and the NOT gate is used to generate the bypass signal when the receiving unit is turned off.

[0088] As an example, the NOT gate can be a controllable NOT gate, such as a tri-state NOT gate. When the receiving unit is turned on, the tri-state NOT gate can be controlled to not work, and the bypass signal can be connected to a fixed high level through a first path. A switch can be set on this first path, and the switch is in the on state at this time. When the receiving unit is turned off, the tri-state gate is controlled to output a signal opposite to the input signal. The bypass signal can be connected to the output of the tri-state NOT gate through a second path. Correspondingly, the switch on the first path is controlled to switch to the off state, thereby cooperating with the above signal receiving circuit to realize memory signal input adapted to different scenarios.

[0089] In the signal receiving circuit of this example, the bypass unit includes an XOR gate. When the receiving unit is turned on, the bypass signal is fixed at a high level. When the receiving unit is turned off, the bypass signal is opposite to the input signal. This ensures that the XOR gate can output a final signal consistent with the input signal to the internal circuit regardless of whether the receiving unit is turned on or off. This allows for signal input to be adapted to different scenarios, avoids damage to the receiving unit, and simplifies the circuit structure and reduces product size by implementing the bypass unit through the XOR gate.

[0090] In some examples, the bypass unit 42 can be implemented using a data selector; therefore, based on the aforementioned examples, such as... Figure 10 As shown, Figure 10 This is a structural example diagram of a signal receiving circuit provided in one embodiment. The bypass unit 42 includes: a data selector 63;

[0091] The input terminal of the data selector 63 is connected to the output terminal of the receiving unit 41 and the bypass signal, and the output terminal of the data selector 63 is connected to the internal circuit 43.

[0092] The data selector 63 is used to select the signal output by the output receiving unit 41 or the bypass signal according to the control signal; wherein, when the receiving unit 41 is turned off, the bypass signal is consistent with the input signal.

[0093] The logic function of the data selector is to select one data source as the output signal from multiple data sources under the control of the control signal. In this example, the bypass unit is implemented through the data selector. Specifically, when the receiving unit 41 is turned on, it transmits the received input signal to the data selector 63. At this time, the data selector 63 can choose to output the input signal and provide it to the internal circuit 43 of the memory. It should be noted that the bypass signal is not output by the data selector at this time, so the level of the bypass signal is not limited. For example, the bypass signal may not be input to the data selector, or the bypass signal may be any fixed level, or the input signal may always be consistent with the input signal, etc.

[0094] When the receiving unit 41 is turned off, the receiving unit does not transmit the input signal to the data selector 63. The data selector 63 can select to output a bypass signal. The bypass signal is consistent with the input signal. Therefore, the final signal output by the data selector 63 is consistent with the input signal. This final signal is provided to the internal circuit 43 of the memory.

[0095] In order to achieve accurate control of the data selector when the receiving unit is in different states, in one example, the signal receiving circuit further includes: a control module 64;

[0096] The control module 64, connected to the data selector 63, is used to output the control signal of the first level state to the data selector 63 when the receiving unit 41 is turned on; and to output the control signal of the second level state to the data selector 63 when the receiving unit 41 is turned off.

[0097] The data selector 63 is used to select the signal output by the output receiving unit 41 according to the control signal in the first level state; and to select the bypass signal according to the control signal in the second level state.

[0098] The control module generates control signals for the data selector. These control signals have different voltage levels. Specifically, when the receiving unit 41 is on, the control module 64 provides a first-level control signal to the data selector 63 to select the output signal of the receiving unit 41 (i.e., the input signal after passing through the receiving unit) and output it to the internal circuit 43. When the receiving unit 41 is off, the control module 64 provides a second-level control signal to the data selector 63 to select a bypass signal consistent with the input signal and output it to the internal circuit 43. The first and second voltage levels are different; for example, the first voltage level can be high and the second voltage level can be low, or vice versa.

[0099] In this example signal receiving circuit, a bypass unit is implemented using a data selector. Based on the on / off state of the receiving unit, the data selector selects either the input signal output by the receiving unit or a bypass signal that matches the input signal. Constructing a bypass unit using a data selector improves circuit integration, simplifies fabrication, and facilitates device updates and maintenance by using conventional circuit modules.

[0100] In practical applications, bypass signals for different scenarios can be generated using circuit modules, such as bypass signals when the receiving unit is on or off. In one example, such as... Figure 11 As shown, Figure 11 The diagram shows a structural example of a signal receiving circuit provided in one embodiment. Based on any of the foregoing examples, the signal receiving circuit further includes: a signal generation module 65;

[0101] The signal generation module 65 is connected to the bypass unit 42 and is used to output the bypass signal according to the bypass control signal.

[0102] As an example, the signal generation module may include a register. Specifically, a bypass signal can be generated using a register with set-to-0 and set-to-1 functions. The register can be pre-set with a signal generation strategy based on the states of the bypass signals in different situations as described in the foregoing examples. When the signal receiving circuit is operating, the bypass signals required for different situations are generated according to the pre-set signal generation strategy.

[0103] It should be noted that the aforementioned examples can be implemented individually or in combination. For example, when the bypass unit is implemented as an XOR gate, the bypass unit can also be further provided by a signal generation module. Specifically, in the example where the bypass unit is an XOR gate, when the receiving unit is on, the bypass signal is fixed at a high level; when the receiving unit is off, the bypass signal is the inverted signal of the input signal. In one example, when the receiving unit is on, the bypass signal can be provided by the signal generation module, i.e., fixed at a high level; when the receiving unit is off, the bypass signal opposite to the input signal can be provided by the NOT gate.

[0104] The signal receiving circuit provided in this embodiment includes a receiving unit and a bypass unit. When the receiving unit is turned on, the input signal can be transmitted to the bypass unit through the receiving unit. The bypass unit outputs a signal consistent with the input signal to the internal circuit based on the input signal and a bypass signal. When the receiving unit is turned off, the bypass unit outputs a signal consistent with the input signal to the internal circuit based on the bypass signal. In the above scheme, the receiving unit can be turned off as needed, such as during aging tests. Even when the receiving unit is turned off, it can still output a signal consistent with the original input signal to the internal circuit, thereby supporting the normal operation of the memory. This is well-suited for aging test scenarios and avoids affecting the receiving unit during the aging test process.

[0105] Example 2

[0106] Figure 12 A structural example diagram of a memory provided in an embodiment of this disclosure is shown below. Figure 12 As shown, the memory includes: a signal receiving circuit 40 and an internal circuit 43 as described in Embodiment 1;

[0107] The signal receiving circuit 40 is used to receive the input signal and output a final signal that is consistent with the input signal.

[0108] The internal circuit 43 is connected to the signal receiving circuit 40 and is used to perform corresponding operations according to the final signal and operation instructions.

[0109] The input signals include, but are not limited to, clock signals or chip select signals. The operation instructions include, but are not limited to, read operations and / or write operations. In practical applications, the number of memory pins and internal circuits is typically multiple. Therefore, in one example, there are multiple signal receiving circuits 40, each corresponding to a different input signal. Specifically, for different input signals, such as the chip select signal CS and the clock signal CLK, corresponding signal receiving circuits are configured.

[0110] In the memory provided in this embodiment, the signal receiving circuit includes a receiving unit and a bypass unit. When the receiving unit is turned on, the input signal can be transmitted to the bypass unit through the receiving unit. The bypass unit outputs a signal consistent with the input signal to the internal circuit based on the input signal and the bypass signal. When the receiving unit is turned off, the bypass unit outputs a signal consistent with the input signal to the internal circuit based on the bypass signal. In the above scheme, the receiving unit can be turned off as needed, such as during aging tests. Even when the receiving unit is turned off, it can still output a signal consistent with the original input signal to the internal circuit, thereby supporting the normal operation of the memory. This approach is well-suited for aging test scenarios and avoids affecting the receiving unit during the aging test process.

[0111] The foregoing has provided examples of the signal receiving circuit and the structure of the memory. In conjunction with the foregoing, the following describes an example of the control method for the signal receiving circuit, which is applied to the signal receiving circuit as described in any of the foregoing examples.

[0112] Example 3

[0113] Figure 13 This is a flowchart illustrating a control method for a signal receiving circuit provided in an embodiment of the present disclosure, as shown below. Figure 13 As shown, the method includes:

[0114] Step 101: Determine the current state of the receiving unit, including an on state or an off state;

[0115] Step 102: Based on the current state of the receiving unit, control the level of the bypass signal so that the final signal output by the bypass unit to the internal circuit is consistent with the input signal.

[0116] To illustrate with a practical example: In a normal scenario, the memory can normally power on its receiving unit. Once powered on, the receiving unit transmits the received input signal normally to the bypass unit. Correspondingly, the bypass unit, based on the input signal and the bypass signal, outputs a final signal consistent with the input signal, which is then provided to the internal circuitry. In a testing scenario, such as an aging test, the receiving unit can be powered off to avoid damaging it. After the receiving unit is powered off, the bypass unit outputs a final signal consistent with the input signal based on the received bypass signal. Since the input to the bypass unit differs depending on the receiving unit's state, the bypass signal input to the bypass unit needs to be controlled and adjusted to ensure the output signal matches the input signal. Specifically, in this embodiment, the current state of the receiving unit is first determined, and then the level of the bypass signal is controlled based on the current state of the receiving unit to ensure that the final signal output by the bypass unit matches the input signal.

[0117] Furthermore, the control strategy will be adjusted accordingly based on different structures. In one example, such as... Figure 6 As shown, the bypass unit includes an OR gate; the first input of the OR gate is connected to the output of the receiving unit, the second input of the OR gate is connected to the bypass signal, and the output of the OR gate is connected to the internal circuit. Accordingly, step 102 may specifically include:

[0118] If the receiving unit is in the on state, the bypass signal is controlled to be fixed at a low level;

[0119] If the receiving unit is in the off state, the bypass signal is controlled to be consistent with the input signal.

[0120] Through the above control method, for the signal receiving circuit of the bypass unit including the OR gate, a fixed low-level bypass signal can be provided to the OR gate when the receiving unit is turned on, and a bypass signal consistent with the input signal can be provided to the OR gate when the receiving unit is turned off, thereby supporting the bypass unit to output a final signal consistent with the input signal in different states of the receiving unit.

[0121] In another example, such as Figure 8 As shown, the bypass unit includes an XOR gate; the first input terminal of the XOR gate is connected to the output terminal of the receiving unit, the second input terminal of the XOR gate is connected to the bypass signal, and the output terminal of the XOR gate is connected to the internal circuit. Accordingly, step 102 may specifically include:

[0122] If the receiving unit is in the on state, the bypass signal is controlled to be fixed at a high level;

[0123] If the receiving unit is in the off state, the bypass signal is controlled to be the inverted signal of the input signal.

[0124] Through the above control method, for the signal receiving circuit including the XOR gate in the bypass unit, a fixed high-level bypass signal can be provided to the XOR gate when the receiving unit is turned on, and a bypass signal opposite to the input signal can be provided to the XOR gate when the receiving unit is turned off, thereby supporting the bypass unit to output the final signal consistent with the input signal in different states of the receiving unit.

[0125] In yet another example, such as Figure 10 As shown, the bypass unit includes: a data selector; the input terminal of the data selector is connected to the output terminal of the receiving unit and the bypass signal, and the output terminal of the data selector is connected to the internal circuit. Accordingly, step 102 may specifically include:

[0126] If the receiving unit is in the off state, the bypass signal is controlled to be consistent with the input signal.

[0127] Through the above control method, for the signal receiving circuit of the bypass unit including the data selector, when the receiving unit is turned on, the bypass signal can be any signal or no bypass signal is provided, and the data selector can select the input signal output by the receiving unit for output; and when the receiving unit is turned off, a bypass signal consistent with the input signal is provided to the data selector, and the data selector can select the bypass signal consistent with the input signal for output, thereby supporting the bypass unit to output the final signal consistent with the input signal in different states of the receiving unit.

[0128] As an example, such as Figure 11 As shown, based on any of the foregoing examples, the signal receiving circuit further includes: a signal generation module; the signal generation module is connected to the bypass unit and is used to output the bypass signal according to the bypass control signal; correspondingly, step 102 may specifically include:

[0129] Based on the current state of the receiving unit, the level of the bypass signal output by the signal generation module is controlled by outputting a corresponding bypass control signal.

[0130] Specifically, in this example, the bypass unit is generated by the signal generation module. Therefore, the aforementioned process of controlling the output bypass signal based on the current state of the receiving unit can be implemented by controlling the signal generation module. As an example, the level of the bypass signal output by the signal generation module can be controlled by outputting a bypass control signal to the signal generation module.

[0131] In the control method for the signal receiving circuit provided in this embodiment, the signal receiving circuit includes a receiving unit and a bypass unit. When the receiving unit is turned on, the input signal can be transmitted to the bypass unit through the receiving unit. The bypass unit outputs a signal consistent with the input signal to the internal circuit based on the input signal and a bypass signal. When the receiving unit is turned off, the bypass unit outputs a signal consistent with the input signal to the internal circuit based on the bypass signal. In the above scheme, the receiving unit can be turned off as needed, such as during aging tests. Even when the receiving unit is turned off, it can still output a signal consistent with the original input signal to the internal circuit, thereby supporting the normal operation of the memory. This method is well-suited for aging test scenarios and avoids affecting the receiving unit during the aging test process.

[0132] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the following claims.

[0133] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is limited only by the appended claims.

Claims

1. A signal receiving circuit, characterized in that, include: Receiving unit and bypass unit; The receiving unit is used to transmit the input signal to the bypass unit when the power is on. The bypass unit is coupled to the receiving unit and the internal circuit, and is used to output a final signal consistent with the input signal to the internal circuit based on the input signal and the bypass signal when the receiving unit is turned on. Furthermore, when the receiving unit is turned off, a final signal consistent with the input signal is output to the internal circuit based on the bypass signal.

2. The circuit according to claim 1, characterized in that, The bypass unit includes: logic gates; The input terminal of the logic gate is connected to the output terminal of the receiving unit and the bypass signal, and the output terminal of the logic gate is connected to the internal circuit. The logic gate is used to perform logical operations on the input signal and the bypass signal output by the receiving unit when the receiving unit is turned on, and output a signal consistent with the input signal; and to perform logical operations on the bypass signal when the receiving unit is turned off, and output a signal consistent with the current input signal.

3. The circuit according to claim 2, characterized in that, The logic gates include: OR gates; The first input terminal of the OR gate is connected to the output terminal of the receiving unit, the second input terminal of the OR gate is connected to the bypass signal, and the output terminal of the OR gate is connected to the internal circuit. Specifically, when the receiving unit is turned on, the bypass signal is fixed at a low level; when the receiving unit is turned off, the bypass signal is consistent with the input signal.

4. The circuit according to claim 2, characterized in that, The logic gates include: XOR NOT gates; The first input terminal of the XOR gate is connected to the output terminal of the receiving unit, the second input terminal of the XOR gate is connected to the bypass signal, and the output terminal of the XOR gate is connected to the internal circuit. Specifically, when the receiving unit is turned on, the bypass signal is fixed at a high level; when the receiving unit is turned off, the bypass signal is the inverted signal of the input signal.

5. The circuit according to claim 4, characterized in that, The logic gates also include: NOT gates; The input terminal of the NOT gate is connected to the input signal, and the NOT gate is used to generate the bypass signal when the receiving unit is turned off.

6. The circuit according to claim 1, characterized in that, The bypass unit includes: a data selector; The input terminal of the data selector is connected to the output terminal of the receiving unit and the bypass signal, and the output terminal of the data selector is connected to the internal circuit. The data selector is used to select, based on a control signal, either to output the signal from the receiving unit or to output the bypass signal; wherein, when the receiving unit is off, the bypass signal is consistent with the input signal.

7. The circuit according to claim 6, characterized in that, The circuit also includes: a control module; The control module is connected to the data selector and is used to output a control signal of a first level state to the data selector when the receiving unit is turned on; and to output a control signal of a second level state to the data selector when the receiving unit is turned off. The data selector is configured to select the signal output by the receiving unit according to the control signal in the first level state; and to select the bypass signal according to the control signal in the second level state.

8. The circuit according to any one of claims 1-7, characterized in that, The input signal includes a clock signal or a chip select signal.

9. The circuit according to any one of claims 1-7, characterized in that, The circuit also includes: a signal generation module; The signal generation module is connected to the bypass unit and is used to output the bypass signal according to the bypass control signal.

10. The circuit according to claim 9, characterized in that, The signal generation module includes: a register.

11. A memory, characterized in that, include: The signal receiving circuit and internal circuit as described in any one of claims 1-10; The signal receiving circuit is used to receive the input signal and output a final signal that is consistent with the input signal. The internal circuit is connected to the signal receiving circuit and is used to perform corresponding operations based on the final signal and operation instructions.

12. The memory according to claim 11, characterized in that, The number of signal receiving circuits is multiple, and the multiple signal receiving circuits are configured to correspond to multiple input signals.

13. A control method for a signal receiving circuit, characterized in that, The method, applied to a signal receiving circuit as described in any one of claims 1-10, comprises: Determine the current state of the receiving unit, including an on state or an off state; Based on the current state of the receiving unit, the level of the bypass signal is controlled so that the final signal output by the bypass unit to the internal circuit is consistent with the input signal.

14. The method according to claim 13, characterized in that, The bypass unit includes an OR gate; the first input terminal of the OR gate is connected to the output terminal of the receiving unit, the second input terminal of the OR gate is connected to the bypass signal, and the output terminal of the OR gate is connected to the internal circuit. The step of controlling the level state of the bypass signal according to the current state of the receiving unit includes: If the receiving unit is in the on state, the bypass signal is controlled to be fixed at a low level; If the receiving unit is in the off state, the bypass signal is controlled to be consistent with the input signal.

15. The method according to claim 13, characterized in that, The bypass unit includes an XOR gate; the first input terminal of the XOR gate is connected to the output terminal of the receiving unit, the second input terminal of the XOR gate is connected to the bypass signal, and the output terminal of the XOR gate is connected to the internal circuit. The step of controlling the level state of the bypass signal according to the current state of the receiving unit includes: If the receiving unit is in the on state, the bypass signal is controlled to be fixed at a high level; If the receiving unit is in the off state, the bypass signal is controlled to be the inverted signal of the input signal.

16. The method according to claim 13, characterized in that, The bypass unit includes: a data selector; the input terminal of the data selector is connected to the output terminal of the receiving unit and the bypass signal, and the output terminal of the data selector is connected to the internal circuit; The step of controlling the level state of the bypass signal according to the current state of the receiving unit includes: If the receiving unit is in the off state, the bypass signal is controlled to be consistent with the input signal.

17. The method according to any one of claims 13-16, characterized in that, The signal receiving circuit further includes: a signal generation module; the signal generation module is connected to the bypass unit and is used to output the bypass signal according to the bypass control signal; The step of controlling the level state of the bypass signal according to the current state of the receiving unit includes: Based on the current state of the receiving unit, the level of the bypass signal output by the signal generation module is controlled by outputting a corresponding bypass control signal.

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