A refresh address generation circuit

Abstract

This application discloses a refresh address generation circuit, including a refresh control circuit and an address generator. The refresh control circuit sequentially receives multiple first refresh instructions and performs multiple first refresh operations accordingly. When the number of first refresh operations is less than m, it outputs a first clock signal; and when the number of first refresh operations is equal to m, it outputs a second clock signal. The refresh control circuit also masks duplicate instructions when duplicate instructions appear in the first refresh instructions. The address generator pre-stores a first address and receives either the first clock signal or the second clock signal. During each first refresh operation, it outputs the address to be refreshed in response to the first clock signal, and changes the first address in response to the second clock signal. This application ensures that refresh operations are performed without omission, maintains address integrity, and saves circuit power consumption.

Description

Technical Field

[0001] This application relates to, but is not limited to, a refresh address generation circuit. Background Technology

[0002] In memory, the memory is divided into multiple banks. There are two modes for refreshing memory addresses: All Bank Refresh, which refreshes all banks together for the same address; and Same Bank Refresh, which refreshes different banks within the same bank group sequentially for the same address. During Same Bank Refresh, the generation and storage of addresses are problems that need to be solved.

[0003] Meanwhile, repeated instructions in the refresh command will trigger repeated refreshes of already refreshed memory, resulting in wasted current. Summary of the Invention

[0004] In view of this, the present application provides a refresh address generation circuit that can generate the address to be refreshed and maintain the pre-stored first address during the refresh operation, thereby ensuring that the refresh operation is performed without omission and maintaining the integrity of the address; at the same time, it can avoid the current waste caused by repeated refresh and save the power consumption of the circuit.

[0005] The technical solution of this application embodiment is implemented as follows:

[0006] This application embodiment provides a refresh address generation circuit, the refresh address generation circuit comprising:

[0007] A refresh control circuit is configured to sequentially receive multiple first refresh instructions and perform multiple first refresh operations accordingly. When the number of first refresh operations is less than m, a first clock signal is output, and when the number of first refresh operations is equal to m, a second clock signal is output, where m is an integer greater than or equal to 1. The refresh control circuit is also configured to block duplicate instructions when duplicate instructions appear in the first refresh instructions.

[0008] An address generator, coupled to the refresh control circuit, is used to pre-store a first address and receive either the first clock signal or the second clock signal. During each of the first refresh operations, it outputs the address to be refreshed in response to the first clock signal and changes the first address in response to the second clock signal.

[0009] Therefore, this application provides a refresh address generation circuit, including a refresh control circuit and an address generator. The refresh control circuit sequentially receives multiple first refresh instructions and performs multiple first refresh operations accordingly. When the number of first refresh operations is less than m, it outputs a first clock signal; and when the number of first refresh operations equals m, it outputs a second clock signal, where m is an integer greater than or equal to 1. The refresh control circuit also masks duplicate instructions when duplicate instructions appear in the first refresh instructions. The address generator is coupled to the refresh control circuit and pre-stores a first address. It receives the first clock signal or the second clock signal, outputs the address to be refreshed in response to the first clock signal during each first refresh operation, and changes the first address in response to the second clock signal. Thus, during the first refresh operation, the address generator responds to the first clock signal, outputting the address to be refreshed including either the first or second address, while maintaining the first address unchanged. After the number of first refresh operations equals m, the address generator responds to the second clock signal and changes the first address, thereby ensuring that the refresh operation is performed without omission and maintaining the integrity of the address. Meanwhile, the refresh control circuit shields the repeated instructions in the first refresh instruction, avoiding the current waste caused by repeated refreshes, thereby saving the circuit's power consumption. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 1 ;

[0011] Figure 2 This is a signal diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 1 ;

[0012] Figure 3 This is a signal diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 2 ;

[0013] Figure 4 This is a schematic diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 2 ;

[0014] Figure 5 This is a signal diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 3 ;

[0015] Figure 6 This is a signal diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 4 ;

[0016] Figure 7 This is a schematic diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 3 ;

[0017] Figure 8 This is a schematic diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 4 ;

[0018] Figure 9 This is a schematic diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 5 ;

[0019] Figure 10 This is a signal diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 5 ;

[0020] Figure 11 This is a schematic diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 6 ;

[0021] Figure 12 This is a schematic diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 7 ;

[0022] Figure 13 This is a signal diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 6 ;

[0023] Figure 14 This is a schematic diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 8 ;

[0024] Figure 15 This is a signal diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 7 ;

[0025] Figure 16 This is a schematic diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 9 ;

[0026] Figure 17 This is a signal diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 8 ;

[0027] Figure 18 This is a signal diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 9 ;

[0028] Figure 19 This is a schematic diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 10 ;

[0029] Figure 20 This is a schematic diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 10 one;

[0030] Figure 21 This is a signal diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 10 ;

[0031] Figure 22 This is a schematic diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 10 two;

[0032] Figure 23 This is a signal diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 10 one;

[0033] Figure 24 This is a schematic diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 10 three;

[0034] Figure 25 This is a signal diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 10 two;

[0035] Figure 26 This is a schematic diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 10 Four;

[0036] Figure 27 This is a schematic diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 10 five;

[0037] Figure 28 This is a signal diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 10 three;

[0038] Figure 29 This is a schematic diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 10 six;

[0039] Figure 30 This is a signal diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 10 Four;

[0040] Figure 31 This is a signal diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 10 five;

[0041] Figure 32 This is a schematic diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 10 seven;

[0042] Figure 33 This is a signal diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 10 six;

[0043] Figure 34 This is a signal diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 10 seven;

[0044] Figure 35 This is a schematic diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 10 eight;

[0045] Figure 36 This is a signal diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 10 eight;

[0046] Figure 37 This is a signal diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 10 Nine;

[0047] Figure 38 This is a schematic diagram of the refresh address generation circuit provided in the embodiments of this application. Figure 10 Nine. Detailed Implementation

[0048] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application are further described in detail below with reference to the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on this application. All other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0049] In the following description, references are made to “some embodiments,” which describe a subset of all possible embodiments. However, it is understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0050] If the application documents contain similar descriptions such as "first / second", the following explanation shall be added: In the following description, the terms "first / second / third" are used only to distinguish similar objects and do not represent a specific order of objects. It is understood that "first / second / third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this application described herein can be implemented in an order other than that illustrated or described herein.

[0051] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0052] Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM) is commonly used in electronic devices. In DDR4 SDRAM or earlier, refresh operations were performed on all banks simultaneously, meaning all banks refreshed at the same address at the same time—this is known as All Bank Refresh. DDR5 SDRAM introduced Same Bank Refresh. This means that in Same Bank Refresh mode, different banks within the same bank group cannot be refreshed simultaneously, which can lead to issues with address generation and storage.

[0053] Figure 1 This is a schematic diagram of a refresh address generation circuit provided in an embodiment of this application, as shown below. Figure 1 As shown, this application embodiment provides a refresh address generation circuit 10, including: a refresh control circuit 101 and an address generator 102.

[0054] The refresh control circuit 101 is used to sequentially receive multiple first refresh instructions SB CMD<0:m-1> and perform multiple first refresh operations accordingly. When the number of first refresh operations is less than m, it outputs a first clock signal; and when the number of first refresh operations is equal to m, it outputs a second clock signal, where m is an integer greater than or equal to 1. The refresh control circuit 101 is also used to mask duplicate instructions when duplicate instructions appear in the first refresh instructions SB CMD<0:m-1>.

[0055] Address generator 102, coupled to refresh control circuit, is used to pre-store a first address and receive a first clock signal or a second clock signal. During each first refresh operation, it outputs the address to be refreshed in response to the first clock signal and changes the first address in response to the second clock signal.

[0056] It should be noted that, in the embodiments of this application, the coupling methods include: direct electrical connection, and electrical connection through other electrical components (such as resistors, timers, or inverters). The term "coupling" as used below will encompass these methods, and will not be elaborated upon further.

[0057] In this embodiment of the application, the refresh control circuit 101 can sequentially receive multiple first refresh instructions SB CMD<0:m-1>, where SB CMD<0:m-1> represents m first refresh instructions SB CMD. <0> ~SB CMD <m-1>Each first refresh instruction (SB CMD) corresponds to a bank in each bank group, and each SB CMD triggers the corresponding bank in each bank group to perform a first refresh operation (i.e., Same Bank Refresh). Accordingly, multiple first refresh instructions (SB CMD<0:m-1>) received in sequence will trigger the corresponding banks in each bank group to perform a first refresh operation in sequence, that is, multiple first refresh operations will be performed in sequence.

[0058] In this embodiment, the Bank Group includes m Banks, and the number of Banks m is set according to chip design standards. Each Bank includes multiple rows of storage cells, and the address to be refreshed is the row address of the storage cell in the Bank. During the first refresh operation performed by the refresh control circuit 101, the address generator 102 outputs the address to be refreshed during the first refresh operation, and the storage cell in the Bank corresponding to the address to be refreshed by the first refresh instruction SB CMD is refreshed.

[0059] In this embodiment, the refresh control circuit 101 can output a SameBank refresh clock signal SB CBR CLK, which includes a first clock signal and a second clock signal. If the number of first refresh operations is less than m, it indicates that there are still banks in the Bank Group that have not yet undergone the first refresh operation on the memory cell containing the address to be refreshed. In this case, the refresh control circuit 101 outputs the first clock signal. If the number of first refresh operations is equal to m, it indicates that the memory cell containing the address to be refreshed in all banks of the Bank Group has completed the first refresh operation. In this case, the refresh control circuit 101 outputs the second clock signal.

[0060] like Figure 2 As shown, taking m=4 as an example, SB CMD <0> SB CMD <1> SBCMD <2> and SB CMD <3> These are the first refresh commands received sequentially by the refresh control circuit, each corresponding to one of the four banks in the same Bank Group: Bank0, Bank1, Bank2, and Bank3. Correspondingly, SB CMD <0> SB CMD <1> SB CMD <2> and SB CMD <3> The pulses in the clock signal can sequentially trigger the refresh control circuit 101 to perform the first refresh operation. The SameBank refresh clock signal SB CBR CLK includes a first clock signal and a second clock signal. The second clock signal includes pulses, while the first clock signal remains at a low level.

[0061] In this embodiment, the address generator 102 pre-stores a first address. Upon receiving a first clock signal, during each first refresh operation, it outputs a refreshable address (Address) in response to the first clock signal. The refreshable address (Address) includes either the first address or a second address, where the least significant bit of the second address is opposite to the least significant bit of the first address. Since the address is a binary code, the second address with the opposite least significant bit and the first address are adjacent addresses. If the first address is n, then the second address is n+1 or n-1; that is, when the least significant bit of the first address n is 0, the second address is 1 after inverting the least significant bit of n, and the second address is n+1; when the least significant bit of the first address n is 1, the second address is 0 after inverting the least significant bit of n, and the second address is n-1. Upon receiving a second clock signal, the address generator 102 changes its pre-stored first address in response to the second clock signal. That is, during the next first refresh operation, the address generator 102 pre-stores the changed first address. The address generator 102 can change the first address by accumulating the value, which can be controlled by the second clock signal.

[0062] like Figure 2 As shown, the address to be refreshed includes a first address and a second address, where the first address is n and the second address is n+1 or n-1. When the SameBank refresh clock signal SB CBR CLK is the first clock signal, the address generator 102 outputs the address to be refreshed as the first address and the second address output sequentially. Each set of the first address and the second address is specified in the first refresh instruction SB CMD. <0> SB CMD <1> SBCMD <2> and SB CMD <3> The refresh control circuit 101 is triggered sequentially to perform the first refresh operation during the output period. That is, the first refresh instruction SB CMD... <0> When the refresh control circuit 101 is triggered to perform the first refresh operation, the address generator 102 outputs the address to be refreshed, which includes the first address n and the immediately following second address n+1 or n-1. That is, the refresh controller will refresh the corresponding memory cell of Bank0 according to the address to be refreshed. Similarly, the second first refresh instruction SB CMD <1> When the refresh control circuit 101 is triggered to perform the second first refresh operation, the address generator 102 outputs the same address to be refreshed, namely the first address n and the immediately following second address n+1 or n-1. The refresh controller refreshes the corresponding memory cell in Bank1 according to the address to be refreshed; and so on, until the corresponding memory cell in Bank3 is refreshed. In this way, the memory cells corresponding to the first address n and the second address n+1 or n-1 in all Banks of the Bank Group (i.e., Bank0, Bank1, Bank2 and Bank3) have been refreshed, that is, all Banks in the Bank Group have completed the refresh of two adjacent addresses.

[0063] Continue to refer to Figure 2 The address output signal Addr Counter Output represents the first address stored in the address generator 102. When the refresh control circuit 101 performs the first refresh operation less than m times, the first address n stored in the address generator 102 remains unchanged, and the address output signal Addr Counter Output continues to be the first address n. When the memory cells corresponding to two adjacent addresses in all banks of the BankGroup are refreshed, that is, when the refresh control circuit 101 performs the first refresh operation m times, the address generator 102 changes the first address n in response to the second clock signal. The second clock signal includes two pulses. Under the trigger of these two pulses, the address generator 102 increments the first address n by 1 twice, and the address output signal Addr Counter Output becomes n+2, thus matching the progress of the refresh address. In the subsequent m first refresh operations, the address generator 102 continues to output the address to be refreshed based on the first address that has become n+2, so as to refresh the memory cells corresponding to the next two adjacent addresses of each bank in the BankGroup. In this way, the memory cells corresponding to all addresses of each bank in the BankGroup can be refreshed sequentially.

[0064] In this embodiment, the refresh control circuit 101 is further configured to mask duplicate instructions when duplicate instructions appear in the first refresh instruction SB CMD<0:m-1>. That is, the signals output by the refresh control circuit 101 and the address generator 102 will not be affected by duplicate instructions.

[0065] Figure 3 The diagram shows the signal waveform when a duplicate instruction appears in the first refresh instruction. Here, a duplicate instruction refers to an additional refresh instruction issued to a specific bank when the first refresh operation has not been completed for all banks at the same address, such as... Figure 3 As shown, when the first address has not changed (e.g., the first address is n), meaning the first refresh operation for all banks at the same address has not yet been completed, the first refresh instruction SB CMD is used. <0> The signal consists of two pulses. The first pulse has already triggered the first refresh operation of Bank0, and the second pulse is the repeat instruction.

[0066] Combination Figure 2 and Figure 3 , Figure 3 The address to be refreshed, Address, and the address output signal, Addr CounterOutput, are related to... Figure 2 The corresponding signal waveforms are the same. That is to say, in Figure 3 In the middle, when the first refresh command SB CMD <0> When a duplicate instruction occurs, the address to be refreshed (Address) and the address output signal (Addr Counter Output) are not affected and do not change, meaning the duplicate instruction is masked.

[0067] Understandably, during the first refresh operation, the address generator 102 responds to the first clock signal and outputs the address to be refreshed, including the first address or the second address, while keeping the first address unchanged. After the number of first refresh operations reaches a preset value m, the address generator 102 responds to the second clock signal and changes the first address. In this way, the refresh operation is carried out without omission, and the integrity of the address is maintained.

[0068] Meanwhile, the refresh control circuit 101 shields the repeated instructions in the first refresh instruction, avoiding the current waste caused by repeated refreshes, thereby saving the power consumption of the circuit.

[0069] Figure 4 for Figure 1 The diagram shows an optional structure of the refresh control circuit 101. Figure 5 and Figure 6 For corresponding Figure 4 A schematic diagram of the signal.

[0070] It should be noted that, Figure 5 The signal timing of the refresh control circuit 101 receiving multiple first refresh instructions SB CMD sequentially and performing a first refresh operation is shown, wherein the preset quantity value m of the first refresh instructions SB CMD is equal to 4 as an example. Figure 6 The signal timing of the refresh control circuit 101 receiving the second refresh command AB CMD and performing the second refresh operation is shown.

[0071] In addition, Figure 5 and Figure 6 In the diagram, except for the first refresh instruction SB CMD, the counter signal Bank Counter, the counter reset signal Bank Counter Reset, and the SameBank refresh clock signal SB CBR CLK, all signals are shown as waveforms spanning four cycles. If each cycle contains two valid pulses, the valid pulse occurring earlier in the timing sequence is the first pulse, and the valid pulse occurring later in the timing sequence is the second pulse. The signal waveforms in subsequent figures are also divided according to a similar rule, which will not be elaborated upon further.

[0072] In some embodiments of this application, such as Figure 4 and Figure 5 As shown, the refresh control circuit 101 includes a refresh window signal generation circuit 201 and a clock pulse generation circuit 202.

[0073] The refresh window signal generation circuit 201 is used to receive multiple first refresh commands SB CMD (i.e., Figure 4 SBCMD shown <0> To SB CMD <m-1>The system generates a refresh window signal (Refresh Window) based on multiple first refresh instructions (SB CMD) and the refresh window reset signal (Refresh Window Reset). Reference... Figure 5 The pulse duration of the Refresh Window signal is the window time for the refresh control circuit 101 to perform one refresh operation. The Refresh Window Reset signal is used to reset the refresh window signal generation circuit 201 after a refresh operation is completed. Here, the refresh operation performed by the refresh control circuit 101 is the first refresh operation, that is, the first refresh operation is performed on the Bank corresponding to the first refresh instruction SB CMD.

[0074] A clock pulse generation circuit 202 is coupled to a refresh window signal generation circuit 201. It receives the refresh window signal Refresh Window and the first refresh instruction SB CMD. Before the m-th first refresh operation ends, the clock pulse generation circuit 202 generates a first clock signal if the number of first refresh instructions SB CMD received is less than or equal to m. Alternatively, after the m-th first refresh operation ends, a second clock signal is generated. (Reference) Figure 5 The SameBank refresh clock signal includes a first clock signal and a second clock signal, that is, the first clock signal and the second clock signal are the values ​​of the SameBank refresh clock signal at different time periods.

[0075] In some embodiments of this application, such as Figure 4 and Figure 5 As shown, the clock pulse generation circuit 202 includes: a counting circuit 203, a counting reset signal generation circuit 204, and a first pulse generation sub-circuit 205.

[0076] The counting circuit 203 is used to receive the first refresh instruction SB CMD and the counting reset signal Bank CounterReset, count the first refresh instruction SB CMD and output the counting signal Bank Counter<0:m-1>, and reset according to the counting reset signal Bank Counter Reset.

[0077] The counter reset signal generation circuit 204 is coupled to the counter circuit 203 and the refresh window signal generation circuit 201, and is used to generate the counter reset signal Bank Counter Reset after the first refresh operation of the mth time.

[0078] The first pulse generation sub-circuit 205 is coupled to the count reset signal generation circuit 204, and is used to generate a first clock signal according to the count signal Bank Counter<0:m-1> when the first refresh instruction SBCMD is less than m, or to generate a second clock signal according to the count reset signal Bank Counter Reset when the first refresh instruction SBCMD is equal to m.

[0079] In some embodiments of this application, such as Figure 4 and Figure 5 As shown, the refresh window signal generation circuit 201 includes: multiple repeat instruction masking circuits 206, multiple refresh window sub-signal generation circuits 207, and refresh window sub-signal processing circuits 208.

[0080] Multiple duplicate instruction masking circuit 206 is coupled to counting circuit 203, and is used to receive multiple first refresh instructions SB CMD and multiple counting signals Bank Counter<0:m-1> respectively. According to the multiple counting signals Bank Counter<0:m-1>, when no duplicate instruction appears in the multiple first refresh instructions SB CMD, multiple first refresh instructions SB CMD are output, and when a duplicate instruction appears in the multiple first refresh instructions SB CMD, the duplicate instruction is masked and not output.

[0081] Multiple refresh window sub-signal generation circuit 207 is used to receive the refresh window reset signal Refresh WindowReset and to receive multiple first refresh instructions SB CMD in sequence, and to output multiple refresh window sub-signals ReW in sequence according to the multiple first refresh instructions SB CMD and the refresh window reset signal Refresh Window Reset. Figure 4 The ReW shown <0> To ReW <m-1>).

[0082] The refresh window sub-signal processing circuit 208 is coupled to multiple refresh window sub-signal generation circuits 207, and is used to sequentially receive multiple refresh window sub-signals ReW, perform logical operations on the refresh window sub-signals ReW, and output the refresh window signal Refresh Window.

[0083] In some embodiments of this application, such as Figure 4 and Figure 6 As shown, the refresh control circuit 101 is also used to receive the second refresh command AB CMD and perform the second refresh operation.

[0084] The multiple refresh window sub-signal generation circuit 207 is also used to simultaneously receive the second refresh instruction AB CMD and the refresh window reset signal Refresh Window Reset, and generate multiple identical refresh window sub-signals ReW according to the second refresh instruction AB CMD and the refresh window reset signal Refresh Window Reset.

[0085] The refresh window sub-signal processing circuit 208 is also used to receive multiple refresh window sub-signals ReW, perform logical operations on the refresh window sub-signals ReW, and output the refresh window signal Refresh Window.

[0086] It should be noted that the second refresh operation is performed simultaneously on all banks in the Bank Group, i.e., AllBank Refresh. When the refresh control circuit 101 receives the second refresh instruction AB CMD and performs the second refresh operation, the first refresh instruction SB CMD does not contain a valid pulse and remains at a low level, i.e., the first refresh instruction SB CMD is invalid. Consequently, the counting signal Bank Counter<0:m-1> also remains at a low level, and the counting refresh signal Bank Counter Reset does not generate a valid pulse and remains at a low level.

[0087] Correspondingly, when the refresh control circuit 101 receives multiple first refresh instructions SB CMD sequentially and performs the first refresh operation, the second refresh instruction AB CMD does not include a valid pulse and remains at a low level, that is, the second refresh instruction SBCMD is invalid.

[0088] In this embodiment, when the multiple refresh window sub-signal generation circuits 207 receive multiple first refresh commands SBCMD, the multiple refresh window sub-signals ReW generated are all different because the multiple first refresh commands SBCMD are different. However, when the multiple refresh window sub-signal generation circuits 207 receive a second refresh command AB CMD, they can generate multiple identical refresh window sub-signals ReW.

[0089] Understandably, the refresh control circuit 101 can receive multiple first refresh commands SBCMD sequentially and perform a first refresh operation as needed, or receive a second refresh command AB CMD and perform a second refresh operation. In other words, a single refresh control circuit 101 can flexibly perform both refresh operations, thus improving circuit compatibility.

[0090] In some embodiments of this application, such as Figure 4 As shown, the refresh control circuit 101 also includes: a second pulse generation sub-circuit 209, an internal refresh window signal generation circuit 210, an address command signal generation circuit 211, and a refresh window reset signal generation circuit 212.

[0091] In this embodiment of the application, reference is made to Figure 4 , Figure 5 and Figure 6 The second pulse generation sub-circuit 209 is coupled to the refresh window signal generation circuit 208 and is used to receive the refresh window signal Refresh Window and the address command signal Addr CMD. When the refresh control circuit 101 starts to perform the first refresh operation or the second refresh operation, it generates the first pulse of the third clock signal AB CBR CLK and outputs the second pulse of the third clock signal AB CBR CLK according to the first pulse of the address command signal Addr CMD, thereby outputting the third clock signal AB CBR CLK.

[0092] refer to Figure 5 When the refresh control circuit 101 sequentially receives multiple first refresh commands SB CMD and performs a first refresh operation, the first pulse of the third clock signal AB CBR CLK is aligned with the multiple first refresh commands SB CMD. <0> ~SB CMD <3> The effective pulse, namely the first pulse of the third clock signal AB CBR CLK, is generated when the refresh control circuit 101 starts performing the first refresh operation; the second pulse of the third clock signal AB CBR CLK is aligned with the first pulse of the address command signal AddrCMD, that is, the second pulse of the third clock signal AB CBR CLK is generated based on the first pulse of the address command signal AddrCMD.

[0093] refer to Figure 6 When the refresh control circuit 101 receives the second refresh instruction AB CMD and performs the second refresh operation, the first pulse of the third clock signal AB CBR CLK is aligned with the valid pulse of the second refresh instruction AB CMD, that is, the first pulse of the third clock signal AB CBR CLK is generated when the refresh control circuit 101 starts performing the second refresh operation; the second pulse of the third clock signal AB CBR CLK is aligned with the first pulse of the address command signal Addr CMD, that is, the second pulse of the third clock signal AB CBR CLK is generated according to the first pulse of the address command signal Addr CMD.

[0094] In this embodiment of the application, reference is made to Figure 4 , Figure 5 and Figure 6 The internal refresh window signal generation circuit 210 receives the third clock signal AB CBR CLK and generates the internal refresh window signal Inner ACTWindow based on it. The first pulse of the internal refresh window signal Inner ACTWindow is generated after the first pulse of the third clock signal AB CBR CLK and ends before the second pulse of the third clock signal AB CBR CLK. The second pulse of the internal refresh window signal Inner ACTWindow is generated after the second pulse of the third clock signal AB CBR CLK and ends before the pulse of the refresh window signal Refresh Window ends. It should be noted that the refresh controller in the memory receives the internal refresh window signal Inner ACTWindow and the address to be refreshed, and refreshes the memory cell according to the internal refresh window signal Inner ACTWindow. Therefore, the duration of the pulse of the internal refresh window signal Inner ACTWindow is the time required to refresh the memory cell.

[0095] In this embodiment of the application, reference is made to Figure 4 , Figure 5 and Figure 6 The address command signal generation circuit 211 generates a first pulse and a second pulse of the address command signal Addr CMD based on the falling edge of the inner refresh window signal Inner ACT Window. The first pulse of the address command signal Addr CMD is used to generate the second pulse of the inner refresh window signal Inner ACT Window and the second pulse of the third clock signal AB CBR CLK. A falling edge of the inner refresh window signal Inner ACT Window indicates the end of refreshing an address, thereby generating the address command signal Addr CMD to control the generation of the next address.

[0096] refer to Figure 5 and Figure 6 The effective pulse of the inner refresh window signal Inner ACT Window can be compressed and shifted to obtain the effective pulse of the inner pre-command signal Inner PRE CMD. That is, the falling edge of the inner pre-command signal Inner PRE CMD is first obtained based on the falling edge of the inner refresh window signal Inner ACT Window. Then, the address command signal generation circuit 211 can generate the first pulse and the second pulse of the address command signal Addr CMD based on the falling edge of the inner pre-command signal Inner PRE CMD.

[0097] In this embodiment of the application, reference is made to Figure 4 , Figure 5 and Figure 6 The refresh window reset signal generation circuit 212 receives the inner refresh window signal Inner ACT Window and generates the pulse of the refresh window reset signal Refresh Window Reset based on the falling edge of the second pulse of the inner refresh window signal Inner ACT Window.

[0098] In some embodiments of this application, such as Figure 4 As shown, the refresh control circuit 101 also includes a signal selection circuit 213.

[0099] In this embodiment of the application, reference is made to Figure 4 , 4 5. Signal selection circuit 213 is coupled to counting circuit 203, first pulse generation sub-circuit 205 and second pulse generation sub-circuit 209, and is used to receive counting signal Bank Counter<0:m-1>, first clock signal, second clock signal (the first clock signal and the second clock signal are the SameBank refresh clock signal SB CBRCLK) and third clock signal AB CBR CLK). When refresh control circuit 101 performs the first refresh operation, it outputs the first clock signal or the second clock signal according to counting signal Bank Counter<0:m-1>, or when refresh control circuit 101 performs the second refresh operation, it outputs the third clock signal AB CBR CLK according to counting signal Bank Counter<0:m-1>.

[0100] refer to Figure 4 and Figure 5 When the refresh control circuit 101 performs the first refresh operation, if any counting signal Bank Counter is high, the signal selection circuit 213 outputs the first clock signal, that is, the SameBank refresh clock signal SB CBR CLK is low. If all counting signals Bank Counter jump to low, the signal selection circuit 213 outputs the second clock signal, that is, two consecutive valid pulses in the SameBank refresh clock signal SB CBR CLK.

[0101] refer to Figure 4 and Figure 6 When the refresh control circuit 101 performs a second refresh operation, all counting signals Bank Counter remain at a low level. Figure 6 (not shown), then the signal selection circuit 213 outputs the valid pulse in the third clock signal AB CBRCLK.

[0102] In some embodiments of this application, such as Figure 4 As shown, the refresh control circuit 101 also includes an address flag signal generation circuit 214.

[0103] In this embodiment of the application, reference is made to Figure 4 , Figure 5 and Figure 6 The address flag signal generation circuit 214 is coupled to the address command signal generation circuit 211 and the refresh window signal generation circuit 208. It is used to receive the address command signal Addr CMD and the refresh window signal Refresh Window. It generates the rising edge of the address flag signal AddrFlag based on the first rising edge of the address command signal Addr CMD, and generates the falling edge of the address flag signal Addr Flag based on the falling edge of the refresh window signal Refresh Window.

[0104] In some embodiments of this application, such as Figure 7 As shown, the address generator 102 includes an address counter 301 and an address processing circuit 302.

[0105] Address counter 301 is coupled to signal selection circuit 213 for pre-storing the first address and receiving SameBank refresh clock signal SB CBR CLK or third clock signal AB CBR CLK from signal selection circuit 213. Figure 7 (Not shown in the image). Address counter 301 can change the first address to the third address according to the second clock signal in the SameBank refresh clock signal SB CBR CLK, or change the first address and output the fourth and fifth addresses according to the third clock signal AB CBR CLK.

[0106] Address processing circuit 302 is coupled to address counter 301 and refresh window sub-signal generation circuit 207. It is used to receive address flag signal Addr Flag and obtain a first address when refresh control circuit 101 performs a first refresh operation. The first address is output before the rising edge of address flag signal Addr Flag arrives, or a second address is output after the rising edge of address flag signal Addr Flag arrives. The least significant bit of the first address and the least significant bit of the second address are opposite. Address processing circuit 302 is also used to sequentially obtain a fourth address and a fifth address when refresh control circuit 101 performs a second refresh operation, and sequentially output the fourth address and the fifth address according to multiple refresh window sub-signals ReW.

[0107] In this embodiment, when the refresh control circuit 101 performs the first refresh operation, the first address is a pre-stored address, and the second address is obtained by inverting the least significant bit of the first address. That is, the first address and the second address are two consecutive addresses. Therefore, the third address is incremented by 2 based on the first address to avoid repeatedly performing the first refresh operation on the same address. Thus, after all banks have completed the first refresh operation on the first and second addresses, the first address is incremented by 2 to become the third address. The refresh control circuit 101 can then use the third address as a pre-stored address to perform a new round of the first refresh operation, thereby ensuring that the first refresh operation is performed without omission.

[0108] In this embodiment, when the refresh control circuit 101 performs a second refresh operation, the first address is a pre-stored address, the fourth address is incremented by 1 based on the first address, and the fifth address is incremented by 1 based on the fourth address. That is, the first address, the fourth address, and the fifth address are three consecutive addresses. In this way, the refresh control circuit 101 can perform the second refresh operation on all Bank addresses sequentially according to the address order, thereby ensuring that the second refresh operation is performed without omission.

[0109] In this embodiment of the application, combined with Figure 5 and Figure 7 When the signal selection circuit 213 outputs the second clock signal (i.e., two valid pulses in SBCBR CLK) to the address counter 301, the address counter 301 can sequentially increment the value by 2 based on the first address according to the two valid pulses of the second clock signal to obtain the third address. When the signal selection circuit 213 outputs the third clock signal AB CBR CLK to the address counter 301, the address counter 301 can increment the value by 1 based on the first pulse of the third clock signal AB CBR CLK to obtain the fourth address. Then, the address counter 301 can increment the value by 1 based on the fourth address according to the second pulse of the third clock signal AB CBR CLK to obtain the fifth address.

[0110] In some embodiments of this application, such as Figure 8 As shown, the address processing circuit 302 includes a control signal generation circuit 303 and an address selection circuit 304.

[0111] The control signal generation circuit 303 is coupled to the refresh window sub-signal generation circuit 207 and the address flag signal generation circuit 214, and is used to receive multiple refresh window sub-signals ReW and address flag signals Addr Flag, and generate an address control signal Addr Ctrl based on the multiple refresh window sub-signals ReW and address flag signals Addr Flag.

[0112] Address selection circuit 304 is coupled to address counter 301 and control signal generation circuit 303. When refresh control circuit 101 receives the first refresh instruction SB CMD, it outputs the first address according to address control signal Addr Ctrl, or inverts the least significant bit of the first address according to address control signal Addr Ctrl to obtain and output the second address. Address selection circuit 304 is also used to output the fourth and fifth addresses sequentially in response to address control signal Addr Ctrl when refresh control circuit 101 receives the second refresh instruction AB CMD.

[0113] In some embodiments of this application, such as Figure 9 As shown, the counting circuit 203 includes: multiple first inverters D1, multiple first latches L1, and a second inverter D2. The inputs of the multiple first inverters D1 sequentially receive multiple first refresh instructions (SB CMD). The input of the second inverter D2 receives a count reset signal (Bank Counter Reset). The set terminals of the multiple first latches L1 are sequentially connected to the outputs of the multiple first inverters D1, and the reset terminals of the multiple first latches L1 are all connected to the outputs of the second inverters D2. The multiple first latches L1 sequentially output multiple count signals (Bank Counter).

[0114] In the embodiments of this application, Figure 10 The signal timing diagram when m=4, combined with Figure 9 and Figure 10 Each valid pulse in the first refresh instruction SB CMD can trigger the corresponding counting signal Bank Counter to switch from low to high, as in the first refresh instruction SB CMD. <0> The pulse in the signal can trigger the instruction counting signal Bank Counter. <0> The change from low to high level is also indicated by the first refresh instruction SB CMD. <1> SB CMD <2> and SB CMD <3> The pulses in the signal can trigger the instruction counting signal Bank Counter respectively. <1> Bank Counter <2> and Bank Counter <3> The signal changes from low to high. A valid pulse in the Bank Counter Reset signal can trigger all BankCounter signals. <0> ~Bank Counter <3> The signal transitions from high to low. The valid pulse in the Bank CounterReset signal is generated after the refresh control circuit completes the m-th first refresh operation.

[0115] In some embodiments of this application, such as Figure 11 As shown, the counter reset signal generation circuit 204 includes: a first AND gate A1, a third inverter D3, a second AND gate A2, a first delay unit H1, a fourth inverter D4, and a third AND gate A3. The input of the first AND gate A1 receives multiple counting signals (Bank Counter). The input of the third inverter D3 receives a refresh window signal (Refresh Window). The input of the second AND gate A2 is connected to the outputs of the first AND gate A1 and the third inverter D3. The input of the first delay unit H1 is connected to the output of the second AND gate A2. The input of the fourth inverter D4 is connected to the output of the first delay unit H1. The input of the third AND gate A3 is connected to the outputs of the second AND gate A2 and the fourth inverter D4, and the third AND gate A3 outputs a counter reset signal (Bank Counter Reset).

[0116] In some embodiments of this application, such as Figure 12 As shown, the first pulse generation sub-circuit 205 includes: a second delay unit H2, a third delay unit H3, and a first OR gate B1. The input of the second delay unit H2 receives the count reset signal BankCounter Reset. The input of the third delay unit H3 is connected to the output of the second delay unit H2. The input of the first OR gate B1 is connected to the outputs of the second delay unit H2 and the third delay unit H3, respectively. The first OR gate B1 outputs either a first clock signal or a second clock signal; that is, the first OR gate B1 outputs the SameBank refresh clock signal SB CBR CLK.

[0117] In the embodiments of this application, Figure 13 The signal timing diagram when m=4, combined with Figure 11 , Figure 12 and Figure 13 In the case of the first refresh operation, the pulse in the Bank Counter Reset signal is based on the BankCounter signal. <0> Bank Counter <1> Bank Counter <2> Bank Counter <3> This is generated in conjunction with the Refresh Window signal. A valid pulse from the Bank Counter Reset signal, after passing through the second delay unit H2, the third delay unit H3, and the first OR gate B1, generates two valid pulses in SB CBR CLK. Specifically, the first delay unit H1 can delay the received signal by 0–2 ns, the second delay unit H2 can delay the received signal by 1–3 ns, and the third delay unit H3 can delay the received signal by 4–6 ns.

[0118] In some embodiments of this application, such as Figure 14 As shown, each repeat instruction masking circuit 206 includes a fifth inverter D5 and a fourth AND gate A4. The input of the fifth inverter D5 receives the corresponding counting signal Bank Counter. The first input of the fourth AND gate A4 is connected to the output of the fifth inverter D5, and the second input of the fourth AND gate A4 receives the corresponding first refresh instruction SB CMD. The output of the fourth AND gate A4 serves as the output of the repeat instruction shielding circuit 206.

[0119] In this embodiment of the application, combined with Figure 14 and Figure 15 Taking m=4 as an example, the first refresh instruction is SB CMD <0> and counting signal Bank Counter <0> Transmitted to the same instruction masking circuit 206, correspondingly, the first refresh instruction SB CMD <1> and counting signal Bank Counter <1> Transmitted to the same instruction masking circuit 206, the first refresh instruction SB CMD <2> and counting signal Bank Counter <2> Transmitted to the same instruction masking circuit 206, the first refresh instruction SB CMD <3> and counting signal Bank Counter <3> They are transmitted to the same instruction masking circuit 206. The first refresh instruction is SB CMD. <0> A repeated instruction occurred, and at the moment the repeated instruction occurred, the counting signal Bank Counter... <0> The signal is high. Thus, the fifth inverter D5 and the fourth AND gate A4 can be connected according to the counting signal Bank Counter. <0> The repeat instruction is masked, and the fourth AND gate A4 does not output a valid pulse (i.e., the output of the fourth AND gate A4 remains low).

[0120] At the same time, the first refresh command SB CMD <0> ~SB CMD <3> Regular instructions other than repeat instructions (i.e., pulses other than the pulse of the repeat instruction) correspond to the counting signal Bank Counter. <0> ~Bank Counter <3> The rising edge of the counter signal (Bank Counter). <0> ~Bank Counter <3> After being delayed and inverted by the fifth inverter D5, the signal is then input to the fourth AND gate A4, thus avoiding any shielding effect on regular instructions. In this way, the valid pulses of regular instructions can be output by the fourth AND gate A4.

[0121] It should be noted that, based on the relevant rules of digital circuit logic elements, the circuit in the example in S12 can also be replaced with a circuit composed of logic elements such as NOR gates, and no restrictions are imposed here.

[0122] It is understandable that by utilizing the different levels of the counting signal Bank Counter, the repeated instructions in the first refresh instruction can be masked, thus avoiding the current waste caused by repeated refreshes and saving circuit power consumption.

[0123] In some embodiments of this application, such as Figure 16 As shown, the refresh window sub-signals include: the first refresh window sub-signal ReW. Or the second refresh window sub-signal ReW <ab>Each refresh window sub-signal generation circuit 207 includes: a first NOR gate E1 and a second latch L2. The first input of the first NOR gate E1 is connected to the output of the corresponding repeat instruction masking circuit 206. When the refresh control circuit performs the first refresh operation, the first input of the first NOR gate E1 receives the corresponding first refresh instruction SB CMD. Alternatively, when the refresh control circuit performs a second refresh operation, the second input of the first NOR gate E1 receives the second refresh instruction AB CMD. The set input of the second latch L2 is connected to the output of the first NOR gate E1, and the reset input of the second latch L2 receives the refresh window reset signal Refresh Window Reset; when the refresh control circuit performs a first refresh operation, the second latch L2 outputs the corresponding first refresh window sub-signal ReW. Alternatively, when the refresh control circuit performs a second refresh operation, the second latch outputs the corresponding second refresh window sub-signal ReW. <ab>Here, i is greater than or equal to 0 and less than or equal to m-1, and the first refresh instruction is SB CMD. For any of a plurality of first refresh instructions, the first refresh window sub-signal ReW Corresponding to the first refresh command SB CMD .

[0124] In the embodiments of this application, Figure 17 The signal timing diagram when m=4, combined with Figure 16 and Figure 17 When the refresh control circuit performs the first refresh operation, the first refresh instruction SB CMD is executed. <0> The valid pulse in the signal triggers the first refresh window sub-signal ReW. <0> The transition from low to high level triggers the first valid pulse in the Refresh Window Reset signal, which in turn triggers the first refresh window sub-signal, ReW. <0> The signal transitions from high to low, thus obtaining the first refresh window sub-signal ReW. <0> The valid pulse. Similarly, the first refresh instruction SB CMD <0> SB CMD <1> and SB CMD <2> The valid pulses in the signal trigger the first refresh window sub-signal ReW respectively. <0> ReW <1> and ReW <2> The transition from low to high level triggers the second to fourth valid pulses in the Refresh Window Reset signal, which in turn trigger the first Refresh Window sub-signal ReW. <0> ReW <1> and ReW <2> The signal transitions from high to low, thus obtaining the first refresh window sub-signal ReW. <0> ReW <1> and ReW <2> The effective pulse.

[0125] In this embodiment of the application, combined with Figure 16 and Figure 18 When the refresh control circuit performs the second refresh operation, the valid pulse in the second refresh instruction AB CMD triggers the second refresh window sub-signal ReW. <ab>The transition from low to high level triggers the second window refresh sub-signal, ReW, when a valid pulse in the Refresh Window Reset signal is applied. <ab>The signal transitions from high to low, thus generating the second refresh window sub-signal ReW. <ab>The effective pulse.

[0126] In some embodiments of this application, combined with Figure 16 and Figure 19 The refresh window sub-signal processing circuit 208 includes a second OR gate B2. When the refresh control circuit performs a first refresh operation, the input of the second OR gate B2 receives multiple first refresh window sub-signals ReW from the multiple refresh window sub-signal generation circuits 207. Alternatively, when the refresh control circuit performs a second refresh operation, the input of the second OR gate receives the same multiple second refresh window sub-signals ReW from the multiple refresh window sub-signal generation circuit 207. <ab>The second OR gate B2 outputs the Refresh Window signal.

[0127] In this embodiment of the application, reference is made to Figure 19 The refresh window signal generation circuit 201 also includes a fourteenth inverter D14. The refresh window reset signal Refresh Window Reset is transmitted to multiple refresh window sub-signal generation circuits 207 after passing through the fourteenth inverter D14.

[0128] In this embodiment of the application, reference is made to Figure 17 and Figure 19 When the refresh control circuit performs the first refresh operation, due to the first refresh window sub-signal ReW... <0> ~ReW <3> Both are active high; therefore, the Refresh Window signal output from the second OR gate B2 will include the first Refresh Window sub-signal ReW. <0> ~ReW <3> All valid pulses in the sequence.

[0129] In this embodiment of the application, reference is made to Figure 18 and Figure 19 When the refresh control circuit performs the second refresh operation, the second OR gate B2 receives the same multiple second refresh window sub-signals ReW. <ab>The refresh window signal RefreshWindow output from the second OR gate B2 and the second refresh window sub-signal ReW <ab>The waveforms are the same.

[0130] In some embodiments of this application, such as Figure 20 As shown, the second pulse generation sub-circuit 209 includes: a fourth delay unit H4, a sixth inverter D6, a fifth AND gate A5, a seventh inverter D7, a sixth AND gate A6, a second NOR gate E2, and an eighth inverter D8. The input of the fourth delay unit H4 receives the refresh window signal Refresh Window. The input of the sixth inverter D6 is connected to the output of the fourth delay unit H4. The first input of the fifth AND gate A5 receives the refresh window signal Refresh Window, and the second input of the fifth AND gate A5 is connected to the output of the sixth inverter D6. The input of the seventh inverter D7 receives the address flag signal Addr Flag. The first input of the sixth AND gate A6 is connected to the output of the seventh inverter D7, and the second input of the sixth AND gate A6 receives the address command signal Addr CMD. The input of the second NOR gate E2 is connected to the outputs of the fifth AND gate A5 and the sixth AND gate A6, respectively. The input of the eighth inverter D8 is connected to the output of the second NOR gate E2, and the eighth inverter D8 outputs the third clock signal AB CBR CLK.

[0131] In this embodiment of the application, reference is made to Figure 20 and Figure 21 The fourth delay unit H4 can delay the received refresh window signal Refresh Window by 1 to 3 ns. Then, after passing through the fourth delay unit H4, the sixth inverter D6, and the fifth AND gate A5, the refresh window signal Refresh Window can be converted into the internal activation command signal Inner ACT CMD. The pulse in the internal activation command signal Inner ACT CMD corresponds to the rising edge of the refresh window signal Refresh Window. This pulse, after passing through the second NOR gate E2 and the eighth inverter D8, constitutes the first pulse of the third clock signal AB CBR CLK. The second pulse of the third clock signal AB CBR CLK is formed based on the address flag signal Addr Flag and the address command signal AddrCMD.

[0132] In some embodiments of this application, such as Figure 22 As shown, the address command signal generation circuit 211 includes: a ninth inverter D9, a fifth delay unit H5, and a seventh AND gate A7. The input of the ninth inverter D9 receives the inner refresh window signal InnerACT Window. The input of the fifth delay unit H5 is connected to the input of the ninth inverter D9 and also receives the inner refresh window signal InnerACT Window. The input of the seventh AND gate A7 is connected to the outputs of the ninth inverter D9 and the fifth delay unit H5, respectively, and the seventh AND gate A7 outputs the address command signal Addr CMD.

[0133] In this embodiment, the fifth delay unit H5 can delay the received inner refresh window signal Inner ACTWindow by 0 to 2 ns. Combined with... Figure 22 and Figure 23 After passing through the ninth inverter D9, the fifth delay H5, and the seventh AND gate A7, the first pulse of the Inner ACT Window signal can be converted into the first pulse of the Address Command signal Addr CMD, and the second pulse of the Inner ACT Window signal can be converted into the second pulse of the Address Command signal Addr CMD.

[0134] In some embodiments of this application, such as Figure 22 As shown, the internal refresh window signal generation circuit 210 includes a third latch L3. The set terminal of the third latch L3 receives the third clock signal AB CBR CLK, the reset terminal of the third latch L3 is connected to the output terminal of the ninth inverter D9, and the third latch L3 outputs the internal refresh window signal Inner ACT Window.

[0135] In some embodiments of this application, such as Figure 24 As shown, the refresh window reset signal generation circuit 212 includes: a sixth delay unit H6, an eighth AND gate A8, and a seventh delay unit H7. The input of the sixth delay unit H6 receives the address flag signal AddrFlag. The first input of the eighth AND gate A8 is connected to the output of the sixth delay unit H6, and the second input of the eighth AND gate A8 receives the inner refresh window signal Inner ACT Window. The input of the seventh delay unit H7 is connected to the output of the eighth AND gate A8, and the seventh delay unit H7 outputs the refresh window reset signal Refresh Window Reset.

[0136] In this embodiment, the sixth delay unit H6 can delay the received address flag signal Addr Flag by 0-2ns, and the seventh delay unit H7 can delay the received signal by 4-6ns. Combined with... Figure 24 and Figure 25 After passing through the sixth delay H6, the eighth AND gate A8, and the seventh delay H7, the refresh window reset signal Refresh Window Reset can be obtained from the inner refresh window signal Inner ACT Window and the address flag signal Addr Flag.

[0137] In some embodiments of this application, such as Figure 26 As shown, the signal selection circuit 213 includes: a third NOR gate E3, a third OR gate B3, and a ninth AND gate A9. The inputs of the third NOR gate E3 receive multiple counting signals, Bank Counter. The first input of the third OR gate B3 receives either a first clock signal or a second clock signal; specifically, the first input of the third OR gate B3 receives the SameBank refresh clock signal SB CBR CLK, and the second input of the third OR gate B3 receives the third clock signal AB CBRCLK. The first input of the ninth AND gate A9 is connected to the output of the third NOR gate E3, and the second input of the ninth AND gate A9 is connected to the output of the third OR gate B3. The ninth AND gate A9 outputs either the first clock signal, the second clock signal, or the third clock signal ABCBR CLK.

[0138] In this embodiment of the application, combined with Figure 5 and Figure 26 During the first refresh operation, the waveforms of each signal received by the signal selection circuit 213 are as follows: Figure 5 As shown, the signal output by the third OR gate B3 can include all the valid pulses in the SameBank refresh clock signal SB CBR CLK and the third clock signal AB CBR CLK. However, the signal output by the third NOR gate E3 can mask the valid pulses in the third clock signal AB CBR CLK. Therefore, the signal output by the ninth AND gate A9 has the same waveform as the SameBank refresh clock signal SB CBR CLK. That is, in the case of performing the first refresh operation, the ninth AND gate A9 outputs either the first clock signal or the second clock signal.

[0139] During the second refresh operation, multiple counting signals (Bank Counter) <0> ~Bank Counter <3> Both the SameBank refresh clock signal SB, CBR, and CLK remain low. Figure 5 (not shown in the image), while the waveform of the third clock signal AB CBR CLK remains as shown. Figure 5 As shown, the signal output by the ninth AND gate A9 is the same as the waveform of the third clock signal ABCBRCLK. That is, when performing the first refresh operation, the ninth AND gate A9 outputs the third clock signal ABCBRCLK.

[0140] In some embodiments of this application, such as Figure 27 As shown, the address flag signal generation circuit 214 includes a tenth inverter D10 and a fourth latch L4. The input of the tenth inverter D10 receives the address command signal Addr CMD. The set terminal of the fourth latch L4 is connected to the output of the tenth inverter D10, the reset terminal of the fourth latch L4 receives the refresh window signal Refresh Window, and the fourth latch L4 outputs the address flag signal Addr Flag.

[0141] In this embodiment of the application, combined with Figure 27 and Figure 28 The first pulse of the address command signal Addr CMD triggers the address flag signal Addr Flag to transition from low to high. The falling edge of the refresh window signal Refresh Window triggers the address flag signal Addr Flag to transition from high to low, thus obtaining... Figure 28 The waveform of the address flag signal AddrFlag is shown.

[0142] Figure 29 An optional implementation of the refresh control circuit 101 is shown. Figure 29 This includes Figure 9 , Figure 11 , Figure 12 , Figure 14 , Figure 16 , Figure 19 , Figure 20 , Figure 22 , Figure 24 , Figure 26 and Figure 27 The circuit elements shown in the figure. Figure 30 and Figure 31 It shows Figure 29 An optional waveform diagram of the middle part of the signal, wherein, Figure 30 This is a schematic diagram of the signals corresponding to the first refresh operation performed by the refresh control circuit 101. Figure 31 A schematic diagram of the signals corresponding to the second refresh operation performed by the refresh control circuit 101.

[0143] Figure 29 Taking the Bank Group with a number of Banks m=4 as an example, therefore, Figure 29 It includes four first latches L1, four first inverters D1, and four refresh window sub-signal generation circuits 207.

[0144] Combination Figure 29 and Figure 30 When the refresh control circuit 101 performs the first refresh operation, four first refresh instructions SB CMD are issued. <0> SB CMD <1> SB CMD <2> and SB CMD <3> It includes valid pulses, and the second refresh instruction ABCMD ( Figure 30 (Not shown in the image) The second refresh instruction AB CMD remains low, meaning it does not include a valid pulse. Therefore, the set terminals of the four first latches L1 receive the four first refresh instructions SB CMD respectively through the four first inverters D1. <0> SB CMD <1> SB CMD <2> and SB CMD <3> The four first latches L1 output four counting signals, namely Bank Counter. <0> Bank Counter <1> Bank Counter <2> and Bank Counter <3> The signals are fed to the inputs of the third NOR gate E3 and the first AND gate A1. Then, the signal selection circuit 213 outputs the SameBank refresh clock signal SBCBR CLK (i.e., the first clock signal or the second clock signal) through the ninth AND gate A9. Simultaneously, the set terminals of the four second latches L2 receive the four first refresh instructions SB CMD through the four first NOR gates E1. <0> SB CMD <1> SB CMD <2> and SB CMD <3> The four second latches L2 output four first refresh window sub-signals ReW respectively. <0> ReW <1> ReW <2> and ReW <3> .

[0145] Combination Figure 8 , Figure 29 and Figure 30 It can be seen that when the refresh control circuit 101 performs the first refresh operation, the signal selection circuit 213 outputs the SameBank refresh clock signal SB CBR CLK (i.e., the first clock signal or the second clock signal) to the address processing circuit 102, and the four refresh window sub-signal generation circuits 207 output four first refresh window sub-signals ReW. <0> ReW <1> ReW <2> and ReW <3> The address flag signal generation circuit 214 outputs the address flag signal Addr Flag to the address processing circuit 102.

[0146] Combination Figure 29 and Figure 31 When the refresh control circuit 101 performs a second refresh operation, four first refresh instructions SB CMD are executed. <0> SB CMD <1> SB CMD <2> and SB CMD <3> ( Figure 31 (Not shown in the image) None of the signals include valid pulses, i.e., the four first refresh instructions SB CMD. <0> SB CMD <1> SB CMD <2> and SB CMD <3> All remain at a low level, while the second refresh instruction AB CMD includes a valid pulse. Therefore, the four counting signals BankCounter output from the four first latches L1... <0> Bank Counter <1> Bank Counter <2> and Bank Counter <3> All remain at low level ( Figure 31 (Not shown in the image). Furthermore, the signal selection circuit 213 outputs the third clock signal AB CBR CLK through the ninth AND gate A9. Simultaneously, the set terminals of the four second latches L2 receive the second refresh instruction AB CMD through four first NOR gates E1, and each of the four second latches L2 outputs four identical second refresh window sub-signals ReW. <ab>.

[0147] Combination Figure 8 , Figure 29 and Figure 31 It can be seen that when the refresh control circuit 101 performs the second refresh operation, the signal selection circuit 213 outputs the third clock signal AB CBR CLK to the address processing circuit 102, and the four refresh window sub-signal generation circuits 207 output four identical second refresh window sub-signals ReW. <ab>The address flag signal generation circuit 214 outputs the address flag signal Addr Flag to the address processing circuit 102.

[0148] In some embodiments of this application, such as Figure 32 As shown, the control signal generation circuit 303 includes: a tenth AND gate A10, an eleventh inverter D11, and a fourth NOR gate E4. The inputs of the tenth AND gate A10 respectively receive multiple refresh window sub-signals ReW. The input of the eleventh inverter D11 receives the address flag signal Addr Flag. The first input of the fourth NOR gate E4 is connected to the output of the tenth AND gate A10, the second input of the fourth NOR gate E4 is connected to the output of the eleventh inverter D11, and the fourth NOR gate E4 outputs the address control signal Addr Ctrl.

[0149] In the embodiments of this application, Figure 33 Taking m=4 as an example, combined with Figure 32 and Figure 33 When the refresh control circuit performs the first refresh operation, each input of the tenth AND gate A10 receives multiple first refresh window sub-signals ReW. <0> ReW <1> ReW <2> and ReW <3> Then the signal ReW output by the tenth AND gate A10 <and>The signal is always low, so the address control signal Addr Ctrl and the address flag signal Addr Flag have the same waveform. In other words, the address flag signal Addr Flag retains its waveform after passing through the control signal generation circuit 303.

[0150] Combination Figure 32 and Figure 34 When the refresh control circuit performs a second refresh operation, each input of the tenth AND gate A10 receives the same second refresh window sub-signal ReW. <ab>Then the signal ReW output by the tenth AND gate A10 <and>With the second refresh window sub-signal ReW <ab>The waveforms are the same, but the signal ReW <and>The high-level region of the address flag signal (Addr Flag) overlaps with the high-level region of the address flag signal (Addr Flag). Thus, through the fourth NOR gate E4, the signal ReW... <and>The high-level region of the address flag signal Addr Flag can be shielded, so that the address control signal Addr Ctrl is always low. In other words, the address flag signal Addr Flag is shielded after passing through the control signal generation circuit 303.

[0151] It should be noted that, Figure 33 The multiple first refresh window sub-signals ReW shown <0> ReW <1> ReW <2> and ReW <3> and Figure 17 The multiple first refresh window sub-signals ReW shown <0> ReW <1> ReW <2> and ReW <3> The waveforms are the same, meaning that... Figure 33 Multiple first refresh window sub-signals ReW <0> ReW <1> ReW <2> and ReW <3> You can follow Figure 17 We can obtain this from examples. Figure 34 The second refresh window sub-signal ReW is shown. <ab>and Figure 18 The second refresh window sub-signal ReW is shown. <ab>The waveforms are the same, meaning that... Figure 34 The second refresh window sub-signal ReW <ab>You can follow Figure 18 We can obtain this from examples.

[0152] In some embodiments of this application, such as Figure 35 As shown, the address selection circuit 304 includes: a non-inverting output module 305, an inverting output module 306, a twelfth inverter D12, and an address delay module 307.

[0153] The input terminal of the non-inverting output module 305 is connected to the address counter 301. The first control terminal of the non-inverting output module 305 is used to receive the address control signal Addr Ctrl, and the second control terminal of the non-inverting output module 305 is used to receive the address control signal Addr Ctrl through the twelfth inverter D12. When the refresh control circuit receives the first refresh command and the address flag signal Addr Flag is the first value, the non-inverting output module 305, in response to the address control signal Addr Ctrl, obtains and outputs the least significant bit of the first address.

[0154] The input terminal of the inverting output module 306 is connected to the address counter 301. The first control terminal of the inverting output module 306 is used to receive the address control signal Addr Ctrl through the twelfth inverter D12, and the second control terminal of the inverting output module 306 is used to receive the address control signal Addr Ctrl. When the refresh control circuit receives the first refresh command and the address flag signal Addr Flag is the second value, the inverting output module 306, in response to the address control signal Addr Ctrl, obtains the least significant bit of the first address, inverts the least significant bit of the first address, and outputs it.

[0155] Address delay module 307 is connected to address counter 301 and is used to obtain other bits of the first address when the refresh control circuit receives the first refresh instruction, and output the other bits of the first address after delay. The other bits are address bits other than the least significant bit.

[0156] In this embodiment, the address selection circuit 304 receives the first address from the address counter 301, which is then transmitted in two parts. The least significant bit of the first address is transmitted to the non-inverting output module 305 and the inverting output module 306, while the other bits of the first address are transmitted to the delay module 307. Both the non-inverting output module 305 and the inverting output module 306 receive the address control signal Addr Ctrl. Under the control of the address control signal Addr Ctrl, the non-inverting output module 203 outputs the least significant bit of the first address, while the inverting output module 204, under the control of the address control signal Addr Ctrl, inverts the least significant bit of the first address before outputting it. Since the least significant bit of the first address will be delayed in timing after passing through the non-inverting output module 305 or the inverting output module 306, the other bits of the first address need to pass through the address delay module 307 to match the timing.

[0157] It should be noted that the number of address bits in the first address can be set according to actual needs. For example, if the first address Address<15:0> is a 16-bit address, then the least significant bit of the first address Address<15:0> is the 15th address bit. <15> In the first address Address<15:0>, the address bits excluding the least significant bit are bits 0 to 14 of the address Address<14:0>. This application does not impose any restrictions on this.

[0158] In this embodiment of the application, reference is made to Figure 35 and Figure 36 When the refresh control circuit receives the first refresh command, the address counter 301 receives the SameBank refresh clock signal SB CBR CLK, that is, it receives the first clock signal or the second clock signal.

[0159] When address counter 301 receives the first clock signal, since the first clock signal does not include a valid pulse, it will not trigger address counter 301 to change the first address. The address output signal Addr Counter Output represents the first address stored in address counter 301. (Refer to...) Figure 36 When address counter 301 receives the first clock signal, the first address n remains unchanged; while the address selection circuit 304 outputs the address to be refreshed, which is controlled by the address control signal Addr Ctrl, alternately outputting n and n+1, or alternately outputting n and n-1. Here, n+1 or n-1 is the second address, and the least significant bit of the second address is opposite to the least significant bit of the first address n. When the least significant bit of the first address n is 0, the second address is n+1. When the least significant bit of the first address n is 1, the second address is n-1. Each pair of n and n+1, or n and n-1, output by the address to be refreshed will be used to perform the first refresh operation on the corresponding SameBank in the Bank Group, until all Banks in the Bank Group have completed the first refresh operation, that is, the number of first refresh operations reaches m ( Figure 36 (Taking m=4 as an example), during this process, the first address stored in address counter 301 remains unchanged at n.

[0160] When the number of first refresh operations reaches m, meaning all banks have completed the first refresh operation of this round, address counter 301 receives the second clock signal. Since the second clock signal includes two valid pulses, address counter 301 will increment by 2 at the first address, thus changing the first address to the third address. At this point, all banks in the Bank Group have completed the previous round of first refresh operations. After the refresh control circuit receives the next round of first refresh instructions, it can perform the next round of first refresh operations according to the third address.

[0161] For example, if the current first address is 0000, the least significant bit of the first address is flipped to become the second address 0001. The second address is then incremented by 1 relative to the first address, and this process is repeated for each bank in the first refresh operation (Same Bank Refresh). After all banks have completed this round of the first refresh operation, the address generator 102 is triggered by two pulses in the second clock signal, increments the first address by 2, outputs 0010, and then performs the next round of the first refresh operation. As another example, if the current first address is 0001, the least significant bit of the first address is flipped to become the second address 0000. The second address is then decremented by 1 relative to the first address. After all banks have completed this round of the first refresh operation, the address generator 102 is triggered by two pulses in the second clock signal, increments the first address by 2, outputs 0011, and then performs the next round of the first refresh operation.

[0162] It should be noted that, Figure 36 and Figure 2 The waveforms of the first clock signal or the second clock signal shown are the same, that is to say, Figure 36 The first clock signal or the second clock signal shown can be transmitted through the clock signal. Figure 2 We can obtain this from examples.

[0163] Understandably, when performing the first refresh operation on a SameBank within a Bank Group, it refreshes two adjacent addresses (i.e., n and n+1, or n and n-1) within that SameBank, while the first address n remains unchanged during this process. Once all Banks in the Bank Group have completed their first refresh operations on the two adjacent addresses (i.e., after all Banks in the Bank Group have completed the previous round of first refresh operations), the first address is incremented by 2 to become the third address, which can then be used for the next round of first refresh operations. This ensures that the addresses in each Bank are refreshed sequentially, guaranteeing the continuity of refreshed addresses and preventing any addresses from being missed during the first refresh operation.

[0164] In this embodiment of the application, reference is made to Figure 35 The in-phase output module 305 is also used to obtain and output the least significant bit of the fourth address or the least significant bit of the fifth address in response to the address control signal Addr Ctrl when the refresh control circuit receives the second refresh instruction.

[0165] The address delay module 307 is also used to obtain other bits of the fourth address or the other bits of the fifth address when the refresh control circuit receives the second refresh instruction, and output the other bits of the fourth address or the other bits of the fifth address after delay.

[0166] In this embodiment, the address selection circuit 304 receives the fourth or fifth address from the address counter 301 and transmits it in two parts. The least significant bit of the address is transmitted to the non-inverting output module 305 and the inverting output module 306, while the other bits of the address are transmitted to the delay module 307. Both the non-inverting output module 305 and the inverting output module 306 receive the address control signal Addr Ctrl. Under the control of the address control signal Addr Ctrl, the non-inverting output module 203 outputs the least significant bit of the address, while the inverting output module 204, under the control of the address control signal Addr Ctrl, inverts the least significant bit of the address before outputting it. Since the least significant bit of the address is delayed in timing after passing through the non-inverting output module 305 or the inverting output module 306, the other bits of the address need to pass through the address delay module 307 to match the timing.

[0167] refer to Figure 35 and Figure 37 When the refresh control circuit receives the second refresh command, the address counter 301 receives the third clock signal AB CBR CLK. Each valid pulse in the third clock signal AB CBR CLK triggers the address counter 301 to increment by 1 at the first address. The address output signal Addr Counter Output represents the first address stored in the address counter 301, as shown in the reference. Figure 37 The address output signal, Addr Counter Output, is incremented under the trigger of the third clock signal, ABCBR CLK. Figure 37 The third clock signal AB CBR CLK shown contains four cycles, with each cycle consisting of two valid pulses. Thus, in the first cycle, the first address n is triggered to change to the fourth address n+1 and the fifth address n+2; in the second cycle, n+2 is triggered to change to the fourth address n+3 and the fifth address n+4 as the first address, and so on.

[0168] Simultaneously, the address control signal Addr Ctrl remains low, thus the inverting output module 306 is inactive, and the least significant bit of the address is output through the non-inverting output module 305. In other words, the address to be refreshed for the second refresh operation is consistent with the address output signal Addr Counter Output. This allows for the second refresh operation to be performed on all addresses in the Bank in the order of addresses, avoiding any omissions that prevent the second refresh operation from being performed.

[0169] It should be noted that, Figure 37 and Figure 6 The waveforms of the third clock signal AB CBR CLK shown are the same, that is, Figure 37 The third clock signal AB CBR CLK shown can be... Figure 6 We can obtain this from examples.

[0170] Understandably, when all banks in the Bank Group undergo the second refresh operation, address generator 102 generates consecutive addresses to be refreshed based on the third clock signal AB CBR CLK, ensuring that each address in all banks completes the second refresh operation sequentially (i.e., All Bank Refresh). This allows for the second refresh operation on addresses in all banks according to their order, guaranteeing the continuity of refreshed addresses and preventing any addresses from being missed and thus avoiding the need for a second refresh operation. Furthermore, using a single address generator 102 allows for flexible execution of both refresh operations, thereby improving circuit compatibility.

[0171] In some embodiments of this application, such as Figure 38 As shown, the non-inverting output module 305 includes a first PMOS transistor P1 and a first NMOS transistor N1. The inverting output module 306 includes a thirteenth inverter D13, a second PMOS transistor P2, and a second NMOS transistor N2.

[0172] The gate of the first PMOS transistor P1 serves as the first control terminal of the non-inverting output module 305, and the gate of the first NMOS transistor N1 serves as the second control terminal of the non-inverting output module 305. The source of the first PMOS transistor P1 is connected to the drain of the first NMOS transistor N1 and serves as the input terminal of the non-inverting output module 305. The drain of the first PMOS transistor P1 is connected to the source of the first NMOS transistor N1 and serves as the output terminal of the non-inverting output module 305. The gate of the second PMOS transistor P2 serves as the first control terminal of the inverting output module 306, and the gate of the second NMOS transistor N2 serves as the second control terminal of the inverting output module 306. The input terminal of the thirteenth inverter D13 serves as the input terminal of the inverting output module 306, and the output terminal of the thirteenth inverter D13 is connected to the source of the second PMOS transistor P2 and the drain of the second NMOS transistor N2. The drain of the second PMOS transistor P2 is connected to the source of the second NMOS transistor N2 and serves as the output terminal of the inverting output module 306.

[0173] In this embodiment, the source of the first PMOS transistor P1 is connected to the drain of the first NMOS transistor N1 and serves as the input terminal of the non-inverting output module 305, receiving the least significant bit of the address from the address counter 301. If the address control signal Addr Ctrl is low, the first PMOS transistor P1 and the first NMOS transistor N1 are in the enabled state, and the least significant bit of the address is output from the drain of the first PMOS transistor P1 and the source of the first NMOS transistor N1; if the address control signal Addr Ctrl is high, the first PMOS transistor P1 and the first NMOS transistor N1 are in the disabled state, and there is no output signal from the drain of the first PMOS transistor P1 and the source of the first NMOS transistor N1.

[0174] The input terminal of the thirteenth inverter D13 serves as the input terminal of the inverting output module 306, receiving the least significant bit of the address from the address counter 301. This least significant bit is inverted after passing through the thirteenth inverter D13. If the address control signal AddrCtrl is high, the second PMOS transistor P2 and the second NMOS transistor N2 are enabled, and the inverted least significant bit of the address is output from the drain of the second PMOS transistor P2 and the source of the second NMOS transistor N2. If the address control signal AddrCtrl is low, the second PMOS transistor P2 and the second NMOS transistor N2 are disabled, and there is no output signal from the drain of the second PMOS transistor P2 and the source of the second NMOS transistor N2.

[0175] It should be noted that the non-inverting output module 305 can also be configured to output the least significant bit of the address when the address control signal Addr Ctrl is high, and the inverting output module 306 can also be configured to invert the least significant bit of the address and output it when the address control signal Addr Ctrl is low. There are no restrictions here.

[0176] It should be noted that, in this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.

[0177] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this application can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined to obtain new method or device embodiments without conflict.

[0178] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.< / ab> < / ab> < / ab> < / and> < / and> < / ab> < / and> < / ab> < / and> < / ab> < / ab> < / ab> < / ab> < / ab> < / ab> < / ab> < / ab> < / ab> < / ab>

Claims

1. A refresh address generation circuit, characterized in that, The refresh address generation circuit includes: A refresh control circuit is configured to sequentially receive multiple first refresh instructions and perform multiple first refresh operations accordingly. When the number of first refresh operations is less than m, a first clock signal is output, and when the number of first refresh operations is equal to m, a second clock signal is output, where m is an integer greater than or equal to 1. The refresh control circuit is also configured to block duplicate instructions when duplicate instructions appear in the first refresh instructions. An address generator, coupled to the refresh control circuit, is used to pre-store a first address and receive a first clock signal or a second clock signal. During each of the first refresh operations, it outputs the address to be refreshed in response to the first clock signal and changes the first address in response to the second clock signal. The refresh control circuit includes: A refresh window signal generation circuit is configured to receive multiple first refresh instructions and a refresh window reset signal, generate a refresh window signal based on the multiple first refresh instructions and the refresh window reset signal, and, when a duplicate instruction appears in the first refresh instructions, mask the duplicate instruction; wherein, the pulse duration of the refresh window signal is the window time for the refresh control circuit to perform one refresh operation, and the refresh window reset signal is used to reset the refresh window signal generation circuit after one refresh operation is completed; A clock pulse generation circuit, coupled to the refresh window signal generation circuit, is used to receive the refresh window signal and the first refresh instruction. Before the number of the first refresh instructions received by the clock pulse generation circuit is less than or equal to m and before the m-th first refresh operation ends, the first clock signal is generated; or, after the m-th first refresh operation ends, the second clock signal is generated.

2. The circuit according to claim 1, characterized in that, The clock pulse generation circuit includes: A counting circuit is configured to receive the first refresh instruction and a counting reset signal, count the first refresh instruction and output a counting signal, and reset according to the counting reset signal. A count reset signal generation circuit, coupled to the counting circuit and the refresh window signal generation circuit, is used to generate the count reset signal after the m-th first refresh operation is completed; The first pulse generation sub-circuit, coupled to the counting reset signal generation circuit, is used to generate the first clock signal according to the counting signal when the first refresh instruction is less than m, or to generate the second clock signal according to the counting reset signal when the first refresh instruction is equal to m.

3. The circuit according to claim 2, characterized in that, The refresh window signal generation circuit includes: Multiple duplicate instruction shielding circuits, coupled to the counting circuit, are used to receive multiple first refresh instructions and multiple counting signals respectively, and output multiple first refresh instructions when no duplicate instruction appears in the multiple first refresh instructions according to the multiple counting signals, and shield the duplicate instruction and do not output it when a duplicate instruction appears in the multiple first refresh instructions; Multiple refresh window sub-signal generation circuits are respectively coupled to multiple repeat instruction shielding circuits, and are used to receive refresh window reset signals and receive multiple first refresh instructions from multiple repeat instruction shielding circuits, and output multiple refresh window sub-signals in sequence according to multiple first refresh instructions and refresh window reset signals. A refresh window sub-signal processing circuit, coupled to the plurality of refresh window sub-signal generation circuits, is used to sequentially receive the plurality of refresh window sub-signals, perform logical operations on the refresh window sub-signals, and output the refresh window signal.

4. The circuit according to claim 3, characterized in that, The refresh control circuit is further configured to receive a second refresh command and perform a second refresh operation; wherein, The multiple refresh window sub-signal generation circuits are also used to simultaneously receive the second refresh instruction and the refresh window reset signal, and generate the same multiple refresh window sub-signals one-to-one according to the second refresh instruction and the refresh window reset signal; The refresh window sub-signal processing circuit is further configured to receive multiple refresh window sub-signals, perform logical operations on the refresh window sub-signals, and output the refresh window signal.

5. The circuit according to claim 4, characterized in that, The refresh control circuit also includes: The second pulse generation sub-circuit, coupled to the refresh window signal generation circuit, is used to receive the refresh window signal and the address command signal, generate the first pulse of the third clock signal when the refresh control circuit starts to perform the first refresh operation or the second refresh operation, and output the second pulse of the third clock signal according to the first pulse of the address command signal, thereby outputting the third clock signal. An internal refresh window signal generation circuit receives the third clock signal and generates the internal refresh window signal based on the third clock signal; wherein, the first pulse of the internal refresh window signal is generated after the first pulse of the third clock signal and ends before the second pulse of the third clock signal is generated; the second pulse of the internal refresh window signal is generated after the second pulse of the third clock signal and ends before the pulse of the refresh window signal ends. The address command signal generation circuit is used to generate a first pulse and a second pulse of the address command signal based on the falling edge of the internal refresh window signal; wherein, the first pulse of the address command signal is used to generate the second pulse of the internal refresh window signal and the second pulse of the third clock signal; A refresh window reset signal generation circuit receives the internal refresh window signal and generates a pulse for the refresh window reset signal based on the falling edge of the second pulse of the internal refresh window signal.

6. The circuit according to claim 5, characterized in that, The refresh control circuit also includes: A signal selection circuit, coupled to the counting circuit, the first pulse generation sub-circuit, and the second pulse generation sub-circuit, is used to receive the counting signal, the first clock signal, the second clock signal, and the third clock signal. When the refresh control circuit performs the first refresh operation, it outputs the first clock signal or the second clock signal according to the counting signal; or, when the refresh control circuit performs the second refresh operation, it outputs the third clock signal according to the counting signal.

7. The circuit according to claim 6, characterized in that, The refresh control circuit also includes: The address flag signal generation circuit, coupled to the address command signal generation circuit and the refresh window signal generation circuit, is used to receive the address command signal and the refresh window signal, generate the rising edge of the address flag signal based on the first rising edge of the address command signal, and generate the falling edge of the address flag signal based on the falling edge of the refresh window signal.

8. The circuit according to claim 7, characterized in that, The address generator includes: An address counter, coupled to the signal selection circuit, is used to pre-store the first address, change the first address to a third address according to the second clock signal, or change the first address and output a fourth and a fifth address according to the third clock signal; the first address, the fourth address, and the fifth address are three consecutive addresses. The address processing circuit, coupled to the address counter and the refresh window sub-signal generation circuit, is used to receive the address flag signal when the refresh control circuit performs the first refresh operation, obtain the first address and process the first address, output the first address before the rising edge of the address flag signal arrives, or output the second address after the rising edge of the address flag signal arrives, wherein the least significant bit of the first address and the least significant bit of the second address are opposite. The address processing circuit is further configured to, when the refresh control circuit performs the second refresh operation, sequentially acquire the fourth address and the fifth address, and sequentially output the fourth address and the fifth address according to the plurality of refresh window sub-signals.

9. The circuit according to claim 8, characterized in that, The address processing circuit includes: A control signal generation circuit, coupled to the refresh window sub-signal generation circuit and the address flag signal generation circuit, is used to receive multiple refresh window sub-signals and the address flag signal, and generate an address control signal based on the multiple refresh window signals and the address flag signal; The address selection circuit, coupled to the address counter and the control signal generation circuit, is used to output the first address according to the address control signal when the refresh control circuit receives the first refresh instruction, or to invert the least significant bit of the first address according to the address control signal to obtain and output the second address. The address selection circuit is further configured to, in response to the address control signal, sequentially output the fourth address and the fifth address when the refresh control circuit receives the second refresh instruction.

10. The circuit according to claim 2, characterized in that, The counting circuit includes: Multiple first inverters, the input terminals of the multiple first inverters sequentially receive multiple first refresh commands; The second inverter receives the count reset signal at its input terminal. Multiple first latches are provided, with the set terminals of the multiple first latches sequentially connected to the output terminals of the multiple first inverters, and the reset terminals of the multiple first latches connected to the output terminals of the second inverters. The multiple first latches sequentially output multiple counting signals.

11. The circuit according to claim 2, characterized in that, The counting reset signal generation circuit includes: A first AND gate, the input of which receives a plurality of the counting signals; The third inverter receives the refresh window signal at its input terminal. The second AND gate has its input terminals connected to the output terminals of the first AND gate and the third inverter, respectively. A first delay unit, the input of which is connected to the output of the second AND gate; A fourth inverter, the input of which is connected to the output of the first delay unit; The third AND gate has its input terminals connected to the output terminals of the second AND gate and the fourth inverter, respectively, and outputs the count reset signal.

12. The circuit according to claim 2, characterized in that, The first pulse generation sub-circuit includes: The second delay unit receives the count reset signal at its input terminal; A third delay unit, wherein the input terminal of the third delay unit is connected to the output terminal of the second delay unit; The first OR gate has its input terminals connected to the output terminals of the second delay unit and the third delay unit, respectively, and outputs either the first clock signal or the second clock signal.

13. The circuit according to claim 3, characterized in that, Each of the repeat instruction masking circuits includes: The fifth inverter receives the corresponding counting signal at its input terminal; The fourth AND gate has its first input connected to the output of the fifth inverter, its second input receiving the corresponding first refresh instruction, and its output serving as the output of the repeat instruction shielding circuit.

14. The circuit according to claim 4, characterized in that, The refresh window sub-signal includes: a first refresh window sub-signal or a second refresh window signal; each refresh window sub-signal generation circuit includes: The first NOR gate has its first input connected to the output of the corresponding repeat instruction shielding circuit. When the refresh control circuit performs the first refresh operation, the first input of the first NOR gate receives the corresponding first refresh instruction; or, when the refresh control circuit performs the second refresh operation, the second input of the first NOR gate receives the second refresh instruction. The second latch has its set terminal connected to the output terminal of the first NOR gate, and its reset terminal receiving the refresh window reset signal. When the refresh control circuit performs the first refresh operation, the second latch outputs the corresponding first refresh window sub-signal; or, when the refresh control circuit performs the second refresh operation, the second latch outputs the corresponding second refresh window sub-signal.

15. The circuit according to claim 14, characterized in that, The refresh window sub-signal processing circuit includes: The second OR gate receives multiple first refresh window sub-signals at its input terminal when the refresh control circuit performs the first refresh operation, or receives the same multiple second refresh window sub-signals at its input terminal when the refresh control circuit performs the second refresh operation; the second OR gate outputs the refresh window signal.

16. The circuit according to claim 5, characterized in that, The second pulse generation sub-circuit includes: The fourth delay unit receives the refresh window signal at its input. The sixth inverter, the input of which is connected to the output of the fourth delay unit; The fifth AND gate, the first input of which receives the refresh window signal, and the second input of which is connected to the output of the sixth inverter; The seventh inverter receives an address flag signal at its input terminal; The sixth AND gate has its first input connected to the output of the seventh inverter, and its second input receiving the address command signal. The second NOR gate, the input of the second NOR gate is connected to the output of the fifth AND gate and the output of the sixth AND gate respectively; The eighth inverter has its input connected to the output of the second NOR gate, and outputs the third clock signal.

17. The circuit according to claim 5, characterized in that, The address command signal generation circuit includes: The ninth inverter receives the internal refresh window signal at its input terminal; The fifth delay unit, whose input is connected to the input of the ninth inverter, receives the internal refresh window signal; The seventh AND gate has its input terminals connected to the output terminals of the ninth inverter and the fifth delay unit, respectively, and outputs the address command signal.

18. The circuit according to claim 17, characterized in that, The internal refresh window signal generation circuit includes: The third latch has a set terminal that receives the third clock signal, a reset terminal that is connected to the output terminal of the ninth inverter, and an output of the internal refresh window signal.

19. The circuit according to claim 5, characterized in that, The refresh window reset signal generation circuit includes: The sixth delay unit receives the address flag signal at its input terminal; The eighth AND gate, the first input of which is connected to the output of the sixth delay, and the second input of which receives the internal refresh window signal; The seventh delay unit has its input connected to the output of the eighth AND gate, and outputs the refresh window reset signal.

20. The circuit according to claim 6, characterized in that, The signal selection circuit includes: The third NOR gate receives multiple counting signals at its input terminals. The third OR gate has a first input terminal that receives the first clock signal or the second clock signal, and a second input terminal that receives the third clock signal. The ninth AND gate has its first input connected to the output of the third NOR gate, and its second input connected to the output of the third OR gate. The ninth AND gate outputs the first clock signal, the second clock signal, or the third clock signal.

21. The circuit according to claim 7, characterized in that, The address flag signal generation circuit includes: The tenth inverter receives the address command signal at its input terminal; The fourth latch has its set terminal connected to the output terminal of the tenth inverter, its reset terminal receiving the refresh window signal, and its outputting the address flag signal.

22. The circuit according to claim 9, characterized in that, The control signal generation circuit includes: The tenth AND gate, whose input terminals respectively receive multiple refresh window sub-signals; The eleventh inverter receives the address flag signal at its input terminal. The fourth NOR gate has its first input connected to the output of the tenth AND gate, and its second input connected to the output of the eleventh inverter. The fourth NOR gate outputs the address control signal.

23. The circuit according to claim 9, characterized in that, The address selection circuit includes: a non-inverting output module, an inverting output module, a twelfth inverter, and an address delay module; The input terminal of the non-inverting output module is connected to the address counter; the first control terminal of the non-inverting output module is used to receive the address control signal; the second control terminal of the non-inverting output module is used to receive the address control signal through the twelfth inverter; the non-inverting output module is used to, in response to the address control signal, obtain and output the least significant bit of the first address when the refresh control circuit receives the first refresh instruction and the address flag signal is a first value. The input terminal of the inverting output module is connected to the address counter; the first control terminal of the inverting output module is used to receive the address control signal through the twelfth inverter; the second control terminal of the inverting output module is used to receive the address control signal; the inverting output module is used to, in response to the address control signal, obtain the least significant bit of the first address, invert the least significant bit of the first address, and output it when the refresh control circuit receives the first refresh instruction and the address flag signal is the second value. The address delay module is connected to the address counter and is used to obtain other bits of the first address when the refresh control circuit receives the first refresh instruction, and output the other bits of the first address after delay; the other bits are address bits other than the least significant bit.

24. The circuit according to claim 23, characterized in that, The in-phase output module is further configured to, in response to the address control signal, acquire and output the least significant bit of the fourth address or the least significant bit of the fifth address when the refresh control circuit receives the second refresh instruction; The address delay module is further configured to, when the refresh control circuit receives the second refresh instruction, obtain other bits of the fourth address or other bits of the fifth address, and output the other bits of the fourth address or other bits of the fifth address after delay.

25. The circuit according to claim 23, characterized in that, The non-inverting output module includes a first PMOS transistor and a first NMOS transistor; the inverting output module includes a thirteenth inverter, a second PMOS transistor, and a second NMOS transistor. The gate of the first PMOS transistor serves as the first control terminal of the non-inverting output module, the gate of the first NMOS transistor serves as the second control terminal of the non-inverting output module, the source of the first PMOS transistor is connected to the drain of the first NMOS transistor and serves as the input terminal of the non-inverting output module, and the drain of the first PMOS transistor is connected to the source of the first NMOS transistor and serves as the output terminal of the non-inverting output module. The gate of the second PMOS transistor serves as the first control terminal of the inverting output module, the gate of the second NMOS transistor serves as the second control terminal of the inverting output module, the input terminal of the thirteenth inverter serves as the input terminal of the inverting output module, the output terminal of the thirteenth inverter is connected to the source of the second PMOS transistor and the drain of the second NMOS transistor, and the drain of the second PMOS transistor is connected to the source of the second NMOS transistor and serves as the output terminal of the inverting output module.

Images