Method of operating a storage device, non-volatile storage device, and storage system

Abstract

Embodiments of the present application provide an operating method of a storage device, a nonvolatile storage device and a storage system. The storage device includes a plurality of memory strings, each of which includes a first memory cell group, a dummy memory cell group and a second memory cell group connected in sequence. The operating method includes: performing a pre-programming operation or an erase operation on the first memory cell group by applying a first preset voltage to one end of the memory string close to the first memory cell group; and during the application of the first preset voltage, applying a second preset voltage to the gate of the dummy memory cell group to make the channel potential of the dummy memory cell group higher than the channel potential of the first memory cell group. The embodiments of the present application can reduce the influence of the pre-programming / erase stage of the first memory cell group on the second memory cell group.

Description

Technical Field

[0001] The embodiments of this application relate to the field of semiconductor technology, and more specifically, to a method of operating a storage device, a non-volatile storage device, and a storage system. Background Technology

[0002] Flash memory has been widely used in microcomputers, automation control, and other fields due to its advantages such as high integration density, fast access speed, and ease of erasure and rewriting. To further improve the bit density of flash memory, three-dimensional memory technology has been proposed. With the continuous increase in the number of stacked layers in three-dimensional memory, its structure has changed from the traditional single-layer structure to a dual-layer structure.

[0003] For a three-dimensional memory with a dual-layer structure, it is possible to perform erase and program operations on the two layers separately, but the two layers are prone to mutual interference. Summary of the Invention

[0004] Embodiments of this application provide an operation method for a storage device. The storage device includes multiple storage strings, each storage string including a first storage cell group, a pseudo storage cell group, and a second storage cell group connected in series. The operation method includes: performing a pre-programming operation or an erase operation on the first storage cell group by applying a first preset voltage to one end of the storage string near the first storage cell group; and, during the application of the first preset voltage, applying a second preset voltage to the gate of the pseudo storage cell group to make the channel potential of the pseudo storage cell group higher than the channel potential of the first storage cell group.

[0005] In one embodiment of this application, during the application of a first preset voltage, one end of the memory string that is away from the first memory cell group is floated.

[0006] In one embodiment of this application, the duration for which the second preset voltage is applied is greater than or equal to the duration for which the first preset voltage is applied.

[0007] In one embodiment of this application, the magnitude of the second preset voltage is positively correlated with the magnitude of the first preset voltage.

[0008] In one embodiment of this application, during the pre-programming operation, the magnitude of the first preset voltage is 5-7V, and the magnitude of the second preset voltage is 5-7V.

[0009] In one embodiment of this application, during the erasure operation, the magnitude of the first preset voltage is 18-22V and the magnitude of the second preset voltage is 14-16V.

[0010] In one embodiment of this application, the memory string further includes a first select gate transistor connected in series with the first memory cell group, and the operation method further includes: during the application of a first preset voltage, by applying a third preset voltage to the gate of the first select gate transistor, a voltage difference is formed between the source or drain of the first select gate transistor and the gate of the first select gate transistor.

[0011] In one embodiment of this application, the memory string further includes a second select gate transistor connected in series with the second memory cell group; wherein, during the application of a first preset voltage, the gate of the second select gate transistor is floating.

[0012] In some embodiments of this application, the magnitude of the third preset voltage is 0V during the pre-programming operation.

[0013] In some embodiments of this application, the magnitude of the third preset voltage is 8-12V during the erasure operation.

[0014] In some embodiments of this application, the operation method further includes: applying a fourth preset voltage to the gate of a memory cell in the first memory cell group during the application of a first preset voltage; and maintaining data in the second memory cell group by applying a fifth preset voltage to the gate of a memory cell in the second memory cell group.

[0015] In some embodiments of this application, the magnitude of the fifth preset voltage is 0V during the pre-programming operation.

[0016] In some embodiments of this application, the magnitude of the fifth preset voltage is 4-6V during the erasure operation.

[0017] Another embodiment of this application provides a non-volatile memory device, comprising: a memory block including a plurality of memory strings, each memory string including a first memory cell group, a pseudo memory cell group and a second memory cell group connected in series; peripheral circuitry coupled to the memory block and configured to: perform a pre-programming / erasing operation on the first memory cell group by applying a first preset voltage to one end of the memory string near the first memory cell group; and, during the application of the first preset voltage, apply a second preset voltage to the gate of the pseudo memory cell group to make the channel potential of the pseudo memory cell group higher than the channel potential of the first memory cell group.

[0018] In one embodiment of this application, during the application of a first preset voltage, one end of the memory string that is away from the first memory cell group is floated.

[0019] In one embodiment of this application, the memory string further includes a first select gate transistor connected in series with the first memory cell group, and the peripheral circuit is further configured to: during the application of a first preset voltage, by applying a third preset voltage to the gate of the first select gate transistor, form a voltage difference between the source or drain of the first select gate transistor and the gate of the first select gate transistor.

[0020] In one embodiment of this application, the memory string further includes a second select gate transistor connected in series with the second memory cell group; wherein, during the application of a first preset voltage, the gate of the second select gate transistor is floating.

[0021] In one embodiment of this application, the peripheral circuit is further configured to: apply a fourth preset voltage to the gate of a memory cell in the first memory cell group during the application of a first preset voltage; and maintain data in the second memory cell group by applying a fifth preset voltage to the gate of a memory cell in the second memory cell group.

[0022] Another embodiment of this application provides a non-volatile storage system, including: a non-volatile storage device as mentioned in the above embodiments; and a controller coupled to the storage device and configured to control the storage device.

[0023] According to the embodiments of this application, during the pre-programming / erasing operation of the first memory cell group by the non-volatile storage device, during the application of the first preset voltage, a second preset voltage is applied to the pseudo memory cell group to form a high potential near the channel of the pseudo memory cell group, thereby blocking the transmission of holes generated by the first memory cell group under the first preset voltage to the second memory cell group, reducing the number of holes entering the second memory cell group, and reducing the impact of the pre-programming / erasing operation of the first memory cell group on the second memory cell group. Attached Figure Description

[0024] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Wherein:

[0025] Figure 1 This is a schematic block diagram of a non-volatile storage device according to an embodiment of this application;

[0026] Figure 2 This is an equivalent circuit diagram of a storage block according to an embodiment of this application;

[0027] Figure 3 It is based on Figure 2 The equivalent circuit diagram of a portion of the memory block is shown;

[0028] Figure 4 It is based on Figure 3A partial structural diagram of the storage string is shown;

[0029] Figure 5 This is a schematic diagram of the voltage waveform of the BL side GIDL pre-programming method according to an embodiment of this application;

[0030] Figure 6 This is a schematic diagram of the voltage waveform of the SL side GIDL pre-programming method according to an embodiment of this application;

[0031] Figure 7 This is a comparison diagram of the voltage distribution at the edge of the read window using the half-block programming method and the whole-block programming method in the embodiments of this application;

[0032] Figure 8 This is a flowchart of an operation method of a storage device according to an embodiment of this application;

[0033] Figure 9 yes Figure 5 The diagram shows the cavitation flow generated by the BL side GIDL pre-programming method.

[0034] Figure 10 yes Figure 6 The diagram shows the cavitation flow generated by the SL side GIDL pre-programming method.

[0035] Figure 11 This is a schematic diagram of hole flow according to one embodiment of this application;

[0036] Figure 12 This is a schematic diagram of hole flow according to another embodiment of this application;

[0037] Figure 13 This is a schematic diagram of voltage waveforms during pre-programming and programming operations performed by a storage device according to an embodiment of this application;

[0038] Figure 14 This is a schematic diagram of voltage waveforms during pre-programming and programming operations performed by a storage device according to another embodiment of this application;

[0039] Figure 15 This is a schematic diagram of the voltage waveform during an erase operation performed by a storage device according to an embodiment of this application;

[0040] Figure 16 This is a schematic diagram of the voltage waveform during an erase operation performed by a storage device according to another embodiment of this application;

[0041] Figure 17 and Figure 18 This is a comparison diagram of channel potentials according to embodiments of this application;

[0042] Figure 19 This is a block diagram of a non-volatile memory system according to an embodiment of this application;

[0043] Figure 20 This is a schematic diagram of the structure of a non-volatile storage system according to an exemplary embodiment of this application;

[0044] Figure 21 This is a schematic diagram of the structure of another non-volatile storage system according to an exemplary embodiment of this application. Detailed Implementation

[0045] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements.

[0046] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. For example, without departing from the teachings of this application, the first group of storage cells discussed in this application may also be referred to as the second group of storage cells, and the first pseudo-storage cell group may be referred to as the second pseudo-storage cell group, and vice versa.

[0047] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0048] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0049] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0050] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be performed in any order or in parallel. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0051] Furthermore, when the term "connection" or "linkage" is used in this application, it may indicate direct or indirect contact between the corresponding components, unless otherwise expressly defined or deduced from the context.

[0052] Figure 1 This is a schematic block diagram of a non-volatile storage device 100 according to an embodiment of this application. Figure 2 This is an equivalent circuit diagram of storage block BLK1 according to an embodiment of this application. Figure 3 It is based on Figure 2 The diagram shown is an equivalent circuit diagram of a portion of memory block BLK1. Figure 4 It is based on Figure 3 The diagram shows a partial structural diagram of the storage string MS.

[0053] In one embodiment of this application, see Figure 1 The non-volatile memory device 100 may, for example, include a first semiconductor structure 110 and a second semiconductor structure 120. The first semiconductor structure 110 may, for example, include a memory cell array 111, which may include, for example, one or more memory blocks BLK1 to BLK2. The second semiconductor structure 120 may, for example, include peripheral circuitry electrically connected to the first semiconductor structure 110, the peripheral circuitry being configured to perform the operation methods of the memory device mentioned in the embodiments of this application.

[0054] For example, see Figure 1 and Figure 2 The peripheral circuitry may include, for example, an address decoder 121, a page buffer 122, a control logic circuit 123, an I / O circuit 124, and a voltage generator 125.

[0055] The memory cell array 111 can be connected to the address decoder 121 via, for example, memory layer word lines WL, top redundant word lines TRL, middle redundant word lines IRL, bottom redundant word lines BRL, top select word lines TSL, and bottom select word lines BSL, and to the page buffer 122 via, for example, bit lines BL. The memory cell array 111 may include multiple memory blocks BLK1 to BLK2, and each memory block may include multiple pages. Exemplarily, the non-volatile memory device 100 performs erase operations on a memory block BLK basis and performs programming or read operations on a page basis.

[0056] Address decoder 121 can control, in response to control logic circuit 123, the memory layer word line WL, top redundant word line TRL, middle redundant word line IRL, bottom redundant word line BRL, top select word line TSL, and bottom select word line BSL connected to the memory cell array 111. Specifically, memory layer word line WL is connected to the memory layer, top redundant word line TRL is connected to the top redundant layer, middle redundant word line IRL is connected to the middle redundant layer, bottom redundant word line BRL is connected to the bottom redundant layer, top select word line TSL is connected to the top select layer, and bottom select word line BSL is connected to the bottom select layer. In other words, address decoder 121 can receive and decode address ADDR from control logic circuit 123, and select one of multiple memory blocks BLK1 to BLKz in memory cell array 111 based on the decoded address ADDR. For example, one of multiple pages in the selected memory block can be selected. Each memory layer word line WL can be used to control one page. Address decoder 121 can apply the voltage required for the memory layer word line WL from voltage generator 125 to the selected memory layer word line WL in the selected memory block BLK.

[0057] Page buffer 122 can function as a write driver or a sense amplifier depending on the operating mode. For example, in a programming operation, page buffer 122 can apply a bit line voltage corresponding to the data DATA to be programmed to the bit line BL of the memory cell array 111. The data DATA can be multiple bits of data to be programmed. In a read operation, page buffer 122 can sense the data stored in the selected memory cell via the bit line BL and output the sensed data DATA to the I / O circuit 124. Page buffer 122 may include multiple page buffers respectively connected to the bit line BL.

[0058] Control logic circuitry 123 can control address decoder 121, page buffer 122, and voltage generator 125 in response to commands CMD (e.g., programming commands and read commands) and address ADDR from I / O circuitry 124. Furthermore, control logic circuitry 123 can control non-volatile memory device 100 to perform programming operations via a multi-step method. The multi-step method can execute programming operations multiple times to configure a desired programming state and may include pre / master programming methods, reprogramming methods, shadow programming methods, etc.

[0059] The voltage generator 125 can generate, under the control of the control logic circuit 123, the voltage required to be applied to the word line WL, the top redundant word line TRL, the middle redundant word line IRL, the bottom redundant word line BRL, the top select word line TSL, and the bottom select word line BSL.

[0060] Those skilled in the art will understand that the operations performed by the address decoder 121, page buffer 122, control logic circuit 123, and voltage generator 125 described in this application can be executed by a processing circuit. This processing circuit may include, but is not limited to, hardware of logic circuits or a hardware / software combination of a processor executing software.

[0061] In one embodiment of this application, see Figure 2 The storage block BLK has multiple storage strings MS11 to MSnm, which can be arranged in a two-dimensional array on the xy plane. Each storage string MS can extend along the z-axis. Each storage string MS includes multiple storage cell groups DECK1 to DECK2. Each storage cell group DECK includes multiple storage cells MC connected in series, and storage cells MC of the same storage layer are connected to the same storage layer word line WL.

[0062] The memory string MS may, for example, also include a top select gate transistor TST connected to bit lines BL1 to BLm and a bottom select gate transistor BST connected to the source line SL. The top select gate transistor TST may, for example, be connected to the top select word line TSL, for example, TST11 is connected to TSL11, and the bottom select gate transistor BST may, for example, be connected to the bottom select word line BSL.

[0063] The memory string MS may, for example, also include pseudo memory cell groups (e.g., a first pseudo memory cell group DMY1), a second pseudo memory cell group DMY2, and a third pseudo memory cell group DMY3. The first pseudo memory cell group DMY1 is located between memory cell groups DECK, and may include one or more intermediate pseudo memory cells IDMC1 to IDMC3, which are respectively connected to their corresponding intermediate redundant word lines IRL1 to IRL3. The second pseudo memory cell group DMY2 is located between the top select gate transistor and multiple memory cell groups DECK, and may, for example, include one or more top pseudo memory cells TDMC1 to TDMC4, which are respectively connected to their corresponding top redundant word lines TRL1 to TRL4. The third pseudo memory cell group DMY3 is located between the bottom select gate transistor and multiple memory cell groups DECK, and may include one or more bottom pseudo memory cells BDMC1 to BDMC4, which are respectively connected to their corresponding bottom redundant word lines BRL1 to BRL4.

[0064] It should be understood that, in order to clarify, Figure 2 Taking a memory string MS comprising two top select gate transistors TST11-TST12, two bottom select gate transistors BST11-BST12, two memory cell groups DECK1-DECK2, a first pseudo memory cell group DMY1, a second pseudo memory cell group DMY2, and a third pseudo memory cell group DMY3 as an example, in other embodiments, the number of select gate transistors TST / BST, the number of memory cell groups DECK, and the number of the first pseudo memory cell group DMY1 on each memory string MS can be adaptively adjusted, and this application does not limit this.

[0065] It should be understood that, without departing from the teachings of this application, the number of storage cells MC in each storage cell group DECK, the number of pseudo storage cells IDMC in the first pseudo storage cell group DMY1, the number of pseudo storage cells TDMC in the second pseudo storage cell group DMY2, and the number of pseudo storage cells BDMC in the third pseudo storage cell group DMY3 can be set as needed, and this application does not make specific limitations in this regard.

[0066] Optionally, the pseudo-memory cells TDMC / IDMC / BDMC and the memory cell MC can be charge-trapping MOS transistors, capable of changing their threshold voltage using the tunneling effect, thereby placing the pseudo-memory cells TDMC / IDMC / BDMC and the memory cell MC in different storage states. The select gate transistors TST / BST can be conventional MOS transistors or charge-trapping MOS transistors; this application does not impose specific limitations on them.

[0067] Multiple memory strings MS11 to MSnm on memory block BLK1 can be connected to the source line SL. For example, the source terminals of multiple bottom select gate transistors (BSTs) located at the ends of the multiple memory strings MS11 to MSnm can be connected to the source line SL. This source line SL can be, for example, a common source line.

[0068] The gates of memory cells MC located at the same or similar height from the source line SL in multiple memory strings MS11 to MSnm can be connected to the same memory layer word line WL. According to the above description, memory cells MC connected to the same memory layer word line WL for simultaneous programming can constitute a page, and a memory block BLK can include multiple pages. Similarly, the gates of pseudo memory cells TDMC / IDMC / BDMC located at the same or similar height from the source line SL in multiple memory strings MS11 to MSnm can be connected to the same redundant word line TRL / IRL / BRL.

[0069] In a plurality of memory strings (e.g., MS11 to MS1m) arranged along the y-axis, the gate of a top select gate transistor (TST) (e.g., TST11) located at the same or similar height from the source line SL can be connected to the same top select word line TSL11. Similarly, the gate of a bottom select gate transistor (BST) located at the same or similar height from the source line SL in a plurality of memory strings (e.g., MS11 to MS1m) arranged along the y-axis can be connected to the same bottom select word line BSL. As an alternative, such as Figure 2 As shown, multiple bottom select word lines (BSLs) located at the same or similar height from the source line SL can be connected to each other. In other words, similar to the memory layer word lines (WL) and redundant word lines (TRL / IRL / BRL), the gate terminals of the bottom select gate transistors (BSTs) in multiple memory strings (MS11 to MSnm) located at the same or similar height from the source line SL can be connected to the same bottom select word line (BSL).

[0070] It should be understood that, without departing from the teachings of this application, the gate terminals of the bottom select gate transistors BST located at the same or similar height from the source line SL in multiple memory strings MS11 to MSnm can also be connected to different bottom select word lines BSL, and this application does not limit this.

[0071] Multiple memory strings MS11 to MSnm on memory block BLK1 can be connected to multiple bit lines BL1 to BLm. Specifically, the drain terminal of the top select gate transistor TST located at the same or similar height from the source line SL among the multiple memory strings (e.g., MS11 to MSn1) arranged in the x-axis direction can be connected to the same bit line BL.

[0072] It should be understood that this application uses storage block BLK1 as an example for detailed description. Storage block BLK1 may be the same as or similar to other storage blocks BLK2 to BLKz in the storage cell array 111.

[0073] In one embodiment of this application, Figure 3 Multiple memory strings MS11 to MSn1 connected to the same bit line BL1 are shown. The gate terminals of the top select gate transistors TST11 to TSTn1 in memory strings MS11 to MSn1 can be connected to the top select word lines TSL11 to TSLn1, respectively, and the gate terminals of the top select gate transistors TST12 to TSTn2 in memory strings MS11 to MSn1 can be connected to the top select word lines TSL12 to TSLn2, respectively. The operation method of the memory device will be described exemplarily below with reference to the accompanying drawings.

[0074] Figure 4 This is a partial structural schematic diagram of an exemplary storage device according to some embodiments of this application. For example... Figure 4 As shown, the storage device 100 may include, for example, a bit line 110, a source 120, a stacked structure 130 located between the bit line 110 and the source 120, and a channel structure 140 extending through the stacked structure 130, the channel structure 140 being substantially perpendicular to the source 120.

[0075] In some embodiments, the source 120 may be located, for example, in the semiconductor layer of the memory device 100. The memory string MS extends generally vertically above the semiconductor layer. The semiconductor layer may include silicon (e.g., single-crystal silicon), silicon-germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material. The semiconductor layer may include, for example, well regions, which may be, for example, P-wells or N-wells, and this application is not limited thereto.

[0076] In some embodiments, the stacked structure 130 may include, for example, multiple memory stacked layer groups (e.g., upper memory stacked layer group 1311 and lower memory stacked layer group 1312), intermediate redundant layer groups (e.g., 1321) located between the memory stacked layer groups, a top redundant layer group 1322, a bottom redundant layer group 1323, a top select layer group 1331, and a bottom select layer group 1332. These layer groups include interleaved conductive layers (e.g., 134) and dielectric layers (not shown). The memory stacked layer groups (e.g., 1311 and 1312) and the channel structure 140 form memory cell groups DECK1 to DECK2 in a memory string MS. Each conductive layer (i.e., memory layer) in the memory stacked layer groups (e.g., 1311 and 1321) and the channel structure 140 respectively form memory cells MC (e.g., 1311A and 1312A) including memory cell groups DECK1 to DECK2. Intermediate redundancy layer group 1321 and channel structure 140 form a first pseudo memory cell group DMY1. The conductive layer (i.e., intermediate redundancy layer) of intermediate redundancy layer group 1321 and channel structure 140 form an intermediate pseudo memory cell IDMC (e.g., 1321A). Top redundancy layer group 1322 and channel structure 140 form a second pseudo memory cell group DMY2. The conductive layer (i.e., top redundancy layer) of top redundancy layer group 1322 and channel structure 140 form a top pseudo memory cell TDMC (e.g., 1322A). Bottom redundancy layer group 1323 and channel structure 140 form a second pseudo memory cell group DMY3. The conductive layer (i.e., bottom redundancy layer) of bottom redundancy layer group 1323 and channel structure 140 form a bottom pseudo memory cell BDMC (e.g., 1323A). The conductive layer (i.e., top select layer) of top select layer group 1331 and channel structure 140 form a top select gate transistor TST (e.g., 1331A). The conductive layer (i.e., the bottom select layer) of the bottom select layer group 1332 and the channel structure 140 form a top select gate transistor (BST) (e.g., 1332A).

[0077] According to some embodiments, the conductive layer (e.g., 134) surrounding the channel structure 140 of the memory string MS is the control gate of the top select gate transistor TST, top pseudo memory cell TDMC, memory cell MC, middle pseudo memory cell IDMC, bottom pseudo memory cell BDMC, and bottom select gate transistor BST in the memory string MS. The conductive layer (e.g., 134) forming the control gate is also referred to as a word line coupled to the memory string MS (e.g., Figure 1The memory includes word lines WL, TSL, TRL, ISL, BSL, and BRL, which are capable of receiving word line voltages for controlling the operation of the memory cell MC, for example, through read, erase, and program operations. The conductor layer (e.g., 134) may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicides, or any combination thereof.

[0078] It should be understood that, Figure 4 Taking the storage device 100, which includes 2 top selection layers, 4 top redundancy layers, 3 middle redundancy layers, 4 bottom redundancy layers and 2 bottom selection layers as an example, its structure is illustrated. Without departing from this application, the number of each layer can be adjusted as needed, and this application does not limit this.

[0079] It should be understood that, Figure 4 The storage device 100 includes two storage unit groups. Taking a first pseudo storage unit group as an example, its structure is illustrated. Without departing from this application, the number of storage unit groups and the first pseudo storage unit group can be adjusted and increased as needed, and this application does not limit this.

[0080] It should be understood that, Figure 4 Taking a storage unit group comprising 16 storage layers as an example, the structure is illustrated. Without departing from this application, the number of storage layers in each storage unit group can be adjusted as needed, and this application does not impose any restrictions on this.

[0081] In some embodiments of this application, the storage device 100 may perform erase or pre-programming operations on the storage block BLK using half-block mode (HBM). Taking the storage device 100 performing a pre-programming operation on the upper storage stack group 1311 as an example, after erasing the data in the upper storage stack group 1311, before programming the upper storage stack group 1311, the channel pre-charge of the upper storage stack group 1311 can be performed using the bit line side (BL side) gate-induced drain leakage (GIDL) pre-programming method. A voltage waveform diagram of the BL side GIDL pre-programming method is shown below. Figure 5 As shown. During the pre-programming phase (t0-t3), a pre-programming voltage V can be applied to the selected bit line sel BL and the unselected bit line unsel BL. gidl_preA low-level voltage V is applied to the gate sel TSG of the selected top select gate transistor TST, the gate unsel TSG of the unselected top select gate transistor TST, the unselected word line Upper deck unsel WL in the upper memory stack group 1311, the selected word line Upper deck sel WL in the upper memory stack group 1311, the intermediate redundancy layer IDPDUM, and the word line Lower deck WL of the lower memory stack group 1312. SS The bottom select gate transistor (BST) has its gate BSG and source line SL floating. The BL-side GIDL pre-programming method creates a higher voltage difference between the bit line and the gate of the top select gate transistor (TST) (i.e., between the drain and gate of the TST), causing band-to-band tunneling (BTB) to occur nearby, resulting in holes in the channel structure 140 near the TST. These holes can propagate downwards through the channel structure 140 and recombine with electrons in the channel structure 140, thereby reducing the electron concentration in the channel structure 140 and achieving channel pre-charging. During the programming stage, a low-level voltage can be applied to the selected bit line BL, the unselected top select gate transistor TST's gate unsel TSG, the intermediate redundancy layer IDPDUM, the bottom select gate transistor BST's gate BSG, and the source line SL. A bit line suppression voltage V is applied to the unselected bit line unsel BL. inhibit A transistor turn-on voltage V is applied to the gate sel TSG of the selected top-select gate transistor TST. tsq A pass voltage V is applied to the unselected word line Upper deck unsel WL in the upper storage stack group 1311 and the word line Lower deck WL in the lower storage stack group 1312. pass The programming voltage V is applied to the selected word line Upper decksel WL in the upward storage stack group 1311. pgm The selected memory cell is programmed. Similarly, after erasing only the data in the lower memory stack group 1312, before programming the lower memory stack group 1312, the channel pre-charge of the lower memory stack group 1312 can be performed using the source line-side (SL side) gate-induced drain leakage (GIDL) pre-programming method. A voltage waveform diagram of the SL side GIDL pre-programming method is shown below. Figure 6 As shown, where, Figure 6 The meanings of each parameter can be found in the reference. Figure 5 The description will not be repeated here.

[0082] When using the BL-side GIDL pre-programming method or the SL-side GIDL pre-programming method to pre-charge the channel of an erase-state memory stack, it can affect other memory stacks. For example, pre-charging the channel of an erase-state memory stack can have a weak erase effect on a programmed memory stack, leading to an increased bit error rate in the programmed memory stack, and in severe cases, read failures and data loss. For example, Figure 7 This is a comparison of the read window edge voltage distribution from the source end (i.e., the bottom word line (Bottom WL) of the stacked structure 130) through the intermediate redundancy layer (IDPDUM) to the bit line end (i.e., the top word line (Top WL) of the stacked structure 130) after programming using the half-block program (HBP) and full-block program (FBP) methods in the embodiments of this application. In the half-block program method, taking the programming of the upper memory stack group 1311 as an example, the channel is pre-charged using the BL side GIDL pre-programming method before programming. Figure 7 It is known that the BL side GIDL pre-programming operation will have a weak erasure effect on the programmed storage stack layer group, affecting the storage performance of storage device 100. Similarly, the BL side GIDL erasure operation will have an erasure effect on the programmed storage stack layer group, affecting the storage performance of storage device 100.

[0083] Figure 8 This is a flowchart illustrating the operation method 200 of a storage device 100 according to some embodiments of this application.

[0084] In some embodiments of this application, see Figures 1 to 4 The storage device 100 includes multiple storage strings MS, each storage string MS including a first storage cell group DECK1, a pseudo storage cell group (i.e., the first pseudo storage cell group DMY1), and a second storage cell group DECK2, which are connected in series. For example... Figure 8 As shown, the operation method 200 of the storage device 100 may include, for example:

[0085] Step S11: By applying a first preset voltage to one end of the storage string near the first storage cell group, a pre-programming operation or an erase operation is performed on the first storage cell group.

[0086] Step S12: During the application of the first preset voltage, by applying a second preset voltage to the gate of the pseudo memory cell group (i.e., the first pseudo memory cell group DMY1), the channel potential of the pseudo memory cell group (i.e., the first pseudo memory cell group DMY1) is made higher than the channel potential of the first memory cell group.

[0087] According to the embodiments of this application, during the pre-programming / erasing operation of the first memory cell group by the non-volatile storage device, during the application of the first preset voltage, a second preset voltage is applied to the pseudo memory cell group to form a high potential near the channel of the pseudo memory cell group, thereby blocking the transmission of holes generated by the first memory cell group under the first preset voltage to the second memory cell group, reducing the number of holes entering the second memory cell group, and reducing the impact of the pre-programming / erasing operation of the first memory cell group on the second memory cell group.

[0088] Furthermore, the inventors discovered that holes generated by pre-programming / erasing operations may be transmitted to memory cell groups that do not require pre-programming / erasing operations, adversely affecting these groups. For example, holes transmitted to a second memory cell group in a programmed state will have a weak erasing effect, causing its threshold to drift, leading to an increased bit error rate during reading, and in severe cases, even read failure and data loss. Figure 5 The schematic diagram of hole flow generated by the BLside GIDL pre-programming method shown can be, for example... Figure 9 As shown, during the pre-programming stage, the holes h generated by the structure connected to the bit line (e.g., the top select gate transistor TST) under the first preset voltage induction will pass through the channel structure 140A corresponding to the upper memory stack 1311 and the channel structure 140B corresponding to the intermediate redundant layer group 1321 to reach the channel structure 140C corresponding to the lower memory stack 1312, thereby producing a weak erase effect on the lower memory stack 1312. Figure 6 The schematic diagram of hole flow generated by the SL side GIDL pre-programming method shown can be, for example... Figure 10 As shown, during the pre-programming stage, the holes h generated by the structure connected to the source (e.g., the bottom select gate transistor BST) under the first preset voltage induction will pass through the channel structure 140C corresponding to the lower storage stack 1312 and the channel structure 140B corresponding to the intermediate redundant layer 1321 to reach the channel structure 140A corresponding to the upper storage stack 1311, thereby generating a weak erase effect on the upper storage stack 1311.

[0089] Therefore, in the embodiments of this application, during the pre-programming / erasing operation of the first memory cell group by the non-volatile storage device, during the application of the first preset voltage, a second preset voltage is applied to the pseudo memory cell group, forming a high potential near the channel of the pseudo memory cell group. This blocks the transmission of holes generated by the first memory cell group under the first preset voltage to the second memory cell group, reducing the number of holes entering the second memory cell group and reducing the impact of the pre-programming / erasing operation of the first memory cell group on the second memory cell group. For example, if the second memory cell group is in a programmed state, the embodiments of this application can reduce the weak erasure effect of the pre-programming / erasing operation of the first memory cell group on the second memory cell group, reduce the read window threshold drift of the second memory cell group, improve the read window threshold retention characteristics of the memory cell, and thus reduce the increase in bit error rate, read failure, and data loss of the storage device due to pre-programming.

[0090] For example, with Figure 4 Taking the storage device 100 shown as an example, if the storage stacking layer group corresponding to the first storage cell group is the upper storage stacking layer group 1311 (i.e., the first storage cell group is...), Figure 2 As shown in DECK1), the storage stacking layer group corresponding to the first pseudo-memory cell group is the intermediate redundancy layer group 1321 (i.e., the first pseudo-memory cell group is...). Figure 2 As shown in DMY1), the stacking group corresponding to the second storage cell group is the lower storage stacking group 1312 (i.e., the second storage cell group is...). Figure 2 The diagram of cavitation flow shown in DECK2 can be illustrated for example. Figure 11 As shown. By Figure 11 It can be seen that, since a second preset voltage is applied at the intermediate redundant layer group 1321, the channel potential near the intermediate redundant layer group 1321 is higher than the channel potential near the upper storage stack layer group 1311. This can block the downward transmission of holes h generated by the preprogramming / erasing operation, reduce the number of holes entering the channel structure 140C corresponding to the lower storage stack layer group 1312, and thus reduce the weak erasure effect of the preprogramming / erasing operation on the lower storage stack layer group 1312.

[0091] If the storage stacking group corresponding to the first storage unit group is the lower storage stacking group 1312 (i.e., the first storage unit group is...), Figure 2 As shown in DECK2), the storage stacking layer group corresponding to the first pseudo-memory cell group is the intermediate redundancy layer group 1321 (i.e., the first pseudo-memory cell group is...). Figure 2 As shown in DMY1), the stacking group corresponding to the second storage cell group is the upper storage stacking group 1311 (i.e., the second storage cell group is...). Figure 2 The schematic diagram of cavitation flow shown in DECK1 can be, for example... Figure 12 As shown. By Figure 12It can be seen that, since a second preset voltage is applied at the intermediate redundant layer group 1321, the channel potential near the intermediate redundant layer group 1321 is higher than the channel potential near the lower memory stack layer group 1312. This can block the upward transmission of holes h generated by the preprogramming / erasing operation, reduce the number of holes entering the channel structure 140A corresponding to the upper memory stack layer group 1311, and thus reduce the weak erasure effect of the preprogramming / erasing operation on the upper memory stack layer group 1311.

[0092] In some embodiments of this application, the duration for which the storage device 100 applies a second preset voltage to a first pseudo-storage cell group (e.g., DMY1) between the first and second storage cell groups is greater than or equal to the duration for which the storage device 100 applies a first preset voltage to the first storage cell group. In other words, throughout the entire pre-programming / erasing phase of the first storage cell group, the storage device 100 applies the second preset voltage to the first pseudo-storage cell group (e.g., DMY1), so that the first pseudo-storage cell group DMY1 can block hole transmission to the second storage cell group during the pre-programming / erasing phase of the first storage cell group, thereby better reducing the impact of the pre-programming phase of the first storage cell group on parameters such as the read window threshold of the second storage cell group.

[0093] As an example, the storage device 100 may apply a second preset voltage to a first pseudo-storage cell group (e.g., DMY1) while applying a first preset voltage to the first storage cell group.

[0094] As another example, the storage device 100 may also apply a second preset voltage to the first pseudo-storage cell group (e.g., DMY1) before applying a first preset voltage to the first storage cell group.

[0095] It should be understood that, without departing from the teachings of this application, the storage device 100 may also apply a second preset voltage to the first pseudo-storage cell group at any time after the storage device 100 applies a first preset voltage to the first storage cell group and before the storage device 100 stops applying the first preset voltage to the first storage cell group (i.e., at any time during the pre-programming / erasing phase of the first storage cell group). During the application of the second preset voltage, the first pseudo-storage cell group between the first and second storage cell groups can block hole transport and reduce the impact of the pre-programming / erasing phase of the first storage cell group on parameters such as the read window threshold of the second storage cell group. Therefore, in other embodiments, the timing of applying the second preset voltage can be selected according to the structure of the storage device 100, storage performance requirements, etc., and this application does not impose any restrictions on this.

[0096] In some embodiments of this application, the magnitude of the second preset voltage is positively correlated with the magnitude of the first preset voltage. Since the second preset voltage is greater than the channel potential of the first pseudo-memory cell group, and the channel potential of the first pseudo-memory cell group depends on the magnitude of the first preset voltage, the magnitude of the second preset voltage is related to the magnitude of the first preset voltage. When the first preset voltage is large, the channel potential of the first memory cell group is large, and the second preset voltage can be, for example, a large voltage value. When the first preset voltage is small, the channel potential of the first memory cell group is small, and the second preset voltage can be, for example, a small voltage value.

[0097] For example, the storage device 100 performs a pre-programming operation on the first storage cell. The first preset voltage is 7V, and the channel potential of the first storage cell group is 1V lower than the preset voltage, i.e., the channel potential is 6V. Then, the second preset voltage can be greater than 6V. For example, the second preset voltage is 6-7V.

[0098] As an example, storage device 100 performs a pre-programming operation on the first storage cell. During the pre-programming operation, the magnitude of the first preset voltage may be, for example, 5-7V. Considering that an excessively high preset voltage may have an erasing effect, storage device 100 may select a first preset voltage of 5-7V to pre-program the first storage cell group.

[0099] As an alternative, since the magnitude of the second preset voltage is related to the magnitude of the first preset voltage, in the pre-programming operation, if the magnitude of the first preset voltage is approximately 5-7V, the magnitude of the second preset voltage can be, for example, 5-7V.

[0100] As another example, the storage device 100 performs an erase operation on a first storage cell. During the erase operation, the magnitude of a first preset voltage may be, for example, 18-22V. To erase the data in the first storage cell group, an erase high voltage (e.g., 18-22V) is applied to one end of the storage string closest to the first storage cell group, and the data stored in the first storage cell group is erased. Since the magnitude of a second preset voltage is related to the magnitude of the first preset voltage, if the magnitude of the first preset voltage is approximately 18-22V, the magnitude of the second preset voltage may be, for example, 14-16V, to reduce the number of holes flowing into the channels of the second storage cell group.

[0101] In some embodiments of this application, during the application of a first preset voltage, one end of the storage string MS that is furthest from the first storage cell group is floated. It should be understood that when an element (or component, assembly, member, etc.) is referred to as floating, it is intended to indicate that the element (or component, assembly, member, etc.) does not form an electrical path with other elements (or components, assemblies, members, etc.).

[0102] by Figure 4For example, if the storage stacking layer group corresponding to the first storage cell group is the upper storage stacking layer group 1311 (i.e., the first storage cell group is...) Figure 2 As shown in DECK1), the storage device 100 can apply a first preset voltage to the bit line 110, and the source 120 is floating. If the storage stacking layer group corresponding to the first storage cell group is the lower storage stacking layer group 1312 (i.e., the first storage cell group is...), the storage device 100 can apply a first preset voltage to the bit line 110, and the source 120 is floating. Figure 2 As shown in DECK2), the storage device 100 can apply a first preset voltage to the source 120, and the bit line 110 is floating.

[0103] In some embodiments of this application, see Figures 1 to 4 The memory string MS of the memory device 100 may also include, for example, a first select gate transistor connected in series with the first memory cell group. During the application of a first preset voltage, the memory device 100 may, by applying a third preset voltage to the gate of the first select gate transistor, create a voltage difference between the source or drain of the first select gate transistor and its gate.

[0104] As an example, storage device 100 performs a pre-programming operation on a first storage cell. During the pre-programming operation, a third preset voltage may be, for example, a low-level voltage, such as the ground voltage of 0V.

[0105] As another example, the storage device 100 performs an erase operation on the first storage cell. During the erase operation, the magnitude of the third preset voltage may be, for example, 8-12V, to reduce the possibility that the first preset voltage (here, the erase high voltage) applied by the storage device to the side of the storage string closer to the first storage cell group would cause data to be stored in the first select gate transistor.

[0106] Alternatively, the memory string may also include a second select gate transistor connected in series with the second memory cell group; wherein, during the application of a first preset voltage, the gate of the second select gate transistor is floating.

[0107] For example, see Figure 4 If the storage stacking layer group corresponding to the first storage cell group is the upper storage stacking layer group 1311 (i.e., the first storage cell group is...), Figure 2 As shown in DECK1), the first select gate transistor includes a top select gate transistor (TST), and the second select gate transistor includes a bottom select gate transistor (BST). The memory device 100 can apply a third preset voltage to the gate of the top select gate transistor (TST) during the application of a first preset voltage, while the gate of the bottom select gate transistor (BST) is floating. If the memory stacking layer group corresponding to the first memory cell group is the lower memory stacking layer group 1312 (i.e., the first memory cell group is...), then... Figure 2As shown in DECK2), the first select gate transistor includes a bottom select gate transistor BST, and the second select gate transistor includes a top select gate transistor TST. The storage device 100 can apply a third preset voltage to the gate of the bottom select gate transistor BST while applying a first preset voltage, and the gate of the top select gate transistor TST is floating.

[0108] In some embodiments of this application, see Figures 1 to 4 The memory string MS also includes a second pseudo memory cell group DMY2 disposed between the top select gate transistor TST and the plurality of memory cell groups DECK1 to DECK2. The memory device 100 may also apply a low-level voltage, such as a ground voltage of 0V, to the gate of the second pseudo memory cell group DMY2, for example, during the application of a first preset voltage, to prevent the second pseudo memory cell group DMY2 from entering the programming stage.

[0109] In some embodiments of this application, see Figures 1 to 4 The memory string MS also includes a third pseudo memory cell group DMY3 disposed between the bottom select gate transistor BST and the plurality of memory cell groups DECK1 to DECK2. The memory device 100 may also apply a low-level voltage, such as a ground voltage of 0V, to the gate of the third pseudo memory cell group DMY3 during the application of a first preset voltage, to prevent the third pseudo memory cell group DMY3 from entering the programming stage.

[0110] In some embodiments of this application, the storage device 100 may, for example, apply a fourth preset voltage to the gate of a storage cell in the first storage cell group during the application of a first preset voltage to perform a pre-programming operation or an erase operation on the first storage cell group; and retain the data in the second storage cell group by applying a fifth preset voltage to the gate of a storage cell in the second storage cell group. For example, storage cells located on the same storage layer in the storage device are connected to the same storage layer word line; the storage device applies a fourth preset voltage to each storage layer word line WL in the first storage cell group and applies a fifth preset voltage to each storage layer word line WL in the second storage cell group.

[0111] In some embodiments of this application, the fourth preset voltage may be, for example, a low-level voltage, which may be, for example, a ground voltage of 0V, to prevent the memory cells MC of the first memory cell group from entering the programming stage.

[0112] As an example, storage device 100 performs a pre-programming operation on the first group of storage cells. During the pre-programming operation, the magnitude of the fifth preset voltage is 0V to prevent the storage cells MC of the second group of storage cells from entering the programming stage.

[0113] As another example, storage device 100 performs an erase operation on the first group of storage cells. During the erase operation, a fifth preset voltage is 4-6V to prevent data in the storage cells MC of the second group of storage cells from being erased.

[0114] The pre-programming and programming processes of the storage device 100 are described below by way of example.

[0115] Taking the storage stacking layer group corresponding to the first storage cell group as the upper storage stacking layer group 1311, the storage stacking layer group corresponding to the first pseudo storage cell group as the intermediate redundancy layer group 1321, and the stacking layer group corresponding to the second storage cell group as the lower storage stacking layer group 1312, with the fourth preset voltage and the fifth preset voltage both being low-level voltages as an example, the voltage waveform diagram applied to the storage device 100 is shown below. Figure 13 As shown. During the pre-programming phase (t0-t3), the storage device 100 may, for example, begin applying a pre-programming voltage (i.e., a first preset voltage) V to the selected bit line sel BL and the unselected bit line unsel BL at time t0. gidl_pre Apply a bias voltage (i.e., the second preset voltage) V to the intermediate redundant layer IDPDUM. bias A low-level voltage V is applied to the gate sel TSG of the selected top select gate transistor TST, the gate unsel TSG of the unselected top select gate transistor TST, the unselected word line Upper deck unsel WL in the upper memory stack group 1311, the selected word line Upper deck sel WL in the upper memory stack group 1311, and the word line Lower deck WL in the lower memory stack group 1312. SS And the gate BSG and source line SL of the bottom select gate transistor BST are floated. The low-level voltage V... SS For example, the ground voltage 0V. This operation method can create a higher voltage difference between the bit line and the gate of the top select gate transistor TST (i.e., between the drain and gate of the top select gate transistor), causing interband tunneling (BTB) to occur nearby, resulting in holes in the channel structure 140 near the top select gate transistor TST. The holes can travel downwards through the channel structure 140 and recombine with electrons in the channel structure 140, thereby reducing the electron concentration in the channel structure 140 and achieving channel pre-charge. During the programming phase, the memory device 100 can, for example, start applying a low-level voltage V at time t4 to the selected bit line sel BL, the gate unsel TSG of the unselected top select gate transistor TST, the intermediate redundancy layer IDPDUM, the gate BSG of the bottom select gate transistor BST, and the source line SL. SS Apply bit line suppression voltage V to the unselected bit line unsel BL inhibitA transistor turn-on voltage V is applied to the gate sel TSG of the selected top-select gate transistor TST. tsq A pass voltage V is applied to the unselected word line Upper deck unsel WL in the upper storage stack group 1311 and the word line Lower deck WL in the lower storage stack group 1312. pass The programming voltage V is applied to the selected word line Upper deck sel WL in the upward storage stack layer group 1311. pgm This allows for programming of the selected memory cells.

[0116] Taking the storage stacking layer group corresponding to the first storage cell group as the lower storage stacking layer group 1312, the storage stacking layer group corresponding to the first pseudo storage cell group as the intermediate redundancy layer group 1321, and the stacking layer group corresponding to the second storage cell group as the upper storage stacking layer group 1311, with the fourth preset voltage and the fifth preset voltage both being low-level voltages as an example, the voltage waveform diagram applied to the storage device 100 is shown below. Figure 14 As shown. During the pre-programming stage, the storage device 100 may, for example, begin applying a pre-programming voltage (i.e., a first preset voltage) V to the source line SL at time t0. gidl_pre Apply a bias voltage (i.e., the second preset voltage) V to the intermediate redundant layer IDPDUM. bias A low-level voltage V is applied to the word line Upper deck WL of the upper storage stack 1311, the selected word line Lower deck sel WL of the lower storage stack 1312, the unselected word line Lower deck unsel WL of the lower storage stack 1312, and the gate BSG of the bottom select gate transistor BST. SS The selected bit line sel BL, the unselected bit line unsel BL, the gate sel TSG of the selected top-select gate transistor TST, and the gate unsel TSG of the unselected top-select gate transistor TST are floated. This operation method creates a higher voltage difference between the source and the gate of the bottom-select gate transistor (i.e., between the drain and gate of the bottom-select gate transistor), causing inter-band tunneling (BTB) to occur nearby, resulting in holes in the channel structure 140 near the top-select gate transistor TST. The holes can travel upward through the channel structure 140 and recombine with electrons in the channel structure 140, thereby reducing the electron concentration in the channel structure 140 and achieving channel pre-charging. During the programming phase, a low-level voltage V can be applied, for example, at time t4, to the selected bit line sel BL, the gate unsel TSG of the unselected top-select gate transistor TST, the intermediate redundancy layer IDPDUM, the gate BSG of the bottom-select gate transistor BST, and the source line SL. SSApply bit line suppression voltage V to the unselected bit line unsel BL inhibit A transistor turn-on voltage V is applied to the gate sel TSG of the selected top-select gate transistor TST. tsq A pass voltage V is applied to the word line Upper deck WL in the upper storage stack group 1311 and the unselected word line Upper deck unsel WL in the lower storage stack group 1312. pass The programming voltage V is applied to the selected word line in the lower deck sel WL of the downward storage stack layer group 1312. pgm This allows for programming of the selected memory cells.

[0117] After providing an exemplary description of the pre-programming and programming operations, the erasure operation of the storage device 100 will now be described in an exemplary manner.

[0118] Taking the storage stacking layer group corresponding to the first storage cell group as the upper storage stacking layer group 1311, the storage stacking layer group corresponding to the first pseudo storage cell group as the intermediate redundancy layer group 1321, and the stacking layer group corresponding to the second storage cell group as the lower storage stacking layer group 1312 as an example, the voltage waveform diagram applied to the storage device 100 is shown below. Figure 15 As shown. During the erase phase, the storage device 100 applies an erase voltage (i.e., a first preset voltage) V to the bit line BL. erase V erase For example, it can be 18-22V; the storage device 100 applies a third preset voltage V to the gate sel TSG of the selected top-select gate transistor TST and the gate unsel TSG of the unselected top-select gate transistor TST. bias2 V bias2 For example, it can be 8-12V; the storage device 100 applies a fourth preset voltage to the upper deck WL of the storage layer word line in the upper storage stack 1311, the fourth preset voltage being, for example, a low-level voltage V. SS Storage device 100 applies a bias voltage (i.e., a second preset voltage) V to the intermediate redundancy layer IDPDUM. bias1 V bias1 For example, 14-16V; a fifth preset voltage V is applied to the lower deck WL of the storage layer word line of the storage device 100 in the lower storage stack 1312. bias3 V bias3 For example, 4-6V; the storage device 100 floats the gate BSG and source line SL of the bottom select gate transistor BST. The low-level voltage V... SSFor example, the ground voltage could be 0V. This operation method creates a higher voltage difference between the bit line and the gate of the top select gate transistor (TST) (i.e., between the drain and gate of the TST), causing inter-band tunneling (BTB) to occur nearby, resulting in holes in the channel structure 140 near the TST. The holes can travel downwards through the channel structure 140 and recombine with electrons in the channel structure 140, thereby reducing the electron concentration in the channel structure 140 to erase data from the upper memory stack group 1311.

[0119] Taking the storage stacking layer group corresponding to the first storage cell group as the lower storage stacking layer group 1312, the storage stacking layer group corresponding to the first pseudo storage cell group as the intermediate redundancy layer group 1321, and the stacking layer group corresponding to the second storage cell group as the upper storage stacking layer group 1311 as an example, the voltage waveform diagram applied to the storage device 100 is as follows: Figure 16 As shown. During the erase phase, the memory device 100 can float the bit line BL, the gate sel TSG of the selected top select gate transistor TST, and the gate unsel TSG of the unselected top select gate transistor TST; the memory device 100 applies a fifth preset voltage V to the memory layer word line Upper deck WL in the upper memory stack 1311. bias3 V bias3 For example, it can be 4-6V; the storage device 100 applies a bias voltage (i.e., a second preset voltage) V to the intermediate redundancy layer IDPDUM. bias V bias1 For example, it can be 14-16V; the storage device 100 can apply a fourth preset voltage to the lower deck WL of the storage layer word line of the lower storage stack 1312, the fourth preset voltage being, for example, a low-level voltage V. SS The storage device 100 applies a third preset voltage V to the gate BSG of the bottom select gate transistor BST. bias2 V bias2 For example, it can be 8-12V; the storage device 100 can apply an erase voltage (i.e., a first preset voltage) V to the source line SL. erase V erase For example, it can be 18-22V. This operation method creates a higher voltage difference between the source and the gate of the bottom select gate transistor (i.e., between the drain and gate of the bottom select gate transistor), causing interband tunneling (BTB) to occur nearby, resulting in holes in the channel structure 140 near the top select gate transistor (TST). The holes can travel upward through the channel structure 140 and recombine with electrons in the channel structure 140, thereby reducing the electron concentration in the channel structure 140 to perform an erase operation on the lower memory stack 1312.

[0120] The following is Figure 13Taking the corresponding operation method as an example, the effects that can be achieved by the implementation method of this application will be illustrated by way of example.

[0121] For example, for a certain storage string (e.g., MS11) Figure 5 The corresponding operation method is pre-programmed (referred to as pre-programming 1), and another memory string (e.g., MS12) is used. Figure 13 The corresponding operation method is pre-programmed (referred to as pre-programming 2). The comparison diagram of the channel potentials of the two memory strings at time t2 is shown below. Figure 17 As shown in the diagram, the channel potential comparison at time t3 is as follows: Figure 18 As shown. From Figure 17 It can be seen that in the pre-programming stage, Figure 13 The pre-programming stage of the corresponding operation method can generate a high potential in the intermediate redundancy layer IDPDUM, while the channel potential corresponding to the lower storage stack 1312 is lower, indicating that the intermediate redundancy layer IDPDUM plays a role in blocking holes from entering the lower storage stack 1312. Figure 18 It can be seen that using Figure 13 The corresponding operation method, after pre-programming, results in a channel potential lower than that used in the lower storage stack group 1312. Figure 13 The corresponding operation method completes the pre-programmed channel potential of the lower storage stack group 1312, indicating the use of... Figure 13 Corresponding pre-programming methods can reduce weak erase effects. Therefore, through Figure 17 and Figure 18 As can be seen, in the implementation of this application, during the application of the first preset voltage, a high potential is formed near the channel of the first pseudo memory cell group by applying a second preset voltage to the first pseudo memory cell group. This blocks the holes generated by the first memory cell group under the first preset voltage from being transmitted to the second memory cell group, thereby reducing the number of holes entering the second memory cell group, reducing the weak erasure effect of the pre-programming stage of the first memory cell group on the second memory cell group, reducing the read window threshold drift, improving the read window threshold retention characteristics of the memory cell, and thus reducing the increase in the bit error rate, read failure and data loss of the storage device due to pre-programming.

[0122] This application also provides a non-volatile storage device 100, see [link to relevant documentation]. Figures 1 to 4The non-volatile memory device 100 may include, for example, a memory block BLK and peripheral circuitry (e.g., an address decoder 121, a page buffer 122, control logic circuitry 123, I / O circuitry 124, and a voltage generator 125). The memory block BLK includes a plurality of memory strings MS, each memory string MS including a plurality of memory cell groups DECK connected in series and a first pseudo memory cell group DMY1 located between the memory cell groups DECK. The peripheral circuitry is coupled to the memory block BLK. For example, the peripheral circuitry is configured to: perform a pre-programming / erasing operation on the first memory cell group by applying a first preset voltage to one end of the memory string MS near the first memory cell group; and, during the application of the first preset voltage, to make the channel potential of the first pseudo memory cell group higher than the channel potential of the first memory cell group by applying a second preset voltage to the gate of the pseudo memory cell group.

[0123] In the embodiments of this application, during the pre-programming / erasing operation of the first memory cell group by the non-volatile storage device, while applying the first preset voltage, a second preset voltage is applied to the pseudo memory cell group, forming a high potential near the channel of the pseudo memory cell group. This blocks the transmission of holes generated by the first memory cell group under the first preset voltage to the second memory cell group, reducing the number of holes entering the second memory cell group and mitigating the impact of the pre-programming / erasing operation of the first memory cell group on the second memory cell group. For example, if the second memory cell group is in a programmed state, the embodiments of this application can reduce the weak erasure effect of the pre-programming / erasing operation of the first memory cell group on the second memory cell group, reduce the read window threshold drift of the second memory cell group, improve the read window threshold retention characteristics of the memory cell, and thereby reduce the increase in bit error rate, read failure, and data loss of the storage device due to pre-programming.

[0124] For example, a schematic diagram of the storage device 100 can be found here. Figure 4 If the storage stacking layer group corresponding to the first storage cell group is the upper storage stacking layer group 1311 (i.e., the first storage cell group is...), Figure 2 As shown in DECK1), the storage stacking layer group corresponding to the first pseudo-memory cell group is the intermediate redundancy layer group 1321 (i.e., the first pseudo-memory cell group is...). Figure 2 As shown in DMY1), the stacking group corresponding to the second storage cell group is the lower storage stacking group 1312 (i.e., the second storage cell group is...). Figure 2 The diagram of cavitation flow shown in DECK2 can be found in [reference needed]. Figure 11 .Depend on Figure 11It can be seen that, since a second preset voltage is applied at the intermediate redundant layer group 1321, the channel potential near the intermediate redundant layer group 1321 is higher than the channel potential near the upper storage stack layer group 1311. This can block the downward transmission of holes h generated by the preprogramming / erasing operation, reduce the number of holes entering the channel structure 140C corresponding to the lower storage stack layer group 1312, and thus reduce the weak erasure effect of the preprogramming / erasing operation on the lower storage stack layer group 1312.

[0125] If the storage stacking group corresponding to the first storage unit group is the lower storage stacking group 1312 (i.e., the first storage unit group is...), Figure 2 As shown in DECK2), the storage stacking layer group corresponding to the first pseudo-memory cell group is the intermediate redundancy layer group 1321 (i.e., the first pseudo-memory cell group is...). Figure 2 As shown in DMY1), the stacking group corresponding to the second storage cell group is the upper storage stacking group 1311 (i.e., the second storage cell group is...). Figure 2 The schematic diagram of cavitation flow shown in DECK1 can be found in [reference needed]. Figure 12 .Depend on Figure 12 It can be seen that, since a second preset voltage is applied at the intermediate redundant layer group 1321, the channel potential near the intermediate redundant layer group 1321 is higher than the channel potential near the lower memory stack layer group 1312. This can block the upward transmission of holes h generated by the preprogramming / erasing operation, reduce the number of holes entering the channel structure 140A corresponding to the upper memory stack layer group 1311, and thus reduce the weak erasure effect of the preprogramming / erasing operation on the upper memory stack layer group 1311.

[0126] In some embodiments of this application, the duration for which the storage device 100 applies a second preset voltage to the first pseudo-memory cell group (e.g., DMY1) is greater than or equal to the duration for which the storage device 100 applies a first preset voltage to the first memory cell group. In other words, throughout the entire pre-programming / erasing phase of the first memory cell group, the storage device 100 applies the second preset voltage to the first pseudo-memory cell group (e.g., DMY1), so that the first pseudo-memory cell group DMY1 can block hole transmission to the second memory cell group during the pre-programming / erasing phase of the first memory cell group, thereby better reducing the impact of the pre-programming phase of the first memory cell group on parameters such as the read window threshold of the second memory cell group.

[0127] As an example, the storage device 100 may apply a second preset voltage to a first pseudo-storage cell group (e.g., DMY1) while applying a first preset voltage to the first storage cell group.

[0128] As another example, the storage device 100 may also apply a second preset voltage to the first pseudo-storage cell group (e.g., DMY1) before applying a first preset voltage to the first storage cell group.

[0129] It should be understood that, without departing from the teachings of this application, the storage device 100 may also apply a second preset voltage to the first pseudo-storage cell group at any time after the storage device 100 applies a first preset voltage to the first storage cell group and before the storage device 100 stops applying the first preset voltage to the first storage cell group (i.e., at any time during the pre-programming / erasing phase of the first storage cell group). During the application of the second preset voltage, the first pseudo-storage cell group between the first and second storage cell groups can block hole transport and reduce the impact of the pre-programming / erasing phase of the first storage cell group on parameters such as the read window threshold of the second storage cell group. Therefore, in other embodiments, the timing of applying the second preset voltage can be selected according to the structure of the storage device 100, storage performance requirements, etc., and this application does not impose any restrictions on this.

[0130] In some embodiments of this application, the magnitude of the second preset voltage is positively correlated with the magnitude of the first preset voltage. Since the second preset voltage is greater than the channel potential of the first pseudo-memory cell group, and the channel potential of the first pseudo-memory cell group depends on the magnitude of the first preset voltage, the magnitude of the second preset voltage is related to the magnitude of the first preset voltage. When the first preset voltage is large, the channel potential of the first memory cell group is large, and the second preset voltage can be, for example, a large voltage value. When the first preset voltage is small, the channel potential of the first memory cell group is small, and the second preset voltage can be, for example, a small voltage value.

[0131] For example, the peripheral circuit is configured to pre-program the first memory cell. The first preset voltage is 7V, and the channel potential of the first memory cell group is 1V lower than the preset voltage, i.e., the channel potential is 6V. Then, the second preset voltage can be greater than 6V. For example, the second preset voltage is 6-7V.

[0132] Alternatively, the peripheral circuitry is configured to pre-program the first memory cells, with a first preset voltage of, for example, 5-7V. Considering that an excessively high preset voltage might have an erasing effect, the storage device 100 may select a first preset voltage of 5-7V to pre-program the first group of memory cells.

[0133] As an alternative, since the magnitude of the second preset voltage is related to the magnitude of the first preset voltage, in the pre-programming operation, if the magnitude of the first preset voltage is approximately 5-7V, the magnitude of the second preset voltage can be, for example, 5-7V.

[0134] As another example, the peripheral circuitry is configured to perform an erase operation on the first memory cell, with a first preset voltage of 18-22V. To erase the data in the first memory cell group, an erase voltage (e.g., 18-22V) is applied to one end of the memory string closest to the first memory cell group, erasing the data stored in the first memory cell group. Since the magnitude of the second preset voltage is related to the magnitude of the first preset voltage, when the magnitude of the first preset voltage is approximately 18-22V, the magnitude of the second preset voltage can be, for example, 14-16V, to reduce the number of holes flowing into the channels of the second memory cell group.

[0135] In some embodiments of this application, during the application of a first preset voltage, one end of the storage string MS that is furthest from the first storage cell group is floated.

[0136] by Figure 4 For example, if the storage stacking layer group corresponding to the first storage cell group is the upper storage stacking layer group 1311 (i.e., the first storage cell group is...) Figure 2 As shown in DECK1), the storage device 100 can apply a first preset voltage to the bit line 110, and the source 120 is floating. If the storage stacking layer group corresponding to the first storage cell group is the lower storage stacking layer group 1312 (i.e., the first storage cell group is...), the storage device 100 can apply a first preset voltage to the bit line 110, and the source 120 is floating. Figure 2 As shown in DECK2), the storage device 100 can apply a first preset voltage to the source 120, and the bit line 110 is floating.

[0137] In some embodiments of this application, see Figures 1 to 4 The memory string MS also includes a first select gate transistor connected in series with the first memory cell group, and the peripheral circuit is further configured to: during the application of a first preset voltage, by applying a third preset voltage to the gate of the first select gate transistor, form a voltage difference between the source or drain of the first select gate transistor and the gate of the first select gate transistor.

[0138] As an example, the peripheral circuitry is configured to pre-program the first memory cell, and the third preset voltage may be, for example, a low-level voltage, such as the ground voltage of 0V.

[0139] As another example, the peripheral circuitry is configured to perform an erase operation on the first memory cell, and the magnitude of the third preset voltage may be, for example, 8-12V, to reduce the possibility that the first preset voltage (here, the erase high voltage) applied by the storage device to the side of the memory string closer to the first memory cell group will cause data to be stored in the first select gate transistor.

[0140] Alternatively, the memory string may also include a second select gate transistor connected in series with the second memory cell group; wherein, during the application of a first preset voltage, the gate of the second select gate transistor is floating.

[0141] For example, see Figure 4 If the storage stacking layer group corresponding to the first storage cell group is the upper storage stacking layer group 1311 (i.e., the first storage cell group is...), Figure 2 As shown in DECK1), the first select gate transistor includes a top select gate transistor (TST), and the second select gate transistor includes a bottom select gate transistor (BST). The memory device 100 can apply a third preset voltage to the gate of the top select gate transistor (TST) during the application of a first preset voltage, while the gate of the bottom select gate transistor (BST) is floating. If the memory stacking layer group corresponding to the first memory cell group is the lower memory stacking layer group 1312 (i.e., the first memory cell group is...), then... Figure 2 As shown in DECK2), the first select gate transistor includes a bottom select gate transistor BST, and the second select gate transistor includes a top select gate transistor TST. The storage device 100 can apply a third preset voltage to the gate of the bottom select gate transistor BST while applying a first preset voltage, and the gate of the top select gate transistor TST is floating.

[0142] In some embodiments of this application, see Figures 1 to 4 The memory string MS also includes a second pseudo memory cell group DMY2 disposed between the top select gate transistor TST and the plurality of memory cell groups DECK1 to DECK2. The memory device 100 may also apply a low-level voltage, such as a ground voltage of 0V, to the gate of the second pseudo memory cell group DMY2, for example, during the application of a first preset voltage, to prevent the second pseudo memory cell group DMY2 from entering the programming stage.

[0143] In some embodiments of this application, see Figures 1 to 4 The memory string MS also includes a third pseudo memory cell group DMY3 disposed between the bottom select gate transistor BST and the plurality of memory cell groups DECK1 to DECK2. The memory device 100 may also apply a low-level voltage, such as a ground voltage of 0V, to the gate of the third pseudo memory cell group DMY3 during the application of a first preset voltage, to prevent the third pseudo memory cell group DMY3 from entering the programming stage.

[0144] In some embodiments of this application, the peripheral circuitry is further configured to: apply a fourth preset voltage to the gate of a memory cell in the first memory cell group during the application of a first preset voltage, thereby performing a pre-programming operation or an erase operation on the first memory cell group; and retain the data in the second memory cell group by applying a fifth preset voltage to the gate of a memory cell in the second memory cell group. For example, memory cells located on the same memory layer in the storage device are connected to the same memory layer word line, and the storage device applies a fourth preset voltage to each memory layer word line WL in the first memory cell group and a fifth preset voltage to each memory layer word line WL in the second memory cell group.

[0145] In some embodiments of this application, the fourth preset voltage may be, for example, a low-level voltage, which may be, for example, a ground voltage of 0V, to prevent the memory cells MC of the first memory cell group from entering the programming stage.

[0146] As an example, the peripheral circuit is configured to pre-program the first memory cell group, with a fifth preset voltage of 0V to prevent the memory cells MC of the second memory cell group from entering the programming stage.

[0147] As another example, the peripheral circuit is configured to perform an erase operation on the first memory cell group, with a fifth preset voltage of 4-6V to prevent the data in the memory cells MC of the second memory cell group from being erased.

[0148] It should be understood that the process of the storage device 100 performing pre-programming, programming and erasing operations on the first storage cell group can be referred to the relevant description above, and will not be repeated here.

[0149] Figure 19 This is a block diagram of a non-volatile storage system according to an embodiment of this application. Figure 20 and Figure 21 This is a schematic diagram of the structure of a non-volatile storage system according to an exemplary embodiment of this application. For example... Figure 19 As shown, the non-volatile storage system 300 includes a non-volatile storage device 100 and a controller 310.

[0150] The non-volatile storage device 100 may be the same as the non-volatile storage device 100 described in any of the embodiments above, and will not be described again in this application.

[0151] The controller 310 can control the non-volatile storage device 100 via the channel CH, and can control the non-volatile storage device 100 to perform operations in response to a request from the host 400. The non-volatile storage device 100 can receive a command CMD and an address ADDR from the controller 310 via the channel CH and access a region selected from the memory cell array in response to the address. In other words, the non-volatile storage device 100 can perform internal operations corresponding to the command on the region selected by the address. More specifically, the controller 310 sends a command CMD and an address ADDR via the channel CH to execute the operation method 200 described in any of the embodiments above, causing the non-volatile storage device 100 to execute the operation method 200.

[0152] In such Figure 20In the example shown, the controller 310 and a single non-volatile storage device 100 can be integrated into a memory card. The memory card may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a compact flash (CF) card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a universal flash memory card (UFS), etc. The memory card may also include a memory card connector 320 that couples the memory card to the host 400.

[0153] In such Figure 21 In another example shown, the controller 310 and multiple non-volatile storage devices 100 can be integrated into a solid-state drive (SSD). The SSD may also include an SSD connector 330 that couples the SSD to a host (not shown). In some embodiments, the storage capacity and / or operating speed of the SSD is higher than... Figure 20 The storage capacity and / or operating speed of the memory card shown.

[0154] Although the structure of the non-volatile storage device 100 and the non-volatile storage system 300 has been described herein, it will be understood that one or more features may be omitted, substituted, or added from the non-volatile storage device 100 and the non-volatile storage system 300.

[0155] The above description is merely an illustration of the embodiments of this application and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method for operating a storage device, characterized in that, The storage device includes multiple storage strings, each storage string including a first storage cell group, a pseudo storage cell group, and a second storage cell group connected in series. The operation method includes: By applying a first preset voltage to one end of the storage string near the first storage cell group, a pre-programming operation or an erase operation is performed on the first storage cell group. During the application of the first preset voltage, a second preset voltage is applied to the gate of the dummy memory cell group, causing the channel potential of the dummy memory cell group to be higher than the channel potential of the first memory cell group, wherein the magnitude of the second preset voltage is positively correlated with the magnitude of the first preset voltage; and The data in the second memory cell group is maintained by applying a fifth preset voltage to the gate of the memory cell in the second memory cell group.

2. The operating method according to claim 1, wherein, During the application of the first preset voltage, the end of the memory string furthest from the first memory cell group is floated.

3. The operating method according to claim 1 or 2, wherein, The duration for which the second preset voltage is applied is greater than or equal to the duration for which the first preset voltage is applied.

4. The operating method according to claim 1 or 2, wherein, The storage string further includes a first select gate transistor connected in series with the first storage cell group, and the operation method further includes: During the application of the first preset voltage, a voltage difference is formed between the source or drain of the first select gate transistor and the gate of the first select gate transistor by applying a third preset voltage to the gate of the first select gate transistor.

5. The operating method according to claim 4, wherein, The memory string also includes a second select gate transistor connected in series with the second memory cell group; During the application of the first preset voltage, the gate of the second select gate transistor is floating.

6. The operating method according to claim 1 or 2, wherein, The operation method further includes: During the application of the first preset voltage, a fourth preset voltage is applied to the gate of a memory cell in the first memory cell group.

7. A non-volatile storage device, characterized in that, include: A storage block includes multiple storage strings, each of which includes a first storage cell group, a pseudo storage cell group, and a second storage cell group connected in series. The peripheral circuitry, coupled to the memory block, is configured as follows: By applying a first preset voltage to one end of the storage string near the first storage cell group, a pre-programming operation or an erase operation is performed on the first storage cell group. During the application of the first preset voltage, a second preset voltage is applied to the gate of the pseudo memory cell group to make the channel potential of the pseudo memory cell group higher than that of the first memory cell group, wherein the magnitude of the second preset voltage is positively correlated with the magnitude of the first preset voltage; as well as, The data in the second memory cell group is maintained by applying a fifth preset voltage to the gate of the memory cell in the second memory cell group.

8. The non-volatile storage device according to claim 7, wherein, During the application of the first preset voltage, the end of the storage string that is furthest from the first storage cell group is floated.

9. The non-volatile storage device according to claim 7 or 8, wherein, The memory string further includes a first select gate transistor connected in series with the first memory cell group, and the peripheral circuitry is further configured to: During the application of the first preset voltage, a voltage difference is formed between the source or drain of the first select gate transistor and the gate of the first select gate transistor by applying a third preset voltage to the gate of the first select gate transistor.

10. The non-volatile storage device according to claim 9, wherein, The memory string also includes a second select gate transistor connected in series with the second memory cell group; During the application of the first preset voltage, the gate of the second select gate transistor is floating.

11. The non-volatile storage device according to claim 7 or 8, wherein, The peripheral circuit is also configured to: During the application of the first preset voltage, a fourth preset voltage is applied to the gate of a memory cell in the first memory cell group.

12. A non-volatile storage system, characterized in that, include: The non-volatile storage device as described in any one of claims 7 to 11; as well as A controller coupled to the storage device and configured to control the storage device.

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