A method, apparatus and computer-readable storage medium for testing through-silicon vias (TSVs).

Abstract

This disclosure provides a through-silicon via (TSV) testing method, apparatus, and computer-readable storage medium applied to a chip stack structure. The chip stack structure includes multiple stacked chips connected vias. The method includes: writing first test data to a first chip based on a first preset array; writing second test data to a second chip based on a second preset array; performing data reading processing on the first and second chips to obtain first target data and second target data; comparing the first target data with the corresponding first test data, and comparing the second target data with the corresponding second test data; and determining whether the TSVs in the chip stack structure have a failure risk based on the comparison results. Thus, this disclosure provides a testing method for TSVs that can test whether TSVs have a failure risk without affecting device performance.

Description

Technical Field

[0001] This disclosure relates to the field of circuit testing technology, and in particular to a through-silicon via (TSV) testing method, apparatus, and computer-readable storage medium. Background Technology

[0002] Currently, for memory chips, three-dimensional design offers superior performance compared to planar design. In three-dimensional integrated structures, through-silicon vias (TSVs) are commonly used to achieve vertical interconnects between different chips. TSV technology involves etching through-holes into a silicon substrate and filling them with conductive materials, including but not limited to copper, tungsten, and other metallic materials, to form the vertical interconnects between memory chips. For memory chips employing three-dimensional integrated structures, TSVs are crucial for ensuring proper chip operation, making their testing an important task. Summary of the Invention

[0003] This disclosure provides a method, apparatus, and computer-readable storage medium for testing through-silicon vias (TSVs), which can test whether TSVs have a risk of failure.

[0004] The technical solution disclosed herein is implemented as follows:

[0005] In a first aspect, embodiments of this disclosure provide a through-silicon via (TSV) testing method applied to a chip stack structure, the chip stack structure comprising multiple stacked chips connected to each other via TSVs; the method includes:

[0006] Based on the first preset array, first test data is written to the first chip; wherein, the first chip refers to any chip in the chip stack structure;

[0007] Based on the second preset array, second test data is written to the second chip; wherein the second chip and the first chip are adjacent, and the structures of the first preset array and the second preset array are different;

[0008] Data reading processing is performed on the first chip and the second chip to obtain first target data and second target data;

[0009] The first target data and the first test data are compared accordingly, and the second target data and the second test data are compared accordingly. Based on the comparison results, it is determined whether there is a risk of failure of the through-silicon via in the chip stacking structure.

[0010] In some embodiments, before writing first test data to the first chip based on the first preset array, the method further includes: initializing the chip stack structure.

[0011] In some embodiments, writing first test data to the first chip based on the first preset array includes:

[0012] Based on the first preset array, data is written to a data block in the first chip according to the preset writing rules; after traversing all data blocks of the first chip, the data writing of the first chip is completed.

[0013] In some embodiments, writing second test data to the second chip based on the second preset array includes:

[0014] Based on the second preset array, data is written to a data block in the second chip according to the preset writing rules; after traversing all data blocks of the second chip, the data writing of the second chip is completed.

[0015] In some embodiments, the preset write rule includes: opening one word line of the data block and sequentially writing the storage unit corresponding to the word line, then closing the word line and opening the next adjacent word line, then sequentially writing the storage unit corresponding to the word line, until all word lines in the data block are traversed to complete the data writing of the data block.

[0016] In some embodiments, the method further includes: writing third test data to the first chip based on a third preset array; wherein the third preset array is different from the first preset array; writing fourth test data to the second chip based on a fourth preset array; wherein the fourth preset array and the second preset array have different structures, and the fourth preset array is different from the third preset array; performing data reading processing on the first chip and the second chip to obtain third target data and fourth target data; performing a corresponding comparison between the third target data and the third test data, and performing a corresponding comparison between the fourth target data and the fourth test data, and determining whether there is a failure risk in the through-silicon vias in the chip stacking structure based on the comparison results.

[0017] In some embodiments, the method further includes: selecting a first preset array, a second preset array, a third preset array, and a fourth preset array from preset array structures; wherein the preset array structures include at least the following structure types: a first chessboard structure, a second chessboard structure, a first row-connected structure, a second row-connected structure, a third row-connected structure, and a fourth row-connected structure; in the first chessboard structure or the second chessboard structure, the data at any position is different from the data at adjacent positions, and the starting position of the first chessboard structure is the first data, and the starting position of the second chessboard structure is the second data; in the first row-connected structure, the (4n+1)th row stores the first data, and the other rows store the second data; in the second row-connected structure, the (4n+2)th row stores the first data, and the other rows store the second data; in the third row-connected structure, the (4n+3)th row stores the first data, and the other rows store the second data; in the fourth row-connected structure, the (4n+4)th row stores the first data, and the other rows store the second data; n is a natural number.

[0018] In some embodiments, the method further includes: performing a refresh process on the first chip and the second chip based on a preset refresh cycle to maintain the data in the first chip and the second chip.

[0019] Secondly, embodiments of this disclosure provide a through-silicon via (TSV) testing device applied to a chip stacking structure, wherein the chip stacking structure includes multiple chips stacked together, and the different chips are connected through TSVs; the TSV testing device includes a first write module, a second write module, a read module, and a comparison module; wherein...

[0020] The first writing module is configured to write first test data to a first chip based on a first preset array; wherein, the first chip refers to any chip in the chip stack structure;

[0021] The second writing module is configured to write second test data to the second chip based on the second preset array; wherein the second chip and the first chip are adjacent, and the structures of the first preset array and the second preset array are different;

[0022] The reading module is configured to perform data reading processing on the first chip and the second chip to obtain first target data and second target data;

[0023] The comparison module is configured to perform a corresponding comparison between the first target data and the first test data, and to perform a corresponding comparison between the second target data and the second test data, and to determine whether there is a risk of failure of the through-silicon via in the chip stacking structure based on the comparison results.

[0024] In some embodiments, the through-silicon via (TSV) testing apparatus further includes an initialization module; the initialization module is configured to perform initialization processing on the chip stack structure.

[0025] In some embodiments, the first writing module is specifically configured to write data to a data block in the first chip according to a preset writing rule based on the first preset array; and to complete the data writing of the first chip after traversing all data blocks of the first chip.

[0026] In some embodiments, the second writing module is specifically configured to write data to a data block of the second chip according to a preset writing rule based on the second preset array; and to complete the data writing of the second chip after traversing all data blocks of the second chip.

[0027] In some embodiments, the first writing module is further configured to write third test data to the first chip based on a third preset array; wherein the third preset array is different from the first preset array; the second writing module is further configured to write fourth test data to the second chip based on a fourth preset array; wherein the fourth preset array and the second preset array have different structures, and the fourth preset array is different from the third preset array; the reading module is further configured to perform data reading processing on the first chip and the second chip to obtain third target data and fourth target data; the comparison module is further configured to perform a corresponding comparison between the third target data and the third test data, and to perform a corresponding comparison between the fourth target data and the fourth test data, and determine whether there is a failure risk in the through-silicon vias in the chip stacking structure based on the comparison results.

[0028] Thirdly, embodiments of this disclosure provide a through-silicon via (TSV) testing apparatus, including a memory and a processor; wherein,

[0029] The memory is configured to store computer programs that can run on the processor;

[0030] The processor is configured to execute the method as described in the first aspect when running the computer program.

[0031] Fourthly, embodiments of this disclosure provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the method described in the first aspect.

[0032] This disclosure provides a through-silicon via (TSV) testing method, apparatus, and computer-readable storage medium applied to a chip stack structure comprising multiple stacked chips connected vias. The method includes: writing first test data to a first chip based on a first preset array; writing second test data to a second chip based on a second preset array; the first and second preset arrays having different structures; performing data reading processing on the first and second chips to obtain first target data and second target data; comparing the first target data with the corresponding first test data, and comparing the second target data with the corresponding second test data; and determining whether the TSVs in the chip stack structure have a failure risk based on the comparison results. Thus, this disclosure provides a testing method for TSVs that can identify TSVs with a failure risk without affecting device performance. Attached Figure Description

[0033] Figure 1 This is a schematic diagram of a chip stacking structure;

[0034] Figure 2 This is a magnified schematic diagram of a through-silicon via (TSV).

[0035] Figure 3 This is a schematic diagram of a through-silicon via (TSV) fabrication process.

[0036] Figure 4 This is a schematic diagram of substrate noise coupling.

[0037] Figure 5 This is a schematic diagram of a through-silicon via (TSV) testing method provided in an embodiment of this disclosure;

[0038] Figure 6 This is a schematic diagram of another through-silicon via (TSV) testing method provided in an embodiment of this disclosure;

[0039] Figure 7 A schematic diagram of a through-silicon via (TSV) testing method provided in this embodiment of the present disclosure;

[0040] Figure 8 This is a schematic diagram of the structure of a through-silicon via (TSV) testing device provided in an embodiment of this disclosure;

[0041] Figure 9 This is a schematic diagram of another through-silicon via (TSV) testing device provided in an embodiment of the present disclosure;

[0042] Figure 10 An example of a specific hardware structure of a through-silicon via (TSV) testing device provided in the application embodiments;

[0043] Figure 11 A schematic diagram of the structure of a test platform provided in the disclosed embodiments. Detailed Implementation

[0044] The technical solutions of the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely for explaining the relevant applications and are not intended to limit the applications. Furthermore, it should be noted that, for ease of description, only the parts relevant to the relevant applications are shown in the accompanying drawings.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of this disclosure only and is not intended to limit the scope of this disclosure. In the following description, references to "some embodiments" describe a subset of all possible embodiments; however, it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict. It should be noted that the terms "first, second, third" used in the embodiments of this disclosure are only used to distinguish similar objects and do not represent a specific ordering of objects. It is understood that "first, second, third" may be interchanged in a specific order or sequence where permitted, so that the embodiments of this disclosure described herein can be implemented in an order other than that illustrated or described herein.

[0046] Dynamic Random Access Memory (DRAM) is a type of semiconductor memory widely used in multi-computer systems. The DRAM structure includes transistors, word lines, bit lines, capacitors, metal interconnects, and an outer edge region.

[0047] To increase storage capacity, DRAM can be stacked. See also Figure 1 It shows a schematic diagram of a chip stacking structure. For example... Figure 1 As shown, two chips are stacked, and the different chips are vertically interconnected through through-silicon vias (TSVs). See also... Figure 2 This illustrates an enlarged schematic diagram of a through-silicon via (TSV). Figure 2 In this context, AA refers to the active region, STI refers to shallow trench isolation structure, Cell refers to memory array, BL refers to bit line, BWL refers to buried word line, and M0, M1, M2, and M3 refer to different metal interconnect layers. For example... Figure 1 and Figure 2 As shown, by forming vertically conductive through-silicon vias between chips, interconnection between chips can be achieved, maximizing the density of chip stacking in three dimensions and minimizing the overall size, thereby improving chip speed and power consumption.

[0048] See Figure 3 The diagram illustrates a fabrication process flow for through-silicon vias (TSVs). Figure 3 As shown in (a), a substrate is provided, on which an oxide layer (OX) is present, and an active device (specifically a field-effect transistor) is formed in the oxide layer; as Figure 3 As shown in (b), a mask structure for through-silicon vias (TSVs) is formed above the oxide layer, and the mask structure is subjected to photolithography to form a TSV pattern; as shown in (b). Figure 3 As shown in (c), the through-silicon via (TSV) pattern is transferred downwards into the substrate by etching to form holes, and the mask structure is then removed; as Figure 3 As shown in (d), linear oxidation (Linear OX) is performed in the pores of the substrate to obtain a linear oxide layer; as... Figure 3 As shown in (e), tantalum (Ta) / tantalum nitride (TaN) continues to be deposited in the pores to form a barrier layer; as Figure 3 As shown in (f), copper (Cu) is filled into the pores by electrochemical deposition to form a conductive medium; as Figure 3 As shown in (g), unwanted copper (Cu) is removed by polishing to obtain a through-silicon via structure.

[0049] In chip stacking structures employing through-silicon via (TSV) technology, the TSVs may cause noise coupling with active devices. See also Figure 4 This illustrates a schematic diagram of substrate noise coupling. (For example...) Figure 4 As shown, through-silicon vias (TSVs) can generate noise coupling with the N-wells (N+) in the active device region, thereby interfering with the performance and read / write capabilities of the active device. Furthermore, TSVs can also fail due to open / short circuits. Therefore, testing TSVs is of great importance.

[0050] This disclosure provides a through-silicon via (TSV) testing method applied to a chip stack structure. The chip stack structure includes multiple stacked chips connected vias. The method includes: writing first test data to a first chip based on a first preset array; wherein the first chip refers to any chip in the chip stack structure; writing second test data to a second chip based on a second preset array; wherein the second chip and the first chip are adjacent, and the first and second preset arrays have different structures; performing data reading processing on the first and second chips to obtain first target data and second target data; comparing the first target data with the corresponding first test data, and comparing the second target data with the corresponding second test data, and determining whether the TSVs in the chip stack structure have a failure risk based on the comparison results. Thus, by comparing the corresponding data (first test data / first target data, second test data / second target data), corresponding data errors can be detected, and the failure risk of the corresponding TSVs can be determined without affecting the device's performance and stability.

[0051] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0052] In one embodiment of this disclosure, see Figure 5 This illustration shows a structural schematic diagram of a through-silicon via (TSV) testing method provided in an embodiment of this disclosure. Figure 5 As shown, the method may include:

[0053] S101: Write first test data to the first chip based on the first preset array; wherein, the first chip refers to any chip in the chip stack structure.

[0054] It should be noted that the through-silicon via (TSV) testing method provided in this disclosure is applied to a chip stacking structure. The chip stacking structure includes multiple chips stacked together, and the multiple chips are connected to each other through TSVs, as detailed above. Figure 1 or Figure 2 .

[0055] S102: Write second test data to the second chip based on the second preset array; wherein the second chip and the first chip are adjacent, and the structures of the first preset array and the second preset array are different.

[0056] In other words, the first chip and the second chip refer to any two adjacent chips in a chip stacking structure.

[0057] In some embodiments, such as Figure 6 As shown, before writing the first test data to the first chip based on the first preset array, the method may further include:

[0058] S201: Initialize the chip stack structure.

[0059] Thus, before step S101, the data in both the first and second chips are initialized to the same value to prepare for through-silicon via (TSV) testing.

[0060] It should be noted that the first and second preset arrays can be selected from the following preset array structures:

[0061] (1) The first chessboard structure, also known as Checkerboard "1". As shown in Table 1, the data at any position is different from the data at the adjacent positions, and the starting position is the first data "1". In Table 1, WL represents word line and BL represents bit line. The subsequent Tables 2 to 6 can be interpreted accordingly.

[0062] (2) The second chessboard structure, also known as Checkerboard “0”. As shown in Table 2, the data at any position is different from the data at the adjacent positions, and the starting position is the second data “0”.

[0063] Table 1

[0064] BL0 1 0 1 0 1 0 1 0 BL1 0 1 0 1 0 1 0 1 BL2 1 0 1 0 1 0 1 0 BL3 0 1 0 1 0 1 0 1 BL4 1 0 1 0 1 0 1 0 BL5 0 1 0 1 0 1 0 1 BL6 1 0 1 0 1 0 1 0 BL7 0 1 0 1 0 1 0 1

[0065] Table 2

[0066]

[0067]

[0068] (3) The first row is a linked structure, also known as “1”Coupling1 / 4. As shown in Table 3, the (4n+1)th row stores the first data “1”, and the other rows store the second data “0”, where n is a positive integer.

[0069] (4) The second row is a linked structure, also known as “1”Coupling1 / 4. As shown in Table 4, the (4n+2)th row stores the first data “1”, and the other rows store the second data “0”, where n is a positive integer.

[0070] (5) The third row is a linked structure, also known as “1”Coupling1 / 4. As shown in Table 5, the (4n+3)th row stores the first data “1”, and the other rows store the second data “0”, where n is a positive integer.

[0071] (6) The fourth row is a linked structure, also known as “1”Coupling1 / 4. As shown in Table 6, the (4n+4)th row stores the first data “1”, and the other rows store the second data “0”, where n is a positive integer.

[0072] Table 3

[0073] BL0 1 1 1 1 1 1 1 1 BL1 0 0 0 0 0 0 0 0 BL2 0 0 0 0 0 0 0 0 BL3 0 0 0 0 0 0 0 0 BL4 1 1 1 1 1 1 1 1 BL5 0 0 0 0 0 0 0 0 BL6 0 0 0 0 0 0 0 0 BL7 0 0 0 0 0 0 0 0

[0074] Table 4

[0075]

[0076]

[0077] Table 5

[0078] BL0 0 0 0 0 0 0 0 0 BL1 0 0 0 0 0 0 0 0 BL2 1 1 1 1 1 1 1 1 BL3 0 0 0 0 0 0 0 0 BL4 0 0 0 0 0 0 0 0 BL5 0 0 0 0 0 0 0 0 BL6 1 1 1 1 1 1 1 1 BL7 0 0 0 0 0 0 0 0

[0079] Table 6

[0080] BL0 0 0 0 0 0 0 0 0 BL1 0 0 0 0 0 0 0 0 BL2 0 0 0 0 0 0 0 0 BL3 1 1 1 1 1 1 1 1 BL4 0 0 0 0 0 0 0 0 BL5 0 0 0 0 0 0 0 0 BL6 0 0 0 0 0 0 0 0 BL7 1 1 1 1 1 1 1 1

[0081] Besides the structures mentioned above, the preset array structure can also be in other topological forms. For example, in the first column array structure, the (4n+1)th column stores the first data "1", and the other columns store the second data "0"; in the second column array structure, the (4n+2)th column stores the first data "1", and the other columns store the second data "0"; in the third column array structure, the (4n+3)th column stores the first data "1", and the other columns store the second data "0"; in the fourth column array structure, the (4n+4)th column stores the first data "1", and the other columns store the second data "0". The positions of the first data "1" and the second data "0" in the row array or column array structure can be swapped, and so on.

[0082] It should be understood that both the first and second chips are composed of multiple memory banks, each containing a large number of memory cells, and each memory cell is located via word lines and bit lines. It should also be understood that in each data block, the number of word lines and bit lines is more than eight; Tables 1 to 6 above represent a single cycle unit. When writing data to the chip, expansion can be performed according to the corresponding array structure.

[0083] In some embodiments, data writing to the chip can be performed block by block. Specifically, writing the first test data to the first chip based on the first preset array may include:

[0084] Based on the first preset array, data is written to a data block in the first chip according to the preset writing rules; after traversing all data blocks of the first chip, the data writing of the first chip is completed.

[0085] Similarly, in some embodiments, writing second test data to the second chip based on the second preset array may include:

[0086] Based on the second preset array, data is written to a data block in the second chip according to the preset writing rules; after traversing all data blocks of the second chip, the data writing of the second chip is completed.

[0087] In one specific embodiment, the preset write rule can refer to the Forward X-Fast write mode: after opening one word line of the data block and sequentially writing the memory unit corresponding to the word line, the word line is closed and the next adjacent word line is opened, and then the memory unit corresponding to the word line is sequentially written, until all word lines in the data block are traversed to complete the data writing of the data block.

[0088] In this way, the Forward X-Fast writing method can improve the speed of data writing and increase testing efficiency.

[0089] S103: Perform data reading and processing on the first chip and the second chip to obtain the first target data and the second target data.

[0090] S104: Compare the first target data and the first test data, and compare the second target data and the second test data accordingly. Based on the comparison results, determine whether there is a risk of failure in the through-silicon vias in the chip stacking structure.

[0091] It should be noted that since through-silicon vias (TSVs) are used to interconnect different chips, data from different chips may interfere with each other if there is a risk of TSV failure. Therefore, if the first target data and the corresponding first test data are not completely identical, and / or the second target data and the corresponding second test data are not completely identical, it can be determined that the corresponding TSV is at risk of failure. Whether the TSV has failed and the corresponding cause of failure need to be further investigated and determined. Here, the causes of TSV failure include at least one of the following: substrate coupling noise, TSV open circuit, and TSV short circuit.

[0092] It should be understood that in both the first and second chips, each memory cell is used to store one piece of data. Based on the comparison results of the first target data and the first test data, faulty memory cells can be accurately located, thereby further identifying through-silicon vias (TSVs) at risk of failure. Thus, addressing the problems existing in TSV technology, this disclosure provides an effective testing method that can screen out defective products early to prevent them from reaching customers, and can also provide feedback to the process department for improvement, avoiding waste of production costs.

[0093] It should be noted that steps S101 to S104 can be considered as a complete test cycle. To maximize the fault detection rate, multiple test cycles can be performed using different preset array structures to expand the test scenarios. Therefore, as... Figure 6 As shown, the method may further include:

[0094] S202: Write third test data to the first chip based on the third preset array; wherein the third preset array is different from the first preset array.

[0095] S203: Write fourth test data to the second chip based on the fourth preset array; wherein the fourth preset array and the second preset array have different structures, and the fourth preset array and the third preset array are different.

[0096] S204: Perform data reading and processing on the first chip and the second chip to obtain the third target data and the fourth target data.

[0097] S205: Compare the third target data and the third test data, and compare the fourth target data and the fourth test data. Based on the comparison results, determine whether there is a risk of failure in the through-silicon vias in the chip stacking structure.

[0098] Here, the third and fourth preset arrays are also selected from the aforementioned preset array structures. That is, in some embodiments, the method further includes: selecting a first preset array, a second preset array, a third preset array, and a fourth preset array from the preset array structures; wherein the preset array structures include at least the following structure types: a first chessboard structure (see Table 1 above), a second chessboard structure (see Table 2 above), a first row connection structure (see Table 3 above), a second row connection structure (see Table 4 above), a third row connection structure (see Table 5 above), and a fourth row connection structure (see Table 6 above).

[0099] It should be noted that the third preset array can be the same as the second preset array, and the fourth preset array can also be the same as the first preset array.

[0100] It should be noted that after step S205, different preset array structures can be changed again, and the aforementioned test cycle can be repeated to enrich the test scenarios.

[0101] In this way, by changing the test data of different structures, it is possible to test whether the first chip and the second chip can work normally under different scenarios, thereby increasing the detection probability of failed through-silicon vias.

[0102] In some embodiments, the method may further include: performing refresh processing on the first chip and the second chip based on a preset refresh cycle to maintain the data in the first chip and the second chip.

[0103] Here, refresh processing can be performed on a word-line basis, also known as line refresh processing.

[0104] It should be noted that for dynamic random access memory, the chip stack structure needs to be refreshed periodically to maintain the data in the memory cells.

[0105] This disclosure provides a through-silicon via (TSV) testing method, which has the following advantages: on the one hand, by comparing the corresponding data of the first test data / first target data and the second test data / second target data, corresponding data errors can be detected, and it can be determined whether the corresponding TSV has a failure risk; on the other hand, for mass-produced chip stacking structures, faulty products can be accurately identified, and the fault point can be accurately located; furthermore, the relevant tests can be completed through normal read and write processes, without affecting the performance and stability of the device.

[0106] In another embodiment of this disclosure, taking a chip stack structure comprising two chips as an example, specific steps of the through-silicon via (TSV) testing method are provided.

[0107] See Figure 7 This illustration shows a schematic diagram of a through-silicon via (TSV) testing method provided in an embodiment of this disclosure. Figure 7 In this context, the first chip in a chip stack is called C0, and the second chip in the chip stack is called C1. For example... Figure 7 As shown, each chip includes multiple banks. After selecting a bank, the target memory cell is selected for reading and writing by word lines (along the row direction) and bit lines (along the column direction).

[0108] Through-silicon via (TSV) testing methods include the following:

[0109] Step 1: Initialize C0 and C1 ( Figure 7 (Not shown), at this time it can be regarded that all storage cells in C0 and C1 store the data "0" or all store the data "1".

[0110] Step Two: As Figure 7 As shown in (a), the first test data TP a is written to all banks in C0 along the Forward X-Fast direction (equivalent to the aforementioned preset write rule). Here, the first test data TP a can adopt any preset array structure (see Tables 1 to 6 above), for example, the first test data TP a can be the first row array structure; Forward X-Fast means: after opening a word line, the bit lines are opened sequentially to write data until all memory cells on this word line are written; the word line is closed and the next word line is opened, and the above actions are repeated until all memory cells on the last word line are written, i.e., the "Z" shaped direction.

[0111] Step 3: As Figure 7 As shown in (b), the second test data TP b is written to all banks in C1 along the Forward X-Fast direction (equivalent to the aforementioned preset write rule). Here, the second test data TP b can adopt any preset array structure (see Tables 1 to 6 above), and the second test data TP b is different from the first test data TP a. For example, the second test data TP b can be a first chessboard structure.

[0112] Step 4: After the data writing is complete, perform a self-refresh operation on all banks to preserve the data in C0 and C1.

[0113] Step 5: As Figure 7As shown in (c), C0 is read to obtain the first target data, and the first target data and the first test data are compared to determine whether there is an error.

[0114] Step Six: As Figure 7 As shown in (d), C1 is read to obtain the second target data. The second target data and the second test data are compared to determine whether there is an error.

[0115] In this way, based on the comparison results between the first test data / first target data and the second test data / second target data, the location where the error occurred can be identified, indicating that the corresponding through-silicon via is at risk of failure.

[0116] Furthermore, after completing step six, you can change the test data to different structures and repeat steps two through six to enrich the test scenarios.

[0117] If the written data and the read data differ during this process, it indicates that the corresponding through-silicon via (TSV) is at risk of failure.

[0118] In summary, the present disclosure provides a test method for using through-silicon via (TSV) vertical interconnect technology in three-dimensional integrated circuit (3D IC) technology, which can effectively test the TSV open / short problem and solve the interference to active devices (such as field-effect transistors) caused by substrate noise coupling brought about by TSV.

[0119] In yet another embodiment of this disclosure, see [link to relevant documentation]. Figure 8 It shows a schematic diagram of the structure of a through-silicon via (TSV) testing device 30 provided in an embodiment of this disclosure, such as... Figure 8 As shown, the through-silicon via (TSV) testing device 30 is applied to a chip stacking structure, which includes multiple stacked chips connected to each other vias. The TSV testing device 30 includes a first write module 301, a second write module 302, a read module 303, and a comparison module 304.

[0120] The first writing module 301 is configured to write first test data to a first chip based on a first preset array; wherein, the first chip refers to any chip in the chip stack structure;

[0121] The second writing module 302 is configured to write second test data to the second chip based on the second preset array; wherein the second chip and the first chip are adjacent, and the structures of the first preset array and the second preset array are different;

[0122] Reading module 303 is configured to perform data reading processing on the first chip and the second chip to obtain first target data and second target data.

[0123] The comparison module 304 is configured to perform a corresponding comparison between the first target data and the first test data, and to perform a corresponding comparison between the second target data and the second test data, and to determine whether there is a risk of failure of the through-silicon via in the chip stacking structure based on the comparison results.

[0124] In some embodiments, such as Figure 9 As shown, the through-silicon via (TSV) testing device 30 also includes an initialization module 305; the initialization module 305 is configured to perform initialization processing on the chip stack structure.

[0125] In some embodiments, the first writing module 301 is specifically configured to write data to a data block in the first chip according to a preset writing rule based on a first preset array; and to complete the data writing of the first chip after traversing all data blocks of the first chip.

[0126] In some embodiments, the second writing module 302 is specifically configured to write data to a data block in the second chip according to a preset writing rule based on the second preset array; and to complete the data writing of the second chip after traversing all data blocks of the second chip.

[0127] In some embodiments, the preset write rule includes: opening one word line of the data block and sequentially writing the storage unit corresponding to the word line, then closing the word line and opening the next adjacent word line, then sequentially writing the storage unit corresponding to the word line again, until all word lines in the data block are traversed to complete the data writing of the data block.

[0128] In some embodiments, the first writing module 301 is further configured to write third test data to the first chip based on a third preset array; wherein the third preset array is different from the first preset array.

[0129] The second writing module 302 is further configured to write fourth test data to the second chip based on the fourth preset array; wherein the fourth preset array and the second preset array have different structures, and the fourth preset array is different from the third preset array.

[0130] The reading module 303 is also configured to perform data reading processing on the first chip and the second chip to obtain the third target data and the fourth target data;

[0131] The comparison module 304 is also configured to perform a corresponding comparison between the third target data and the third test data, and to perform a corresponding comparison between the fourth target data and the fourth test data, and to determine whether there is a risk of failure of the through-silicon via in the chip stacking structure based on the comparison results.

[0132] In some embodiments, the first preset array, the second preset array, the third preset array, and the fourth preset array are all selected from preset array structures. The preset array structures include at least the following structure types: a first chessboard structure, a second chessboard structure, a first row-connected structure, a second row-connected structure, a third row-connected structure, and a fourth row-connected structure; in the first or second chessboard structure, the data at any position is different from the data at adjacent positions, and the starting position of the first chessboard structure is the first data, and the starting position of the second chessboard structure is the second data; in the first row-connected structure, the (4n+1)th row stores the first data, and the other rows store the second data; in the second row-connected structure, the (4n+2)th row stores the first data, and the other rows store the second data; in the third row-connected structure, the (4n+3)th row stores the first data, and the other rows store the second data; in the fourth row-connected structure, the (4n+4)th row stores the first data, and the other rows store the second data; n is a natural number.

[0133] In some embodiments, such as Figure 9 As shown, the through-silicon via (TSV) testing device 30 also includes a refresh module 306; the refresh module 306 is configured to perform refresh processing on the first chip and the second chip based on a preset refresh cycle in order to maintain the data in the first chip and the second chip.

[0134] This disclosure provides a through-silicon via (TSV) testing device, which has the following advantages: on the one hand, by comparing the corresponding data of the first test data / first target data and the second test data / second target data, corresponding data errors can be detected, and it can be determined whether the corresponding TSV has a failure risk; on the other hand, for mass-produced chip stacking structures, faulty products can be accurately identified, and the fault point can be accurately located; furthermore, the relevant tests can be completed through normal read and write processes, without affecting the performance and stability of the device.

[0135] Understandably, in this embodiment, a "unit" can be a portion of a circuit, a portion of a processor, a portion of a program or software, etc., and can also be a module or a non-modular component. Furthermore, the components in this embodiment can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional module.

[0136] If the integrated unit is implemented as a software functional module and not sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this embodiment, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) or processor to execute all or part of the steps of the method described in this embodiment. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0137] Therefore, this embodiment provides a computer-readable storage medium storing a computer program that, when executed by at least one processor, implements the steps of the method described in any of the foregoing embodiments.

[0138] Based on the above-described composition of a through-silicon via (TSV) testing device 30 and its computer-readable storage medium, see [link to relevant documentation]. Figure 10 This illustrates a specific hardware structure example of a through-silicon via (TSV) testing device 30 provided in an embodiment of this disclosure, such as... Figure 10 As shown, the through-silicon via (TSV) testing device 40 may include: a communication interface 401, a memory 402, and a processor 403; the various components are coupled together via a bus device 404. It is understood that the bus device 404 is used to realize the connection and communication between these components. In addition to a data bus, the bus device 404 also includes a power bus, a control bus, and a status signal bus. However, for clarity, in... Figure 10 The general will label all buses as bus devices 404. Among them,

[0139] Communication interface 401 is used for receiving and sending signals during the process of sending and receiving information with other external network elements;

[0140] Memory 402 is used to store computer programs that can run on processor 403;

[0141] Processor 403, when running the computer program, performs the following:

[0142] Based on a first preset array, first test data is written to a first chip; wherein the first chip refers to any chip in the chip stack structure; based on a second preset array, second test data is written to a second chip; wherein the second chip and the first chip are adjacent, and the structures of the first preset array and the second preset array are different; data reading processing is performed on the first chip and the second chip to obtain first target data and second target data; the first target data and the first test data are compared accordingly, and the second target data and the second test data are compared accordingly, and the through silicon vias in the chip stack structure are judged based on the comparison results to determine whether there is a failure risk.

[0143] It is understood that the memory 402 in this embodiment can be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. The non-volatile memory can be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. The volatile memory can be random access memory (RAM), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as Static Random Access Memory (SRAM), Dynamic Random Access Memory (DRAM), Synchronous DRAM (SDRAM), Double Data Rate SDRAM (DDRSDRAM), Enhanced Synchronous DRAM (ESDRAM), Synchronous Link DRAM (SLDRAM), and Direct Rambus RAM (DRRAM). The memory 402 of the apparatus and method described in this disclosure is intended to include, but is not limited to, these and any other suitable types of memory.

[0144] The processor 403 may be an integrated circuit chip with signal processing capabilities. In implementation, each step of the above method can be completed by the integrated logic circuitry in the hardware of the processor 403 or by instructions in software form. The processor 403 may be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this disclosure. The general-purpose processor may be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this disclosure can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules may reside in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. The storage medium is located in memory 402. Processor 403 reads the information in memory 402 and, in conjunction with its hardware, completes the steps of the above method.

[0145] It is understood that the embodiments described in this disclosure can be implemented in hardware, software, firmware, middleware, microcode, or a combination thereof. For hardware implementation, the processing unit can be implemented in one or more application-specific integrated circuits (ASICs), digital signal processors (DSPs), digital signal processing devices (DSPDs), programmable logic devices (PLDs), field-programmable gate arrays (FPGAs), general-purpose processors, controllers, microcontrollers, microprocessors, other electronic units for performing the functions described in this disclosure, or combinations thereof.

[0146] For software implementation, the techniques described herein can be implemented through modules (e.g., procedures, functions, etc.) that perform the functions described herein. The software code can be stored in memory and executed by a processor. The memory can be implemented in the processor or external to the processor.

[0147] Alternatively, as another embodiment, the processor 403 is further configured to perform the steps of the method described in any of the foregoing embodiments when running the computer program.

[0148] Based on the above-described composition and hardware structure diagram of the through-silicon via (TSV) testing device 30, see [link / reference]. Figure 11 This illustrates a schematic diagram of the composition structure of a test platform 50 provided in an embodiment of this disclosure. Figure 11 As shown, the test platform 50 includes at least the through-silicon via (TSV) test device 30 as described in any of the foregoing embodiments.

[0149] For the test platform 50, the through-silicon via (TSV) testing device 30 can test the TSVs in the chip stack structure, which has the following advantages: Firstly, by comparing the corresponding data of the first test data / first target data and the second test data / second target data, corresponding data errors can be detected, and it can be determined whether the corresponding TSVs have a failure risk; Secondly, for the chip stack structure produced in batches, faulty products can be accurately identified, and the fault point can be accurately located; Thirdly, the relevant tests can be completed through normal read and write processes, without affecting the performance and stability of the device.

[0150] The above description is merely a preferred embodiment of this disclosure and is not intended to limit the scope of protection of this disclosure. It should be noted that in this disclosure, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. The sequence numbers of the embodiments in this disclosure are merely descriptive and do not represent the superiority or inferiority of the embodiments. The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined to obtain new method embodiments without conflict. The features disclosed in the several product embodiments provided in this disclosure can be arbitrarily combined to obtain new product embodiments without conflict. The features disclosed in the several method or device embodiments provided in this disclosure can be arbitrarily combined to obtain new method or device embodiments without conflict. The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A method for testing through-silicon vias (TSVs), characterized in that, The method is applied to a chip stacking structure, wherein the chip stacking structure includes multiple chips stacked together, and the multiple chips are connected through through-silicon vias (TSVs); wherein a first chip memory cell and a second chip memory cell corresponding to the same address share the same TSV transmission path; the method includes: Based on the first preset array, first test data is written to the first chip; wherein, the first chip refers to any chip in the chip stack structure; Based on the second preset array, second test data is written to the second chip; wherein the second chip and the first chip are adjacent, and the structures of the first preset array and the second preset array are different; Data reading processing is performed on the first chip and the second chip to obtain first target data and second target data; The first target data and the first test data are compared accordingly, and the second target data and the second test data are compared accordingly to obtain the comparison results of the memory cells with the same address in the first chip and the second chip. Based on the comparison results, it is determined whether the through-silicon via in the chip stack structure has a failure risk. If the read and write data of the memory cells with the same address in the first chip and the second chip are inconsistent, it is determined that the through-silicon via connecting the transmission path corresponding to that address has a failure risk.

2. The through-silicon via (TSV) testing method according to claim 1, characterized in that, Before writing the first test data to the first chip based on the first preset array, the method further includes: The chip stack structure is initialized.

3. The through-silicon via (TSV) testing method according to claim 1, characterized in that, The step of writing first test data to the first chip based on the first preset array includes: Based on the first preset array, data is written to a data block in the first chip according to the preset writing rules; After traversing all data blocks of the first chip, the data writing of the first chip is completed.

4. The through-silicon via (TSV) testing method according to claim 1, characterized in that, The step of writing second test data to the second chip based on the second preset array includes: Based on the second preset array, data is written to a data block in the second chip according to the preset writing rules; After traversing all data blocks of the second chip, the data writing to the second chip is completed.

5. The through-silicon via (TSV) testing method according to claim 3 or 4, characterized in that, The preset write rules include: After opening one word line of the data block and sequentially writing the corresponding storage unit, the word line is closed and the next adjacent word line is opened. Then, the storage unit corresponding to the word line is written sequentially again until all word lines in the data block are traversed, thus completing the data writing of the data block.

6. The through-silicon via (TSV) testing method according to claim 1, characterized in that, The method further includes: writing third test data to the first chip based on a third preset array; wherein the third preset array is different from the first preset array; Based on the fourth preset array, fourth test data is written to the second chip; wherein the fourth preset array and the second preset array have different structures, and the fourth preset array is different from the third preset array; Data reading and processing are performed on the first chip and the second chip to obtain the third target data and the fourth target data; The third target data and the third test data are compared accordingly, and the fourth target data and the fourth test data are compared accordingly to obtain the comparison results of the memory cells with the same address in the first chip and the second chip. Based on the comparison results, it is determined whether the through-silicon vias in the chip stack structure have a failure risk. If the read and write data of the memory cells with the same address in the first chip and the second chip are inconsistent, it is determined that the through-silicon vias connecting the transmission path corresponding to that address have a failure risk.

7. The through-silicon via (TSV) testing method according to claim 6, characterized in that, The method further includes: Select the first preset array, the second preset array, the third preset array, and the fourth preset array from the preset array structures; The preset array structure includes at least the following structure types: a first chessboard structure, a second chessboard structure, a first row-connected structure, a second row-connected structure, a third row-connected structure, and a fourth row-connected structure. In the first chessboard structure or the second chessboard structure, the data at any position is different from the data at adjacent positions, and the starting position of the first chessboard structure is the first data, and the starting position of the second chessboard structure is the second data. In the first row-connected structure, the (4n+1)th row stores the first data, and the other rows store the second data. In the second row-connected structure, the (4n+2)th row stores the first data, and the other rows store the second data. In the third row-connected structure, the (4n+3)th row stores the first data, and the other rows store the second data. In the fourth row-connected structure, the (4n+4)th row stores the first data, and the other rows store the second data. n is a natural number.

8. The through-silicon via (TSV) testing method according to claim 1, characterized in that, The method further includes: Based on a preset refresh cycle, the first chip and the second chip are refreshed to maintain the data in the first chip and the second chip.

9. A through-silicon via (TSV) testing device, characterized in that, This is applied to a chip stacking structure, which includes multiple stacked chips connected via through-silicon vias (TSVs). A first chip memory cell and a second chip memory cell corresponding to the same address share the same TSV transmission path. The TSV testing device includes a first write module, a second write module, a read module, and a comparison module. The first writing module is configured to write first test data to a first chip based on a first preset array; wherein, the first chip refers to any chip in the chip stack structure; The second writing module is configured to write second test data to the second chip based on the second preset array; wherein the second chip and the first chip are adjacent, and the structures of the first preset array and the second preset array are different; The reading module is configured to perform data reading processing on the first chip and the second chip to obtain first target data and second target data; The comparison module is configured to perform a corresponding comparison between the first target data and the first test data, and to perform a corresponding comparison between the second target data and the second test data, to obtain the comparison results of the memory cells with the same address in the first chip and the second chip, and to determine whether the through-silicon vias in the chip stack structure have a failure risk based on the comparison results. If the read and write data of the memory cells with the same address in the first chip and the second chip are inconsistent, it is determined that the through-silicon vias connecting the transmission path corresponding to that address have a failure risk.

10. The through-silicon via (TSV) testing apparatus according to claim 9, characterized in that, The through-silicon via (TSV) testing device also includes an initialization module; The initialization module is configured to perform initialization processing on the chip stack structure.

11. The through-silicon via (TSV) testing apparatus according to claim 9, characterized in that, The first writing module is specifically configured to write data to a data block in the first chip according to a preset writing rule based on the first preset array; and to complete the data writing of the first chip after traversing all data blocks of the first chip.

12. The through-silicon via (TSV) testing apparatus according to claim 9, characterized in that, The second writing module is specifically configured to write data to a data block in the second chip according to a preset writing rule based on the second preset array; after traversing all data blocks of the second chip, the data writing of the second chip is completed.

13. The through-silicon via (TSV) testing apparatus according to claim 9, characterized in that, The first writing module is further configured to write third test data to the first chip based on a third preset array; wherein the third preset array is different from the first preset array; The second writing module is further configured to write fourth test data to the second chip based on a fourth preset array; wherein the fourth preset array and the second preset array have different structures, and the fourth preset array is different from the third preset array; The reading module is further configured to perform data reading processing on the first chip and the second chip to obtain third target data and fourth target data; The comparison module is further configured to perform a corresponding comparison between the third target data and the third test data, and to perform a corresponding comparison between the fourth target data and the fourth test data, to obtain the comparison results of the memory cells with the same address in the first chip and the second chip, and to determine whether the through-silicon vias in the chip stack structure have a failure risk based on the comparison results. If the read and write data of the memory cells with the same address in the first chip and the second chip are inconsistent, it is determined that the through-silicon vias connecting the transmission path corresponding to that address have a failure risk.

14. A through-silicon via (TSV) testing device, characterized in that, Includes memory and processor; among which, The memory is configured to store computer programs that can run on the processor; The processor is configured to perform the method as described in any one of claims 1-8 when running the computer program.

15. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the method as described in any one of claims 1-8.

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