Hard mask and method of making same, method of making semiconductor structure

Abstract

The present disclosure relates to a hard mask, a preparation method thereof and a preparation method of a semiconductor structure. The hard mask for etching comprises a mask material layer, a sacrificial layer and a plasma deposition layer which are stacked above the mask material layer; the sacrificial layer comprises a plurality of support portions which are arranged at intervals, and a side wall on the sidewall of any support portion; the side wall is used to define a mask pattern; and the plasma deposition layer covers the support portions and the side walls. The hard mask, the preparation method thereof and the preparation method of the semiconductor structure provided by the present disclosure can effectively avoid the phenomenon that the surface of the plasma deposition layer is uneven due to the inconsistent width of the gap between adjacent side walls, so as to improve the etching precision of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor manufacturing technology, and in particular to a hard mask and its preparation method, and a method for preparing semiconductor structures. Background Technology

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory in computers and other electronic devices, consisting of multiple memory cells. Each memory cell includes a storage capacitor and a transistor electrically connected to the storage capacitor. The transistor includes a gate, a source region, and a drain region. The transistor's gate is used to electrically connect to the word line. The transistor's source region forms the bit line contact region to electrically connect to the bit line through a bit line contact structure. The transistor's drain region forms the memory node contact region to electrically connect to the storage capacitor through a memory node contact structure.

[0003] Currently, with the development of semiconductor technology, the feature size of devices in integrated circuits is getting smaller and smaller. After semiconductor processes entered the deep submicron stage, the size of DRAM is getting smaller and smaller. Some devices in DRAM can be fabricated using self-aligned processes such as self-aligned double patterning (SADP) or self-aligned quadruple patterning (SAQP) or their reverse (R) processes.

[0004] However, in the fabrication of semiconductor structures using R-SADP or R-SAQP processes, a spin-on process is typically required to form a spin-on carbon hard mask to support the small-sized mask pattern. Spin-on carbon hard masks contain liquid solvents, have low mechanical properties, and are prone to surface unevenness due to the varying spacing between the covered device structures. Furthermore, spin-on carbon hard masks have a low selective etching ratio compared to oxides. This can easily lead to localized under-etching or over-etching, resulting in poor etching accuracy and even etching defects. Summary of the Invention

[0005] Based on this, the present disclosure provides a hard mask and its preparation method, as well as a semiconductor structure preparation method, which can avoid adding unnecessary solvents to the hard mask and effectively avoid the phenomenon of uneven surface on the plasma deposition layer due to the inconsistent width of the gap between adjacent sidewalls, thereby improving the etching accuracy of the semiconductor structure.

[0006] To achieve the above objectives, in one aspect, some embodiments of this disclosure provide a hard mask for etching. The hard mask includes: a mask material layer and a sacrificial layer and a plasma deposition layer stacked on top of the mask material layer; wherein, the sacrificial layer includes: a plurality of spaced-apart supports and a sidewall located on the sidewall of any of the supports; the sidewall is used to define the mask pattern; the plasma deposition layer covers the supports and the sidewall.

[0007] In some embodiments, there is a gap between adjacent sidewalls; the plasma deposition layer also fills the gap.

[0008] In some embodiments, the plasma deposition layer comprises a pure carbon deposition layer.

[0009] In some embodiments, the support portion is made of the same material as the plasma deposition layer; and / or, the sidewall is made of a different material than the support portion, wherein the sidewall material includes oxides.

[0010] In some embodiments, the hard mask further includes an anti-reflective layer located between the mask material layer and the sacrificial layer.

[0011] On the other hand, some embodiments of this disclosure provide a method for preparing a hard mask, including the following steps.

[0012] Form a mask material layer.

[0013] Multiple support portions are formed at intervals above the mask material layer.

[0014] A sidewall is formed on the side wall of the support portion, and the sidewall is used to define the mask pattern.

[0015] A first plasma deposition process is used to form a plasma deposition layer on the surface of the support and the sidewall; the plasma deposition layer covers the support and the sidewall.

[0016] In some embodiments, there is a gap between adjacent sidewalls, and the plasma deposition layer also fills the gap.

[0017] In some embodiments, forming a plurality of spaced-apart support portions above the mask material layer includes: forming a sacrificial material layer above the mask material layer using a second plasma deposition process; and patterning the sacrificial material layer using a plasma sputtering etching process to form the support portions.

[0018] In some embodiments, the support portion is made of the same material as the plasma deposition layer; the second plasma deposition process is the same as the first plasma deposition process.

[0019] In some embodiments, before forming a plurality of spaced-apart support portions above the mask material layer, the fabrication method further includes forming an anti-reflective layer on the surface of the mask material layer. Forming the plurality of spaced-apart support portions above the mask material layer includes forming the support portions on the surface of the anti-reflective layer opposite to the mask material layer.

[0020] In some embodiments, the first plasma deposition process includes a pure carbon plasma deposition process.

[0021] In some embodiments, the first plasma deposition process includes: plasma-enhanced chemical vapor deposition, plasma-enhanced atomic layer deposition, or high-density plasma chemical vapor deposition.

[0022] In another aspect, some embodiments of this disclosure provide a method for fabricating a semiconductor structure, including the following steps.

[0023] A substrate is provided on which a layer to be etched is formed.

[0024] A hard mask is formed on the layer to be etched using the preparation methods described in some of the above embodiments.

[0025] The hard mask is etched to form a mask pattern in the mask material layer.

[0026] The mask pattern is transferred to the layer to be etched.

[0027] In some embodiments, etching the hard mask to form a mask pattern in the mask material layer includes the following steps.

[0028] The sidewalls are etched away to form an initial mask pattern.

[0029] The mask material layer is etched based on the initial mask pattern to form the mask pattern in the mask material layer.

[0030] In some embodiments, after transferring the mask pattern to the layer to be etched, the fabrication method further includes: removing the residual hard mask.

[0031] The hard mask and its fabrication method, as well as the semiconductor structure fabrication method provided in this disclosure, are as described above. In this disclosure, the hard mask does not require spin-coated carbon mask material, thus avoiding the introduction of unnecessary solvents into the hard mask and effectively improving the etching selectivity between the plasma-deposited carbon layer and the sidewalls. Furthermore, in this disclosure, the hard mask uses a plasma-deposited layer to cover the support, sidewalls, and gaps between adjacent sidewalls. This allows the plasma-deposited layer to better support adjacent sidewalls, ensuring the accurate shape of the mask pattern defined by each sidewall.

[0032] Furthermore, the plasma deposition layer in this embodiment is formed using a deposition process, which can fill the gaps between adjacent sidewalls from bottom to top. This effectively prevents deformation such as tilting of the sidewall forming surface and avoids surface unevenness caused by inconsistent gap widths between adjacent sidewalls. Therefore, it ensures that during etching using a hard mask, there will be no issues of insufficient or over-etching due to differences in the height of the hard mask surface relative to the surface to be etched. Consequently, the etching accuracy of the semiconductor structure can be effectively improved. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments or conventional technologies of this disclosure, the accompanying drawings used in the description of the embodiments or conventional technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0034] Figure 1 This is a top view schematic diagram of a semiconductor structure provided in one embodiment; Figure 2 This is a schematic diagram of the structure of a hard mask provided in one embodiment; Figure 3 This is a schematic flowchart of a method for preparing a hard mask provided in one embodiment; Figure 4 for Figure 3 A schematic diagram of step S220 in the preparation method shown; Figure 5 This is a schematic flowchart of another method for preparing a hard mask provided in one embodiment; Figure 6 This is a schematic flowchart of a method for fabricating a semiconductor structure provided in one embodiment; Figure 7 for Figure 6 A schematic diagram of step S300 in the preparation method shown; Figures 8-17 This is a schematic cross-sectional view of the structure obtained in each step of a semiconductor structure fabrication method provided in one embodiment.

[0035] Explanation of reference numerals in the attached figures: 1-Hard mask material layer, 2-Sacrificial layer, 21-Support, 210-Sacrificial material layer, 22-Sidewall, G-Gap 3-Plasma deposition layer, 4-Anti-reflective layer, 01-Substrate, 02-Layer to be etched, M0 - Initial mask pattern, M - Mask pattern, M' - Etching pattern R1 - Unit array area, R2 - Peripheral circuit area. Detailed Implementation

[0036] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, which illustrate embodiments of the present disclosure. However, this disclosure can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0038] It should be understood that when a component or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other components or layers, it may be directly on, adjacent to, connected to, or coupled to other components or layers, or there may be intervening components or layers. Conversely, when a component is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other components or layers, there are no intervening components or layers.

[0039] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly. When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items. Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of preferred embodiments (and intermediate structures) of the present disclosure, thus allowing for the expectation of variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the present disclosure should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. The regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device, nor do they limit the scope of the present disclosure.

[0040] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory in computers and other electronic devices, consisting of multiple memory cells. Each memory cell includes a storage capacitor and a transistor electrically connected to the storage capacitor. The transistor includes a gate, a source region, and a drain region. The transistor's gate is used to electrically connect to the word line. The transistor's source region forms the bit line contact region to electrically connect to the bit line through a bit line contact structure. The transistor's drain region forms the memory node contact region to electrically connect to the storage capacitor through a memory node contact structure.

[0041] Currently, with the development of semiconductor technology, the feature size of devices in integrated circuits is getting smaller and smaller. After semiconductor processes entered the deep submicron stage, the size of DRAM is getting smaller and smaller. Some devices in DRAM can be fabricated using self-aligned processes such as self-aligned double patterning (SADP) or self-aligned quadruple patterning (SAQP) or their reverse (R) processes.

[0042] The aforementioned SADP and SAQP refer to processes where, after a single photolithography step, non-photolithography steps (such as thin film deposition and etching) are used to spatially multiply the photolithographic pattern, followed by another photolithography and etching step to remove excess patterns. Correspondingly, R-SADP refers to the reverse alignment process of SADP, and R-SAQP refers to the reverse alignment process of SAQP.

[0043] In some examples, please combine Figure 1 To illustrate, let's take a DRAM semiconductor structure as an example. The semiconductor structure includes a cell array region R1 and a peripheral circuit region R2 located adjacent to R1. The cell array region R1 has at least multiple active regions AA, multiple word lines WL, and multiple bit lines BL. The peripheral circuit region R2 has peripheral circuitry (…). Figure 1(Not shown in the diagram). Multiple active regions AA are arrayed, multiple word lines WL are arranged in parallel and spaced apart, extending along a first direction, and multiple bit lines BL are arranged in parallel and spaced apart, extending along a second direction. The first and second directions intersect, for example, perpendicularly. Furthermore, the connection relationships and relative positions of the active regions AA, word lines WL, and bit lines BL can be found in related technologies and will not be detailed here. Additionally, it can be understood that the device structure distribution density in the cell array region R1 is greater than the device structure distribution density in the peripheral circuit region R2. That is, the spacing between adjacent device structures in the cell array region R1 is much smaller than the spacing between adjacent device structures in the peripheral circuit region R2.

[0044] It should be noted that in the process of fabricating semiconductor structures using R-SADP or R-SAQP processes, a spin-on process is typically required to form a spin-coated carbon hard mask to support the small-sized mask pattern. However, spin-coated carbon hard masks contain liquid solvents, have low mechanical properties, and are prone to surface unevenness due to the varying spacing between the covered device structures. For example, spin-coated carbon hard masks are formed using a spin-on coating followed by baking method. Due to the poor flowability of the spin-coated carbon material, under the same rotation speed, it is easy for the surface to become convex due to smaller spacing between the covered device structures and concave due to larger spacing, resulting in an uneven surface. For example, the height difference between convex and concave points on the same surface of a spin-coated carbon hard mask may be greater than 60 nm.

[0045] As described above, spin-coated carbon hard masks are prone to surface unevenness due to the varying spacing between adjacent device structures in the cell array region R1 and the peripheral circuit region R2. Furthermore, the selective etching ratio between the spin-coated carbon hard mask and oxide is relatively low, for example, 1:1. Therefore, during the fabrication of semiconductor structures using R-SADP or R-SAQP processes, the unevenness of the spin-coated carbon hard mask surface relative to the surface to be etched can easily lead to localized under-etching or over-etching, resulting in poor etching accuracy and even etching defects.

[0046] Based on this, some embodiments of this disclosure provide a hard mask for etching, for example, it can be used in R-SADP or R-SAQP processes to fabricate semiconductor structures. Please refer to... Figure 2 The hard mask includes a mask material layer 1 and a sacrificial layer 2 and a plasma deposition layer 3 stacked on top of the mask material layer 1. The sacrificial layer 2 includes a plurality of spaced-apart support portions 21 and a sidewall 22 located on the sidewall of any support portion 21; the sidewall 22 defines the mask pattern. The plasma deposition layer 3 covers the support portions 21 and the sidewall 22.

[0047] In some examples, the mask material layer 1 includes, but is not limited to, a material layer with high hardness suitable for forming a hard mask, such as a silicon nitride (SiN) material layer, a carbon material layer, a polysilicon (Poly) material layer, or a metal material layer.

[0048] In some examples, the support 21 is made of a carbon material layer with high hardness, such as a pure carbon material layer.

[0049] In some examples, the sidewall 22 covers the sidewall of the support 21 and is used to define the mask pattern. The sidewall 22 may be formed of an oxide material, such as silicon dioxide.

[0050] In some examples, the plasma-deposited layer 3 is formed using a plasma deposition process, which can result in better material density and mechanical properties. For example, the plasma-deposited layer 3 can be a pure carbon deposition layer, formed using a pure carbon plasma deposition process. Thus, using a pure carbon deposition layer 3 can also effectively improve the etching selectivity between the deposition layer and the sidewalls.

[0051] Please continue reading. Figure 2 In some embodiments, there is a gap G between adjacent sidewalls 22. The plasma deposition layer 3 also fills the gap G. In this way, the plasma deposition layer 3 can better support the adjacent sidewalls 22 and ensure the accurate shape of the mask pattern defined by the sidewalls 22.

[0052] In addition, the plasma deposition layer 3 is formed using plasma deposition processes, such as plasma enhanced chemical vapor deposition (PECVD), plasma enhanced atomic layer deposition (PEALD), or high-density plasma chemical vapor deposition (HDPCVD).

[0053] Therefore, in this embodiment of the present disclosure, the plasma deposition layer 3 can fill the gap G between adjacent sidewalls 22 from bottom to top, effectively preventing deformation such as tilting of the forming surface of the sidewalls 22, and effectively avoiding the situation where the height of the surface of the plasma deposition layer 3 is inconsistent due to the inconsistent width of the gap G between adjacent sidewalls 22. That is, after the hard mask in this embodiment of the present disclosure uses the plasma deposition layer 3 to fill the gap between adjacent sidewalls 22, the surface of the plasma deposition layer 3 facing away from the sacrificial layer 2 is relatively flat compared with the surface of the hard mask formed by spin-coating carbon mask material, and is less prone to unevenness, or even if there is slight unevenness, the height difference between its protrusions and depressions will not be greater than 15nm, for example, 9nm. This ensures that during the etching process using the hard mask, there will be no problem of local under-etching or local over-etching due to the height difference between the surface of the hard mask and the surface to be etched, thereby effectively improving the etching accuracy.

[0054] It is understood that in some embodiments, the support portion 21 is made of the same material as the plasma deposition layer 3; and / or, the sidewall 22 is made of a different material than the support portion 21.

[0055] In some examples, the material of the plasma deposition layer 3 is the same as the material of the support portion 21. This simplifies the manufacturing process and helps reduce production costs.

[0056] In some examples, the sidewall 22 is made of a different material than the support 21. This facilitates the subsequent independent removal of the sidewall 22 to form an accurate mask pattern.

[0057] Please continue reading. Figure 2 In some embodiments, the hard mask further includes an anti-reflection layer 4 located between the mask material layer 1 and the sacrificial layer 2. Thus, the anti-reflection layer 4 can be used to increase the photolithography process window of the hard mask, thereby improving the imaging accuracy of the mask pattern.

[0058] In some examples, the antireflective layer 4 includes an organic antireflective coating or a dielectric antireflective coating.

[0059] For example, antireflective layer 4 is a dielectric anti-reflective coating (DARC). The material of antireflective layer 4 is silicon oxynitride or other nitrogen-containing compounds.

[0060] The hard mask structure provided in this embodiment, as described above, eliminates the need for spin-coated carbon mask material in the hard mask layer, avoiding unnecessary solvent incorporation and effectively improving the etching selectivity between the plasma-deposited carbon layer and the sidewalls. Furthermore, this embodiment uses a plasma-deposited layer 3 to cover the support 21, sidewalls 22, and the gap G between adjacent sidewalls 22. This allows the plasma-deposited layer 3 to effectively support the adjacent sidewalls 22, ensuring the accurate shape of the mask pattern defined by each sidewall 22. In addition, the plasma-deposited layer 3 in this embodiment is formed using a deposition process, filling the gap G between adjacent sidewalls 22 from bottom to top. This effectively prevents deformation such as tilting of the sidewall 22's forming surface and effectively avoids surface unevenness caused by inconsistent gap G widths between adjacent sidewalls 22. Therefore, it ensures that during etching using a hard mask, there will be no localized under-etching or over-etching due to differences in the height of the hard mask surface relative to the surface to be etched. Consequently, it effectively improves the etching accuracy of the semiconductor structure.

[0061] Please see Figure 3 This disclosure provides a method for preparing a hard mask according to some embodiments, for preparing the hard mask as described in the above embodiments. The preparation method includes the following steps.

[0062] S210 forms a mask material layer.

[0063] For example, the mask material layer can be formed using silicon nitride, pure carbon, polycrystalline silicon, or metal.

[0064] S220, a plurality of support portions are formed at intervals above the mask material layer.

[0065] For example, the support 21 is formed of pure carbon material with high hardness.

[0066] S230, a sidewall is formed on the side wall of the support, the sidewall being used to define the mask pattern.

[0067] For example, the sidewall 22 may be formed of an oxide material, such as silicon dioxide.

[0068] S240 employs a first plasma deposition process to form a plasma deposition layer on the surface of the support and sidewalls; the plasma deposition layer covers the support and sidewalls.

[0069] In some embodiments, there is a gap between adjacent sidewalls, and the plasma deposition layer also fills the gap.

[0070] For example, the plasma deposition layer 3 can be made of pure carbon material and formed by a plasma deposition process.

[0071] In some embodiments, please refer to Figure 4 In step S220, forming a plurality of spaced-apart support portions above the mask material layer includes the following steps.

[0072] S221 employs a second plasma deposition process to form a sacrificial material layer above the mask material layer.

[0073] S222 uses a plasma sputtering etching process to pattern the sacrificial material layer to form the support.

[0074] It is understood that in some embodiments, the support portion and the plasma deposition layer are made of the same material. Accordingly, the second plasma deposition process can be the same as the first plasma deposition process. Optionally, it is also permissible for the second plasma deposition process to differ from the first plasma deposition process.

[0075] In some embodiments, the first plasma deposition process includes: a pure carbon plasma deposition process.

[0076] It is understandable that plasma-deposited layers are used to fill the gaps between adjacent sidewalls. When the gap has a large depth-to-width ratio, the plasma-deposited layer needs to be formed by repeatedly performing a "deposition-etching-deposition" process; that is, before the previous deposition fails, the gap entrance is reopened by etching for re-deposition, thus completing the filling of the gap by the plasma-deposited layer. In this way, as the feature size of semiconductor structures continues to shrink, the repeated use of the "deposition-etching-deposition" process can effectively fill gaps with smaller widths.

[0077] In some embodiments, the first plasma deposition process includes: plasma-enhanced chemical vapor deposition, plasma-enhanced atomic layer deposition, or high-density plasma-enhanced chemical vapor deposition. This facilitates the simultaneous deposition and etching processes within the same reaction chamber, allowing the plasma-deposited layer to effectively fill the gaps between adjacent sidewalls.

[0078] This embodiment of the invention uses the above-described method to prepare the hard mask, which avoids the introduction of unnecessary solvents into the hard mask and effectively improves the etching selectivity between the hard mask and the material to be etched. Furthermore, this embodiment uses a first plasma deposition process to form the plasma deposition layer, which fills the gaps between adjacent sidewalls from bottom to top, thus providing better support for the adjacent sidewalls. This ensures the accuracy of the mask pattern defined by the sidewalls and effectively prevents deformation such as tilting of the sidewall forming surface. In addition, the first plasma deposition process used in this embodiment effectively avoids surface unevenness caused by inconsistent gap widths between adjacent sidewalls. This ensures that during etching using the hard mask, there will be no localized under-etching or over-etching due to differences in the height of the hard mask surface relative to the surface to be etched. Therefore, it effectively improves the etching accuracy of the semiconductor structure.

[0079] In some embodiments, please refer to Figure 5 Before performing step S220, the preparation method further includes: S215, forming an anti-reflective layer on the surface of the mask material layer. Accordingly, step S220 can be expressed as S220', forming a support portion on the surface of the anti-reflective layer opposite to the mask material layer.

[0080] For example, the anti-reflective layer can be formed by coating with an organic anti-reflective material or a dielectric anti-reflective material.

[0081] For example, the antireflective layer is a dielectric antireflective coating. The material of the antireflective layer is silicon oxynitride or other nitrogen-containing compounds.

[0082] In this embodiment of the disclosure, an anti-reflection layer is formed between the mask material layer and the sacrificial layer. The anti-reflection layer can be used to increase the photolithography process window of the hard mask, thereby improving the imaging accuracy of the mask pattern.

[0083] On the other hand, please refer to Figure 6 This disclosure provides a method for fabricating a semiconductor structure, comprising the following steps.

[0084] S100 provides a substrate on which a layer to be etched is formed.

[0085] S200, a hard mask is formed on the layer to be etched. The hard mask can be formed using the preparation methods described in some of the above embodiments.

[0086] S300, etching hard mask, forms mask pattern in mask material layer.

[0087] S400, the mask pattern is transferred to the layer to be etched.

[0088] In some embodiments, step S300 involves etching a hard mask to form a mask pattern in a mask material layer, including the following steps.

[0089] S310, etch away the sidewalls to form the initial mask pattern.

[0090] S320, etching the mask material layer based on the initial mask pattern to form a mask pattern in the mask material layer.

[0091] In some embodiments, after performing step S400 to transfer the mask pattern to the layer to be etched, the fabrication method further includes: S500, removing the residual hard mask.

[0092] To more clearly illustrate the fabrication methods of the semiconductor structures described in the above embodiments, the following is combined with... Figures 8-16 An exemplary description has been provided.

[0093] In step S100, please refer to Figure 8 A substrate 01 is provided, on which an etchable layer 02 is formed.

[0094] For example, substrate 01 may be a blank substrate or a substrate with partial device structures.

[0095] Furthermore, depending on the semiconductor structure, the etchable layer 02 on the substrate 01 can be implemented in various ways, such as a metal layer, an oxide layer, or a polysilicon layer, etc., which can be selected according to actual needs. This disclosure does not limit this aspect.

[0096] In some examples, please combine Figure 1 and Figure 8 Understandably, the semiconductor structure can be DRAM. Substrate 01 includes a cell array region R1 and a peripheral circuit region R2 located adjacent to the cell array region R1. The device structure distribution density in the cell array region R1 is greater than the device structure distribution density in the peripheral circuit region R2. That is, the spacing between adjacent device structures in the cell array region R1 is much smaller than the spacing between adjacent device structures in the peripheral circuit region R2.

[0097] In step S200, please refer to Figures 8-10 A hard mask 2 is formed on the layer 02 to be etched.

[0098] For example, the hard mask 2 can be formed using the following preparation method.

[0099] In step S210, as Figure 8 As shown, a mask material layer 1 is formed on the layer 02 to be etched.

[0100] For example, the mask material layer 1 can be formed of silicon nitride, pure carbon, polysilicon, or metal. The hard mask material layer 1 covers the layer 02 to be etched, a mask pattern can be formed therein, and the layer 02 to be etched can be etched based on the mask pattern.

[0101] In step S215, as Figure 8 As shown, an anti-reflective layer 4 is formed on the surface of the mask material layer 1.

[0102] For example, the anti-reflective layer 4 can be formed by coating with an organic anti-reflective material or a dielectric anti-reflective material.

[0103] For example, antireflective layer 4 is a dielectric antireflective coating. The material of antireflective layer 4 is silicon oxynitride or other nitrogen-containing compounds.

[0104] In step S220, please refer to Figure 8 and Figure 9 Multiple support portions 21 are formed at intervals above the mask material layer 1.

[0105] In some examples, step S220 includes steps S221 and S222.

[0106] In step S221, as Figure 8 As shown, a second plasma deposition process is used to form a sacrificial material layer 210 above the mask material layer 1.

[0107] In one example, the second plasma deposition process can be a pure carbon plasma deposition process. The sacrificial material layer 210 can be a pure carbon material layer.

[0108] In step S222, as Figure 9 As shown, a plasma sputtering etching process is used to pattern the sacrificial material layer 210 to form the support portion 21.

[0109] Here, multiple support parts 21 are arranged at intervals, and the spacing between adjacent support parts 21 can be selected and set according to actual needs.

[0110] In step S230, as Figure 10 As shown, a sidewall 22 is formed on the sidewall of the support 21, and the sidewall 22 is used to define the mask pattern.

[0111] For example, the sidewall 22 may be formed of an oxide material, such as silicon dioxide.

[0112] In addition, the sidewalls 22 are used to define the mask pattern. The shape and size of the sidewalls 22 can be selected and set according to the mask pattern to be formed. In some examples, there is also a gap G between adjacent sidewalls 22.

[0113] In step S240, as Figure 11 As shown, a first plasma deposition process is used to form a plasma deposition layer 3 on the surfaces of the support portion 21 and the sidewall 22. The plasma deposition layer 3 covers the support portion 21 and the sidewall 22.

[0114] In some examples, there is a gap G between adjacent sidewalls 22, and the plasma deposition layer 3 also fills the gap G.

[0115] In some examples, the plasma-deposited layer 3 can be made of pure carbon material and formed by a plasma deposition process. The first plasma deposition process is, for example, a pure carbon plasma deposition process.

[0116] In some examples, the first plasma deposition process includes: plasma-enhanced chemical vapor deposition, plasma-enhanced atomic layer deposition, or high-density plasma chemical vapor deposition.

[0117] Thus, after the formation of plasma deposition layer 3, the hard mask preparation is complete.

[0118] In step S300, please refer to Figures 12-14 Etch the hard mask to form a mask pattern M in the mask material layer 1.

[0119] In some examples, step S300 includes steps S310 and S320.

[0120] In step S310, please refer to Figure 12 and Figure 13 The sidewalls 22 are etched away to form the initial mask pattern M0.

[0121] It is understood that the plasma deposition layer 3 covers the support portion 21 and the sidewall 22. Therefore, before removing the sidewall 22, it is necessary to etch away part of the plasma deposition layer 3 to expose the top surface of the support portion 21 and the sidewall 22, for example... Figure 12 As shown in the diagram. Thus, the surface of the etched plasma deposition layer 3' is flush with the top surfaces of the support 21 and the sidewall 22. Subsequently, the sidewall 22 is etched away to form the initial mask pattern M0, for example... Figure 13 As shown in the image.

[0122] In some examples, the sidewalls 22 are formed of oxide materials and can be removed using a wet etching process.

[0123] In step S320, please refer to Figure 14 The mask material layer 1 is etched based on the initial mask pattern M0 to form the mask pattern M in the mask material layer 1.

[0124] It is understood that an anti-reflection layer 4 is formed between the mask material layer 1 and the sacrificial layer 2. When etching the mask material layer 1 based on the mask pattern M formed after removing the sidewalls 22, the anti-reflection layer 4 needs to be etched first. In this way, the anti-reflection layer 4 can be used to effectively increase the photolithography process window of the hard mask, thereby improving the imaging accuracy of the mask pattern M.

[0125] Furthermore, after transferring the initial mask pattern M0 formed after removing the sidewalls 22 to the mask material layer 1, the remaining plasma deposition layer 3' and support 21 can be removed, resulting in a structure such as Figure 15 As shown in the image.

[0126] In step S400, please refer to Figure 16 The mask pattern M is transferred to the layer O2 to be etched.

[0127] Specifically, based on the mask pattern M in the mask material layer 1, the layer 02 to be etched is etched, and the mask pattern M can be transferred to the layer 02 to be etched, forming an etched pattern M' in the layer 02.

[0128] In step S500, please refer to Figure 17 Remove any remaining hard mask.

[0129] Specifically, by removing the anti-reflective layer 4 and the mask material layer 1, the resulting structure is as follows: Figure 16 As shown in the image.

[0130] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0131] The embodiments described above are merely illustrative of several implementations of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the scope of protection of this disclosure. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A hard mask for etching, characterized in that, include: A mask material layer and a sacrificial layer and a plasma deposition layer stacked on top of the mask material layer; wherein, The sacrificial layer includes: a plurality of spaced-apart support portions, and a sidewall located on the sidewall of any of the support portions; the sidewall is used to define the mask pattern; The plasma deposition layer covers the support and the sidewall; There are gaps between adjacent sidewalls; the plasma deposition layer also fills the gaps.

2. The hard mask according to claim 1, characterized in that, The plasma deposition layer includes a pure carbon deposition layer.

3. The hard mask according to claim 2, characterized in that, The support portion is made of the same material as the plasma deposition layer; And / or, the sidewall is made of a different material than the support, and the sidewall material includes oxides.

4. The hard mask according to claim 1, characterized in that, The hard mask further includes an anti-reflective layer located between the mask material layer and the sacrificial layer.

5. A method for preparing a hard mask, characterized in that, include: Form a mask material layer; A plurality of support portions are formed at intervals above the mask material layer; A sidewall is formed on the side wall of the support portion, and the sidewall is used to define the mask pattern; A first plasma deposition process is used to form a plasma deposition layer on the surface of the support and the sidewall; The plasma deposition layer covers the support and the sidewall; There are gaps between adjacent sidewalls, and the plasma deposition layer also fills the gaps.

6. The method for preparing a hard mask according to claim 5, characterized in that, The plurality of support portions formed at intervals above the mask material layer include: A sacrificial material layer is formed above the mask material layer using a second plasma deposition process. The sacrificial material layer is patterned using a plasma sputtering etching process to form the support portion.

7. The method for preparing a hard mask according to claim 6, characterized in that, The support portion is made of the same material as the plasma deposition layer; the second plasma deposition process is the same as the first plasma deposition process.

8. The method for preparing a hard mask according to claim 5, characterized in that, Before forming a plurality of spaced-apart support portions above the mask material layer, the preparation method further includes: forming an anti-reflection layer on the surface of the mask material layer; The method of forming a plurality of spaced-apart support portions above the mask material layer includes: forming the support portions on the surface of the anti-reflective layer opposite to the mask material layer.

9. The method for preparing a hard mask according to any one of claims 5 to 8, characterized in that, The first plasma deposition process includes: a pure carbon plasma deposition process.

10. The method for preparing a hard mask according to any one of claims 5 to 8, characterized in that, The first plasma deposition process includes: plasma-enhanced chemical vapor deposition, plasma-enhanced atomic layer deposition, or high-density plasma chemical vapor deposition.

11. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided on which a layer to be etched is formed; A hard mask is formed on the layer to be etched using the preparation method described in any one of claims 5 to 10; The hard mask is etched to form a mask pattern in the mask material layer; The mask pattern is transferred to the layer to be etched.

12. The method for preparing a semiconductor structure according to claim 11, characterized in that, The etching of the hard mask to form a mask pattern in the mask material layer includes: The sidewalls are etched away to form an initial mask pattern; The mask material layer is etched based on the initial mask pattern to form the mask pattern in the mask material layer.

13. The method for preparing a semiconductor structure according to claim 11 or 12, characterized in that, After transferring the mask pattern to the layer to be etched, the fabrication method further includes: Remove any remaining hard mask.

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