形成微电子装置的方法和相关微电子装置、存储器装置和电子系统
By forming a stacked structure of alternating insulating and conductive structures in a non-volatile memory device and inserting low-k dielectric material between conductive plugs, the parasitic capacitance problem between adjacent conductive features is solved, achieving higher memory density and lower power requirements and latency.
CN114823496BActive Publication Date: 2026-07-17MICRON TECHNOLOGY INC
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- MICRON TECHNOLOGY INC
- Filing Date
- 2022-01-26
- Publication Date
- 2026-07-17
AI Technical Summary
Technical Problem
As the size and spacing of conductive features decrease, the parasitic capacitance between adjacent conductive features in non-volatile memory devices increases, leading to higher power requirements and latency in the memory devices.
Method used
By forming a stacked structure that includes alternating insulating and conductive structures, vertically extending pillar structures and conductive plug structures are formed, and low-k dielectric material is inserted between them to reduce parasitic capacitance between adjacent conductive features.
Benefits of technology
It effectively reduces parasitic capacitance, lowers the power requirements and latency of memory devices, and improves memory density and operating efficiency.
✦ Generated by Eureka AI based on patent content.
Smart Images
Figure CN114823496B_ABST
Abstract
本申请涉及形成微电子装置的方法，和相关微电子装置、存储器装置和电子系统。所述形成微电子装置的方法包括形成包括布置成层次的竖直交替的绝缘结构和导电结构的堆叠结构。所述层次中的每一个个别地包括所述绝缘结构中的一个和所述导电结构中的一个。牺牲材料形成于所述堆叠结构之上且柱结构形成为竖直延伸穿过所述堆叠结构和所述牺牲材料。所述方法包括：在所述柱结构的上部部分内形成导电插塞结构；形成竖直延伸穿过所述堆叠结构和所述牺牲材料的狭槽；至少部分地去除所述牺牲材料以形成水平插入在所述导电插塞结构之间的开口；和在所述开口内形成低K介电材料。
Need to check novelty before this filing date? Find Prior Art