Semiconductor device and method of forming the same

Abstract

A semiconductor device and a method of forming the same includes a semiconductor substrate and a stack of channel layers on the semiconductor substrate. A top surface of a topmost channel layer extends along a first height relative to a substrate surface. A bottom surface of a bottommost channel layer extends along a second height relative to the substrate surface. The device further includes a gate structure engaged with the stack of channel layers and extending along a first direction. Additionally, the device includes a source / drain feature on a first sidewall surface of the stack of channel layers and on the substrate, the first sidewall surface extending parallel to the first direction. Furthermore, the source / drain feature has a first width along the first direction at the first height and a second width along the first direction at the second height, and wherein the first width is greater than the second width.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a method of forming the same, and more particularly to a multichannel transistor device and a method of forming the same. Background Technology

[0002] The semiconductor integrated circuit industry has experienced rapid growth. Technological advancements in integrated circuit materials and design have led to several generations of integrated circuits, each with smaller and more complex circuits than the previous generation. During the evolution of integrated circuits, functional density (i.e., the number of interconnects per unit chip area) typically increases while geometry (i.e., the smallest element (or line) that can be manufactured using a process) decreases. This miniaturization process usually benefits by increasing production efficiency and reducing associated costs. However, this miniaturization also increases the complexity of integrated circuit manufacturing and processes, and similar advancements in integrated circuit processes and manufacturing are needed to achieve these progresses.

[0003] For example, nanosheet-based devices have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and mitigating short-channel effects (SCEs). Nanosheet-based devices comprise multiple stacked channel layers to form transistor channels engaged by gate structures. Nanosheet-based devices are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes, allowing for aggressive miniaturization while maintaining gate control and mitigating SCEs. However, achieving a balance between optimal current density and extremely low fringe capacitance can be challenging due to the device's structural complexity. Therefore, while conventional nanosheet-based devices are generally sufficient for their intended purpose, they are not entirely satisfactory in all aspects. Summary of the Invention

[0004] This disclosure provides a semiconductor device comprising: a semiconductor substrate having a substrate surface; a stack of channel layers on the semiconductor substrate, wherein a top surface of the topmost channel layer of the stack extends along a first height relative to the substrate surface, and a bottom surface of the bottommost channel layer of the stack extends along a second height relative to the substrate surface; a gate structure engaging the stack of channel layers and extending along a first direction; and source / drain components on a first sidewall surface of the stack of channel layers and on the substrate, the first sidewall surface extending parallel to the first direction; wherein the source / drain components have a first width along the first direction at the first height and a second width along the first direction at the second height, and wherein the first width is greater than the second width.

[0005] Other embodiments of this disclosure provide a semiconductor device, including: a semiconductor substrate; a first dielectric component on the semiconductor substrate and having a first sidewall surface; a second dielectric component on the semiconductor substrate and having a second sidewall surface, the first sidewall surface facing the second sidewall surface; a third dielectric component on the first sidewall surface and having a third sidewall surface; a fourth dielectric component on the second sidewall surface and having a fourth sidewall surface, the third sidewall surface facing the fourth sidewall surface; and a source / drain component above the semiconductor substrate and having a bottom and a top, the bottom extending between the third sidewall surface and the fourth sidewall surface, and the top extending between the first sidewall surface and the second sidewall surface, wherein a first distance between the third sidewall surface and the fourth sidewall surface is less than a second distance between the first sidewall surface and the second sidewall surface, and wherein the first dielectric component and the second dielectric component each include a first dielectric material, and the third dielectric component and the fourth dielectric component each include a second dielectric material, the second dielectric material being different from the first dielectric material.

[0006] This disclosure further provides a method of forming a semiconductor device, comprising: receiving a semiconductor workpiece having an active region extending above a top surface of a semiconductor substrate; forming a dielectric member on a first opposing sidewall of the active region in a first direction; etching a portion of the active region to form a source / drain trench, the source / drain trench exposing a second opposing sidewall of the active region; etching the dielectric member; and forming a source / drain member in the source / drain trench and on the second opposing sidewall exposed in the active region, the source / drain member being partially formed on the top surface of the dielectric member. Attached Figure Description

[0007] The various aspects of this disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale and are only used for illustrative purposes. In fact, the dimensions of the elements may be arbitrarily enlarged or reduced to clearly demonstrate the features of this disclosure.

[0008] Based on various aspects of this disclosure, Figure 1A , Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A as well as Figure 10A The example workpiece disclosed herein is illustrated in three-dimensional views at various manufacturing stages.

[0009] Based on various aspects of this disclosure, Figure 1B , Figure 2B , Figure 3B , Figure 4B , Figure 5B , Figure 6B , Figure 7B , Figure 8B , Figure 9B as well as Figure 10B The example workpieces disclosed herein are illustrated along... Figure 1A , Figure 2A , Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A as well as Figure 10A A partial cross-sectional view of line B-B' in the diagram.

[0010] Based on various aspects of this disclosure, Figure 9B' as well as Figure 9B "Illustrated example workpiece along the path of this disclosure" Figure 9A A partial cross-sectional view of line B-B' in the diagram.

[0011] Based on various aspects of this disclosure, Figure 3C , Figure 4C , Figure 5C , Figure 6C , Figure 7C , Figure 8C , Figure 9C as well as Figure 10C The example workpieces disclosed herein are illustrated along... Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9Aas well as Figure 10A A partial cross-sectional view of line C-C' in the diagram.

[0012] Based on various aspects of this disclosure, Figure 3D , Figure 4D , Figure 5D , Figure 6D , Figure 7D , Figure 8D , Figure 9D as well as Figure 10D The example workpieces disclosed herein are illustrated along... Figure 3A , Figure 4A , Figure 5A , Figure 6A , Figure 7A , Figure 8A , Figure 9A as well as Figure 10A A partial cross-sectional view of line D-D' in the diagram.

[0013] Based on various aspects of this disclosure, Figure 7E , Figure 8E , Figure 9E as well as Figure 10E The example workpieces disclosed herein are illustrated along... Figure 7A , Figure 8A , Figure 9A as well as Figure 10A A partial cross-sectional view of line E-E' in the diagram.

[0014] Based on various aspects of this disclosure, Figure 7F , Figure 8F , Figure 9F as well as Figure 10F The example workpieces disclosed herein are illustrated along... Figure 7A , Figure 8A , Figure 9A as well as Figure 10A A partial cross-sectional view of line F-F' in the diagram.

[0015] Based on various aspects of this disclosure, Figure 7G , Figure 8G , Figure 9G as well as Figure 10G The example workpieces disclosed herein are illustrated along... Figure 7A , Figure 8A , Figure 9A as well as Figure 10A A partial cross-sectional view of line G-G' in the diagram.

[0016] Based on various aspects of this disclosure, Figure 11 A partial cross-sectional view of an example workpiece of this disclosure is shown.

[0017] Based on various aspects of this disclosure, Figure 12 This is a flowchart of an example method disclosed herein.

[0018] The reference numerals in the attached figures are explained as follows:

[0019] 100: Method

[0020] 102: Steps

[0021] 104: Steps

[0022] 106: Steps

[0023] 108: Steps

[0024] 110: Steps

[0025] 112: Steps

[0026] 114: Steps

[0027] 116: Steps

[0028] 118: Steps

[0029] 120: Steps

[0030] 122: Steps

[0031] 124: Steps

[0032] 126: Steps

[0033] 200: Workpiece (device)

[0034] 202: Substrate

[0035] 204: Semiconductor layer (stacked)

[0036] 206: Sacrifice Layer

[0037] 207: Oxide layer

[0038] 208: Channel Layer

[0039] 209: Hard mask layer

[0040] 212: Fin-like structure (active region)

[0041] 214: Isolation component

[0042] 216: Coating layer

[0043] 218: Dielectric components (dielectric barrier)

[0044] 219: Trench

[0045] 220: Fill layer

[0046] 221: Membrane layer

[0047] 222: Dielectric layer (hard masking layer)

[0048] 230: Gate Stack

[0049] 232: Gate structure

[0050] 234: Spacer

[0051] 236: Trench

[0052] 242: Internal spacer component

[0053] 243: Contact Etching Stop Layer

[0054] 244: Interlayer dielectric layer

[0055] 245: Source / Drain Components

[0056] 270: Air gap

[0057] 280: Contact component

[0058] 316: Trench

[0059] 402: Thickness

[0060] 404: Thickness

[0061] 406: Thickness

[0062] 408: Width (Distance)

[0063] 410: Distance (Width)

[0064] 410: Width

[0065] 412: Altitude

[0066] 414: Thickness

[0067] 416: Altitude

[0068] 418: Altitude (Distance)

[0069] 420: Distance

[0070] 422: Altitude (Distance)

[0071] 424: Altitude

[0072] 426: Width

[0073] 428: Width

[0074] 429: Width

[0075] 430: Width

[0076] 1216: Dielectric components

[0077] 212B: Partial

[0078] 212C: Passage Area

[0079] 212S: Partial

[0080] 212SD: Source / Drain Region

[0081] 236A: Lower part

[0082] 236B: Top

[0083] 245A: Lower part

[0084] 245B: Top Detailed Implementation

[0085] The following provides numerous different embodiments or examples to implement different components of the embodiments of this disclosure. Specific examples of components and configurations are described below to simplify the embodiments of this disclosure. Of course, these are merely examples and are not intended to limit the embodiments of this disclosure. For example, the dimensions of elements are not limited to the disclosed range or values, but may depend on process conditions and / or desired characteristics of the apparatus. Furthermore, the following description of forming a first component above or on a second component may include embodiments where the first and second components are formed in direct contact, and may also include embodiments where an additional component is formed between the first and second components, such that the first and second components do not need to be in direct contact. For simplicity and clarity, various components may be drawn at any scale.

[0086] Furthermore, spatially relative terms such as "below," "below," "lower," "above," and "higher" may be used to facilitate the description of the relationship between one or more components or features in the diagram. Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the diagram. When the device is turned to different orientations (rotated 90 degrees or other orientations), the spatially relative adjectives used will also be interpreted according to the orientation after the turn. Furthermore, when terms such as "approximately" or "approximately" are used to describe numbers or ranges of numbers, the numerical values ​​intended to be covered are those that include the described numbers within a reasonable range, such as within + / - 10% of the described number, or other numerical values ​​understood by one of ordinary skill in the art to which this disclosure pertains. For example, the term "approximately 5 nanometers" covers a size range from 4.5 nanometers to 5.5 nanometers.

[0087] This disclosure generally relates to integrated circuits and semiconductor devices, and methods of manufacturing them. More specifically, this disclosure relates to vertically-stacked and horizontally-oriented multichannel transistors, such as nanowire transistors and nanosheet transistors. These types of transistors are sometimes referred to as fully-wound gate (GAA) transistors, multi-bridge channel (MBC) transistors, or some other names. In this disclosure, they are broadly referred to as nanosheet-based transistors (or transistors, or simply devices). A nanosheet-based device includes multiple channel layers stacked one on top of the other and engaged by gate structures. The channel layers of a nanosheet-based device can include any suitable shape and / or configuration. For example, the channel layers can be one of many different shapes, such as wires (or nanowires), sheets (or nanosheets), rods (or nanorods), and / or other suitable shapes. In other words, the term "nanosheet-based device" broadly encompasses devices having channel layers with nanowires, nanorods, and any other suitable shapes. Furthermore, the channel layers of a nanosheet-based device can be engaged with a single, continuous gate structure or multiple gate structures. A channel layer connects a pair of source / drain components, allowing charge carriers to flow from the source region to the drain region through the channel layer during operation (e.g., when the transistor is turned on). Furthermore, an internal spacer is formed between the source / drain components and the gate structure, allowing the source / drain components to be shielded to prevent operation on the gate structure. The nanosheet-based device of this disclosure can be a complementary metal-oxide-semiconductor (CMOS) device, a p-type MOS (PMOS) device, or an n-type MOS (NMOS) device. Other examples of semiconductor devices that may benefit from aspects of this disclosure will be recognized by those skilled in the art. Furthermore, while this disclosure uses a nanosheet-based device as an example, other examples of semiconductor devices that may benefit from aspects of this disclosure will be recognized by those skilled in the art. For example, other types of metal-oxide-semiconductor field-effect transistors (MOSFETs), such as planar MOSFETs, FinFETs, and other multi-gate FETs, may benefit from aspects of this disclosure.

[0088] In typical nanosheet-based devices, source / drain components grow from and cover the entire sidewall surface of the channel layer. This ensures full utilization of the channel layer's conductivity during operation. Furthermore, the growth of the source / drain components typically extends laterally beyond the edge of the channel layer (e.g., along the longitudinal direction of the gate structure), causing the source / drain components to span a width greater than the channel layer itself. This larger lateral width does not improve the transistor's charge conductivity but does provide a larger landing platform for subsequently formed contact components, which helps reduce the contact resistance between them. However, the increased lateral dimension of the source / drain components relative to the channel layer also contributes to increased fringe capacitance of the device, offsetting the described benefits and sometimes even negatively impacting device performance. Therefore, this disclosure provides a method for forming source / drain components with a narrower bottom and a wider top, such that the contact resistance between the source / drain components and the contact components is minimized, while the fringe capacitance is not unnecessarily increased.

[0089] Various aspects of this disclosure will now be described in more detail with reference to the accompanying drawings. Figures 1A-10A According to some embodiments of the methods disclosed herein, three-dimensional (3D) views of workpiece 200 at different manufacturing stages are illustrated. Figures 1B-10B as well as Figure 11 Draw a cross-sectional view of workpiece 200 (e.g., along the corresponding...) Figures 1A-10A (XZ section of line B-B'). According to various aspects of this disclosure Figures 3C-10C , Figure 3D-Figure 10D , Figures 7E-10E , Figures 7F-10F as well as Figures 7G-10G The example workpiece 200 disclosed herein is illustrated along... Figures 3A-10A Partial cross-sectional views of lines C-C', D-D', E-E', F-F', and G-G'. According to one or more aspects of this disclosure, Figure 12 A flowchart illustrating a method 100 for forming a semiconductor device 200 from a workpiece 200 is provided. Method 100 is merely an example and is not intended to limit this disclosure to the content explicitly described in method 100. For other embodiments of the method, additional steps may be provided before, during, and after method 100, and some described steps may be replaced, eliminated, or moved. For simplicity, this disclosure does not describe all steps in detail. Similarly, for simplicity and clarity, Figures 1A-10A , Figures 1B-10B , Figures 3C-10C , Figure 3D-Figure 10D , Figures 7E-10E , Figures 7F-10F , Figures 7G-10G as well as Figure 11 It is abbreviated and may not include all components.

[0090] Reference Figure 1A , Figure 1B In step 102 of method 100, a workpiece 200 is received (or provided). The workpiece 200 includes a substrate 202 and a stack 204 disposed on the substrate 202. In some embodiments, the substrate 202 may be a silicon (Si) substrate. In some other embodiments, the substrate 202 may include other semiconductors, such as germanium (Ge), silicon germanium (SiGe), or III-V semiconductor materials. Example III-V semiconductor materials may include gallium arsenide (GaAs), indium phosphide (InP), gallium phosphide (GaP), gallium nitride (GaN), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium phosphide (GaInP), and indium gallium arsenide (InGaAs). The substrate 202 may also include an insulating layer, such as a silicon oxide layer, to have a silicon-on-insulator (SOI) structure or a germanium-on-insulator (GOI) structure. In some embodiments, substrate 202 may include one or more well regions, such as n-type well regions doped with n-type dopants (i.e., phosphorus (P) or arsenic (As)) or p-type well regions doped with p-type dopants (i.e., boron (B)) to form different types of devices. The doping of n-type wells and p-type wells can be formed using ion implantation or thermal diffusion.

[0091] The stack of semiconductor layers 204 may include multiple channel layers 208 interleaved (or interweaved) with multiple sacrificial layers 206. The channel layers 208 and the sacrificial layers 206 may have different semiconductor compositions. In some embodiments, the channel layers 208 are formed of silicon (Si), such as crystalline silicon, and the sacrificial layers 206 are formed of silicon germanium (SiGe). In these embodiments, the additional germanium content in the sacrificial layers 206 allows for selective removal or etching of the sacrificial layers 206 with minimal damage to the channel layers 208. In some embodiments, the sacrificial layers 206 and the channel layers 208 may be deposited using epitaxial processes. The stack of semiconductor layers 204 may be epitaxially deposited using chemical vapor deposition (CVD) techniques (e.g., vapor-phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy (MBE), and / or other suitable processes. Sacrificial layer 206 and channel layer 208 are deposited alternately one after the other to form stack 204. For patterning purposes, workpiece 200 may also include a hard mask layer 209 above stack 204. Hard mask layer 209 may be a single layer or multiple layers. In some embodiments, hard mask layer 209 is formed of silicon nitride. As described below, hard mask layer 209 also protects the channel layer in subsequent etching operations. In some embodiments, an additional pad oxide layer 207 may optionally be formed between hard mask layer 209 and the topmost channel layer 208.

[0092] In some embodiments, each channel layer 208 has a thickness 402 of about 3 nanometers to about 15 nanometers, for example, about 5 nanometers to about 10 nanometers. If the thickness 402 is too small, the migration of charge carriers through the channel layer 208 may become a bottleneck limiting device performance. If the thickness 402 is too large, the gate may not be able to effectively control all portions of the channel layer 208. Each sacrificial layer 206 has a thickness 404 of about 3 nanometers to about 15 nanometers, for example, about 5 nanometers to about 10 nanometers. If the thickness 404 is too small, there may not be enough space to subsequently form all the necessary gate layers between adjacent channel layers 208. If the thickness 404 is too large, the additional process and material costs offset any additional benefits. It should be understood that, as Figure 1A as well as Figure 1BAs shown, three sacrificial layers 206 and four channel layers 208 are alternately and vertically arranged; this configuration is for illustrative purposes only and is not intended to limit the scope of this disclosure. The number of film layers depends on the desired number of channels in the semiconductor device. In some embodiments, the number of channel layers 208 is between 2 and 10. The distance between the top surface of the topmost channel layer 208 and the bottom surface of the bottommost channel layer 208 (or the top surface of the substrate 202) may also be referred to as the stack height 412. The stack height is determined by the number of channel layers 208, the thickness of the channel layers, the number of sacrificial layers 206, and the thickness of the sacrificial layers. In some embodiments, the stack height 412 can be from about 35 nanometers to about 65 nanometers. If the stack height is too small, for example less than 35 nanometers, the number or thickness of the channel layers 208 formed in the transistor may be insufficient, resulting in unnecessarily limited conduction paths for operating current. If the stack height is too large, for example greater than 65 nanometers, the additional film layers and / or the greater thickness may not be justified in terms of their manufacturing costs and / or the physical space they occupy.

[0093] In some embodiments, the hard mask layer 209 (or together with the pad oxide layer 207, if present) has a thickness 414. As described later, the thickness 414 determines the height of the subsequently formed high-k hard mask layer, which forms part of the cut-metal-gate dielectric component. In some embodiments, the thickness 414 can be from about 10 nanometers to about 40 nanometers, for example, from about 15 nanometers to about 30 nanometers. If the thickness 414 is too small, for example less than about 10 nanometers, the height of the subsequently formed cut-metal-gate dielectric component may be insufficient to cut through the height of the gate structure. Conversely, if the thickness 414 is too large, for example greater than about 40 nanometers, the additional height does not provide substantial benefit but instead occupies valuable device space.

[0094] Continue to refer to Figure 1A as well as Figure 1BThe stack of semiconductor layers 204 and the substrate 202 immediately beneath them have been patterned using patterning operations to form fin structures 212 (interchangeably referred to as active regions 212 or finned active regions 212). Each fin structure 212 includes a base 212B formed from a portion of the substrate 202 and a stacked portion 212S formed from the stack 204. The stacked portion 212S is disposed above the base 212B. The fin structures 212 extend longitudinally along the Y direction and perpendicularly from the substrate 202 along the Z direction. Suitable processes, including dual patterning or multiple patterning processes, can be used to pattern the fin structures 212. Generally, dual patterning or multiple patterning processes combine lithography with self-alignment processes to create, for example, patterns with a smaller pitch than those obtained using a single, direct lithography process. For example, in one embodiment, a material layer is formed over a substrate and patterned using a lithography process. Spacers are formed alongside the patterned material layer using a self-alignment process. After removing the material layer, the remaining spacers or mandrel can be used to pattern the fin structure 212 by etching the stack 204 and the substrate 202. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. In some embodiments, an additional hard masking layer (e.g., an oxide hard masking layer) can be formed on top of the hard masking layer 209 before patterning the fin structure (e.g., before forming the mandrel). Those additional hard masking layers are removed after the patterning process is complete. In some embodiments, the fin structure 212 is configured to have a width 408 along the X direction. In some embodiments, the width 408 can be approximately 20 nanometers to approximately 40 nanometers.

[0095] The workpiece 200 also includes an isolation member 214 formed between adjacent fin structures 212. The isolation member 214 can be formed by first depositing a precursor layer on the workpiece 200 and filling the spaces (or trenches) between the fin structures 212, and then etching to at least expose the top of the fin structures 212. The dielectric material may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-dielectric-constant dielectrics, combinations thereof, and / or other suitable materials. In various examples, CVD processes, subatmospheric CVD (SACVD) processes, flowable CVD processes, atomic layer deposition (ALD) processes, spin coating, and / or other suitable processes can be used to deposit the dielectric material. In some embodiments, a liner may be formed to wrap around the fin structures 212 prior to forming the isolation member 214. Thus, as Figure 1A as well as Figure 1B As shown, the stacked portion 212S of the fin structure 212 rises above the isolation member 214, while the base 212B is surrounded by the isolation member 214. In some embodiments, the stacked portion 212S has a height of about 45 nanometers to about 60 nanometers. If the height is too small, for example less than about 45 nanometers, the current through the channel layer may be limited; while if the height is too large, for example greater than about 60 nanometers, the additional chip footprint may not justify any performance improvement.

[0096] refer to Figure 2A as well as Figure 2B Method 100 includes step 104, which forms a cladding layer 216 over the fin structure 212. In some embodiments, the cladding layer 216 may have a composition similar to but different from that of the sacrificial layer 206. In one example, the cladding layer 216 may be formed of silicon germanium (SiGe), and the sacrificial layer 206 may also be formed of SiGe. This shared composition allows for efficient selective removal of both the sacrificial layer 206 and the cladding layer 216 in subsequent processes (e.g., the gate replacement process described below) without negatively impacting the channel layer 208 (e.g., formed of Si). However, the cladding layer 216 is also configured to achieve etch selectivity from the sacrificial layer 206 under different etch conditions (e.g., the dielectric replacement process described below). For example, in some embodiments, the cladding layer 216 is formed of amorphous SiGe, while the sacrificial layer 206 is formed of crystalline SiGe. As another example, the percentage of Ge atoms in the cladding layer 216 may differ from the percentage of Ge atoms in the sacrificial layer 206. For example, the cladding layer 216 may include about 15% to about 25% of Ge atoms; while the sacrificial layer 206 may include about 20% to about 30% of Ge atoms. In this case, the cladding layer 216 may include less than about 22.5% of Ge atoms; while the sacrificial layer 206 may include more than about 22.5% of Ge atoms. In some embodiments, the cladding layer 216 may be grown compliantly and epitaxially using vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE). In some alternative embodiments, the cladding layer 216 may be deposited using CVD, ALD, other suitable deposition methods, or combinations thereof. Figure 2A as well as Figure 2BAs shown, an overlay layer 216 is selectively disposed on the sidewalls of the fin structure 212. The overlay layer 216 has a thickness 406. In some embodiments, the thickness 406 is from about 2 nanometers to about 20 nanometers, for example from about 5 nanometers to about 15 nanometers. As described below, the thickness 406 determines the width of the trenches subsequently formed, in which dielectric material is deposited. If the thickness 406 is too small, completely filling the subsequently formed trenches may be challenging. If the thickness is too large, the additional benefits may not justify the required chip footprint.

[0097] refer to Figure 3A as well as Figure 3BMethod 100 includes step 106, which forms a dielectric component 218 (or dielectric barrier 218) between adjacent fin structures 212. In some embodiments, the dielectric component 218 separates adjacent fin structures 212 and, in some embodiments, defines the length of the subsequently formed gate structure. The dielectric component 218 is sometimes implemented in a diced metal gate (CMG) process. The dielectric component 218 may include multiple film layers. For example, in the depicted embodiment, a filler layer 220 is deposited on the workpiece 200. In some embodiments, the composition of the filler layer 220 may be similar to that of the isolation component 214. In some embodiments, the filler layer 220 may be deposited using CVD, SACVD, FCVD, ALD, PVD, spin coating, and / or other suitable processes. The workpiece 200 is then planarized. In some embodiments, the workpiece 200 is planarized using a CMP process until the top surface of the hard mask layer 209 is exposed. In some embodiments, another layer 221 is compliantly formed prior to the deposition of the fill layer 220, interposing it between the fill layer 220 and the overlay layer 216, and between the fill layer 220 and the isolation member 214. Furthermore, in some embodiments, the fill layer 220 is etched so that its top surface extends below the top surface of the hard mask layer 209. In some embodiments, the top surface of the etched fill layer 220 is approximately 4 nanometers to approximately 45 nanometers lower than the top surface of the topmost channel layer 208. Subsequently, a dielectric layer 222 is formed on the etched fill layer 220, the top surface of the hard mask layer 209, and the top surface of the overlay layer 216. The dielectric layer 222 may be formed of a high-dielectric-constant dielectric material and may be interchangeably referred to as a high-dielectric-constant dielectric layer 222 or a high-dielectric-constant hard mask layer 222. As used and described in this disclosure, high-dielectric-constant dielectric materials include dielectric materials having a high dielectric constant, for example, a dielectric constant greater than that of thermally oxidized silicon (~3.9). Dielectric layer 222 may include hafnium oxide. Alternatively, dielectric layer 222 may include other high-dielectric-constant dielectrics, such as TiO2, HfZrO, Ta2O5, HfSiO4, ZrO2, ZrSiO2, La2O3, Al2O3, ZrO, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfLaO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO3 (BST), SiN, SiON, combinations thereof, or other suitable materials. In some embodiments, a CMP process is performed to remove excess material and expose the top surface of the hard mask layer 209. In this process stage, the etched filling layer 220, film layer 221, and dielectric layer 222 together form the dielectric component 218, which isolates the fin-like structures 212 from each other. Figure 3BAs shown, the sidewall surfaces of adjacent dielectric components 218 are spaced apart by a distance 410. The distance 410 is equal to the sum of the width 408 and twice the thickness 406 (or interchangeably referred to as the width 406). As described in more detail below, the distance 410 determines the width of the top of the subsequently formed source / drain components, and is therefore interchangeably referred to as the width 410.

[0098] Continue to refer to Figure 3A as well as Figure 3B Method 100 includes step 108, which forms a gate stack 230 on the fin structure 212. In some embodiments, the gate stack 230 extends perpendicular to the longitudinal direction of the fin structure 212. For example, in the depicted embodiment, the gate stack 230 extends along the X direction. In some embodiments, a gate replacement process (or post-gate process) is employed, wherein the gate stack 230 serves as a placeholder for a subsequently formed functional gate structure (or metal gate). Therefore, the gate stack 230 may alternatively be referred to as a dummy gate stack 230. Other processes and configurations may be included. The gate stack 230 is formed on (and in some embodiments in direct contact with) the top surface of the dielectric layer 222, the top surface of the hard mask layer 209, and in direct contact with the top surface of the overlay layer 216. Therefore, as Figure 3D As shown, a portion of the cladding layer 216 is buried beneath the gate stack 230. Meanwhile, as... Figure 3C As shown, a portion of the cladding layer 216 is exposed in the region between adjacent gate stacks 230. Each gate stack 230 includes a gate electrode (or a dummy gate electrode). In some embodiments, the gate stack 230 may further include other film layers, such as a gate dielectric layer, an interface layer, other suitable film layers, or combinations thereof. The film layers of the gate stack 230 can be formed by any suitable method, such as CVD. In some embodiments, a gate-top hard mask (not shown) is deposited on a material layer for the gate electrode, which facilitates the patterning of the gate electrode. The gate-top hard mask may be multilayered and includes a silicon nitride mask layer and a silicon oxide mask layer above the silicon nitride mask layer. The material layer for the gate electrode is then patterned using a lithography process to form the gate electrode. In some embodiments, the gate electrode may include polysilicon. In some embodiments, an oxide layer is formed interposed between the top surface of the topmost channel layer 208 and the gate stack 230.

[0099] refer to Figures 4A-4D Method 100 includes Figure 12Step 110 involves removing the cladding layer 216 between the dielectric component 218 and the fin structure 212 in a selective etching operation. In some embodiments, the selective etching operation is configured to remove the cladding layer 216 not covered by the gate stack 230 entirely without etching the film layer 221, the channel layer 208, or the sacrificial layer 206. Thus, a trench 316 is formed by partially removing the cladding layer 216. The trench 316 has dimensions similar to the cladding layer 216. For example, the trench 316 may have a width 406 of about 5 nanometers to about 15 nanometers. The sidewall surfaces of the film layer 221, the channel layer 208, and the sacrificial layer 206 are exposed in the trench 316. Meanwhile, the portion of the cladding layer 216 covering the gate stack 230 remains intact, such as... Figure 4D As shown.

[0100] refer to Figures 5A-5D as well as Figure 12 In step 112, dielectric material is deposited into trench 316 to substantially fill trench 316, thereby forming dielectric component 1216 (also referred to as source / drain spacer). Therefore, dielectric component 1216 has a width 406. Furthermore, because dielectric components 1216 are formed at both ends of fin structure 212, the sidewall surfaces of adjacent dielectric components 1216 are spaced apart by a width 408 (alternately and interchangeably referred to as distance 408). As described below, in some embodiments, distance 408 defines the dimension of the lower portion of the subsequently formed source / drain component. The dielectric material can be selected based at least on its etch resistance to the etch conditions subsequently used. For example, in some embodiments, the dielectric material can serve as a spacer between the gate structure and the epitaxial source / drain component. For example, the dielectric material can be configured to resist etch conditions employed in source / drain trench formation, channel release (or wafer formation), and contact trench etching operations. Therefore, the dielectric material protects the subsequently formed source / drain components and prevents gate-to-source / drain short circuits or leakage current. In some embodiments, the dielectric material includes a low dielectric constant dielectric material. For example, the dielectric material may include silicon carbonitride (SiCN), silicon oxycarbonitride (SiCON), silicon carbide (SiC), other suitable dielectric materials, or combinations thereof. The deposition of the dielectric material can be performed using any suitable deposition technique, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), other suitable deposition techniques, or combinations thereof. In some embodiments, the dielectric material is initially formed above the top surface of dielectric layer 222, above the top surface of hard mask layer 209, and on the sidewall surfaces of gate stack 230. Subsequently, an etch-back operation is performed to remove excess dielectric material and expose the top surface of dielectric layer 222 and the sidewall surfaces of gate stack 230. Therefore, as Figure 5BAs shown, the remaining portion of the dielectric material forms dielectric components 1216, with their top surfaces exposed. Each dielectric component 1216 may have a height 416, measured from the top surface of the substrate 202 (and the top surface of the insulating component 214) to the top surface of the dielectric component 1216. In some embodiments, a CMP operation gives the dielectric component 1216 and the hard mask layer 209 concaved top surfaces. In these embodiments, height 416 refers to the average height of the dielectric component 1216 across its width dimension along the X direction. In the depicted embodiment, the top surface of the dielectric component 1216 extends below the top surface of the dielectric component 218 but above the top surface of the fill layer 220. In some embodiments, an etching operation is performed at this process stage to etch the dielectric component 1216. However, due to the constraints of adjacent components, regulating and tuning the dimensions of the dielectric component 1216 can be challenging. In the depicted embodiment, the height of the dielectric component 1216 is adjusted at a later process stage, as described in more detail below.

[0101] During the etch-back operation, the hard mask layer 209 can be partially removed. For example, after the etch-back operation, the top surface of the hard mask layer 209 can become recessed. The presence of the hard mask layer 209 protects the underlying channel layer 208 from damage. After the etch-back operation is completed, refer to... Figures 6A-6DThe exposed portion of the hard mask layer 209 is selectively etched to form trench 219. For example, a wet etching process is used to remove the hard mask layer 209 (and the oxide liner 207, if present) with minimal impact on the underlying channel layer 208. In some embodiments, the etching operation may be performed as dry etching, wet etching, or a combination thereof. In some embodiments, the etching operation is configured to form a substantially right angle (approximately 90°) between the sidewalls of the gate stack 230 and the top surface of the channel layer 208. This reduces the formation of undesirable dielectric residues after subsequent spacer deposition. Meanwhile, the hard mask layer 209 covering the gate stack 230 is largely preserved. Trench 219 is defined by the sidewall surfaces of the dielectric component 1216 along the X direction and the planes along the sidewall surfaces of the gate stack 230 along the Y direction. At this fabrication stage, the top surface of the channel layer 208 is exposed in trench 219. Furthermore, gate spacers 234 are formed along the sidewalls of the gate stack 230. Gate spacer 234 may include one or more gate spacer layers. Gate spacer 234 may include a dielectric material, such as a dielectric material that allows selective removal of gate stack 230 without affecting gate spacer 234. Suitable dielectric materials may include silicon nitride, silicon carbonitride, silicon carbonitride, silicon oxide, silicon carbonitride, silicon carbide, silicon oxynitride, and / or combinations thereof. Gate spacer 234 may be deposited compliantly over workpiece 200 using CVD, subatmospheric CVD (SACVD), ALD, other suitable methods, or combinations thereof. For example, gate spacer 234 is formed on the top surface and sidewall surfaces of gate stack 230. In the depicted embodiment, gate spacer 234 extends into trench 219 and covers the sidewall surfaces of the remaining portion of hard mask layer 209, and is further formed on and in direct contact with the top surface of topmost channel layer 208. Furthermore, gate spacers 234 are formed on and in direct contact with the top surface of the dielectric component 1216, and on and in direct contact with the top surface of the dielectric layer 222. The gate stack 230 and the gate spacers 234 together form the gate structure 232.

[0102] refer to Figures 7A-7G as well as Figure 12 In step 114, the region of the fin structure 212 below the gate structure 232 can be referred to as channel region 212C. Each channel region 212C in the fin structure 212 is horizontally sandwiched between two source / drain regions 212SD, and source / drain components are subsequently formed in the source / drain regions 212SD. In this process stage, the source / drain regions 212SD are etched to form source / drain trenches 236. Using the gate structure 232 as an etching mask, the workpiece 200 isotropically etched to form source / drain trenches 236 in the source / drain regions 212SD. Figure 7BIn some embodiments shown, the operation of step 114 can substantially remove the stacked portion 212S of the fin structure 212 in the source / drain region 212SD, and the source / drain trench 236 can extend into the base 212B, the base of which is formed by the substrate 202 (comparative). Figure 6B The anisotropic etching at step 114 may include a dry etching process or a suitable etching process. For example, a dry etching process may apply oxygen-containing gas, hydrogen, fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), chlorine-containing gas (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gas (e.g., HBr and / or CHBR3), iodine-containing gas, other suitable gases and / or plasma and / or combinations thereof. The anisotropic etching at step 114 may implement a masking element. In some embodiments, the masking element covers the dielectric components 1216 so that they are retained during the anisotropic etching. Therefore, the height 416 and width 406 of the dielectric components 1216 remain unchanged. Therefore, the source / drain trench 236 is defined by the sidewall surface of the dielectric components 1216 in the X direction and by the plane along the sidewall surface of the gate spacer 234 in the Y direction. For example, the source / drain trench 236 has a width of 408 in the X direction. During this processing stage, the source / drain trench 236 may have a substantially uniform width (width 408) along its respective height in the Z direction. Furthermore, anisotropic etching creates new sidewall surfaces for the fin structure 212. Therefore, the new sidewall surfaces of the channel layer 208 and the sacrificial layer 206 are now exposed in the source / drain trench 236 (see reference). Figure 7F ).

[0103] refer to Figures 8A-8DMethod 100 includes step 116, forming an inner spacer component 242. In some embodiments, the sacrificial layer 206 exposed in the source / drain trench 236 is selectively and partially etched to form an inner spacer notch, while the exposed channel layer 208 remains largely unaffected. In embodiments where the channel layer 208 is primarily formed of crystalline silicon (Si) and the sacrificial layer 206 is primarily formed of silicon germanium (SiGe), the selective and partial etching of the sacrificial layer 206 may include a SiGe oxidation process followed by removal of the SiGe oxide. In the above embodiments, the SiGe oxidation process may include the use of ozone (O3), and the degree of etching of the sacrificial layer 206 is determined by the duration of the oxidation process. In some other embodiments, selective etching may be a selective isotropic etching process (e.g., a selective dry etching process or a selective wet etching process), and the degree of etching of the sacrificial layer 206 is controlled by the duration of the etching process. Selective dry etching processes may include the use of one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. Selective wet etching processes may include hydrofluoric acid (HF) or NH4OH etchants. In some embodiments, selective etching of the sacrificial layer 206 is configured to remove a portion of the sacrificial layer 206 perpendicularly below the gate spacer 234, while a portion of the sacrificial layer 206 below the gate stack 230 is retained. Subsequently, as Figure 8C as well as Figure 8F As shown, an inner spacer material layer is then deposited over workpiece 200 using CVD or ALD, including above and within the inner spacer recess. The inner spacer material may include silicon nitride, silicon carbonitride, silicon carbonitride, silicon oxide, silicon carbonitride, silicon carbide, silicon oxynitride, other suitable materials, or combinations thereof. After depositing the inner spacer material layer, the inner spacer material layer is etched back to form the inner spacer component 242. Therefore, in the depicted embodiment, the inner spacer component 242 is formed between the ends of vertically adjacent channel layers 208 and between horizontally adjacent dielectric components 1216 along the X direction. Furthermore, the inner spacer component 242 is formed vertically below the gate spacer 234. The inner spacer component 242 isolates the remainder of the sacrificial layer 206 from the region forming the source / drain components, ensuring that subsequent etching operations on the sacrificial layer 206 do not affect the integrity of the source / drain components.

[0104] refer to Figures 9A-9G Method 100 includes step 118, which involves etching the dielectric component 1216 along the Z-direction. For example, the height of the dielectric component 1216 varies from height 416 (reference 416). Figure 8BThe height is reduced to 418 (or interchangeably referred to as distance 418). In some embodiments, the etched dielectric component 1216 has a top surface extending below the top surface of the dielectric component 218. For example, the etched dielectric component 1216 may have a top surface extending below the top surface of the fill layer 220. In some embodiments, the width 406 of the dielectric component 1216 is generally retained. The etching of the dielectric component 1216 can be performed using any suitable etching method. In some embodiments, a dry etching method is performed. Furthermore, as described below, the parameters of the etching operation are adjusted according to the desired height 418 to adjust the height of the dielectric component 1216. For example, the duration of the etching operation is adjusted to achieve the desired height 418 and the desired ratio of height 418 to height 416.

[0105] In some embodiments, height 418 may be from about 5 nanometers to about 40 nanometers. For example, the ratio of height 418 to height 416 may be from about 0.05:1 to about 0.7:1. In some embodiments, height 418 may be from about 10 nanometers to about 30 nanometers. For example, the ratio of height 418 to height 416 may be from about 0.1:1 to about 0.5:1. As described below, the etched dielectric features help to adjust the profile of the subsequently formed source / drain features and help to reduce device edge capacitance. If height 418 is too small, for example less than about 5 nanometers, or if the ratio is too small, for example less than about 0.05:1, the benefit of reducing capacitance may be limited; if height 418 is too large, for example greater than about 40 nanometers, or if the ratio is too large, for example greater than about 0.7:1, the landing platform of the contact features subsequently formed on the source / drain features may be reduced and result in increased contact resistance. Simultaneously, because the top of the dielectric component 1216 is removed, the sidewall surfaces of the dielectric component 218 are exposed in the source / drain trench 236. As described above, the sidewall surfaces of adjacent dielectric components 218 are spaced apart by a distance 410. The distance 410 determines the width of the top of the source / drain component subsequently formed in the source / drain trench 236, and is therefore interchangeably referred to as the width 410. Thus, each of the source / drain trenches 236 has a lower portion 236A and a top portion 236B, the lower portion 236A having a width 408 in the X direction, and the upper portion 236B having a width 410 in the X direction. In some embodiments, the ratio of width 410 to width 408 is from about 1.5:1 to about 2:1. If the ratio is too small, for example less than about 1.5:1, any reduction in capacitance resulting from the formation of the dielectric component 1216 may be limited. Conversely, if the ratio is too large, for example greater than about 2:1, the additional benefits gained may not be sufficient to offset the additional process costs. The distance between the top surface of the etched dielectric component 1216 and the top surface of the dielectric layer 222 is called the distance 420. The distance 420 is slightly smaller than the distance 416 (e.g., about 1% to about 20% smaller).

[0106] Alternatively, refer to Figure 9B' In some embodiments, the dielectric component 1216 is not only vertically etched but also laterally etched, such that the width of the remaining portion of the dielectric component 1216 is from a width of 406 (reference). Figure 8B The width is reduced to 426. In such an embodiment, the width of the lower portion 236A of the source / drain trench 236 is increased to a width of 428, while the width of the higher portion 236B of the source / drain trench 236 remains at a width of 410. In some embodiments, the lateral etching operation adjusts the lateral width of the subsequently formed source / drain components to achieve the design dimensions along the X direction. For example, this allows for fine-tuning of the profile of the subsequently formed source / drain components. As described below, in some embodiments, a larger width 428 helps ensure that the entire sidewall surface of the channel layer 208 is covered by the source / drain components, so that the full capacity of the channel layer 208 is utilized. In some embodiments, the ratio of width 410 to width 428 is from about 1.7:1 to about 4:1.

[0107] Therefore, this disclosure provides a source / drain trench 236 with a stepped sidewall profile in an XZ section (e.g., perpendicular to the direction in which the fin structure 212 extends), such that the source / drain trench 236 has a wider opening at the top than at the bottom. This configuration allows for minimizing the contact resistance between the subsequently formed source / drain components and the contact components above, as well as minimizing the capacitance at the bottom of the source / drain components. This disclosure also covers other methods for forming a similar stepped profile for the source / drain trench 236 (and the subsequently formed source / drain components). For example, Figure 9B "Another embodiment is shown in which the top of the dielectric component 1216 is not removed, but is laterally etched to a reduced width (e.g., width 429). Meanwhile, the bottom of the dielectric component 1216 is not etched, allowing it to maintain a width of 408. In some embodiments, the ratio of width 429 to width 408 is from about 1.2:1 to about 1.7:1. In other embodiments, both the top and bottom of the dielectric component 1216 may be laterally etched, albeit to varying degrees, to form a stepped profile with similar size proportions. The following disclosure is by..." Figure 9B This can be started with one embodiment, however similar operations can be started with other similar embodiments.

[0108] refer to Figures 10A-10GMethod 100 includes step 120, wherein source / drain components 245 are formed in a source / drain trench 236 and substantially fill the majority of the source / drain trench 236. In some embodiments, the source / drain components 245 are selectively and epitaxially formed on the exposed sidewall surfaces of the channel layers 208 and on the exposed top surface of the substrate 202 in the source / drain trench 236. Furthermore, the growth (or “overgrowth”) of the source / drain components 245 by the respective channel layers 208 and by the substrate 202 eventually merges on the remaining portion of the sidewall surfaces of the source / drain trench 236, for example, over the sidewall surfaces of the dielectric components 1216 and 218. As described above, the source / drain trench 236 includes a lower portion 236A having a smaller width (width 408) along the X direction and a top portion 236B having a larger width (width 410) along the X direction. Therefore, each source / drain component 245 includes a lower portion 245A extending between the two etched dielectric components 1216 and a top portion 245B above the lower portion 245A and above the top surface of the etched dielectric components 1216. Furthermore, the top portion 245B extends between and directly contacts the sidewall surfaces of the dielectric component 218. In the depicted embodiment, the lower portion 245A has a height 418 and a width 428 (see reference). Figure 10B In the depicted embodiment, source / drain trench portions 236A and 236B each have generally straight sidewalls. Therefore, the width of the lower portion 245A of the source / drain component 245 and the width of the top portion 245B of the source / drain component 245 are generally uniform. The width of the lower portion 245A along the X direction can be approximately similar to (or matched with) the length of the channel layer 208 along the X direction. Therefore, the entire conductive capacitance of the channel layer 208 is fully utilized without forming an excessively large lower portion 245A that tends to result in higher capacitance. Meanwhile, the width 410 of the top portion 245B is greater than the width of the lower portion 245A, such that the top surface of the top portion 245B has a larger surface area for better contact with subsequently formed contact components. In the depicted embodiment, the difference between width 410 and width 408 is twice the thickness (or width 406) of the dielectric component 1216.

[0109] Furthermore, in the depicted embodiment, the top 245B has a height 422. In other words, the top (or top 245B) of the source / drain component 245 extends at a distance 422 above the top surface of the dielectric component 1216. In some embodiments, the distance 422 can be from approximately 5 nanometers to approximately 40 nanometers. The distance 422 (or height 422) is less than the distance 420. Therefore, the source / drain component 245 has a height 424, which is equal to the sum of the distances 418 and 422. In some embodiments, the ratio of distance 418 to distance 422 is from approximately 0.1:1 to approximately 10:1, for example, from approximately 0.5:1 to approximately 2:1. In other words, the ratio of height 424 to height 418 is from approximately 1.1:0.1 to approximately 11:10, for example, from approximately 1.5:0.5 to approximately 3:2. If the ratio is too small, the effect of reducing capacitance may be limited; if the ratio is too large, the landing platform for subsequent contact members formed on the source / drain components may be reduced, leading to increased resistance. In some embodiments, the top 245B completely covers and directly contacts the top surface of the dielectric component 1216. In some embodiments, the growth of the source / drain component 245 is configured to leave an air gap 270 between the top surface of the dielectric component 1216 and the top 245B of the source / drain component 245. In some embodiments, the air gap 270 helps to reduce the capacitance of the device.

[0110] The source / drain components 245 can be formed using epitaxial processes, such as vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. The source / drain components 245 can be n-type or p-type. When the source / drain components 245 are n-type, they can include silicon (Si) and may be doped with n-type dopants, such as phosphorus (P) or arsenic (As). When the source / drain components 245 are p-type, they can include silicon germanium (SiGe) or germanium (Ge) and may be doped with p-type dopants, such as boron (B) or gallium (Ga). In some embodiments, the source / drain components 245 may each have multiple film layers.

[0111] refer to Figure 11Method 100 includes step 122, which involves forming a contact etch stop layer (CESL) 243 and an interlayer dielectric (ILD) layer 244 over a workpiece 200. In the example process, the CESL 243 is first compliantly deposited on the workpiece 200, followed by a blanketky deposition of the ILD layer 244 on the CESL 243. The CESL 243 may comprise silicon nitride, silicon oxide, silicon oxynitride, and / or other materials known in the art. The CESL 243 may be deposited using ALD, plasma-enhanced CVD (PECVD) processes, and / or other suitable deposition or oxidation processes. In some embodiments, the ILD layer 244 may include materials such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxides such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphoric silicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials. The ILD layer 244 may be deposited by spin coating, FCVD processes, or other suitable deposition techniques. In some embodiments, after the formation of the ILD layer 244, the workpiece 200 may be annealed to improve the integrity of the ILD layer 244. To remove excess material and expose the top surface of the gate electrode, a planarization process (e.g., chemical mechanical polishing (CMP)) may be performed on the workpiece 200.

[0112] In some embodiments, method 100 performs a gate replacement process that replaces the gate stack 230 (see reference) with a functional gate structure. Figure 12Step 124). For example, a gate replacement process is described in U.S. Patent Application No. 16 / 657,606, filed October 18, 2019, the entire contents of which are incorporated herein by reference. For example, the method at step 122 includes removing the gate stack 230 to form a gate trench. The remaining portion of the sacrificial layer 206 between the channel layers 208 in the channel region 212C is selectively removed from the sidewalls exposed in the gate trench. In addition, the remaining portion of the overlay layer 216 beneath the gate stack 230 is also removed. This process releases the channel layers 208 to form channel members. The channel members are stacked vertically along the Z-direction. The selective removal of the sacrificial layer 206 can be achieved by selective dry etching, selective wet etching, or other selective etching processes. In some embodiments, the selective wet etching process includes APM etching (e.g., an ammonium hydroxide-hydrogen peroxide-water mixture). In some alternative embodiments, selective removal includes SiGe oxidation followed by removal of the SiGe oxide. For example, oxidation can be provided by ozone cleaning, followed by removal of the SiGe oxide by an etchant such as NH4OH. An interface layer and a gate dielectric layer are deposited in the gate trench to surround each channel member. In some embodiments, the interface layer comprises silicon oxide and may be formed in a pre-cleaning process. Example pre-cleaning processes may include using RCA SC-1 (ammonia, hydrogen peroxide, and water) and / or RCA SC-2 (hydrochloric acid, hydrogen peroxide, and water). The pre-cleaning process oxidizes the exposed surfaces of the channel members to form the interface layer. The gate dielectric layer is then deposited on the interface layer using ALD, CVD, and / or other suitable methods. The gate dielectric layer may be formed of a high dielectric constant dielectric material. A gate electrode layer is deposited in the gate trench. The gate electrode layer may be a multilayer structure comprising at least one work function layer and a metal filling layer. For example, at least one work function layer may comprise titanium nitride (TiN), aluminum titanium (TiAl), aluminum titanium nitride (TiAlN), tantalum nitride (TaN), aluminum tantalum (TaAl), aluminum tantalum nitride (TaAlN), aluminum tantalum carbide (TaAlC), tantalum carbonitride (TaCN), or tantalum carbide (TaC). The metal filler layer may include aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), silicon tantalum nitride (TaSiN), copper (Cu), other refractory metals, or other suitable metallic materials or combinations thereof. In various embodiments, the gate electrode layer may be formed using ALD, PVD, CVD, electron beam evaporation, or other suitable processes. Therefore, the functional gate structure is formed to surround the channel member in the channel region 212C and includes an interface layer, a gate dielectric layer, and a gate electrode layer.

[0113] In some embodiments, a planarization process, such as CMP, may be performed to remove excess material to provide a generally flat top surface of the gate structure. A gate cap layer, a self-aligned-contact (SAC) dielectric layer, a silicide layer, and / or source / drain contacts may be formed on workpiece 200. Reference Figure 12 Step 126 and Figure 11 Contact components 280 are formed in the ILD layer 244. In some embodiments, an etching process is used to remove a portion of the ILD layer 244 to form contact trenches. In some embodiments, the etching operation also removes a portion of the CESL 243, exposing the source / drain components 245 in the contact trenches. In the depicted embodiments, the contact component 280 may have a bottom surface having a width 430 along the X direction. In some embodiments, the width 430 is smaller than the width 410. In such embodiments, the full dimensions of the contact component 280 along the X direction are utilized to minimize contact resistance. In some embodiments, the width 430 is from about 15 nanometers to about 30 nanometers. In some embodiments, the ratio of width 430 to width 410 is from about 1.5:1 to about 3:1. Furthermore, in some embodiments, the width 430 is greater than the width 408. In some methods, the width 430 is smaller than the width 408. In such methods, the dimensions of the contact component 280 may not be maximized, and the contact resistance between the contact component 280 and the source / drain components 245 may not be minimized. In some embodiments, the ratio of width 430 to width 408 is approximately 0.5:1 to approximately 1.2:1.

[0114] The above method produces several features in the manufactured device. For example, the device includes a source / drain component 245 having a stepped sidewall profile in the longitudinal direction of the gate stack. The width 410 of the top 245B of the source / drain component 245 along the X direction may be greater than the width 408 of the bottom 245A of the source / drain component 245. The top 245B of the source / drain component is partially disposed on the top surface of the dielectric component 1216. Furthermore, the top 245B of the source / drain component 245 extends between the opposing sidewall surfaces of the dielectric component 218 and directly contacts the sidewall surfaces. However, the bottom 245A of the source / drain component 245 extends between the opposing sidewall surfaces of the dielectric component 1216 and is spaced apart from the dielectric component 218. Furthermore, the bottom 245A and the top 245B each intersect with dielectric components of different materials. The device also includes a contact component 280 having a width 430 along the X direction. In some embodiments, width 430 may be greater than width 408 and less than width 410. In some embodiments, the ratio of width 410 to width 408 of the channel layer may be approximately 1.5:1 to approximately 2:1. Source / drain components 245 are connected via a stack of channel layers 208. In some embodiments, the topmost channel layer 208 is connected to the top 245B. In some embodiments, the bottommost channel layer is connected to the lower portion 245A of the source / drain component 245. In other words, the source / drain component 245 has different lateral widths at the top surface height of the topmost channel layer 208 and at the bottom surface height of the bottommost channel layer 208. These device features allow for optimization of device performance. For example, the source / drain component has a larger landing platform for intersecting with contact components to reduce resistance, and the source / drain component has a smaller bottom dimension to reduce edge capacitance. Conversely, in methods that do not implement the components of this disclosure, for example, source / drain components with generally straight profiles and uniform lateral dimensions at their respective heights, optimizing both contact resistance and edge capacitance can be challenging.

[0115] According to some embodiments of the present disclosure, a semiconductor device is provided, comprising: a semiconductor substrate having a substrate surface; a stack of channel layers on the semiconductor substrate, wherein the top surface of the topmost channel layer of the stack extends along a first height relative to the substrate surface, and the bottom surface of the bottommost channel layer of the stack extends along a second height relative to the substrate surface; a gate structure engaging the stack of channel layers and extending along a first direction; and source / drain components on a first sidewall surface of the stack of channel layers and on the substrate, the first sidewall surface extending parallel to the first direction; wherein the source / drain components have a first width along the first direction at the first height and a second width along the first direction at the second height, and wherein the first width is greater than the second width.

[0116] In some embodiments, a first dielectric component is further included on the second sidewall surface of the stacked channel layers, wherein the second sidewall surface extends perpendicular to the first direction, and wherein the first dielectric component has a third width along the first direction, and the third width is substantially equal to half the difference between the first width and the second width.

[0117] In some embodiments, the first dielectric member has a top surface extending along a third height above the surface of the substrate, wherein the third height is greater than the second height and less than the first height.

[0118] In some embodiments, the first dielectric component includes one of silicon carbonitride (SiCN), silicon oxycarbonitride (SiCON), and silicon carbide (SiC).

[0119] In some embodiments, the source / drain component has a first portion above a second portion, the second portion directly contacting the substrate, the first portion having a first width and the second portion having a second width, and wherein the first portion has a third height relative to the substrate surface and the second portion has a fourth height relative to the substrate surface, and wherein the ratio of the third height to the fourth height is from about 1.5:0.5 to about 3:2.

[0120] In some embodiments, a second dielectric component is further included, extending along a second direction perpendicular to the first direction, wherein the top of the source / drain component directly contacts the second dielectric component, and the bottom of the source / drain component is spaced apart from the second dielectric component.

[0121] In some embodiments, the ratio of the first width to the second width is approximately 1.5:1 to approximately 2:1.

[0122] In some embodiments, each of the stacked channel layers has a fourth width along a first direction, and wherein the fourth width is approximately the same as the second width.

[0123] In some embodiments, the source / drain component has a sidewall with a stepped profile, wherein the stepped profile is defined by a first component of a first dielectric material and a second component of a second dielectric material, the second dielectric material being different from the first dielectric material.

[0124] According to other embodiments of this disclosure, a semiconductor device is provided, comprising: a semiconductor substrate; a first dielectric component on the semiconductor substrate and having a first sidewall surface; a second dielectric component on the semiconductor substrate and having a second sidewall surface, the first sidewall surface facing the second sidewall surface; a third dielectric component on the first sidewall surface and having a third sidewall surface; a fourth dielectric component on the second sidewall surface and having a fourth sidewall surface, the third sidewall surface facing the fourth sidewall surface; and a source / drain component above the semiconductor substrate and having a bottom and a top, the bottom extending between the third sidewall surface and the fourth sidewall surface, and the top extending between the first sidewall surface and the second sidewall surface, wherein a first distance between the third sidewall surface and the fourth sidewall surface is less than a second distance between the first sidewall surface and the second sidewall surface, and wherein the first dielectric component and the second dielectric component each include a first dielectric material, and the third dielectric component and the fourth dielectric component each include a second dielectric material, the second dielectric material being different from the first dielectric material.

[0125] In other embodiments, the top of the source / drain component directly contacts the top surface of the third dielectric component and directly contacts the top surface of the fourth dielectric component.

[0126] In other embodiments, the ratio of the first distance to the second distance is approximately 1:1.5 to approximately 1:2.

[0127] In other embodiments, the third and fourth dielectric components each have a first height, the top of the source / drain components has a second height, and the ratio of the first height to the second height is about 1:0.5 to about 1:2.

[0128] According to further embodiments of the present disclosure, a method of forming a semiconductor device is provided, comprising: receiving a semiconductor workpiece having an active region extending above a top surface of a semiconductor substrate; forming a dielectric member on a first opposing sidewall of the active region in a first direction; etching a portion of the active region to form a source / drain trench, the source / drain trench exposing a second opposing sidewall of the active region; etching the dielectric member; and forming a source / drain member in the source / drain trench and on the second opposing sidewall exposed in the active region, the source / drain member being partially formed on the top surface of the dielectric member.

[0129] In some other embodiments, the etched dielectric component includes etching to reduce the height of the dielectric component relative to the top surface of the semiconductor substrate.

[0130] In some other embodiments, the etched dielectric component includes etching a stepped profile to form source / drain trenches.

[0131] In some other embodiments, forming the dielectric component includes: forming a cladding layer on a first opposing sidewall of the active region, the cladding layer having exposed sidewall surfaces; forming a dielectric barrier on the exposed sidewall surfaces of the cladding layer; removing a portion of the cladding layer between the dielectric barrier and the active region, thereby forming a gap therebetween; and depositing dielectric material in the gap.

[0132] In some other embodiments, each active region includes a stack of a first semiconductor layer and a second semiconductor layer over a semiconductor substrate, wherein the first semiconductor layer and the second semiconductor layer have different material compositions and alternate with each other in their respective stacks. The method further includes: replacing a first portion of the second semiconductor layer to form a dielectric spacer between the ends of vertically adjacent first semiconductor layers before etching the dielectric components; removing the remaining portion of the second semiconductor layer to form a gap after forming source / drain components; and forming a metal gate stack in the gap.

[0133] In some other embodiments, the first semiconductor layer comprises crystalline silicon, the second semiconductor layer comprises silicon germanium and has a first atomic percentage of germanium, and the cladding layer comprises silicon germanium and has a second atomic percentage of germanium, wherein the first atomic percentage is different from the second atomic percentage.

[0134] In some other embodiments, the etched dielectric components expose the top of the sidewalls of the dielectric barrier, and the formation of source / drain components includes forming on the exposed top of the sidewalls of the dielectric barrier.

[0135] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand the viewpoints of the embodiments described herein. Those skilled in the art will understand that other processes and structures can be easily designed or modified based on the embodiments described herein to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art will also understand that such equivalent structures do not depart from the spirit and scope of this disclosure, and various changes, substitutions, and replacements can be made without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the appended claims.

Claims

1. A semiconductor device, comprising: A semiconductor substrate having a substrate surface; A stack of multiple channel layers on the semiconductor substrate, wherein a top surface of a topmost channel layer of the stack extends along a first height relative to the surface of the substrate, and a bottom surface of a bottommost channel layer of the stack extends along a second height relative to the surface of the substrate. A gate structure that engages the stack of the channel layers and extends along a first direction; A source / drain component is located on the stacked first sidewall surfaces of the channel layer and on the substrate, the first sidewall surfaces extending parallel to the first direction. The source / drain component has a first width along the first direction at the first height and a second width along the first direction at the second height, wherein the first width is greater than the second width; and A first dielectric component is located on the surface of the plurality of second sidewalls of the stack in the channel layer. The second sidewall surface extends perpendicular to the first direction, and The first dielectric component has a third width along the first direction, and the third width is approximately equal to half the difference between the first width and the second width.

2. The semiconductor device of claim 1, wherein the first dielectric member has a top surface extending along a third height above the surface of the substrate, and The third height is greater than the second height and less than the first height.

3. The semiconductor device of claim 1, wherein the first dielectric component comprises one of silicon carbonitride, silicon oxycarbonitride, and silicon carbide.

4. The semiconductor device of claim 1, wherein the source / drain member has a first portion above a second portion, the second portion directly contacting the substrate, the first portion having the first width and the second portion having the second width, and The first portion has a third height relative to the surface of the substrate, and the second portion has a fourth height relative to the surface of the substrate. The ratio of the third height to the fourth height is between 1.5:0.5 and 3:

2.

5. The semiconductor device of claim 1, further comprising a second dielectric member extending along a second direction perpendicular to the first direction. One top of the source / drain component is in direct contact with the second dielectric component, and one bottom of the source / drain component is separated from the second dielectric component.

6. The semiconductor device of claim 1, wherein the ratio of the first width to the second width is 1.5:1 to 2:

1.

7. The semiconductor device of claim 1, wherein each of the stacked channel layers has a fourth width along the first direction, and wherein the fourth width is the same as the second width.

8. The semiconductor device of claim 1, wherein the source / drain component has a sidewall having a stepped profile, wherein the stepped profile is defined by a first component of a first dielectric material and a second component of a second dielectric material, the second dielectric material being different from the first dielectric material.

9. A semiconductor device, comprising: A semiconductor substrate; A first dielectric component is on the semiconductor substrate and has a first sidewall surface; A second dielectric component is on the semiconductor substrate and has a second sidewall surface, with the first sidewall surface facing the second sidewall surface; A third dielectric component, on the surface of the first sidewall and having a third sidewall surface; A fourth dielectric component is on the second sidewall surface and has a fourth sidewall surface, with the third sidewall surface facing the fourth sidewall surface; as well as A source / drain component is provided above the semiconductor substrate and has a bottom and a top. The bottom extends between the third sidewall surface and the fourth sidewall surface, and the top extends between the first sidewall surface and the second sidewall surface. Wherein a first distance between the third sidewall surface and the fourth sidewall surface is less than a second distance between the first sidewall surface and the second sidewall surface, and The first dielectric component and the second dielectric component each include a first dielectric material, and the third dielectric component and the fourth dielectric component each include a second dielectric material, which is different from the first dielectric material.

10. The semiconductor device of claim 9, wherein the top of the source / drain component directly contacts a top surface of the third dielectric component and directly contacts a top surface of the fourth dielectric component.

11. The semiconductor device of claim 9, wherein the ratio of the first distance to the second distance is from 1:1.5 to 1:

2.

12. The semiconductor device of claim 9, wherein the third dielectric component and the fourth dielectric component each have a first height, the top of the source / drain component has a second height, and wherein the ratio of the first height to the second height is 1:0.5 to 1:

2.

13. A method of forming a semiconductor device, comprising: Receive a semiconductor workpiece having a plurality of active regions extending above a top surface of a semiconductor substrate; In a first direction, a plurality of dielectric components are formed on a plurality of first opposing sidewalls of the active region; Multiple portions of the active region are etched to form multiple source / drain trenches, the source / drain trenches exposing multiple second opposing sidewalls of the active region; The dielectric component is etched. as well as A plurality of source / drain components are formed in the source / drain trench and on the second opposing sidewall exposed in the active region. The source / drain components are partially formed on a plurality of top surfaces of the dielectric component. The etching of the dielectric component includes etching to reduce the height of the dielectric component relative to the top surface of the semiconductor substrate.

14. The method of forming a semiconductor device as claimed in claim 13, wherein etching the dielectric component includes etching to form a stepped profile of the source / drain trench.

15. The method of forming a semiconductor device as claimed in claim 13, wherein forming the dielectric component comprises: A covering layer is formed on the first opposite sidewall of the active region, the covering layer having a plurality of exposed sidewall surfaces; Multiple dielectric barriers are formed on the exposed sidewall surface of the coating layer; A portion of the coating layer between the dielectric barrier and the active region is removed, thereby forming a plurality of gaps therebetween. as well as A dielectric material is deposited in the gap.

16. The method of forming a semiconductor device as claimed in claim 15, wherein the first semiconductor layer comprises crystalline silicon, the second semiconductor layer comprises silicon germanium and has a first atomic percentage of germanium, and the cladding layer comprises silicon germanium and has a second atomic percentage of germanium, and wherein the first atomic percentage is different from the second atomic percentage.

17. The method of forming a semiconductor device as claimed in claim 15, wherein each active region comprises a stack of a plurality of first semiconductor layers and a plurality of second semiconductor layers above the semiconductor substrate, wherein the first semiconductor layers and the second semiconductor layers have different material compositions and alternate with each other in their respective stacks. The method also includes: Before etching the dielectric component, a first portion of the second semiconductor layer is replaced to form a plurality of dielectric spacers between the ends of the vertically adjacent first semiconductor layers; After forming the source / drain components, a remaining portion of the second semiconductor layer is removed to form a plurality of gaps; as well as Multiple metal gate stacks are formed in the gap.

18. The method of forming a semiconductor device as claimed in claim 17, wherein etching the dielectric component exposes a plurality of tops of a plurality of sidewalls of the dielectric barrier, and wherein forming the source / drain component includes forming on the exposed tops of the sidewalls of the dielectric barrier.

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