Semiconductor device and method of forming the same

Abstract

A method of forming a semiconductor device is disclosed, including: removing dummy gate stacks to form first trenches between gate spacers; forming replacement gate stacks in the first trenches; recessing the replacement gate stacks to form second trenches between the gate spacers; selectively depositing a conductive cap in the second trenches; forming a dielectric hardmask in the second trenches and over the conductive cap; and etching the dielectric hardmask using an etching gas to form openings in the dielectric hardmask. The replacement gate stacks are exposed at the openings. The conductive cap is more resistant to the etching gas than the replacement gate stacks. The method further includes forming gate contact plugs over and contacting the conductive cap. Embodiments of the invention also relate to semiconductor devices.

Description

Technical Field

[0001] Embodiments of the present invention relate to semiconductor devices and methods for forming the same. Background Technology

[0002] To achieve faster speeds, lower power consumption, and higher integration, transistors are being manufactured to increasingly smaller sizes. For example, the metal gates of transistors are becoming narrower. The contact area between the metal gate and the gate contact plug above it is also decreasing, resulting in higher contact resistance. Summary of the Invention

[0003] Some embodiments of the present invention provide a method for forming a semiconductor device, comprising: removing a dummy gate stack to form a first trench between first gate spacers; forming a first replacement gate stack in the first trench; recessing the first replacement gate stack to form a second trench between the first gate spacers; selectively depositing a first conductive capping layer in the second trench; forming a dielectric hard mask in the second trench and over the first conductive capping layer; etching the dielectric hard mask using an etching gas to form an opening in the dielectric hard mask, wherein the first replacement gate stack is exposed at the opening; and forming a gate contact plug located over and in contact with the first conductive capping layer.

[0004] Other embodiments of the present invention provide a semiconductor device comprising: a semiconductor region; gate spacers located on the semiconductor region; a gate stack located above the semiconductor region and between the gate spacers, wherein the gate stack comprises a plurality of layers; a conductive capping layer located above and contacting the plurality of layers of the gate stack; a dielectric hard mask located above the conductive capping layer and between the gate spacers; and a gate contact plug penetrating the dielectric hard mask to be positioned on the conductive capping layer.

[0005] Further embodiments of the present invention provide a semiconductor device including: a source region and a drain region; a gate stack located between the source region and the drain region, wherein the gate stack includes a plurality of layers and each of the plurality of layers has a basin shape, the basin shape having a bottom and a sidewall portion located above the bottom and engaging with the bottom; a gate spacer located on opposite sidewalls of the gate stack; and a conductive layer located above the top surface of the sidewall portion of the plurality of layers and contacting the top surface of the sidewall portion of the plurality of layers. Attached Figure Description

[0006] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industrial practice, the various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0007] Figures 1 to 6 , Figure 7A , Figure 7B , Figure 8 , Figure 9A , Figure 9B , Figures 10 to 11 , Figure 12A , Figure 12B , Figure 13A , Figure 13B and Figure 14A Perspective and cross-sectional views are shown of an intermediate stage in forming a transistor having a conductive overlay layer located on a metal gate, according to some embodiments.

[0008] Figure 14B , Figure 14C , Figure 14D and Figure 14E A metal gate with a conductive overlay is shown according to some embodiments.

[0009] Figure 15 A cross-sectional view of a metal gate in a plane parallel to the gate length direction is shown according to some embodiments.

[0010] Figure 16 The diagram illustrates a process flow for forming a transistor having a conductive overlay layer located on a metal gate, according to some embodiments. Detailed Implementation

[0011] The following disclosure provides numerous different embodiments or examples of various components for implementing the invention. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are in direct contact, and may also include embodiments where an additional component may be formed between the first and second components, thereby allowing the first and second components to not be in direct contact. Furthermore, reference numerals and / or characters may be repeated in various instances of the invention. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0012] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," and "upper" may be used to describe the relationship between one element or component and another (or other elements or components) as shown in the figure. In addition to the orientation shown in the figure, spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein can be interpreted accordingly.

[0013] A transistor having a metal gate and a conductive overlay is provided, and a method for forming the same is also provided. According to some embodiments of the invention, an alternative gate stack is formed for the transistor. The alternative gate stack is recessed, and a conductive overlay is formed on the alternative gate stack. The conductive overlay may have a higher conductivity value than at least some layers in the gate stack (such as a work function layer). Low contact resistance is achieved for electrically connecting the gate electrode in the gate stack to the gate contact plug above it. Although a FinFET is used as an example, other types of transistors, such as planar transistors and nanostructure transistors (such as gate all-around (GAA) transistors, nanowire transistors, nanosheet transistors, etc.), are within the scope of this invention. The embodiments discussed herein are intended to provide examples enabling the making or use of the subject matter of the invention, and those skilled in the art will readily understand that modifications can be made while remaining within the intended scope of the different embodiments. Similar reference numerals are used to indicate similar elements throughout the various views and illustrative embodiments. Although method embodiments may be discussed as being performed in a particular order, other method embodiments may be performed in any logical order.

[0014] Figures 1 to 6 , Figure 7A , Figure 7B , Figure 8 , Figure 9A , Figure 9B , Figures 10 to 11 , Figure 12A , Figure 12B , Figure 13A , Figure 13B and Figure 14A Perspective and cross-sectional views are shown of an intermediate stage in the formation of a transistor having a conductive overlay layer located on a metal gate, according to some embodiments. Also... Figure 16 The process flow shown schematically reflects the corresponding process.

[0015] refer to Figure 1A substrate 20 is provided. The substrate 20 may be a semiconductor substrate, such as a bulk semiconductor substrate, a semiconductor-on-insulator (SOI) substrate, etc., which may be doped (e.g., with p-type or n-type dopants) or undoped. The semiconductor substrate 20 may be a portion of wafer 10, such as a silicon wafer. Typically, the SOI substrate is a layer of semiconductor material formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. An insulating layer is provided on the substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, may also be used. In some embodiments, the semiconductor material of the semiconductor substrate 20 may include silicon; germanium; compound semiconductors, including carbon-doped silicon, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, SiP, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0016] Further reference Figure 1 A well region 22 is formed in the substrate 20. In such a case... Figure 16 In the illustrated process flow 200, the corresponding process is shown as process 202. According to some embodiments of the present invention, the well region 22 is a p-type well region formed by implanting a p-type dopant, such as boron or indium, into the substrate 20. According to other embodiments of the present invention, the well region 22 is an n-type well region formed by implanting an n-type dopant, such as phosphorus, arsenic, or antimony, into the substrate 20. The resulting well region 22 can extend to the top surface of the substrate 20. The concentration of the n-type or p-type dopant can be equal to or less than 10. 18 cm -3 Such as in about 10 17 cm -3 With about 10 18 cm -3 Within the range between.

[0017] refer to Figure 2 The isolation region 24 is formed to extend from the top surface of the substrate 20 into the substrate 20. The isolation region 24 is optionally referred to below as a shallow trench isolation (STI) region. Figure 16In the process flow 200 shown, the corresponding process is illustrated as process 204. The portion of substrate 20 between adjacent STI regions 24 is referred to as semiconductor strip 26. To form the STI regions 24, a pad oxide layer 28 and a hard mask layer 30 are formed on the semiconductor substrate 20, and then the pad oxide layer 28 and the hard mask layer 30 are patterned. The pad oxide layer 28 may be a thin film formed of silicon oxide. According to some embodiments of the invention, the pad oxide layer 28 is formed in a thermal oxidation process, wherein the top surface layer of the semiconductor substrate 20 is oxidized. The pad oxide layer 28 acts as an adhesion layer between the semiconductor substrate 20 and the hard mask layer 30. The pad oxide layer 28 may also serve as an etch stop layer for etching the hard mask layer 30. According to some embodiments of the invention, the hard mask layer 30 is formed of silicon nitride, for example, using low-pressure chemical vapor deposition (LPCVD), atomic layer deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), high-density plasma chemical vapor deposition (HDPCVD), etc. A hard mask layer 30 (not shown) is formed, and then a photoresist is patterned. The patterned photoresist is then used as an etching mask to pattern the hard mask layer 30 to form, as shown... Figure 2 The hard mask 30 shown.

[0018] Next, a patterned hard mask layer 30 is used as an etching mask to etch the pad oxide layer 28 and the substrate 20, followed by filling the resulting trenches in the substrate 20 with one or more dielectric materials. A planarization process, such as chemical mechanical polishing (CMP) or mechanical grinding, is performed to remove excess dielectric material, and the remaining portion of one or more dielectric materials is the STI region 24. The STI region 24 may include a pad dielectric (not shown), which may be a thermal oxide formed by thermal oxidation of a surface layer of the substrate 20. The pad dielectric may also be a deposited silicon oxide layer, silicon nitride layer, etc., formed using, for example, atomic layer deposition (ALD), low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), high-density plasma chemical vapor deposition (HDPCVD), or chemical vapor deposition (CVD). The STI region 24 may also include dielectric material located above the pad oxide, wherein the dielectric material may be formed using flowable chemical vapor deposition (FCVD), spin coating, etc. According to some embodiments, the dielectric material located above the pad dielectric may include silicon oxide.

[0019] The top surface of the hard mask 30 and the top surface of the STI region 24 can be substantially flush with each other. Semiconductor strips 26 are located between adjacent STI regions 24. According to some embodiments of the invention, semiconductor strips 26 are portions of the original substrate 20, and therefore the material of semiconductor strips 26 is the same as that of the substrate 20. According to an alternative embodiment of the invention, semiconductor strips 26 are replacement strips formed by etching portions of the substrate 20 between the STI regions 24 to form grooves and performing epitaxy to regrow another semiconductor material in the grooves. Therefore, semiconductor strips 26 are formed of a semiconductor material different from that of the substrate 20. According to some embodiments, semiconductor strips 26 are formed of silicon-germanium, silicon-carbon, or group III-V compound semiconductor materials.

[0020] refer to Figure 3 The STI region 24 is recessed so that the top of the semiconductor strip 26 protrudes above the top surface 24TS of the remaining portion of the STI region 24, forming a protruding fin 36. In such a way... Figure 16 In the process flow 200 shown, the corresponding process is illustrated as process 206. Etching can be performed using a dry etching process, wherein HF, NH3, and C are... x H y F z (x = 1 to 6, y = 0 to 9, and z = 0 to 12), NF3, HBr, CO, CO2, COS, SO2, SF6, BCl3, Cl2, CF4, CH4, CHF3, TiCl x TaCl x WCl x The etching gas may include argon, O2, N2, and H2. According to an alternative embodiment of the invention, a wet etching process is used to create the recesses in the STI region 24. For example, the etching chemical may include diluted HF.

[0021] In the above embodiments, fins can be patterned using any suitable method. For example, fins can be patterned using one or more photolithography processes including dual patterning or multiple patterning processes. Typically, dual patterning or multiple patterning processes combine photolithography with a self-aligned process, thereby allowing the creation of patterns, for example, with a pitch smaller than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers or mandrels can then be used to pattern fins.

[0022] refer to Figure 4 This forms a dummy gate stack 38 extending on the top surface and sidewalls of the (protruding) fin 36. In such a way... Figure 16In the process flow 200 shown, the corresponding process is illustrated as process 208. The dummy gate stack 38 may include a dummy gate dielectric 40 ( Figure 7B The dummy gate electrode 42 is located above the dummy gate dielectric 40. The dummy gate electrode 42 can be formed using, for example, polysilicon, and other materials may also be used. Each dummy gate stack 38 may also include one (or more) hard mask layers 44 above the dummy gate electrode 42. The hard mask layer 44 may be formed of silicon nitride, silicon oxide, silicon carbonitride, or multiple layers thereof. The dummy gate stack 38 may span one or more protruding fins 36 and / or STI regions 24. The dummy gate stack 38 also has a longitudinal direction perpendicular to the longitudinal direction of the protruding fins 36.

[0023] Next, gate spacers 46 are formed on the sidewalls of the dummy gate stack 38. Figure 16 In the process flow 200 shown, the corresponding process is also shown as process 208. According to some embodiments of the present invention, the gate spacer 46 is formed of a dielectric material such as silicon nitride, silicon carbonitride, or silicon oxycarbonitride, and may have a single-layer structure or a multilayer structure including multiple dielectric layers.

[0024] Then an etching process is performed to etch the portion of the protruding fin 36 that is not covered by the dummy gate stack 38 and the gate spacer 46, thereby producing Figure 5 The structure shown. In, as... Figure 16 In the illustrated process flow 200, the corresponding process is shown as process 210. The recess can be anisotropic, and therefore, the portion of fin 36 located directly beneath the dummy gate stack 38 and gate spacer 46 is protected from etching. According to some embodiments, the top surface of the recessed semiconductor strip 26 can be lower than the top surface 24TS of the STI region 24. A groove 50 is formed accordingly. The groove 50 includes a portion located on opposite sides of the dummy gate stack 38 and a portion located between the remaining portion of the protruding fin 36.

[0025] Next, an epitaxial region (source / drain region) 54 is formed by selectively growing (by epitaxy) semiconductor material in the groove 50, thereby generating Figure 6 The structure within. In, for example... Figure 16In the illustrated process flow 200, the corresponding process is shown as process 212. Depending on whether the resulting FinFET is a p-type FinFET or an n-type FinFET, p-type or n-type dopants can be doped in situ as epitaxy progresses. For example, when the resulting FinFET is a p-type FinFET, silicon germanium boron (SiGeB) or silicon boron (SiB) can be grown. Conversely, when the resulting FinFET is an n-type FinFET, silicon phosphide (SiP) or silicon carbon phosphide (SiCP) can be grown. According to an optional embodiment of the invention, the epitaxial region 54 comprises a III-V compound semiconductor, such as GaAs, InP, GaN, InGaAs, InAlAs, GaSb, AlSb, AlAs, AlP, GaP, combinations thereof, or multiple layers thereof. After the trench 50 is filled with the epitaxial region 54, further epitaxial growth of the epitaxial region 54 causes the epitaxial region 54 to extend horizontally and can form a sectional shape. Further growth of the epitaxial region 54 can also cause adjacent epitaxial regions 54 to merge with each other. It can create voids (air gaps) 56.

[0026] Following the epitaxial step, the epitaxial region 54 can be further implanted with p-type or n-type dopant to form source and drain regions, which are also indicated by reference numeral 54. According to an optional embodiment of the invention, when the epitaxial region 54 is in-situ doped with p-type or n-type dopant during epitaxy, the implantation step is skipped.

[0027] Figure 7A A perspective view of the structure after the formation of the contact etch stop layer (CESL) 58 and the interlayer dielectric (ILD) 60 is shown. Figure 16 In the process flow 200 shown, the corresponding process is illustrated as process 214. CESL 58 can be formed from silicon oxide, silicon nitride, silicon carbonitride, etc., and can be formed using CVD, ALD, etc. ILD 60 can include a dielectric material formed using, for example, FCVD, spin coating, CVD, or another deposition method. ILD 60 can be formed from an oxygen-containing dielectric material, which can be a silicon oxide-based material, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc. A planarization process, such as CMP or mechanical polishing, can be performed to flush the top surfaces of ILD 60, dummy gate stack 38, and gate spacer 46 with each other.

[0028] Figure 7B Show Figure 7A Reference section 7B-7B shows the dummy gate stack 38. Next, the dummy gate stack 38, including the hard mask layer 44, the dummy gate electrode 42, and the dummy gate dielectric 40, is etched to form trenches 62 between the gate spacers 46, as shown. Figure 8 As shown. In the case of Figure 16 In the process flow 200 shown, the corresponding process is shown as process 216. The top surface and sidewalls of the protruding fin 36 are exposed to the groove 62.

[0029] Next, as Figure 9A and Figure 9B As shown, in trench 62 ( Figure 8 A replacement gate stack 80 is formed in the process. In such a process... Figure 16 In the process flow 200 shown, the corresponding process is shown as process 218. The replacement gate stack 80 includes a gate dielectric 68 and a corresponding gate electrode 78.

[0030] Figure 9B Show Figure 9A Reference section 9B-9B is shown. According to some embodiments of the invention, the gate dielectric 68 includes an interface layer (IL) 64 as its lower portion, such as... Figure 9B As shown. An IL 64 is formed on the exposed surface of the protruding fin 36. The IL 64 may include an oxide layer, such as a silicon oxide layer or a silicon-germanium oxide layer, which is formed by a thermal oxidation, chemical oxidation, or deposition process of the protruding fin 36. The gate dielectric 68 may also include a high-k dielectric layer 66 deposited above the IL 64. The high-k dielectric layer 66 includes a high-k dielectric material, such as hafnium oxide, lanthanum oxide, aluminum oxide, zirconium oxide, etc. The dielectric constant (k value) of the high-k dielectric material is greater than 3.9 and may be greater than about 7.0 or higher. The high-k dielectric layer 66 is located above the IL 64 and may be in contact with the IL 64. The high-k dielectric layer 66 is formed as a conformal layer and extends on the sidewalls of the protruding fin 36 and the top and sidewalls of the gate spacer 46. According to some embodiments of the invention, the high-k dielectric layer 66 is formed using ALD, CVD, PECVD, LPCVD, HDPCVD, FCVD, molecular beam deposition (MBD), etc.

[0031] Further reference Figure 9B A gate electrode 78 is formed on the gate dielectric 68. The gate electrode 78 may include a plurality of stacked layers 70, 72, and 74 that may be formed as conformal layers, and a fill metal region 76 that fills the remaining trenches not filled by the plurality of stacked layers 70, 72, and 74. Each of the plurality of stacked layers 70, 72, and 74 may have a sidewall portion including a bottom and forming a ring and engaging to the bottom (e.g., Figure 9B (As shown in the cross-section) The shape of the basin. The brief formation process of the gate stack 80 is discussed below. It should be understood that the layers discussed are examples and different layer schemes can be used.

[0032] According to some embodiments, an adhesion layer (also a diffusion barrier layer) 70 is formed above the high-k dielectric layer 66. The adhesion layer 70 may be formed of or comprise Ti, TiN, or titanium silicon nitride (TiSiN). The TiN layer can be formed using ALD or CVD, and the TiSiN layer may comprise alternating deposited TiN and SiN layers, which are formed using, for example, ALD. Because the TiN and SiN layers are very thin, these layers may not be distinguishable from each other and are therefore referred to as TiSiN layers.

[0033] A square work function layer 72 is formed on the adhesion layer 70. The work function layer 72 determines the work function of the gate and includes at least one layer or multiple layers formed of different materials. The material of the work function layer is selected according to whether the corresponding FinFET is an n-type FinFET or a p-type FinFET. For example, when the FinFET is an n-type FinFET, the work function layer 72 may include TiC, TaC, TiAl, TiAlC, Ti, Al, Sc, Y, Er, La, Hf, their alloys and / or multiple layers thereof. When the FinFET is a p-type FinFET, the work function layer 72 may include TiN, TaN, TiAlN, TiSiN, WCN, MOCN, Pt, Pd, Ni, Au, their alloys and / or multiple layers thereof.

[0034] According to some embodiments of the present invention, a cover layer 74 is formed above the work function layer 72, such as... Figure 9B As shown. According to some embodiments, the capping layer 74 can be formed of TiN, and other materials such as TaN can be used. According to some embodiments, ALD, CVD, etc. are used to form the capping layer 74.

[0035] If the capping layer 74 does not completely fill the corresponding trench, a filler metal region 76 is formed above the capping layer 74. According to some embodiments, the filler metal region 76 is formed of tungsten, cobalt, aluminum, or alloys thereof, and can be formed using CVD, FCVD, PECVD, HDPCVD, plating, etc. According to some embodiments where the metal region 76 includes tungsten, WF6, WCl5, WCl6, SiH4, H2, etc., or combinations thereof, can be used as process gases for tungsten deposition. After forming the filler metal region 76, a planarization process can be performed to remove excess portions of the deposited layers including the high-k dielectric layer 66, stacked layers 70, 72, and 74, and the filler metal region 76. The remaining portion of the layers is the gate stack 80, such as... Figure 9A and Figure 9B As shown.

[0036] refer to Figure 10 The gate stack 80 is recessed, thereby forming a trench 82. In such a way... Figure 16In the process flow 200 shown, the corresponding process is illustrated as process 220. The etching process can be a wet etching process, a dry etching process, or a combination of wet and dry etching processes. Depending on the structure and material of the gate stack 80, when dry etching is used, the etching chemical can be selected from BCl3, Cl2, CF4, CH4, CHF3, C x H y F z (x = 1 to 6, y = 0 to 9, and z = 0 to 12), NF3, HBr, CO, CO2, COS, SO2, SF6, TiCl x TaCl x WCl x O2, Ar, or combinations thereof. When using wet etching, the etching solution may include phosphoric acid, NH4OH, a mixture of NaHCO3 / H2O2, a mixture of NaHCO3 / NaOH / H2O2, an aqueous solution of alkali metal hydroxide, etc. Furthermore, depending on the desired top surface profile, such as whether the gate stack 80 is desired to have a flat top surface, a concave top surface, a convex top surface, a wavy top surface, etc., different percentages of etching gas (or wet etching chemical) can be selected. Selecting different percentages of etching gas (or wet etching chemical) may cause certain layers to be etched more or less specifically than other layers, thereby tuning the top surface profile of the gate stack 80 to the desired profile.

[0037] According to some embodiments, such as Figure 10 As shown, in the recess, the gate spacer 46 is not recessed. According to an alternative embodiment, in the recess, the gate spacer 46 is also recessed, and the top surface of the resulting gate spacer 46 is shown by dashed line 84. When the gate spacer 46 is also etched, the top surface of the gate spacer 46 is lower than the top surfaces of ILD 60 and CESL 58. When recessed, the top surface of the gate spacer 46 can be higher than, flush with, or lower than the top surface of the gate stack 80. Adjustment of the height of the top surface of the gate spacer 46 is also achieved by selecting an appropriate combination of etch chemicals.

[0038] According to some embodiments, a high-k dielectric layer 66 is etched during the recess of the gate stack 80. Recessing the high-k dielectric layer 66 can create a wider trench 82, and subsequent gap filling of the trench 82 becomes easier. According to an alternative embodiment, the high-k dielectric layer 66 is not etched. The unetched high-k dielectric layer 66 is shown using dashed lines 86. According to yet another alternative embodiment, the high-k dielectric layer 66 is etched, and the etch rate of the high-k dielectric layer 66 is lower than the etch rate of the gate electrode 78. Therefore, the top surface of the recessed high-k dielectric layer 66 can be at any height below the top surfaces of ILD 60 and CESL 58 and above the top surface of the gate electrode 78.

[0039] Depending on the etching process conditions and etching chemicals (such as the percentage of etching gases), the top surface of a gate stack can have different profiles. For example, dashed line 88A represents a convex top surface of gate stack 80, where the middle portion of the top surface of gate stack 80 is the highest, and the height of the top surface 80 gradually decreases towards the edge of gate stack 80. Dashed line 88B represents a wavy top surface, where some layers of stacked layers 70, 72, and 74 are etched more or less than other layers. For example, work function layer 72 may be etched more (or less) than layers 70 and 74. Dashed line 88C represents a concave top surface of gate stack 80, where the middle portion of the top surface of gate stack 80 is the lowest, and the height of the top surface of gate stack 80 gradually increases towards the edge of gate stack 80. It should also be noted that, due to the shielding effect, the edge portions of the gate stack 80 may also be etched less, wherein the high walls of the gate spacers 46 (and / or CESL 58) on the opposite side of the gate stack 80 shield the edge portions more than the middle portions of the gate stack 80, so that the middle portions of the gate stack 80 are etched faster than the edge portions, thereby creating a concave top surface.

[0040] refer to Figure 11 A conductive capping layer 90 is formed on top of the gate stack 80. In such a case... Figure 16 In the illustrated process flow 200, the corresponding process is shown as process 222. According to some embodiments, the conductive capping layer 90 is formed of a material with stronger resistance to the etch chemicals used to subsequently form the gate contact plug. For example, in forming the gate contact plug 116 ( Figure 14A During the etching process, the gate hard mask 92 is etched to form gate contact openings, and the conductive capping layer 90 protects the gate stack 80 from damage by etching chemicals. Furthermore, the conductive capping layer 90 can have a high conductivity, which can be equal to or higher than the conductivity values ​​of at least some or all of the layers in the gate electrode 78. According to some embodiments, the conductive capping layer 90 is formed by selective deposition processes such as CVD, electroless plating, etc. For example, when tungsten is deposited as the conductive capping layer 90 using CVD, process gases such as WF6, WCl2, WCl5, WCl6, SiH4, GeH4, H2, etc., or combinations thereof, can be used to deposit the tungsten.

[0041] According to some embodiments, for example, when selective plating is used to form the conductive capping layer 90, the conductive capping layer 90 may not be grown directly from the exposed top surface of the high-k dielectric layer 66, and a void (air gap) 91 may be formed directly above the exposed top surface of the high-k dielectric layer 66.

[0042] According to some embodiments, the conductive capping layer 90 is formed or includes tungsten (W), WC, Ti, TiN, TaN, Sc, Y, Er, La, Hf, Al, Ti, Pt, Pd, Ni, Co, Ru, Au, or their alloys or multiple layers thereof. According to some embodiments, each conductive capping layer 90 is a single layer formed of a homogeneous conductive material. According to optional embodiments, each conductive capping layer 90 is a composite layer comprising two or more sublayers formed of different materials. For example, Figure 11 Examples are shown where each conductive capping layer 90 includes a lower layer 90A and an upper layer 90B formed of different materials with different properties. According to some embodiments, the lower layer 90A may have a higher conductivity value than the upper layer 90B, and / or the upper layer 90B may have better etch resistance than the lower layer 90A (as described above). For example, the lower layer 90A may be formed of or include Al, Ti, TiN, TaN, etc., and the upper layer 90B may be formed of or include W, WC, Pt, etc. With a higher conductivity value in the lower layer 90A, the gate resistance (including contact resistance) is reduced more significantly. With better etch resistance in the upper layer 90B, it provides better protection for the underlying layers against damage in subsequent processes.

[0043] According to some embodiments, both the p-type FinFET and the n-type FinFET are formed in the same device die and on the same semiconductor substrate. According to some embodiments of the invention, both the p-type FinFET and the n-type FinFET are also formed. Each p-type FinFET and n-type FinFET may have… Figures 14A to 14EThe structure can be any of the following. As previously described, the gate stack 80 of the p-type FinFET can be different from the gate stack 80 of the n-type FinFET. For example, the work function layers 72 of the p-type FinFET and the n-type FinFET are formed of different materials. The work function layer 72 of the n-type FinFET can have a lower work function than the work function layer 72 of the p-type FinFET. According to some embodiments, the conductive capping layers 90 of the p-type FinFET and the n-type FinFET are formed of the same material, which can be formed in the same formation process or in different formation processes. According to alternative embodiments, the conductive capping layers 90 of the p-type FinFET and the n-type FinFET are formed of different materials by separate formation processes. For example, the conductive capping layer 90 of the p-type FinFET can be formed of a material with a higher work function (which can be a p-type work function greater than about 4.9 eV), while the conductive capping layer 90 of the n-type FinFET can be formed of a material with a lower work function (which can be an n-type work function less than about 4.5 eV). For example, the conductive capping layer 90 of the p-type FinFET can be formed or comprise a high work function material such as Pt, Pd, Ni, Au, or alloys thereof, and the conductive capping layer 90 of the n-type FinFET can be formed or comprise a low work function material such as W, La, Hf, Al, Ti, or alloys thereof. In an optional embodiment where the conductive capping layers 90 of the n-type and p-type FinFETs are multilayered, the lower layers 90A of the n-type and p-type FinFETs are formed from different materials using separate deposition processes. For example, the lower layer 90A of the n-type FinFET can be formed from the low work function material described above, and the lower layer 90A of the p-type FinFET can be formed from the high work function material described above. On the other hand, the upper layer 90B of both n-type and p-type FinFETs can be formed from the same material that is more etch-resistant than the lower layer 90A below, for example, through a common deposition process.

[0044] In subsequent processes, such as Figure 12A and Figure 12B As shown, a hard mask 92 is formed above the conductive capping layer 90. In the case of... Figure 16 In the process flow 200 shown, the corresponding process is shown as process 224. Figure 12A and Figure 12B Cross-sectional and perspective views are shown respectively. According to some embodiments of the invention, forming the hard mask 92 includes a deposition process for forming a blanket dielectric material and a planarization process for removing excess dielectric material over the gate spacers 46 and ILD 60. The hard mask 92 may be formed of, for example, silicon nitride, silicon oxynitride, silicon carbonitride, or other similar dielectric materials.

[0045] Figure 13A and Figure 13B This illustrates the formation of the lower source / drain contact plug 94 and the silicide region 96. (As shown in the image...) Figure 16 In the illustrated process flow 200, the corresponding process is shown as process 226. According to some embodiments of the invention, the formation process includes etching ILD 60 and CESL 58 to form source / drain contact openings, depositing a metal layer (such as a titanium layer, cobalt layer, etc.) extending into the source / drain contact openings, depositing a barrier layer (such as a titanium nitride layer), and performing an annealing process such that the bottom of the metal layer reacts with the source / drain region 54 to form a silicide region 96. Remaining sidewall portions of the barrier layer and metal layer may be removed or left intact. When the barrier layer is removed, another barrier layer, such as a titanium nitride layer, may be deposited. The remaining unfilled source / drain contact openings may be filled with a metallic material, such as cobalt, tungsten, other suitable metals, or alloys thereof. A planarization process, such as a CMP process or a mechanical polishing process, is performed to remove excess material to form contact plugs 94.

[0046] Figure 14A This illustrates the formation of an etch stop layer (ESL) 97 and a dielectric layer 98 (which could also be an ILD) above the ESL 97. In... Figure 16 In the process flow 200 shown, the corresponding process is illustrated as process 228. ESL 97 can be formed from or include multiple layers of silicon nitride, silicon carbonitride, silicon carbide, carbon nitride, aluminum oxide, aluminum nitride, etc. Dielectric layer 98 can be formed from or include multiple layers of silicon nitride, silicon carbonitride, silicon carbide, carbon nitride, aluminum oxide, aluminum nitride, etc., such as silicon dioxide, low-k dielectric materials, silicon oxynitride, PSG, BSG, BPSG, USG, FSG, OSG, SiOC, spin-coated glass, spin-coated polymers, etc. ESL 97 and dielectric layer 98 can be deposited using spin coating, CVD, ALD, LPCVD, plasma-enhanced chemical vapor deposition (PECVD), etc.

[0047] Then, gate contact plug 116 and upper source / drain contact plug 118 are formed. Figure 16In the process flow 200 shown, the corresponding process is illustrated as process 230. The formation process may include etching the dielectric layer 98 and ESL 97 to form an opening until the conductive capping layer 90 and the source / drain contact plug 94 are exposed, filling the opening with a conductive layer, and performing a planarization process to remove excess portions of the conductive layer. The etching process may be anisotropic. For example, depending on the material of the hard mask 92, the etching gas may include HF, NH3, such as CF4, a mixture of O2 and N2, a mixture of NF3 and O2, SF6, a fluorinated gas of a mixture of SF6 and O2, or BCl3, Cl2, CF4, CH4, CHF3, C x H y F z (x = 1 to 6, y = 0 to 9, and z = 0 to 12), NF3, HBr, CO, CO2, COS, SO2, SF6, TiCl x TaCl x WCl x O2, Ar, etc. During the formation of the opening, an etching gas can be selected to have a low etching rate on the conductive capping layer 90, so that the conductive capping layer 90 is not etched. According to some embodiments, if the gate electrode 78 is exposed to the etching gas, the etching gas has the ability to etch the gate electrode 78. In other words, the etching rate of the gate electrode 78 (if exposed to the etching gas) will be higher than the etching rate of the conductive capping layer 90. Furthermore, according to some embodiments where the conductive capping layer 90 is multilayered, the etching rate of the lower sublayer in the conductive capping layer 90 will be higher than the etching rate of the upper sublayer in the conductive capping layer 90. However, according to some embodiments of the invention, the gate electrode 78 is protected from damage due to the protection of the conductive capping layer 90. Thus, a FinFET 120 is formed.

[0048] Figure 14A An embodiment is shown in which the conductive capping layer 90 is flat and conformal and has a uniform thickness (within process variations). Figure 14B , Figure 14C , Figure 14D and Figure 14E A conductive capping layer 90 with different contours is shown. For example, in... Figure 14B In this configuration, the top surface of the gate stack 80 has a concave profile. Figure 14C In this configuration, the top surface of the gate stack 80 has a convex profile. Figure 14D In this configuration, the top surface of the gate stack 80 has a wavy profile. For example, the lowest (or highest) point of the top surface of the gate stack 80 could be a point on the top surface of the work function layer 72. Figure 14E In the middle, the conductive capping layer 90 has an uneven thickness. Although Figure 14EThe conductive capping layer 90 is shown to be thicker in the middle than at the edges, but the middle portion of the conductive capping layer 90 may also be thinner than the edges. It should be understood that... Figure 14A , Figure 14B , Figure 14C , Figure 14D and Figure 14E Multiple components and contours can coexist in the same structure during application. For example, voids 91 may or may not be formed in each of these structures. Furthermore, a conductive overlay 90 with non-uniform thickness, such as... Figure 14E As shown, it can be combined with the concave top surface, convex top surface, or wavy top surface of the gate stack 80.

[0049] Embodiments of the present invention have several advantageous features. Damage to the gate stack is prevented during the formation of the gate contact plug by forming a conductive capping layer with better etch resistance. Furthermore, contact resistance can be reduced by using a material with high conductivity to form the conductive capping layer.

[0050] According to some embodiments of the present invention, the method includes: removing dummy gate stacks to form a first trench between first gate spacers; forming a first replacement gate stack in the first trench; recessing the first replacement gate stack to form a second trench between the first gate spacers; selectively depositing a first conductive capping layer in the second trench; forming a dielectric hard mask in the second trench and over the first conductive capping layer; etching the dielectric hard mask using an etching gas to form an opening in the dielectric hard mask, wherein the first replacement gate stack is exposed at the opening; and forming a gate contact plug located over and contacting the first conductive capping layer. In an embodiment, during etching, the gate dielectric in the first replacement gate stack is recessed, and the sidewalls of the first gate spacers are exposed to the second trench. In an embodiment, depositing the first conductive capping layer includes: depositing a first sublayer on the first replacement gate stack; and depositing a second sublayer over the first sublayer, wherein the first sublayer has a higher conductivity value than the second sublayer. In an embodiment, the method further includes: recessing a second replacement gate stack to form a third trench between second gate spacers; and selectively depositing a second conductive capping layer in the third trench and over the second replacement gate stack, wherein the second conductive capping layer comprises a material different from the first conductive capping layer. In an embodiment, the first replacement gate stack is included in a p-type transistor, and the second replacement gate stack is included in an n-type transistor, and the first conductive capping layer has a higher work function than the second conductive capping layer. In an embodiment, the first conductive capping layer is more resistant to etching gases than the first replacement gate stack. In an embodiment, after recessing, the first replacement gate stack has a convex or concave top surface. In an embodiment, the first conductive capping layer is selectively deposited by chemical vapor deposition. In an embodiment, the first conductive capping layer is selectively deposited by plating.

[0051] According to some embodiments of the present invention, the device includes: a semiconductor region; gate spacers located on the semiconductor region; a gate stack located above the semiconductor region and between the gate spacers, wherein the gate stack includes multiple layers; a conductive capping layer located above and contacting the multiple layers of the gate stack; a dielectric hard mask located above the conductive capping layer and between the gate spacers; and a gate contact plug extending through the dielectric hard mask to be positioned on the conductive capping layer. In embodiments, the gate stack includes a gate dielectric and a gate electrode, the gate dielectric extending below and on the sidewalls of the gate electrode, wherein the conductive capping layer includes a portion overlapping the gate dielectric. In embodiments, the conductive capping layer is spaced from the gate dielectric by an air gap. In embodiments, the conductive capping layer includes tungsten. In embodiments, the conductive capping layer includes: a first sublayer contacting the gate stack; and a second sublayer located above the first sublayer, wherein the first sublayer has a higher conductivity value than the second sublayer. In embodiments, the gate stack includes a concave top surface. In embodiments, the gate stack includes a convex top surface.

[0052] According to some embodiments of the present invention, the device includes: a source region and a drain region; a gate stack located between the source region and the drain region, wherein the gate stack includes multiple layers, and each layer has a basin shape, the basin shape having a bottom and a sidewall portion located above the bottom portion and engaging with the bottom; gate spacers located on opposite sidewalls of the gate stack; and a conductive layer located above and contacting the top surface of the sidewall portions of the multiple layers. In an embodiment, the conductive layer is located between the gate spacers. In an embodiment, the conductive layer includes multiple sublayers comprising different materials. In an embodiment, the multiple sublayers of the conductive layer include a first sublayer and a second sublayer, the first sublayer having a higher conductivity value than the second sublayer.

[0053] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand aspects of the invention. Those skilled in the art should understand that they can readily use this invention as a basis to design or modify other processes and structures for implementing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of the invention.

Claims

1. A method for forming a semiconductor device, comprising: Remove the dummy gate stack to form a first trench between the first gate spacers; A first replacement gate stack is formed in the first trench; The first replacement gate stack is recessed to form a second trench between the first gate spacers; Selectively depositing a first conductive capping layer in the second trench, wherein depositing the first conductive capping layer includes: depositing a first sublayer on the first replacement gate stack and depositing a second sublayer over the first sublayer, wherein the first sublayer has a higher conductivity value than the second sublayer, and the second sublayer is more resistant to etching gases than the first replacement gate stack and the first sublayer; A dielectric hard mask is formed in the second trench and above the first conductive capping layer; The dielectric hard mask is etched using the etching gas to form an opening in the dielectric hard mask, wherein the first replacement gate stack is exposed at the opening; and A gate contact plug is formed that is located above and in contact with the second sublayer.

2. The method according to claim 1, wherein, During the etching, the gate dielectric in the first replacement gate stack is recessed, and the sidewalls of the first gate spacer are exposed to the second trench.

3. The method according to claim 1, wherein, The conductivity of the first conductive capping layer is higher than that of the work function layer in the first replacement gate stack.

4. The method according to claim 1, further comprising: The second replacement gate stack is recessed to form a third trench between the second gate spacers; as well as A second conductive capping layer is selectively deposited in the third trench and over the second replacement gate stack, wherein the second conductive capping layer comprises a material different from the first conductive capping layer.

5. The method according to claim 4, wherein, The first replacement gate stack is included in a p-type transistor, and the second replacement gate stack is included in an n-type transistor, and the first conductive capping layer has a higher work function than the second conductive capping layer.

6. The method according to claim 1, wherein, The second sublayer comprises tungsten.

7. The method according to claim 1, wherein, Following the recess, the first replacement gate stack has a convex top surface or a concave top surface.

8. The method according to claim 1, wherein, The first conductive capping layer is selectively deposited by chemical vapor deposition.

9. The method according to claim 1, wherein, The first conductive capping layer is selectively deposited by plating.

10. A semiconductor device, comprising: Semiconductor region; A gate spacer is located on the semiconductor region; A gate stack is located above the semiconductor region and between the gate spacers, wherein the gate stack comprises multiple layers; A conductive capping layer is located above and in contact with the plurality of layers of the gate stack, wherein the conductive capping layer includes a first sub-layer in contact with the gate stack and a second sub-layer located above the first sub-layer, wherein the first sub-layer has a higher conductivity value than the second sub-layer, and the second sub-layer has stronger etch resistance than the gate stack and the first sub-layer. A dielectric hard mask is located above the conductive overlay and between the gate spacers; and A gate contact plug penetrates the dielectric hard mask to be positioned on the second sublayer of the conductive overlay.

11. The semiconductor device according to claim 10, wherein, The gate stack includes a gate dielectric and a gate electrode, the gate dielectric extending below and on the sidewalls of the gate electrode, wherein the conductive overlay includes a portion overlapping the gate dielectric.

12. The semiconductor device according to claim 11, wherein, The conductive capping layer is separated from the gate dielectric by an air gap.

13. The semiconductor device according to claim 10, wherein, The conductive coating layer comprises tungsten.

14. The semiconductor device according to claim 10, wherein, The conductivity of the conductive capping layer is higher than that of the work function layer among the plurality of layers in the gate stack.

15. The semiconductor device according to claim 10, wherein, The gate stack includes a recessed top surface.

16. The semiconductor device according to claim 10, wherein, The gate stack includes a convex top surface.

17. A semiconductor device, comprising: Source and drain regions; A gate stack is located between the source region and the drain region, wherein the gate stack includes multiple layers and each of the multiple layers has a basin shape, the basin shape having a bottom and a sidewall portion located above the bottom and engaging with the bottom; Gate spacers are located on opposite sidewalls of the gate stack; A conductive layer is located above and in contact with the top surface of the sidewall portion of the plurality of layers. The conductive layer includes a first sublayer and a second sublayer located above the first sublayer. The first sublayer has a higher conductivity value than the second sublayer, and the second sublayer has stronger etch resistance than the gate stack and the first sublayer. A gate hard mask, located above the conductive layer and between the gate spacers; and A gate contact plug penetrates the gate hard mask to be positioned on the second sublayer of the conductive layer.

18. The semiconductor device according to claim 17, wherein, The conductive layer is located between the gate spacers.

19. The semiconductor device according to claim 17, wherein, The conductive layer comprises the plurality of sublayers containing different materials.

20. The semiconductor device according to claim 19, in, The bottom surface of the gate hard mask overlaps with the top surface of the conductive layer, and the top surface of the gate hard mask is flush with the top surface of the gate spacer.

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