Semiconductor structure and method of forming the same

Abstract

Disclosed herein are semiconductor structures and methods of manufacturing the same. In one embodiment, an exemplary semiconductor structure includes a plurality of first channel members over a substrate; a first gate structure surrounding each of the first channel members; and a dielectric fin structure disposed adjacent to the first gate structure, the dielectric fin structure including a first dielectric layer disposed over the substrate and in direct contact with the first gate structure; a second dielectric layer disposed over the first dielectric layer; a third dielectric layer disposed over the second dielectric layer and spaced apart from the first dielectric layer and the first gate structure by the second dielectric layer; and a first spacer disposed directly over the third dielectric layer.

Description

Technical Field

[0001] The present invention relates to semiconductor structures, and more particularly to semiconductor structures with isolation structures and methods for manufacturing the same. Background Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have yielded generations of ICs, each with smaller and more complex circuitry than the previous generation. In the development of ICs, functional density (the number of interconnect structures per unit area of ​​a chip) has increased dramatically, while geometry (the smallest component (or line) that can be produced using a process) has shrunk. This miniaturization generally provides benefits by increasing production efficiency and reducing associated costs. However, this miniaturization has also increased the complexity of IC processes and manufacturing.

[0003] For example, as semiconductor devices continue to miniaturize, achieving the required density and performance presents challenges. The required density and performance also necessitate efficient and precise etching processes. However, due to densely spaced components and reduced process windows, some sacrificial components may not be removed within the expected etching time, potentially leaving residues that hinder the formation of satisfactory functional structures (e.g., gate structures). While over-etching can reduce unwanted residual sacrificial components, it may damage adjacent components. Therefore, although existing semiconductor devices and their fabrication methods have largely met their intended purpose, they are not satisfactory in all aspects. Summary of the Invention

[0004] This invention provides a semiconductor structure including: a plurality of first channel components above a substrate; a first gate structure surrounding each of the first channel components; and a dielectric fin structure disposed adjacent to the first gate structure. The dielectric fin structure includes: a first dielectric layer disposed above the substrate and in direct contact with the first gate structure; a second dielectric layer disposed above the first dielectric layer; a third dielectric layer disposed above the second dielectric layer and spaced apart from the first dielectric layer and the first gate structure by the second dielectric layer; and a first isolation member disposed directly above the third dielectric layer.

[0005] This invention provides a semiconductor structure comprising: a plurality of first nanostructures and a plurality of second nanostructures extending longitudinally above a substrate along a first direction; a first isolation member disposed between the first and second nanostructures and extending longitudinally along the first direction; and a second isolation member disposed directly above the first isolation member. The second isolation member hangs over the first isolation member along a second direction perpendicular to the first direction.

[0006] This invention provides a method for forming a semiconductor structure, comprising: forming a plurality of semiconductor fin-like stacks protruding from a substrate, each of the semiconductor fin-like stacks comprising alternating vertical stacks of a plurality of first semiconductor layers and a plurality of second semiconductor layers; forming a cladding layer along the sidewalls of each of the semiconductor fin-like stacks; depositing a hybrid film layer compliantly over the substrate, the hybrid film layer comprising: a first film layer; and a second film layer on the first film layer; forming a first dielectric layer over the substrate to fill the space between two adjacent semiconductor fin-like stacks; selectively etching the first dielectric layer and the hybrid film layer to form a trench; forming an isolation member in the trench; selectively removing the cladding layer, a portion of the first film layer extending along the sidewalls of the cladding layer, and the second semiconductor layer to form a plurality of openings; and forming a gate structure in the openings. Attached Figure Description

[0007] The embodiments of the present invention will be described in detail below with reference to the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale and are only for illustrative purposes. In fact, the size of the units can be arbitrarily enlarged or reduced to clearly demonstrate the features of the embodiments of the present invention.

[0008] Figure 1 According to various embodiments of this disclosure, flowcharts of methods for manufacturing semiconductor structures are shown.

[0009] Figure 2 According to various aspects of this disclosure, it is shown that in Figure 1 A partial planar top view of an exemplary workpiece undergoing different operational stages in the method.

[0010] Figure 3 , 4 5, 6, 7, 8, 9, and 10, according to one or more aspects of this disclosure, illustrate exemplary workpieces in Figure 1 During each manufacturing stage of the method along Figure 2 A partial cross-sectional view of line A-A' shown.

[0011] Figure 11A , 12A According to one or more aspects of this disclosure, 13A, 14A and 15A illustrate exemplary workpieces in Figure 1 During each manufacturing stage of the method along Figure 2 A partial cross-sectional view of line A-A' shown.

[0012] Figure 11B , 12B According to one or more aspects of this disclosure, 13B, 14B, and 15B illustrate exemplary workpieces in... Figure 1During each manufacturing stage of the method along Figure 2 A partial cross-sectional view of line B-B' shown.

[0013] Figure 16 , 17 18, 19, 20 Figure 21 , 22 23, 24 and Figure 25 , 26 27 and 28, according to one or more aspects of this disclosure, illustrate first, second, and third alternative embodiments of exemplary workpieces. Figure 1 During each manufacturing stage of the method along Figure 2 A partial cross-sectional view of line A-A' shown.

[0014] Explanation of reference numerals in the attached figures:

[0015] 100: Method

[0016] 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126: Boxes

[0017] 200: Workpiece

[0018] 202: Substrate

[0019] 203: Lining

[0020] 204: Isolation Structure

[0021] 205: Fin-like structure

[0022] 205C: Passage Area

[0023] 205SD: Source / Drain Region

[0024] 206: Sacrificial Layer

[0025] 207: Semiconductor stacking, stacking

[0026] 208: Channel Layer

[0027] 210: Top floor

[0028] 212: Trench

[0029] 214,214': Overlying layer

[0030] 216: Hybrid film

[0031] 218: First membrane, soft membrane

[0032] 218': Soft membrane

[0033] 220: Second membrane, dura mater

[0034] 222: Dielectric filling layer

[0035] 225: Etching process

[0036] 226: Trench

[0037] 228: Hat Layer

[0038] 230,230': Dielectric fins

[0039] 232: Trench

[0040] 234: Dummy Gate Stack

[0041] 236: Gate spacer

[0042] 238: Internal spacer components

[0043] 240: Source / Drain Components

[0044] 242: Contact Etching Stop Layer

[0045] 244: Interlayer dielectric layer

[0046] 246: Trench

[0047] 248: Opening

[0048] 249: Etching process

[0049] 250: Opening

[0050] 252: Trench

[0051] 254: Gate structure

[0052] 254a: Top

[0053] 254b: Bottom

[0054] 254c: Sidewall portion

[0055] 300: Workpiece

[0056] 305: Etching process

[0057] 310: Trench

[0058] 312: Hat layer

[0059] 312s: Conical sidewall

[0060] 320t: Conical top

[0061] 320V: Bottom

[0062] 400: Workpiece

[0063] 402: Hat Layer

[0064] 404, 404': Second Soft Film

[0065] 405: Trench

[0066] 420: Dielectric fins

[0067] 502: Cap layer

[0068] 504: Third Soft Membrane

[0069] 505: Trench

[0070] 520: Dielectric fins

[0071] T1, T2, T3: Thickness

[0072] W1, W2, W3, W4, W5, W6, W t :width

[0073] A-A',B-B': line Detailed Implementation

[0074] Numerous embodiments or examples are disclosed below for implementing different elements of the provided subject matter. Specific examples of each element and its configuration are described below to simplify the description of embodiments of the invention. Of course, these are merely examples and are not intended to limit the embodiments of the invention. For example, if the description refers to a first element formed on a second element, it may include embodiments where the first and second elements are in direct contact, or embodiments where an additional element is formed between the first and second elements such that they are not in direct contact. Furthermore, the embodiments of the invention may repeat element symbols and / or letters in various examples. Such repetition is for the purpose of brevity and clarity, and is not intended to indicate a relationship between the different embodiments and / or configurations discussed.

[0075] Furthermore, spatially relative terms, such as "below," "under," "lower," "above," and "higher," may be used to facilitate the description of the relationship between one or more components or features in the accompanying drawings and another component or feature(s). Spatially relative terms are used to include different orientations of the structure in use or operation, as well as the orientations described in the accompanying drawings. When the structure is rotated to different orientations (rotated 90 degrees or otherwise), the spatially relative adjectives used will also be interpreted according to the orientation after the rotation.

[0076] Furthermore, when terms such as “about,” “approximately,” and similar terms are used to describe numbers or ranges of numbers, those skilled in the art will understand that, taking into account inherent variations in manufacturing, such terms are used to cover numbers within a reasonable range, which includes the described number. For example, a number or range of numbers covers a reasonable range that includes the described number, such as within + / - 10% of the described number. This reasonable range is based on known manufacturing tolerances for the component that has characteristics associated with that number. For example, those skilled in the art know that the manufacturing tolerance associated with a deposited material layer is + / - 15%, and a material layer “about 5 nm” covers a size range of 4.25 nm to 5.75 nm. Additionally, the embodiments of the present invention may repeat element symbols and / or letters in various examples. Such repetition is for the purpose of brevity and clarity and is not intended to indicate a relationship between the different embodiments and / or configurations discussed.

[0077] Recently, multi-gate devices, such as multi-bridge-channel (MBC) transistors (also known as gate-all-around (GAA) transistors, nanosheet transistors, nanowire transistors, or surrounding gate transistors (SGT)), have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and minimizing short-channel effects (SCEs). Forming a multi-bridge-channel (MBC) transistor involves forming a stack of multiple channel layers interleaved with multiple sacrificial layers, wherein the sacrificial layers can be selectively removed to release the channel layers as channel components; then, a gate structure comprising multiple dielectric and conductive layers is formed to surround each channel component. As mentioned above, aggressive miniaturization of ICs results in densely spaced components. For example, the dimensions of each stack and the space between two adjacent stacks are reduced. Due to the densely spaced components, the etch window for removing the sacrificial layers is reduced, resulting in some sacrificial layer remaining in the channel region after the channel release process (e.g., residue). Residues in the sacrificial layer can negatively impact the formation of gate structures around some bottom channel components, leading to uneven gate control and unsatisfactory device performance. One possible approach to largely avoid such residues without altering the device footprint or affecting the electrical isolation between adjacent transistors could involve reducing the size (e.g., width) of each stack to increase the space between adjacent stacks, thereby increasing the etch window. However, this approach provides a reduced channel width, resulting in degraded device performance.

[0078] This disclosure provides semiconductor devices and methods for increasing etch windows associated with channel release processes. An exemplary method for forming a semiconductor device includes: forming a plurality of semiconductor fin stacks protruding from a substrate, wherein each fin stack includes a vertical semiconductor stack consisting of alternating channel layers and sacrificial layers. The exemplary method further includes: forming a cladding layer along the sidewalls of each stack; and compliantly depositing a hybrid film over the substrate. The hybrid film includes: a first film and a second film on the first film. The first film may be selectively removed during an etch process employed in the channel release process. The exemplary method further includes: forming a dielectric fill layer on the hybrid film to fill a space between two adjacent semiconductor fin stacks; selectively etching the dielectric fill layer and the hybrid film to form a trench, forming a helmet layer in the trench; selectively removing the cladding layer, a portion of the first film extending along the sidewalls of the cladding layer, and the sacrificial layer to form an opening; and forming a gate structure in the opening. Forming a hybrid film that can be partially removed during the channel release process can facilitate the removal of the sacrificial layer and form a satisfactory gate structure.

[0079] Various aspects of this disclosure will now be described in more detail with reference to the accompanying drawings. In this respect, according to embodiments of this disclosure, Figure 1 This is a flowchart illustrating a method 100 for forming a semiconductor device. According to an embodiment of method 100, the following is combined with... Figure 2-10 , Figure 11A-15A , Figure 11B-15B as well as Figure 16-28 ( Figure 2-28 This diagram illustrates a partial top view or cross-sectional view of workpiece 200 at different manufacturing stages. Method 100 is merely an example and is not intended to limit the scope of this disclosure as expressly described herein. Additional steps may be provided before, during, and / or after method 100. Some of the described stages may be replaced, omitted, or moved in embodiments of additional methods. For simplicity, not all steps are described in detail herein. Since workpiece 200 is manufactured into semiconductor device 200 after the manufacturing process is completed, workpiece 200 may be referred to as semiconductor device 200 depending on the context. To avoid any doubt, Figure 2-28 The X, Y, and Z directions are used perpendicularly to each other and consistently. Throughout the text, unless otherwise stated, similar element symbols represent similar elements.

[0080] Reference Figure 1 , 2 In method 100, block 102 is included. In block 102, workpiece 200 is received. Figure 2 A top view of an exemplary workpiece 200 is depicted. Figure 3 An exemplary workpiece 200 is depicted along... Figure 2 The cross-sectional view of line A-A' shown. Figure 3 In the illustrated embodiments, workpiece 200 includes substrate 202. In one embodiment, substrate 202 is a bulk silicon substrate. In various embodiments, substrate 202 may include other semiconductor materials, such as germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, GaInAsP, or combinations thereof. In some additional embodiments, substrate 202 may be a semiconductor-on-insulator substrate, such as a silicon-on-insulator (SOI) substrate, a silicon-germanium-on-insulator (SGOI) substrate, or a germanium-on-insulator (GOI) substrate.

[0081] Workpiece 200 includes a plurality of fin-like structures 205 disposed above substrate 202. Each fin-like structure 205 extends longitudinally along the X direction and is divided into channel regions 205C (e.g., Figure 11B(As shown) and source / drain regions 205SD. The fin-like structure 205 can be formed by a combination of lithography and etching steps on a portion of the substrate 202, the vertical semiconductor stack 207, and the top layer 210 above the stack 207. In the depicted embodiment, the stack 207 may include multiple channel layers 208 interleaved with multiple sacrificial layers 206. Each channel layer 208 may include a semiconductor material, such as silicon, germanium, silicon-carbon, silicon-germanium, or other suitable semiconductor materials. However, each sacrificial layer 206 has a different composition than the channel layers 208. The channel layers 208, sacrificial layers 206, and the top layer 210 can be epitaxially deposited on the substrate 202 using molecular beam epitaxy (MBE), vapor-phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), and / or other suitable epitaxial growth processes. In this embodiment, the top layer 210 is also a sacrificial layer, configured to facilitate the formation of the cap layer (discussed in more detail below). In some embodiments, the thickness of the top layer 210 is greater than the thickness of the sacrificial layer 206 and / or the channel layer 208. The top layer 210 may comprise any suitable material, such as a semiconductor material, as long as its composition differs from that of the cap layer and the channel layer 208 disposed below it, to allow removal by a selective etching process. In some embodiments, the top layer 210 has a composition similar to or the same as that of the sacrificial layer 206. In the example depicted, the channel layer 208 is formed of silicon (Si), and the sacrificial layer 206 and the top layer 210 are formed of silicon germanium (SiGe).

[0082] The fin-like structure 205 is separated by the isolation structure 204. The isolation structure 204 may include silicon oxide, tetraethoxysilane (TEOS) oxide, doped silicon oxide (e.g., borophosphosilicate glass (BPSG), fluoride-doped silicate glass (FSG), phosphosilicate glass (PSG), boron-doped silicate glass (BSG), etc.), low-k dielectric materials (dielectric constant less than that of silicon oxide (approximately 3.9)), other suitable materials, or combinations thereof. The isolation structure 204 may include shallow trench isolation (STI) components. In one embodiment, the isolation structure 204 is formed by filling the trenches separating the fin-like structures with the aforementioned dielectric material using any suitable method, such as chemical vapor deposition (CVD), flowable chemical vapor deposition (FCVD), spin-on-glass (SOG), other suitable methods, or combinations thereof. The dielectric material can then be planarized via a chemical-mechanical planarization / polishing (CMP) process and selectively etched back to form the isolation structure 204. The isolation structure 204 may comprise a single-layer or multi-layer structure.

[0083] exist Figure 3 In the illustrated embodiment, workpiece 200 includes a liner 203. Liner 203 may comprise silicon oxide or other suitable materials. A dielectric material layer may be compliantly deposited on workpiece 200 to form liner 203 prior to forming isolation structure 204. The dielectric material layer may be etched back to form liner 203. In one embodiment, liner 203 is formed of silicon oxide deposited by plasma-enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), or other suitable materials, and isolation structure 204 is formed of silicon oxide deposited by flow chemical vapor deposition (FCVD). Liner 203 is denser than isolation structure 204 to provide better device performance. Trench 212 is defined by the top surfaces of liner 203 and isolation structure 204, and the sidewall surfaces of adjacent fin structures 205. The width of trench 212 along the Y direction is denoted as W1.

[0084] refer to Figure 1 , 4In method 100, as described in section 5, block 104 is included. In block 104, a cladding layer 214 is formed over the workpiece 200 and extends along the sidewall surface of each fin-like structure 205. In this embodiment, the cladding layer 214 may have substantially the same composition as the sacrificial layer 206 so that they can be selectively removed by a conventional etching process. In this embodiment, the cladding layer 214 is formed of SiGe. The cladding layer 214 can be formed using the suitable methods discussed above regarding the formation of the stack 207. In some embodiments, such as Figure 4 As shown, a cladding layer 214 is deposited compliantly over the surface of the semiconductor device 200, such that the cladding layer 214 is also formed over the isolation structure 204 and the substrate 203. In some examples, the thickness T1 of the cladding layer 214 can be between approximately 10 nm and approximately 20 nm. Subsequently, refer to... Figure 5 An anisotropic etching process is performed to selectively remove portions of the cladding layer 214 that do not extend along the sidewalls of the fin-like structure 205, exposing portions of the isolation structure 204 and the top surface of the top layer 210. The etching process may include dry etching processes, such as reactive ion etching (RIE). In this embodiment, a portion of the cladding layer 214 partially fills the trench 212. The width of the unfilled portion of the trench 212 along the Y direction is now denoted as W2. W1 is equal to the sum of W2 and twice T1. That is, W1 = W2 + 2 * T1.

[0085] Reference Figure 1 and 6Method 100 includes block 106. In block 106, a first film 218 of a hybrid film 216 is formed over a workpiece 200. In one embodiment, the first film 218 is deposited compliantly to have a substantially uniform thickness T2 over the top surface of the workpiece 200 (e.g., substantially the same thickness on the top surface of the isolation structure 204, the top surface of the fin structure 205, and the top and sidewall surfaces of the cladding layer 214), and partially fills the trench 212. In some embodiments, the thickness T2 is between about 1 nm and 3 nm to enlarge the etch window for removing the sacrificial layer 206 without significantly reducing the size of the subsequently formed second film 220 (described later). In some embodiments, the first film 218 can be formed by performing a deposition process, such as a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, or other suitable deposition processes. The first film 218 may comprise silicon nitride, silicon oxynitride (SiOCN), or other suitable materials. It is noteworthy that when the coating layer 214 comprises silicon germanium, the composition of the first film 218 is substantially oxygen-free to reduce or substantially prevent oxidation of the silicon germanium in the coating layer 214. In this embodiment, the first film 218 comprises silicon nitride. When the first film 218 is formed of silicon oxycarbonitride, the carbon concentration in the silicon oxycarbonitride may be less than about 3%. For example, in some embodiments, the carbon concentration of the silicon oxycarbonitride may be between about 1% and about 3%.

[0086] Continue to refer to Figure 1 and 6Method 100 includes block 108, in which a second film 220 of hybrid film 216 is formed over a first film 218. In one embodiment, the second film 220 is deposited compliantly over the first film 218 to have a generally uniform thickness T3 and to partially fill trench 212. The second film 220 is surrounded by the first film 218. In some embodiments, the thickness T3 is between approximately 3 nm and 6 nm, such that the second film 220 is thick enough to protect the subsequently formed dielectric fill layer 222 from etching in subsequent processes. The partially filled trench 212 has a width W3 along the Y direction. In some embodiments, the second film 220 can be formed by performing a deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or other suitable deposition processes. The second film 220 may include silicon carbonitride (SiCN), silicon oxycarbonate (SiOCN), boron nitride (BN), or other suitable materials. When the second film 220 is formed of silicon oxycarbonitride, the carbon concentration of the silicon oxycarbonitride can be between about 5% and about 15%. The second film 220 is configured to protect the cladding layer 214 from oxidation and to maintain the integrity of the subsequently formed dielectric filling layer 222. Due to the etching selectivity between the first film 218 and the second film 220, and for the channel release process (see below)... Figure 13A Regarding the etching process used in the detailed description, the second film 220 is less likely to be removed than the first film 218. The first film 218 can be referred to as a soft film 218, and the second film 220 can be referred to as a hard film 220. The width of the unfilled portion of the trench 212 along the Y direction is now denoted as W3. W2 is equal to the sum of W3 and twice the thickness of the hybrid film 216. That is, W2 = W3 + 2*(T2 + T3).

[0087] Reference Figure 1 and 7Method 100 includes block 110. In block 110, a dielectric fill layer 222 is formed over a hybrid film 216 to substantially completely fill trench 212. The dielectric fill layer 222 is deposited over workpiece 200 using chemical vapor deposition (CVD), subatmospheric chemical vapor deposition (SACVD), flow chemical vapor deposition (FCVD), atomic layer deposition (ALD), spin coating, and / or other suitable processes. The dielectric fill layer 222 is configured to isolate adjacent fin structures 205 and works with a cap layer to cleave gate structures over adjacent fin structures 205. The dielectric fill layer 222 may include silicon oxide, silicon carbide, silicon doped glass (FSG), or other suitable dielectric materials. In some embodiments, the composition of the dielectric fill layer 222 may be similar to the composition of the isolation structure 204. For example, the dielectric fill layer 222 may be formed of silicon oxide. After depositing the dielectric filler layer 222, a planarization process, such as a chemical mechanical polishing (CMP) process, can be performed to planarize the workpiece 200, remove excess material, and expose the top surface of the top layer 210. Therefore, the dielectric filler layer 222 has a width W3 along the Y direction. As depicted herein, the dielectric filler layer 222 is separated from each sidewall of the fin structure 205 by a coating layer 214 and a hybrid film 216.

[0088] Reference Figure 1 and 8 Method 100 includes block 112. In block 112, an etching process 225 is used to selectively etch the hybrid film 216 and the dielectric fill layer 222 to form a trench 226 between two adjacent fin-like structures 205. Figure 8 As shown, the top surfaces of the recessed hybrid film 216 and the recessed dielectric filling layer 222 are substantially coplanar with the topmost channel layer 208. In other words, the resulting trench 226 formed above the recessed dielectric filling layer 222 (between two adjacent fin-like structures 205) has a width equal to W2 and may have a depth corresponding to the thickness of the top layer 210. The etching process 225 may include any suitable process, such as dry etching, wet etching, other suitable processes, or combinations thereof. Trench 226 with different configurations (e.g., shape, size) are described in more detail below. Figure 16 Groove 310 in the middle Figure 22 The groove 405 in the middle, and Figure 26 (Groove 505 in the middle).

[0089] Reference Figure 1 and 9Method 100 includes a block 114. Within block 114, a cap layer 228 is formed in a trench 226. The cap layer 228 is deposited over a workpiece 200 to fill the trench 226 between fin-like structures 205. The cap layer 228 is spaced from the sidewalls of the fin-like structures 205 by a portion of a cladding layer 214 and has a width of W2 along the Y direction. The cap layer 228 can be a high-k dielectric layer and can include aluminum oxide, aluminum nitride, aluminum oxynitride, zirconium oxide, zirconium nitride, aluminum zirconium oxide, hafnium oxide, other high-k materials, or suitable dielectric materials. The cap layer 228 can be deposited using chemical vapor deposition (CVD), atomic layer deposition (ALD), physical vapor deposition (PVD), and / or other suitable processes. The workpiece 200 is then planarized using a chemical mechanical polishing (CMP) process to remove excess cap layer 228 on the top layer 210. In this embodiment, the cap layer 228 is positioned above the fins to provide isolation for the gate structure 254 formed subsequently. In other words, the cap layer 228 is positioned to truncate the gate structure 254 formed in subsequent process steps into multiple portions. The cap layer 228 may be referred to as a gate isolation component or a gate dicing component. At this point, dielectric fins 230 are generally formed. Each dielectric fin 230 includes a cap layer 228 disposed directly above the dielectric fill layer 222 and the hybrid film 216, and has a uniform width W2 from bottom to top.

[0090] Reference Figure 1 , 10 Method 100 includes block 116, 11A, and 11B. In block 116, a dummy gate stack 234 is formed over workpiece 200. Compared to... Figure 10 The workpiece 200 is etched to selectively remove the top layer 210 and a portion of the cladding layer 214 extending along the sidewalls of the top layer 210 to form a trench 232, while the cap layer 228 or the top channel layer 208 is generally not etched. The trench 232 exposes the top channel layer 208 and has a width W along the Y direction. t In some embodiments, the etching process may include a selective dry etching process. In some embodiments, the etching process may include a selective wet etching process (e.g., selective for SiGe), which includes ammonium hydroxide (NH4OH), hydrogen fluoride (HF), hydrogen peroxide (H2O2), or combinations thereof. The partially recessed cladding layer 214 may be referred to as cladding layer 214'. Claddding layer 214' and the topmost channel layer 208 are substantially coplanar.

[0091] Reference Figure 11A , 11BA dummy gate stack 234 is formed over the channel region 205C of the fin structure 205. In this embodiment, a gate replacement process (or post-gate process) is used, wherein the dummy gate stack 234 serves as a placeholder for the functional gate structure 254. Other processes and configurations are possible. Although not explicitly shown, the dummy gate stack 234 may include a dummy dielectric layer and a dummy electrode disposed above the dummy dielectric layer. The region of the fin structure 205 below the dummy gate stack 234 may be referred to as the channel region 205C. Each channel region 205C in the fin structure 205 is sandwiched between the source region 205SD and the drain region 205SD. In some embodiments, the dummy dielectric layer may include silicon oxide, and the dummy electrode may include polysilicon. After forming the dummy gate stack 234, gate spacers 236 may be formed along the sidewalls of the dummy gate stack 234. The gate spacers 236 may include two or more gate spacers. The dielectric material used for the gate spacer 236 can be selected to allow selective removal of the dummy gate stack 234 with minimal damage to the gate spacer 236. Suitable dielectric materials may include silicon nitride, silicon oxycarbonitride, silicon carbide, silicon oxide, silicon carbide, silicon oxynitride, and / or combinations thereof.

[0092] Reference Figure 1 and 11B Method 100 includes block 118. In block 118, an internal spacer 238 and an epitaxial source / drain component 240 are formed in each fin structure 205 adjacent to the dummy gate stack 234. Using the dummy gate stack 234 and the gate spacer 236 as an etching mask, the source / drain regions 205SD of the fin structures 205 of the workpiece 200 are anisotropically etched to form source / drain openings (filled by the source / drain components 240). The anisotropic etching in block 118 may include a dry etching process and may be performed using hydrogen, fluorine-containing gases (e.g., CF4, SF6, CH2F2, CHF3 and / or C2F6), chlorine-containing gases (e.g., Cl2, CHCl3, CCl4 and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases, other suitable gases and / or plasma, and / or combinations thereof. The source / drain openings can extend not only through the stack 207, but also through a portion of the substrate 202.

[0093] After forming the source / drain openings, the sacrificial layer 206 exposed in the source / drain openings is selectively and partially etched to form inner spacer recesses (filled by the inner spacer members 238), while the exposed channel layer 208 is not etched substantially. In some embodiments, selective etching may include a selective isotropic etching process (e.g., a selective dry etching process or a selective wet etching process), and the degree of recess of the sacrificial layer 206 is controlled by the etching time of the etching process. After forming the inner spacer recesses, an inner spacer material layer is compliantly deposited over the workpiece 200, including over and inside the inner spacer recesses, using chemical vapor deposition (CVD) or atomic layer deposition (ALD). The inner spacer material may include silicon nitride, silicon oxycarbonitride, silicon carbide, silicon oxide, silicon carbide, silicon carbide, or silicon oxynitride. After depositing the inner spacer material layer, the inner spacer material layer is etched back to form the inner spacer members 238, such as... Figure 11B As shown.

[0094] Still refer to Figure 1 and 11B Source / drain components 240 are formed in the source / drain openings using epitaxial processes such as vapor phase epitaxy (VPE), ultra-high vacuum chemical vapor deposition (UHV-CVD), molecular beam epitaxy (MBE), and / or other suitable processes. The source / drain components 240 are thus coupled to the channel layer 208 in the channel region 205C of the fin-like structure 205. Depending on the conductivity type of the transistor subsequently formed, the source / drain components 240 can be n-type or p-type source / drain components. Exemplary n-type source / drain components may include silicon, phosphorus-doped silicon, arsenic-doped silicon, antimony-doped silicon, or other suitable materials, and can be in-situ doped during the epitaxial process by introducing an n-type dopant, such as phosphorus, arsenic, or antimony; or ex-situ doped using a junction implant process. Exemplary p-type source / drain components may include germanium, gallium-doped silicon-germanium, boron-doped silicon-germanium, or other suitable materials, and may be in-situ doped during epitaxial processes by introducing p-type dopants, such as boron or gallium; or ex-situ doped using a junction doping process.

[0095] Still refer to Figure 1 and 11BA contact etch stop layer (CESL) 242 and an interlayer dielectric (ILD) layer 244 are deposited above workpiece 200. The contact etch stop layer (CESL) 242 may include silicon nitride, silicon oxynitride, and / or other suitable materials, and may be formed using atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition (PECVD), and / or other suitable deposition or oxidation processes. Figure 11B As shown, a contact etch stop layer (CESL) 242 can be deposited on the top surface of the source / drain component 240 and the sidewalls of the gate spacer 236. After depositing the contact etch stop layer (CESL) 242, an interlayer dielectric (ILD) layer 244 is deposited over the workpiece 200 using a paste-enhanced chemical vapor deposition (PECVD) process or other suitable deposition techniques. The interlayer dielectric (ILD) layer 244 may include a material similar to the isolation structure 204.

[0096] Reference Figure 1 , 12A In 12B, method 100 includes block 120. In block 120, a dummy gate stack 234 is selectively removed. The dummy gate stack 234 is removed to form a trench 246 between two adjacent cap layers 228 and an opening 248 over the channel region 205C. The etching process may include any suitable process, such as a dry etching process, a wet etching process, or a combination thereof, and is configured to selectively remove the dummy gate stack 234 while substantially not removing the cap layer 228, the topmost channel layer 208, the gate spacer 236, the contact etch stop layer (CESL) 242, or the interlayer dielectric (ILD) layer 244. The trench 246 exposes the cladding layer 214' and the topmost channel layer 208. A soft film 218 is disposed directly beneath the cap layer 228.

[0097] Reference Figure 1 , 13AIn 13B, method 100 includes block 122. In block 122, the sacrificial layer 206 is selectively removed by etching process 249 to form a plurality of openings 250 interleaved with channel layer 208, while the channel layer 208 is substantially not removed. In this embodiment, etching process 249 in the channel release process also removes a coating layer 214' having a composition similar to or the same as that of the sacrificial layer 206. In some embodiments, etching process 249 includes a series of etching processes, such as selective dry etching, selective wet etching, or other selective etching processes. In one example, the wet etching process employs an oxidant, such as ammonium hydroxide (NH4OH), ozone (O3), nitric acid (HNO3), hydrogen peroxide (H2O2), other suitable oxidants, and fluorine-based etchants, such as hydrofluoric acid (HF), ammonium fluoride (NH4F), other suitable etchants, or combinations thereof, to selectively remove the sacrificial layer 206 and the coating layer 214'.

[0098] Due to the etching process 249, a portion of the soft film 218 extending along the sidewalls of the cladding layer 214' is also selectively removed along with the cladding layer 214' to form an enlarged trench 252. The hard film 220 is largely left unetched. With the removal of the sacrificial layer 206, the cladding layer 214', and the portion of the soft film 218 extending along the sidewalls of the cladding layer 214', the trench 252 exposes the liner 203, the isolation structure 204, the channel member 208, and the sidewall surfaces of the hard film 220. The remaining soft film 218 may be referred to as soft film 218'. Figure 13A As shown, the soft film 218' is held vertically between the isolation structure 204 and the horizontal or bottom of the hard film 220. The trench 252 exposes the sidewall surface of the soft film 218'. The resulting dielectric fin 230 can be referred to as dielectric fin 230'. Due to the partial removal of the soft film 218, the width of the dielectric fin 230' is no longer uniform. Specifically, the width W2 of the cap layer 228 of the dielectric fin 230' is greater than the width W4 of the remaining portion of the dielectric fin 230'. That is, the cap layer 228 overhangs over the remaining portion of the dielectric fin 230'. The width difference between the cap layer 228 and the remaining dielectric fin 230' is approximately equal to twice the thickness T2 of the soft film 218 (i.e., 2*T2). That is, W2 = W4 + 2*T2. By selectively and partially removing the soft film 218, the etching window for selectively removing the sacrificial layer 206 is enlarged. Therefore, the sacrificial layer 206 can be largely removed without leaving significant residue in the channel region 205C.

[0099] Reference Figure 1 , 14AIn block 14B, method 100 includes block 124. In block 124, a gate structure 254 is formed over workpiece 200 to surround each channel member 208. The gate structure 254 may include an interface layer, a gate dielectric layer above the interface layer, and a gate electrode layer above the gate dielectric layer. In some embodiments, the interface layer may include silicon oxide. Next, a gate dielectric layer is deposited over the interface layer using atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The gate dielectric layer may include a high-k dielectric material. As used herein, a high-k dielectric material includes a dielectric material having a high dielectric constant, for example, greater than that of thermal silicon oxide (~3.9). In one embodiment, the gate dielectric layer may include hafnium oxide. Alternatively, the gate dielectric layer may include other high-k dielectrics, such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicate (HfSiO4), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), yttrium oxide (Y2O3), strontium titanate (SrTiO3; STO), barium titanate (BaTiO3; BTO), barium zirconium oxide (BaZrO), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), barium strontium titanate ((Ba,Sr)TiO3; BST), silicon nitride (SiN), silicon oxynitride (SiON), combinations thereof, or other suitable materials. A gate electrode layer is deposited above the gate dielectric layer. The gate electrode layer can be a multilayer structure comprising at least one work function layer and a metal filling layer. For example, the at least one work function layer may include titanium nitride (TiN), aluminum titanium (TiAl), aluminum titanium nitride (TiAlN), tantalum nitride (TaN), aluminum tantalum (TaAl), aluminum tantalum nitride (TaAlN), aluminum tantalum carbide (TaAlC), tantalum carbonitride (TaCN), or tantalum carbide (TaC). The metal filling layer may include aluminum (Al), tungsten (W), nickel (Ni), titanium (Ti), ruthenium (Ru), cobalt (Co), platinum (Pt), tantalum silicon nitride (TaSiN), copper (Cu), other refractory metals, or other suitable metallic materials, or combinations thereof. In various embodiments, the gate electrode layer can be formed by atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), electron beam evaporation, or other suitable processes. In various embodiments, planarization processes, such as chemical mechanical polishing (CMP), can be performed to remove excess material and provide a generally flat top surface for the gate structure.

[0100] Reference Figure 14A and 14BThe gate structure 254 includes a top 254a disposed above the channel members 208, a bottom 254b surrounding each channel member 208, and a sidewall portion 254c connecting the top 254a and the bottom 254b. The sidewall portion 254c fills the trench 252 and tracks the shape of the trench 252. That is, the sidewall portion 254c is in direct contact with the dielectric fin 230' and is partially disposed directly below the cap layer 228. Specifically, the sidewall portion 254c directly contacts the vertical portion of the hard film 220 extending along the Z direction. The sidewall portion 254c also directly contacts the sidewall of the soft film 218' disposed between the isolation structure 204 and the hard film 220. The dielectric filling layer 222 is spaced apart from the sidewall portion 254c and the soft film 218 by the hard film 220. The sidewall portion 254c may also be referred to as the end cap portion 254c or the gate end cap portion 254c.

[0101] Reference Figure 1 , 15A As shown in 15B, method 100 includes block 124. In block 124, further processes can be performed to complete the fabrication of semiconductor device 200. For example, as... Figures 15A-15B As shown, method 100 may further include etching the gate structure 254 in an etching process to expose the top surface of the cap layer 228. That is, the top surface of the gate structure 254 is lower than the top surface of the cap layer 228. Therefore, the gate structure 254 is truncated into multiple electrically isolated portions. Such further processing may also include forming various contacts / vias, metal lines, power rails, and other multilayer interconnect components, such as interlayer dielectric (ILD) layers and / or etch stop layers (ESL), over the semiconductor device 200, configured to connect the various components to form a functional circuit including different semiconductor devices.

[0102] In the above embodiment, the cap layer 228 has a uniform width W2 and hangs over the remainder of the dielectric fin 230'. That is, the width W2 of the cap layer 228 is greater than the width W4 of the remainder of the dielectric fin 230'. The cap layer 228 can be configured to have different sizes and shapes to further facilitate the flow of chemicals used in the etching process 249 during the channel release process. According to one or more aspects of this disclosure, Figure 16-28 Additional embodiments that further facilitate the removal of the sacrificial layer 206 are shown. For simplicity, the following are omitted. Figure 1 The processes described in boxes 116, 118 and 120.

[0103] Figure 16-20 Shown in Figure 1 During the various manufacturing stages of the method, the exemplary workpiece 300 moves along... Figure 2A first alternative embodiment of the A-A' line. See also... Figure 1 and 16 Method 100 includes block 112. In block 112, an etching process 305 is used to selectively etch the hybrid film 216 and the dielectric filling layer 222 to form trenches 310 between the fin-like structures 205. It is worth noting that, unlike... Figure 8 The workpiece 200 is shown. Similar to workpiece 200, the top surface of the dielectric filling layer 222 in workpiece 300 is coplanar with the topmost channel layer 208; however, unlike workpiece 200, the top surface of the recessed hybrid film 216 is not coplanar with the topmost channel layer 208. Specifically, the top surface of the hybrid film 216 is inclined and higher than the top surface of the topmost channel layer 208. (Refer to...) Figure 16 Following etching process 305, tapered trenches 310 are formed between the fin-like structures 205. Etching process 305 differs from etching process 225 and may include any suitable process, such as dry etching. In some embodiments, etching process 305 may perform any suitable etching, such as fluorinated etchants (e.g., HF, CF4, other fluorinated etchants, or combinations thereof).

[0104] Reference Figure 1 and 17 Method 100 includes a box 114. Within box 114, a helmet layer 312 is formed in a groove 310. The composition and formation of the helmet layer 312 can be similar to... Figure 9 The composition and formation of the cap layer 228 are described. Notably, the cap layer 312 tracks the shape of the trench 310 and has tapered sidewalls 312s. In other words, the bottom surface of the cap layer 312 is aligned with the top surface of the recessed dielectric filling layer 222 and has a width W3; the width W2 of the top surface of the cap layer 312 is greater than the width W3 and is coplanar with the top surface of the top layer 210; the sidewall surfaces of the cap layer 312 are in direct contact with the first film 218 and the second film 220 of the mixing film 216.

[0105] Reference Figure 1 and 18Method 100 includes block 116. In block 116, a portion of the top layer 210 and the cladding layer 214 extending along the sidewalls of the top layer 210 are selectively removed by a suitable etching process to expose the top channel layer 208 of the stack 207. In one embodiment, the etching process may include a dry etching process. In some embodiments, the top surface of the cladding layer 214' and the top channel layer 208 are substantially coplanar. For simplicity, the processes described in blocks 116, 118, and 120 (e.g., forming the dummy gate stack 234, inner spacer 238, source / drain components 240, and contact etch stop layer (CESL) 242 and interlayer dielectric (ILD) layer 244, and selectively removing the dummy gate stack 234) are omitted. Figure 10 In workpieces 200 and 300, at least a portion of the soft membrane 218 is exposed in the groove 315.

[0106] Reference Figure 1 and 19 Method 100 includes block 122. In block 122, etching process 249 selectively removes a portion of the sacrificial layer 206, the cladding layer 214', and the soft film 218 extending along the sidewalls of the cladding layer 214' to release the channel layer 208. Since the trench 315 exposes at least a portion of the soft film 218, the flow path of the etchant used for the channel release process is further expanded, improving etching efficiency and reducing or even substantially eliminating residual SiGe in the channel region 205C. (Refer to...) Figure 19 The dielectric fins 320 in workpiece 300 and the dielectric fins 230' in workpiece 200 (e.g.) Figure 13A (As shown) is different. For example, the sidewall surface of dielectric fin 320 has a tapered top 320t and a generally vertical bottom 320v. The tapered top 320t is the portion of the tapered sidewall 312s of cap layer 312 that is not covered by hard film 220. That is, hard film 220 is in direct contact not only with the sidewalls and bottom surface of dielectric fill layer 222, but also with the bottom sidewall portion of cap layer 312. In the example depicted above, the shape of cap layer 312 in cross-sectional view includes an inverted trapezoid. It is understood that the shape of cap layer 312 may vary slightly due to different etching processes, but at least a portion of cap layer 312 will overhang over hard film 220. Due to the formation of a denser oxide liner 203, etching process 249 does not significantly etch liner 203, providing a satisfactory gate structure 254. It is worth noting that in Figure 19 In this configuration, the soft membrane 218' is also sandwiched between the horizontal or bottom portion of the isolation structure 204 and the hard membrane 220.

[0107] Reference Figure 1 and 20As shown, method 100 includes block 124. In block 124, a gate structure 254 is formed above workpiece 300. Cap layer 312 still hangs over a portion of gate structure 254. Gate structure 254 may also include an inclined portion that is in direct contact with a portion of the tapered sidewall 312s of cap layer 312.

[0108] Figure 21-24 Shown in Figure 1 During the various manufacturing stages of the method, the exemplary workpiece 400 moves along... Figure 2 A second alternative embodiment of the A-A' line. See also... Figure 1 and 21 Method 100 includes box 114. In box 114, in groove 226 ( Figure 8 A cap layer 402 is formed in the trench 226 (shown). Prior to forming the cap layer 402, a second soft film 404 is compliantly deposited over the trench 226. The width of the second soft film 404 may be smaller than the width of the hybrid film 216 (e.g., T2+T3). The formation and material of the second soft film 404 may be similar to those of the soft film 218. In one embodiment, the composition of the second soft film 404 is the same as that of the soft film 218. In some other embodiments, the composition of the second soft film 404 is different from that of the soft film 218. The cap layer 402 is then deposited over the second soft film 404, and the trench 226 is filled. The composition and formation of the cap layer 402 may be similar to... Figure 9 The composition and formation of the cap layer 228 are described. A planarization process can be performed to remove excess material and expose the top surface of the top layer 210. Notably, due to the formation of the second soft film 404, the width W5 of the cap layer 402 is smaller than the width W2 of the cap layer 228 in the workpiece 200. The width W5 can be approximately equal to or greater than the width W3 to provide satisfactory isolation between the multiple portions of the subsequently formed gate structure, while also providing an expanded flow path for the channel release process.

[0109] Reference Figure 1 and 22 When workpiece 400 is operated in block 116 of method 100, a portion of the top layer 210, a portion of the cladding layer 214 extending along the sidewall of the top layer 210, and a portion of the second soft film 404 in direct contact with the cladding layer 214 are selectively removed to expose the top channel layer 208 of the stack 207, and a trench 405 is formed. The width of the trench 405 is greater than... Figure 12A The width of the trench 246 shown. The cladding layer 214' and the topmost channel layer 208 are substantially coplanar. After the above selective etching process, the remaining second soft film 404 can be referred to as the second soft film 404'. The second soft film 404' is disposed directly below the cap layer 402. The trench 405 exposes at least a portion of the top surface of the soft film 218.

[0110] Reference Figure 1 and 23 Method 100 includes block 122. In block 122, a portion of the sacrificial layer 206, the cladding layer 214', and the soft film 218 extending along the sidewall of the cladding layer 214' are selectively removed by etching process 249 to release the channel layer 208 as a channel member 208. Since the width W5 of the cap layer 402 is smaller than the width W2 of the cap layer 228, and the trench 405 exposes at least a portion of the top surface of the soft film 218, the flow path of the etchant for the channel release process is expanded without changing the footprint, thus improving etching efficiency and reducing or even substantially eliminating SiGe residue in the channel region 205C.

[0111] Reference Figure 1 and 24 Method 100 includes block 124. In block 124, a gate structure 254 is formed above workpiece 300. The final structure of the corresponding dielectric fin 420 in workpiece 400 differs from the final structure of the dielectric fin 230' in workpiece 200. For example, the dielectric fin 420 further includes a second soft film 404' disposed directly above the top surface of the dielectric fill layer 222 and the hard film 220. The width of the dielectric fin 420 is approximately uniform when the width W5 is approximately equal to W4, and the gate structure 254 is in direct contact with and parallel to the dielectric fin 420. Specifically, the soft film 218', the hard film 220, the soft film 404', and the cap layer 402 are in direct contact with the gate structure 254.

[0112] Figure 25-28 Shown in Figure 1 During the various manufacturing stages of the method, the exemplary workpiece 500 moves along... Figure 2 A third alternative embodiment of the A-A' line. See also... Figure 1 and 25 Method 100 includes a box 114. Within box 114, in the groove 226 (e.g., Figure 8 A cap layer 502 is formed in the trench 226. Before forming the cap layer 502 in the trench 226, a third soft film 504 is deposited over the workpiece 500, followed by etching back the third soft film 504 to cover only the sidewalls of the portion of the coating layer 214 exposed in the trench 226. The formation and material of the third soft film 504 can be similar to that of the soft film 218. The cap layer 502 can then be deposited over the workpiece 500 and fill the trench 226. The composition and formation of the cap layer 502 can be similar to... Figure 9The cap layer 228 is described. A planarization process can be performed to remove excess material and expose the top surface of the top layer 210. Notably, due to the formation of the third soft film 504, the width W6 of the cap layer 502 is smaller than the width W2 of the cap layer 228. The width W6 can be approximately equal to the width W3 to provide satisfactory isolation between the multiple portions of the subsequently formed gate structure, while also providing an expanded flow path for the channel release process.

[0113] Reference Figure 1 and 26 The topmost layer 210 is selectively removed to expose the topmost channel layer 208 of the stack 207. In the selective etching process described above, a portion of the cladding layer 214 extending along the sidewalls of the topmost layer 210 and the entire third soft film 504 are also selectively removed to form trenches 505. Due to the formation and removal of the third soft film 504, the width of trench 505 is greater than the width W of trench 232. t (like Figure 10 (As shown). The cladding layer 214' and the topmost channel layer 208 are generally coplanar. The trench 505 exposes at least a portion of the top surface of the soft membrane 218.

[0114] Reference Figure 1 and 27 Method 100 includes block 122. In block 122, a portion of the sacrificial layer 206, the cladding layer 214', and the soft film 218 extending along the sidewall of the cladding layer 214' are selectively removed by an etching process 249 to release the channel layer 208. Since the width W6 of the cap layer 502 is smaller than the width W2 of the cap layer 228, the flow path of the etchant used in the channel release process is widened, which is beneficial to etching efficiency and reduces or even substantially eliminates residues in the channel region 205C.

[0115] Reference Figure 1 and 28 Method 100 includes block 124. In block 124, a gate structure 254 is formed above workpiece 300. The final structure of the corresponding dielectric fin 520 in workpiece 500 is different from the final structure of the dielectric fin 230' in workpiece 200. In one embodiment, W6 can be greater than W3 and less than W4. That is, a portion of the gate structure 254 is disposed directly above the hard film 220.

[0116] While not intended to be limiting, one or more embodiments of this disclosure provide several advantages for semiconductor devices and methods of forming the same. For example, this disclosure provides a method for configuring an isolation structure to cut off a gate structure into multiple portions. The method employs a hybrid film comprising two films with different etch rates relative to the etch process used in the channel release process. By selectively removing portions of the hybrid film, the etch window for the channel release process is expanded without sacrificing the width of the channel elements or substantially affecting the electrical isolation between two adjacent gate structures. Embodiments of the methods disclosed herein can be readily integrated into existing processes and techniques for manufacturing multi-bridge channel field-effect transistors (MBC FETs), fin field-effect transistors (FinFETs), and / or other suitable devices.

[0117] This disclosure provides for many different embodiments. This document discloses semiconductor structures and methods of manufacturing thereof. In one exemplary aspect, this disclosure relates to a semiconductor structure. The semiconductor structure includes: a plurality of first channel members above a substrate; a first gate structure surrounding each of the first channel members; and a dielectric fin structure disposed adjacent to the first gate structure. The dielectric fin structure includes: a first dielectric layer disposed above the substrate and in direct contact with the first gate structure; a second dielectric layer disposed above the first dielectric layer; a third dielectric layer disposed above the second dielectric layer and spaced apart from the first dielectric layer and the first gate structure by the second dielectric layer; and a first isolation member disposed directly above the third dielectric layer.

[0118] In some embodiments, a portion of the first gate structure is disposed directly below the first isolation member. In some embodiments, the semiconductor structure described above may further include: a plurality of second channel members above the substrate; and a second gate structure surrounding each of the second channel members, the second gate structure being spaced from the first gate structure by a dielectric fin structure.

[0119] In some embodiments, the semiconductor structure may include a second isolation member disposed above the substrate. The dielectric fin structure is disposed above the second isolation member and in direct contact with the second isolation member.

[0120] In some embodiments, the second isolation component may include: an oxide liner; and an oxide filler layer disposed above the oxide liner. A portion of the first gate structure described above is in direct contact with the oxide liner.

[0121] In some embodiments, the carbon concentration of the second dielectric layer is greater than that of the first dielectric layer. In some embodiments, the first dielectric layer comprises silicon nitride (SiN) or silicon carbon oxynitride (SiOCN). In some embodiments, the second dielectric layer comprises silicon carbon oxynitride (SiCN), silicon carbon oxynitride (SiOCN), or boron nitride (BN).

[0122] In some embodiments, the dielectric fin structure described above may include a fourth dielectric layer disposed between the third dielectric layer and the first isolation member, and the fourth dielectric layer includes silicon nitride (SiN) or silicon oxynitride (SiOCN).

[0123] In another exemplary aspect, this disclosure relates to a semiconductor structure. The semiconductor structure includes: a plurality of first nanostructures and a plurality of second nanostructures extending longitudinally above a substrate along a first direction; a first isolation member disposed between the first and second nanostructures and extending longitudinally along the first direction; and a second isolation member disposed directly above the first isolation member. The second isolation member overhangs the first isolation member along a second direction perpendicular to the first direction.

[0124] In some embodiments, the semiconductor structure may include: a first gate structure surrounding each of the first nanostructures; and a second gate structure surrounding each of the second nanostructures. The second gate structure is separated from the first gate structure by a first isolation member and a second isolation member, and each of the first gate structure and the second gate structure includes a portion disposed directly below the second isolation member.

[0125] In some embodiments, the first isolation member includes: a first dielectric layer disposed above a substrate; a second dielectric layer disposed above the first dielectric layer; and a third dielectric layer disposed on a sidewall of the second dielectric layer. The second dielectric layer is spaced apart from the first gate structure and the second gate structure by the third dielectric layer.

[0126] In some embodiments, for a wet etching process including the use of ammonium hydroxide and hydrofluoric acid, the etching rate of the first dielectric layer is greater than the etching rate of the third dielectric layer. In some embodiments, the first gate structure and the second gate structure each include a top surface that is lower than the top surface of the second isolation member.

[0127] In some embodiments, the semiconductor structure described above may include a source component and a drain component. A first nanostructure extends between the source component and the drain component along a first direction. In some embodiments, a second isolation component includes tapered sidewalls.

[0128] In another exemplary aspect, this disclosure relates to a method for forming a semiconductor structure. The method for forming the semiconductor structure includes: forming a plurality of semiconductor fin-like stacks protruding from a substrate, each of the semiconductor fin-like stacks comprising alternating vertical stacks of a plurality of first semiconductor layers and a plurality of second semiconductor layers; forming a cladding layer along the sidewalls of each of the semiconductor fin-like stacks; compliantly depositing a hybrid film layer over the substrate, the hybrid film layer comprising: a first film layer; and a second film layer on the first film layer; forming a first dielectric layer over the substrate to fill the space between adjacent semiconductor fin-like stacks; selectively etching the first dielectric layer and the hybrid film layer to form trenches; forming isolation members in the trenches; selectively removing the cladding layer, a portion of the first film layer extending along the sidewalls of the cladding layer, and the second semiconductor layer to form a plurality of openings; and forming gate structures in the openings.

[0129] In some embodiments, after selectively etching the first dielectric layer, the top surface of the hybrid film layer is substantially coplanar with the topmost first semiconductor layer of the semiconductor fin stack.

[0130] In some embodiments, forming an isolation member in the trench includes: depositing a second dielectric layer over a substrate; forming a third dielectric layer over the second dielectric layer; and performing a planarization process to remove excess material and expose a top surface of the cladding layer. The second dielectric layer includes silicon nitride (SiN) or silicon oxynitride (SiOCN).

[0131] In some embodiments, the method of forming the semiconductor structure described above may further include: forming a top sacrificial layer directly above each of the semiconductor fin stacks before conformally depositing a hybrid film layer; selectively removing the top sacrificial layer and a portion of the cladding layer in direct contact with the top sacrificial layer after forming an isolation component in a trench; and performing an etching process to selectively remove the remaining portion of the cladding layer, a portion of a second film layer extending along the sidewalls of the cladding layer, and a second semiconductor layer to form a plurality of openings.

[0132] The foregoing outlines the features of several embodiments to enable those skilled in the art to better understand the viewpoints of the embodiments of the present invention. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments of the present invention to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent processes and structures do not depart from the concept and scope of the present invention, and various changes, substitutions, and replacements can be made without departing from the concept and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the claims.

Claims

1. A semiconductor structure, comprising: Multiple first channel components are located above a substrate; A first gate structure surrounds each of the first channel components; as well as A dielectric fin structure is disposed adjacent to the first gate structure, the dielectric fin structure comprising: A first dielectric layer is disposed above the substrate and in direct contact with the first gate structure; A second dielectric layer is disposed above the first dielectric layer; A third dielectric layer is disposed above the second dielectric layer and spaced apart from the first dielectric layer and the first gate structure by the second dielectric layer; and A first isolation component is disposed directly above the third dielectric layer, wherein the carbon concentration of the second dielectric layer is greater than the carbon concentration of the first dielectric layer.

2. The semiconductor structure of claim 1, wherein a portion of the first gate structure is disposed directly below the first isolation member.

3. The semiconductor structure as described in claim 1, further comprising: Multiple second channel components are located above the substrate; as well as A second gate structure surrounds each of the second channel members, wherein the second gate structure is separated from the first gate structure by the dielectric fin structure.

4. The semiconductor structure as described in claim 1, further comprising: A second isolation component is disposed above the substrate; The dielectric fin structure is disposed above the second isolation component and is in direct contact with the second isolation component.

5. The semiconductor structure as described in claim 4, The second isolation component includes: Oxide liner; and An oxide filler layer is disposed above the oxide liner; as well as A portion of the first gate structure is in direct contact with the oxide liner.

6. The semiconductor structure of claim 1, wherein the first dielectric layer comprises silicon nitride or silicon oxynitride.

7. The semiconductor structure of claim 1, wherein the second dielectric layer comprises silicon carbide, silicon oxynitride, or boron nitride.

8. The semiconductor structure of claim 1, wherein the dielectric fin structure further comprises: A fourth dielectric layer is disposed between the third dielectric layer and the first isolation component, and the fourth dielectric layer comprises silicon nitride or silicon oxynitride.

9. A semiconductor structure, comprising: Multiple first nanostructures and multiple second nanostructures are disposed above a substrate and extend longitudinally along a first direction; A first isolation component is disposed between the first nanostructures and the second nanostructures and extends longitudinally along the first direction; as well as A second isolation component is disposed directly above the first isolation component; The second isolation component is suspended above the first isolation component along a second direction perpendicular to the first direction, wherein the first isolation component includes: A first dielectric layer is disposed above the substrate; as well as A second dielectric layer is disposed above the first dielectric layer, wherein the carbon concentration of the second dielectric layer is greater than the carbon concentration of the first dielectric layer.

10. The semiconductor structure of claim 9, further comprising: A first gate structure surrounds each of the first nanostructures; as well as A second gate structure surrounds each of the second nanostructures, the second gate structure being separated from the first gate structure by the first isolation component and the second isolation component; The first gate structure and the second gate structure each include a portion disposed directly below the second isolation component.

11. The semiconductor structure of claim 10, wherein the first isolation component further comprises: A third dielectric layer is disposed on the sidewall of the second dielectric layer; The third dielectric layer is spaced apart from the first gate structure and the second gate structure by the second dielectric layer.

12. The semiconductor structure of claim 11, wherein for a wet etching process including the use of ammonium hydroxide and hydrofluoric acid, the etching rate of the first dielectric layer is greater than the etching rate of the second dielectric layer.

13. The semiconductor structure of claim 10, wherein the first gate structure and the second gate structure each include a top surface that is lower than a top surface of the second isolation member.

14. The semiconductor structure of claim 9, further comprising: A source component and a drain component, wherein the first nanostructures extend between the source component and the drain component along the first direction.

15. The semiconductor structure of claim 9, wherein the second isolation component includes a tapered sidewall.

16. A method for forming a semiconductor structure, comprising: Multiple semiconductor fin stacks protruding from a substrate are formed, each of the semiconductor fin stacks comprising alternating vertical stacks of multiple first semiconductor layers and multiple second semiconductor layers; A coating layer is formed along the sidewalls of each of the semiconductor fin-like stacks; A hybrid film layer is deposited compliantly over the substrate, the hybrid film layer comprising: A first film layer; and A second film layer is placed on top of the first film layer; A first dielectric layer is formed on the substrate to fill the space between two adjacent semiconductor fin stacks; Selectively etch the first dielectric layer and the hybrid film layer to form a trench; A cap layer is formed in the trench; Selectively remove the coating layer, a portion of the first film layer extending along the sidewalls of the coating layer, and the second semiconductor layer to form a plurality of openings; and A gate structure is formed in these openings.

17. The method of forming a semiconductor structure as claimed in claim 16, wherein after selectively etching the first dielectric layer, a top surface of the hybrid film layer is substantially coplanar with a topmost first semiconductor layer of the semiconductor fin-like stack.

18. The method of forming a semiconductor structure as claimed in claim 16, wherein forming the cap layer in the trench comprises: A second dielectric layer is deposited compliantly on the substrate; A third dielectric layer is formed above the second dielectric layer; as well as A planarization process is performed to remove excess material and expose a top surface of the coating layer; The second dielectric layer includes silicon nitride or silicon oxynitride.

19. The method for forming a semiconductor structure as described in claim 16, further comprising: Before conformally depositing the hybrid film, a topmost sacrificial layer is formed directly above each of the semiconductor fin stacks; After the cap layer is formed in the trench, the topmost sacrificial layer and a portion of the covering layer that is in direct contact with the topmost sacrificial layer are selectively removed; as well as An etching process is performed to selectively remove the remaining portion of the coating layer, the portion of the first film layer extending along the sidewalls of the coating layer, and the second semiconductor layers to form a plurality of openings.

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