Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device and a method of fabricating the same include providing a fin extending from a substrate, where the fin includes an epitaxial layer stack having a plurality of semiconductor channel layers interspersed by a plurality of dummy layers. In some embodiments, the method further includes removing a portion of the epitaxial layer stack within a source / drain region of the semiconductor device to form a trench in the source / drain region, the trench exposing the semiconductor channel layers and a plurality of lateral surfaces of the dummy layers. After forming the trench, in some examples, the method further includes performing a dummy layer recess process to laterally etch a plurality of ends of the dummy layers and form a plurality of first recesses along sidewalls of the trench. In some embodiments, the method further includes conformally forming a cap layer along the exposed lateral surfaces of the semiconductor channel layers and within the first recesses.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices, and more particularly to multi-gate devices. Background Technology

[0002] The electronics industry has experienced a growing demand for smaller and faster electronic devices that can support increasingly complex and sophisticated functionality. Therefore, there has been a persistent trend in the semiconductor industry towards manufacturing low-cost, high-performance, and low-power integrated circuits (ICs). To date, these goals have largely been achieved by miniaturizing semiconductor IC dimensions (e.g., minimum component size), thereby improving production efficiency and reducing associated costs. However, this miniaturization has also increased the complexity of semiconductor manufacturing processes. Therefore, continued progress in semiconductor ICs and devices requires similar advancements in semiconductor manufacturing processes and technologies.

[0003] Recently, multi-gate devices have been introduced to attempt to improve gate control by increasing gate channel coupling, reducing off-state current, and mitigating short-channel effects (SCEs). One such multi-gate device is the fin field-effect transistor (FinFET). The name FinFET comes from its fin-like structures extending from the substrate, which form the channels of the FET. Another multi-gate device introduced to address the performance challenges associated with FinFETs is the gate-all-around (GAA) transistor. The name GAA comes from its gate structure, which extends completely around the channel, providing better electrostatic control than FinFETs. Fin field-effect transistors and fully wound gate transistors are compatible with conventional complementary metal-oxide-semiconductor (CMOS) processes, and their three-dimensional structure allows for radical miniaturization while maintaining gate control and mitigating short-channel effects (SCEs).

[0004] Generally, when fin field-effect transistors (FETs) no longer meet device performance requirements, fully wound gate transistors (WWTs) can be implemented as a substitute. However, the fabrication of WWTs introduces new challenges to semiconductor manufacturing processes and leads to related device reliability issues. Therefore, existing technologies have not yet proven to be completely satisfactory in all aspects. Summary of the Invention

[0005] This disclosure provides a method for manufacturing a semiconductor device, comprising providing a fin extending from a substrate, wherein the fin includes an epitaxial layer stack having a plurality of semiconductor channel layers interspersed by a plurality of dummy layers; removing a portion of the epitaxial layer stack within a source / drain region of the semiconductor device to form a trench in the source / drain region, the trench exposing the semiconductor channel layers and a plurality of lateral surfaces of the dummy layers; after forming the trench, performing a dummy layer recess process to laterally etch a plurality of ends of the dummy layers and form a plurality of first grooves along the sidewalls of the trench; and conformally forming a capping layer along the lateral surfaces exposed by the semiconductor channel layers and within the first grooves.

[0006] This disclosure provides a method for manufacturing a semiconductor device, comprising providing a fin structure, wherein a plurality of epitaxial layers comprising a first component are interpenetrated by a plurality of epitaxial layers comprising a second component, wherein the epitaxial layers comprising the first component are at least twice as thick as the epitaxial layers comprising the second component; forming a dummy gate over the fin structure and forming spacer layers on a plurality of sidewalls of the dummy gate; etching a plurality of lateral ends of the epitaxial layers comprising the first component to form a plurality of grooves, the grooves being disposed below the spacer layers and between a plurality of adjacent epitaxial layers comprising the second component; and forming a silicon capping layer on the opposite ends of the epitaxial layers comprising the second component and within the grooves.

[0007] This disclosure provides a semiconductor device comprising a fin extending from a substrate, wherein the fin includes a plurality of semiconductor channel layers, and each of the semiconductor channel layers includes a channel region and a lightly doped drain region; a capping layer surrounding the lightly doped drain region of each of the semiconductor channel layers; and a plurality of inner spacers disposed between a plurality of first portions of the capping layer, the first portions of the capping layer being disposed in the lightly doped drain regions of a plurality of adjacent semiconductor channel layers; wherein a first thickness of the semiconductor channel layer in the lightly doped drain region, combined with a second thickness of the capping layer, provides an effective thickness of the semiconductor channel layer in the lightly doped drain region, and wherein the effective thickness is greater than a third thickness of the semiconductor channel layer in the channel region. Attached Figure Description

[0008] The embodiments of this disclosure can be best understood from the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale and are for illustrative purposes only. In fact, the dimensions of various components can be arbitrarily enlarged or reduced to clearly demonstrate the features of the embodiments of this disclosure.

[0009] Figure 1A simplified top view layout schematic diagram of a multi-gate device is provided according to some embodiments.

[0010] Figure 2 This is a schematic flowchart illustrating a method for manufacturing a semiconductor device 300, based on one or more aspects of this disclosure.

[0011] Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10A , Figure 10B , Figure 10C , Figure 11A , Figure 11B , Figure 11C as well as Figure 12 According to some embodiments, embodiments of the semiconductor device 300 are provided along substantially parallel to the... Figure 1 A schematic cross-sectional view of the plane defined by section A-A'.

[0012] The reference numerals in the attached figures are explained as follows: 100: Multi-gate device 104: Fin element 105: Source / Drain Region 107: Source / Drain Region 108: Gate structure 200: Method 202: Block 204: Block 206: Block 208: Block 210: Block 212: Block 214: Block 216: Block 218: Block 220: Block 300: Semiconductor Devices 304: Substrate 304A: The substrate portion of the fins 306: Fins 308: Epitaxial layer 310: Epitaxial layer 316: Gate Stack 320: Dielectric layer 322: Electrode layer 328: Spacer layer 330: Trench 402: Groove 405: Dashed line 502: Cap layer 602: Internal spacer 702: Groove 802: Source / Drain Components 804: Hole 902: Gap 904: Concave profile 1002: Surface 1004: Surface 1102: Gate dielectric 1104: Metallic layer 1105: Hole A-A': Cross section a: Thickness b: Thickness b1: Thickness c: Thickness W1: Width W2: Width W3: Width W4: Width W5: Width Detailed Implementation

[0013] The following disclosure provides numerous embodiments or examples for implementing different elements of the provided subject matter. Specific examples of each element and its configuration are described below to simplify the description of embodiments of this disclosure. Of course, these are merely examples and are not intended to limit the embodiments of this disclosure. For example, if the description refers to a first element formed on a second element, it may include embodiments where the first and second elements are in direct contact, or embodiments where an additional element is formed between the first and second elements such that they are not in direct contact. Furthermore, reference values ​​and / or letters may be repeated in various examples of embodiments of this disclosure. Such repetition is for the purpose of brevity and clarity and is not intended to indicate a relationship between the different embodiments and / or configurations discussed.

[0014] Furthermore, spatially relative terms may be used, such as "below," "below," "lower," "above," "higher," etc., to facilitate the description of the relationship between one or more components or features in the diagram. Spatially relative terms are used to include different orientations of the device in use or operation, as well as the orientations described in the diagram. When the device is turned to different orientations (rotated 90 degrees or other orientations), the spatially relative adjectives used will also be interpreted according to the orientation after the turn.

[0015] It is also noteworthy that this disclosure presents several embodiments in the form of multi-gate transistors. Multi-gate transistors include those transistors in which gate structures are formed on at least two sides of a channel region. These multi-gate devices may include P-type metal-oxide-semiconductor devices or N-type metal-oxide-semiconductor multi-gate devices. Due to their fin-like structure, this disclosure may present specific examples and which are referred to as FinFETs. This disclosure also presents several embodiments of a type of multi-gate transistor, referred to as a fully wrapped gate (GAA) transistor. A fully wrapped gate transistor includes any device having a gate structure or a portion of a gate structure formed on the four sides of a channel region (e.g., around a portion of the channel region). The devices presented in this disclosure also include several embodiments having a channel region disposed within a semiconductor channel layer. In various embodiments, the semiconductor channel layer may include nanosheet channels, nanowire channels, bar-shaped channels, and / or other suitable channel configurations. The various embodiments of the devices presented in this disclosure may have one or more channel regions (e.g., multiple semiconductor channel layers) associated with a single, continuous gate structure. However, those skilled in the art to which this disclosure pertains will understand that this teaching can be applied to a single channel (e.g., a single semiconductor channel layer) or any number of channels. Those skilled in the art to which this disclosure pertains will understand other examples of semiconductor devices from which various aspects of this disclosure may benefit.

[0016] In at least some existing embodiments, current crowding in the lightly-doped drain (LDD) region remains a problem, and strain efficiency from the source / drain (S / D) region to the channel region has been consistently poor. This is partly due to various process-related issues. For example, in some cases, removing a thin dummy layer (interlaced with adjacent semiconductor channel layers) during replacement gate (RPG) processes can be very difficult. Furthermore, non-uniform film thickness (e.g., the thickness of the semiconductor channel layer) can degrade device performance; this non-uniformity may in some cases be due to sheet trimming processes performed during replacement gate processes to form H-shaped (or dog-bone shaped) semiconductor channel layers.

[0017] This disclosure provides several advantages over those in the prior art. It should be understood that not all advantages are necessarily discussed herein, nor are all embodiments required to possess specific advantages, and other embodiments may offer different advantages. For example, embodiments described in this disclosure include several methods and structures for providing a multi-gate device (e.g., providing a fully wound gate transistor) with an H-shaped (or dog-bone shaped) semiconductor channel layer while overcoming various prior art challenges. In some examples, devices fabricated according to embodiments of this disclosure provide better current distribution in the lightly doped drain region (LDD), which in turn results in a reduction in resistance (e.g., R0). ov R extension At least some embodiments also provide stronger channel strain efficiency from source / drain stressors. Furthermore, various embodiments provide good short-channel control by maintaining a thin sheet height structure (e.g., a thin semiconductor channel layer).

[0018] In some embodiments, within an epitaxially grown superlattice (e.g., a superlattice comprising alternating multiple semiconductor channel layers and multiple dummy layers), there may be a thin semiconductor channel layer thickness, while having less (or no) wafer trimming during gate replacement (RPG), thereby improving the uniformity of the semiconductor channel layer thickness. Furthermore, in some embodiments, a thinner semiconductor channel layer thickness may correspond to a thicker dummy layer thickness, wherein a thicker dummy layer facilitates the removal of the dummy layer during gate replacement and improves the filling of the metal gate gap or the patterning of the multi-work function metal.

[0019] In various embodiments, H-shaped (or dog-bone shaped) semiconductor channel layers can be formed during source / drain processes (e.g., during source / drain etching processes and optionally subsequent dummy layer etching processes). Generally, in some embodiments, a thicker semiconductor channel layer (at least partially defining the H-shape or dog-bone shape) located beneath the gate sidewall spacers can be used to reduce the risk of current congestion, while also providing a more uniform semiconductor channel layer (e.g., due to less wafer trimming) for better short-channel control. Furthermore, at least some aspects of the various embodiments and advantages discussed in this disclosure are achieved by using an additional silicon (Si) capping layer formed before the dummy layer is etched and after the formation of the inner spacers, as discussed in this disclosure. In some examples, the additional silicon capping layer can also help prevent damage to the inner spacers and the source / drain during the dummy layer removal process. In some cases, the additional silicon capping layer may facilitate the formation of a thicker semiconductor channel layer beneath the gate sidewall spacers.

[0020] Generally, in some embodiments, devices manufactured according to the various methods of this disclosure can provide: (i) uniform and thin wafer thickness during the formation of the superlattice (semiconductor channel layer dummy layer); (ii) improved wafer formation and patterning process of the work function metal during gate replacement (RPG) (e.g., a thicker dummy layer can be provided due to the thinner semiconductor channel layer, while the overall height of the device remains substantially constant); (iii) a more uniform wafer height along the channel due to less (or no) wafer trimming during gate replacement; (iv) stronger channel strain efficiency from source / drain stress sources due to the H-shaped (or dog-bone) semiconductor channel layer beneath the spacers; (v) less current congestion due to the extended regions of the H-shaped (or dog-bone) semiconductor channel layer; and (vi) better R-values ​​due to surface passivation and a better interface between the inner spacers and the semiconductor channel layer (e.g., fewer defects / dits). ov / R extension The resistors (vii) are etched as self-limited (e.g., as an etch stop layer) during the dummy wafer (dummy layer) removal process, and (viii) during dummy layer removal, the risk of gate-to-source / drain and / or gate-to-MD leakage current is reduced due to less internal spacer loss and source / drain epitaxial damage. Other embodiments and advantages will be apparent to those skilled in the art to which this disclosure pertains upon reading this disclosure.

[0021] For the purposes of the following discussion, Figure 1 A simplified top-view layout schematic of a multi-gate device 100 is provided. In various embodiments, the multi-gate device 100 may include fin field-effect transistor (FinFET) devices, fully wrapped gate (GAA) devices, or other types of multi-gate devices. The multi-gate device 100 may include a plurality of fin elements 104 extending from a substrate; a gate structure 108 disposed above and surrounding the fin elements 104; and source / drain regions 105, 107, wherein the source / drain regions 105, 107 are formed in, on, and / or surrounding the fin elements 104. Channel regions of the multi-gate device 100 (which may include a plurality of semiconductor channel layers (e.g., when the multi-gate device 100 includes a fully wrapped gate transistor)) are disposed within the fin elements 104, below the gate structure 108, and along substantially parallel to the... Figure 1 The plane defined by cross section A-A'. In some embodiments, sidewall spacers may also be formed on the multiple sidewalls of the gate structure 108. Various other components of the multi-gate device 100 will be described below. Figure 2 The methods will be discussed in more detail.

[0022] See Figure 2 According to various embodiments, Figure 2 The illustration depicts a method 200 for manufacturing a semiconductor, including manufacturing a semiconductor device 300 (e.g., a multi-gate device). Method 200 will be discussed below with reference to the manufacture of a fully wound gate (GAA) transistor. However, it should be understood that various aspects of method 200 can be equally applied to other types of multi-gate devices, or to other types of devices implemented by multi-gate devices, without departing from the scope of this disclosure. In some embodiments, method 200 can be used to manufacture semiconductors as described above. Figure 1 The multi-gate device 100 is described above. Therefore, one or more aspects discussed above regarding the multi-gate device 100 are equally applicable to method 200. It should be understood that method 200 includes steps characteristic of a complementary metal-oxide-semiconductor (CMOS) technology process flow, and therefore are only briefly described in this disclosure. Additionally, extra steps may be performed before, during, and / or after method 200.

[0023] More notably, in some embodiments, the semiconductor device 300 may include various other devices and components, such as other types of devices, such as additional transistors, bipolar junction transistors (BJTs), resistors, capacitors, inductors, diodes, fuses, and / or other logic circuits, but these are simplified for a better understanding of the inventive concept of this disclosure. In some embodiments, the semiconductor device 300 includes multiple interconnectable semiconductor devices (e.g., transistors). Furthermore, it is worth noting that the process steps of method 200, including any descriptions given with reference to the figures, are merely illustrative and are not intended to limit this disclosure beyond the scope expressly stated in the claims.

[0024] Method 200 begins at block 202, which provides a substrate comprising a partially manufactured device. See also Figure 3 For example, in the embodiment of block 202, a partially manufactured apparatus 300 is provided. Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 , Figure 8 , Figure 9 , Figure 10A , Figure 10B , Figure 10C , Figure 11A , Figure 11B , Figure 11C as well as Figure 12An embodiment of semiconductor device 300 is provided along substantially parallel to the... Figure 1 A schematic cross-sectional view of the plane defined by section A-A' (e.g., along the direction of fin 306). Device 300 may be formed on substrate 304. In some embodiments, substrate 304 may be a semiconductor substrate, such as a silicon substrate. Substrate 304 may include various film layers, including conductive or insulating layers formed on the semiconductor substrate. Substrate 304 may include various doping configurations, depending on design requirements known in the art to which this disclosure pertains. Substrate 304 may also include other semiconductors, such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond. Alternatively, substrate 304 may include compound semiconductors and / or alloy semiconductors. Furthermore, substrate 304 may optionally include an epitaxial layer (epi-layer), which may be strained to enhance performance, may include a silicon-on-insulator (SOI) structure, and / or have other suitable reinforcing components.

[0025] like Figure 3 As illustrated, device 300 includes a fin 306 having a substrate portion 304A (formed from substrate 304), a first-component epitaxial layer 308, and a second-component epitaxial layer 310 intersecting the first-component epitaxial layer 308. In some cases, shallow trench isolation (STI) components may be formed to isolate the fin 306 from adjacent fins. For the purposes of this disclosure, the first-component epitaxial layer 308 includes the aforementioned dummy layer, while the second-component epitaxial layer 310 includes the aforementioned semiconductor channel layer. In an embodiment, the first-component epitaxial layer 308 comprises SiGe, while the second-component epitaxial layer 310 comprises silicon (Si). It is also noteworthy that although the first-component epitaxial layer 308 and the second-component epitaxial layer 310 are illustrated within the fin 306 as having a specific stacking order, with the second-component epitaxial layer 310 being the top layer of the stack of epitaxial layers 308 and 310, other configurations are also possible. For example, in some cases, the first component epitaxial layer 308 may alternatively become the top layer of the stack of epitaxial layers 308 and 310. In other words, the growth order and stacking order of the first component epitaxial layer 308 and the second component epitaxial layer 310 may be switched or differ from those shown in the figures of this disclosure, while remaining within the scope of this disclosure.

[0026] In various embodiments, epitaxial layer 310 (e.g., containing a second component) or multiple portions of epitaxial layer 310 may be formed as channel regions of a fully wound gate (GAA) transistor of device 300. For example, as mentioned above, epitaxial layer 310 may be referred to as a semiconductor channel layer, which is used to form channel regions of a fully wound gate transistor. In various embodiments, the semiconductor channel layer (e.g., epitaxial layer 310 or multiple portions thereof) may include nanosheet channels, nanowire channels, strip channels, and / or other suitable channel configurations. In some embodiments, the semiconductor channel layer may also be used to form multiple portions of the source / drain components of a fully wound gate transistor.

[0027] It is worth noting that although fin 306 is depicted as comprising three (3) epitaxial layers 308 and three (3) epitaxial layers 310, this is for illustrative purposes only and is not intended to limit the present disclosure beyond the scope expressly stated in the claims. It will be understood that any number of epitaxial layers may be formed, for example, depending on the number of semiconductor channel layers required for a fully wrapped gate (GAA) transistor. In some embodiments, the number of epitaxial layers 310, i.e., the number of semiconductor channel layers, is between 3 and 10.

[0028] In some embodiments, each of the first component epitaxial layer 308 (dummy layer) has a thickness ranging from about 5 nanometers to about 15 nanometers. In some cases, each of the second component epitaxial layer 310 (semiconductor channel layer) has a thickness ranging from about 5 nanometers to about 15 nanometers. As mentioned above, the epitaxial layer 310 may serve as a plurality of channel regions of a subsequently formed multi-gate device (e.g., a fully wound gate (GAA) transistor), and the thickness of the epitaxial layer 310 may be selected at least in part based on device performance considerations. The epitaxial layer 308 may serve as a gap distance defining the adjacent (plural) channel regions of a subsequently formed multi-gate device, and the thickness of the epitaxial layer 308 may also be selected at least in part based on device performance considerations. In some embodiments, the thickness of the epitaxial layer 310 (semiconductor channel layer) may be less than the thickness of the epitaxial layer 308 (dummy layer). In some examples, the thickness ratio between the semiconductor channel layer (epitaxygen layer 310) and the dummy layer (epitaxygen layer 308) may be from about 1 / 2 to about 1 / 5. Generally, in various cases, the dummy layer (eptaxial layer 308) can be at least twice as thick as the semiconductor channel layer (eptaxial layer 310). Therefore, embodiments of this disclosure provide a dummy layer that is significantly thicker than the semiconductor channel layer. Thus, the thicker dummy layer helps to facilitate the removal of the dummy layer during gate replacement (RPG) and improves the filling of metal gate gaps or the patterning of multi-function metals.

[0029] Device 300 further includes a gate stack 316 formed above fin 306. In embodiments, the gate stack 316 is a dummy (sacrificial) gate stack that is subsequently removed and replaced with the final gate stack in a later process stage of device 300. For example, the gate stack 316 may be replaced in a later process stage with a high-k (HK) dielectric layer and a metal gate (MG) electrode. While this disclosure is directed to a gate-last process, thereby forming a dummy gate structure and subsequently replacing it, other configurations are possible (e.g., performing a gate-first process). The portion of fin 306 below the gate stack 316 may be referred to as the channel region of device 300. The gate stack 316 may also define source / drain regions of fin 306, for example, regions of fin 306 adjacent to and located on opposite sides of the channel region.

[0030] In some embodiments, the gate stack 316 includes a dielectric layer 320 and an electrode layer 322. In some cases, one or more hard masking layers (e.g., comprising oxide and / or nitride layers) may be formed over the gate stack 316. In some embodiments, the dielectric layer 320 comprises silicon oxide. Alternatively or additionally, the dielectric layer 320 may comprise silicon nitride, a high-dielectric-constant dielectric material, or other suitable materials. In some embodiments, the electrode layer 322 may comprise polycrystalline silicon. In some examples, an optional sacrificial layer may be formed directly beneath the dielectric layer 320. The optional sacrificial layer may comprise SiGe, Ge, or other suitable materials, and in some cases, may be used to prevent the loss of nanosheets (e.g., loss of material from epitaxial layers such as epitaxial layers 308 and 310) during previous process steps.

[0031] In some embodiments, one or more spacer layers 328 may be formed on multiple sidewalls of the gate stack 316. In some cases, the one or more spacer layers 328 may comprise dielectric materials such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, low dielectric constant materials (e.g., materials having a dielectric constant k less than 7), and / or combinations thereof. In some embodiments, the one or more spacer layers 328 comprise multiple film layers, such as a primary spacer layer, a liner, and similar film layers. Notably, in various embodiments, multiple portions of the epitaxial layer 310 (semiconductor channel layer) of the second component disposed beneath the one or more spacer layers 328 may be defined as lightly doped drain regions (LDDs) of the device 300. As illustrated in the figures of this disclosure, the boundary of the channel region of the device 300 adjacent to the lightly doped drain region is schematically depicted as dashed line 405.

[0032] Method 200 then proceeds to block 204, where the source / drain etching process is performed. See also... Figure 3 In the embodiment of block 204, a source / drain etching process is performed on device 300. In some embodiments, the source / drain etching process is performed to remove the first-component epitaxial layer 308 and the second-component epitaxial layer 310 exposed in the source / drain regions of device 300 and form a trench 330 that exposes a portion of the underlying substrate 304. The source / drain etching process is also used to expose the lateral surfaces of epitaxial layers 308 and 310, such as... Figure 3 As illustrated. In some embodiments, the source / drain etching process may similarly remove multiple portions of one or more spacer layers 328 (e.g., from the top surface of the gate stack 316). In some embodiments, the source / drain etching process may include a dry etching process, a wet etching process, and / or a combination thereof.

[0033] Method 200 then proceeds to block 206, where the dummy layer etching process is performed. See also... Figure 3 as well as Figure 4In the embodiment of block 206, a dummy layer etching process is performed on device 300. The dummy layer etching process includes lateral etching of the epitaxial layer 308 (dummy layer) to form a plurality of grooves 402 along the plurality of sidewalls of a previously formed trench 330. In some embodiments, performing the dummy layer etching process is using a dry etching process, a wet etching process, and / or a combination thereof. In some cases, the dummy layer etching process may include etching using standard clean 1 (SC-1) solution, ozone (O3), a solution of ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2) and water (H2O), hydrofluoric acid (HF), diluted hydrofluoric acid, and / or fluorine (F2)-based etching. In some examples, fluorine-based etching may include F2 remote plasma etching. After performing the dummy layer etching process, the recessed epitaxial layer 308 (dummy layer) defines a concave profile along the opposing lateral surfaces of the epitaxial layer 308. In some embodiments, the width 'W1' spanned by the concave profile ranges from about 0.5 nanometers to about 2 nanometers. In other words, the size / shape of the recess 402 is at least partially defined by the concave profile of the sidewall surfaces of the epitaxial layer 308 having a width 'W1'. In some cases, the width 'W2' of the entire recess 402 may be substantially equal to the width 'W3' of one or more spacer layers 328. Furthermore, in some examples, the width 'W4' defined between the concave profiles on the opposing lateral surfaces of the epitaxial layer 308 of the first component may be substantially equal to the width 'W5' of the electrode layer 322 of the gate stack 316. In some embodiments, the width 'W4' corresponds to the gate length of the device 300 and is defined as the distance between the boundaries of the channel regions, schematically illustrated by dashed lines 405. During subsequent process stages, as will be discussed below, the epitaxial layer 308 (dummy layer) will be removed and replaced with a portion of a gate structure (e.g., a metal gate structure) such that the replacement gate structure at least partially defines the concave profile. In various examples, the replacement gate structure will interface with an inner spacer, as described in more detail below.

[0034] See Figure 4The epitaxial layer 310 (semiconductor channel layer) of the second component has a thickness 'a' in the lightly doped drain region (LDD) (e.g., below the spacer layer 328) and a thickness 'b' within the channel region (e.g., below the gate stack 316). In some embodiments, before the dummy layer etching process, thickness 'a' may be substantially equal to thickness 'b'. In some cases, after the dummy layer etching process, multiple ends of the epitaxial layer 310 in the lightly doped drain region of the device 300 may be partially etched, such that the epitaxial layer 310 may be slightly thinner in the lightly doped drain region compared to the channel region. In other words, after the dummy layer etching process, thickness 'a' may be less than thickness 'b'. For example, the consumption from each top and bottom surface of the epitaxial layer 310 in the lightly doped drain region, after the dummy layer etching process, can range from about 0.5 nanometers to about 1 nanometer, and the total consumption from both the top and bottom surfaces of the epitaxial layer 310 can be from about 1 nanometer to about 2 nanometers. Certainly, in some embodiments, the ends of the epitaxial layer 310 in the lightly doped drain region may not be etched during the dummy layer etching process, such that thickness 'a' remains substantially equal to thickness 'b' after the dummy layer etching process. More generally, in various embodiments, thickness 'a' may be less than or equal to thickness 'b' after the dummy layer etching process.

[0035] Method 200 then proceeds to block 208, where a cap layer is deposited. See also... Figure 4 as well as Figure 5 In the embodiment of block 208, a capping layer 502 may be conventionally deposited along the exposed lateral surfaces of the epitaxial layer 310 (semiconductor channel layer) and within the trench 402, including deposition on the exposed top and / or bottom surfaces of the epitaxial layer 310 and on the concave contours of the sidewall surfaces of the epitaxial layer 308 (dummy layer). As shown, the capping layer 502 may also be conventionally deposited on the exposed surface of the substrate portion 304A, which may include the bottom surface of the trench 330. In some cases, the capping layer 502 may be selectively formed on the surfaces of the epitaxial layer 308 and the epitaxial layer 310, as described above. Alternatively, in some embodiments, capping layer 502 may be blanket-deposited over device 300 and within trench 330 and recess 402, and then removed from the top surface of gate stack 316 and the top / side surface of one or more spacer layers 328 by an etch-back process, while capping layer 502 remains on the surface of epitaxial layer 308 and epitaxial layer 310, as described above.

[0036] In some embodiments, capping layer 502 may comprise a silicon (Si) layer. More generally, in some cases, capping layer 502 may comprise substantially the same material composition as epitaxial layer 310 (semiconductor channel layer). Certainly, in some examples, capping layer 502 may comprise a different material composition than epitaxial layer 310 (semiconductor channel layer). Generally, in some cases, capping layer 502 may facilitate current flow between the source / drain components of device 300. In various examples, the thickness of capping layer 502 may range from about 0.5 nanometers to about 1.5 nanometers. In some embodiments, capping layer 502 may have a thickness less than or equal to that of epitaxial layer 310 consumed in the lightly doped drain region (LDD) (e.g., after a dummy layer etching process), as described above. In some aspects, capping layer 502 may thus compensate for the consumption of epitaxial layer 310 in the lightly doped drain region. For example, after the deposition of capping layer 502, the thickness 'c' in the lightly doped drain region (e.g., below spacer layer 328) is equal to the thickness 'a' plus the thickness of capping layer 502 on the top and / or bottom surfaces of epitaxial layer 310, where thickness 'c' may be less than or equal to the thickness 'b' within the channel region. Therefore, for the uppermost epitaxial layer 310, it only has capping layer 502 disposed on the lateral and bottom surfaces of epitaxial layer 310, and thickness 'c' is equal to thickness 'a' plus twice the thickness of capping layer 502. For the other epitaxial layers 310, it has capping layer 502 disposed on the lateral, top, and bottom surfaces of epitaxial layer 310, and thickness 'c' is equal to thickness 'a' plus twice the thickness of capping layer 502. In various embodiments, capping layer 502 can help prevent damage to the inner spacers and source / drain electrodes during dummy layer removal processes. In addition, the capping layer 502 can form a portion of the semiconductor channel layer, thereby effectively providing a thicker semiconductor channel layer in the lightly doped drain region, thus helping to provide an H-shaped (or dog bone-shaped) semiconductor channel layer.

[0037] Method 200 then proceeds to block 210, forming the inner spacer. See also Figure 5 as well as Figure 6In the embodiment of block 210, an inner spacer material is first deposited over device 300, within trench 330, and within recess 402. More specifically, the inner spacer material is deposited over a previously deposited capping layer 502 (block 208). In some cases, the inner spacer material may have a thickness ranging from about 4 nanometers to about 15 nanometers. In some embodiments, the inner spacer material may comprise amorphous silicon. In some examples, the inner spacer material may comprise a dielectric material such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, a low dielectric constant material (e.g., a material having a dielectric constant k less than 7), and / or a combination thereof. For example, the internal spacer material can be deposited above the device 300 using processes such as chemical vapor deposition (CVD), subatmospheric chemical vapor deposition (SACVD), flowable chemical vapor deposition (FCVD), atomic layer deposition (ALD), physical vapor deposition (PVD), or other suitable processes.

[0038] Following the deposition of the spacer material, an inner spacer etch-back process can be performed. In various examples, the inner spacer etch-back process etches the inner spacer material from above device 300 and along the sidewalls of trench 330 (exposing capping layer 502 on the lateral surface of the underlying semiconductor channel layer), while the inner spacer material remains disposed within recess 402 (on top of the underlying capping layer 502), thereby providing inner spacer 602 for device 300. For example, the inner spacer etch-back process can be performed using a wet etching process, a dry etching process, or a combination thereof. In some cases, such as after the inner spacer etch-back process, any residual portions of the inner spacer material remaining on the top surface of device 300 and / or the sidewalls or bottom surface of trench 330 can be removed during subsequent processes (e.g., before epitaxial growth of source / drain components). In various examples, the inner spacer 602 may extend beneath one or more spacer layers 328 (formed on the sidewalls of the gate stack 316) while being adjacent to subsequently formed source / drain components, as described below. In some cases, the inner spacer 602 may extend at least partially beneath the gate stack 316.

[0039] Method 200 then proceeds to block 212, optionally performing a lateral sheet trimming process. See also Figure 6 as well as Figure 7 In the embodiment of block 212, a lateral trimming process may be optionally performed after the formation of the inner spacer 602 (block 210) and before the formation of the epitaxial source / drain components (block 214). In some embodiments, the optional lateral trimming process of block 212 includes lateral etching of a capping layer 502 disposed on the lateral surface of the epitaxial layer 310 (semiconductor channel layer) of the second component, and lateral etching of the epitaxial layer 310 to form a groove 702 along the sidewall of the previously formed trench 330. In some embodiments, the lateral trimming process is performed using a dry etching process, a wet etching process, and / or a combination thereof. In some cases, the lateral trimming process may include etching using a standard cleaning 1 (SC-1) solution, a solution of ozone (O3), a solution of ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2) and water (H2O), hydrofluoric acid (HF), diluted hydrofluoric acid, and / or fluorine (F2)-based etching. In some examples, fluorine-based etching may include F2 remote plasma etching. After performing a lateral trimming process, the recessed epitaxial layer 310 (semiconductor channel layer) defines a concave profile along the opposing lateral surfaces of the epitaxial layer 310. In embodiments where the capping layer 502 contains substantially the same material composition as the epitaxial layer 310 with a second composition, the lateral trimming process may be performed using a single etch process that etches both the capping layer 502 and the epitaxial layer 310. In embodiments where the capping layer 502 contains substantially a different material composition than the epitaxial layer 310, the lateral trimming process may be performed using a multi-etch process (which may be different etch processes) to etch each of the capping layer 502 and the epitaxial layer 310. During subsequent processes, source / drain components formed on both sides of the source / drain regions of the gate stack 316 may be formed in contact with the recessed epitaxial layer 310 (semiconductor channel layer). Following the optional lateral trimming process, the distance between the subsequently formed source / drain components and the channel region of the epitaxial layer 310 (e.g., below the gate stack 316) is reduced, thereby enhancing device performance. Therefore, in some cases, the optional lateral trimming process of block 212 may be referred to as a junction push process.

[0040] To continue the discussion below, assume that the optional lateral trimming process in block 212 is not performed. If the optional lateral trimming process is not performed, method 200 can proceed from block 210 (formation of the inner spacer) to block 214, forming the source / drain components. See [link to relevant documentation] Figure 6 as well as Figure 8In the embodiment of block 214, a source / drain component 802 is formed. In some embodiments, the source / drain component 802 is formed in a source / drain region adjacent to and on both sides of the gate stack 316 of the device 300. For example, the source / drain component 802 may be formed within a trench 330 of the device 300, above an exposed portion of the substrate 304, in contact with a capping layer 502 disposed on the lateral surface of the epitaxial layer 310 (semiconductor channel layer), and adjacent to (but not necessarily in contact with) an inner spacer 602. In other words, the source / drain component 802 may be selectively grown on the exposed surface of the capping layer 502 or on the recessed exposed surface of the epitaxial layer 310 (e.g., if the optional lateral wafer trimming process of block 212 is performed). However, in some cases, the source / drain component 802 may not be formed completely along the exposed surface of the inner spacer 602, which may result in voids 804 forming at the interface between the source / drain and the inner spacer. At least in some examples, the source / drain component 802 may not be completely formed on the inner spacer 602 because the inner spacer 602 also includes a dielectric layer. In some embodiments, a cleaning process may be performed immediately prior to the formation of the source / drain component 802. The cleaning process may include wet etching, dry etching, or a combination thereof. Furthermore, the cleaning process may remove any residual portion of the inner spacer material remaining on the top surface of the device 300 and / or on the sidewalls or bottom surface of the trench 330 (e.g., after an inner spacer back etching process).

[0041] In some embodiments, the source / drain component 802 is formed by epitaxially growing a semiconductor material layer in the source / drain region. In various embodiments, the semiconductor material layer grown to form the source / drain component 802 may comprise Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable materials. The source / drain component 802 may be formed by one or more epitaxial processes. In some embodiments, the source / drain component 802 may be in-situ doped during the epitaxial process. For example, in some embodiments, the epitaxially grown SiGe source / drain component may be doped with boron. In some cases, the epitaxially grown Si epitaxial source / drain component may be doped with carbon to form a Si:C source / drain component, may be doped with phosphorus to form a Si:P source / drain component, or may be doped with both carbon and phosphorus to form a SiCP source / drain component. In some embodiments, the source / drain component 802 is not doped in situ, but rather a doping process is performed to dope the source / drain component 802.

[0042] After the source / drain components 802 are formed (block 214), in some embodiments, a contact etch stop layer (CESL) and an inter-layer dielectric (ILD) may be formed over the device 300. In some examples, the contact etch stop layer may comprise a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, and / or other materials known in the art to which this disclosure pertains. In some cases, the material of the inter-layer dielectric layer may comprise materials such as tetraethylorthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), phosphoric silicate glass (PSG), boron doped silicon glass (BSG), and / or other suitable dielectric materials. In some embodiments, after the formation of the interlayer dielectric layer, the device 300 may perform a high thermal budget process to anneal the interlayer dielectric layer. In some embodiments, after the formation of the contact etch stop layer and the interlayer dielectric layer, a chemical mechanical polishing (CMP) process may be performed to remove portions of the interlayer dielectric layer and the contact etch stop layer located above the gate stack 316, and planarize the top surface of the device 300 and expose the top surface of the gate stack 316 (e.g., containing the gate electrode layer 322). In some embodiments, the CMP process may remove a hard masking layer (if present) above the gate stack 316 to expose the electrode layer 322.

[0043] Method 200 then proceeds to block 216, where the dummy gate is removed and the channel layer release process is performed. See also Figure 8 as well as Figure 9 For example, in the embodiment of block 216, the exposed electrode layer 322 of the gate stack 316 may be removed first by a suitable etching process, followed by an etching process to remove the dielectric layer 320 from the gate stack 316. In some examples, the etching process may include wet etching, dry etching, or a combination thereof.

[0044] Following the removal of the dummy gate, in a further embodiment of block 216, the dummy layer (epitaxy layer 308) in the channel region of device 300 can be selectively removed (e.g., using a selective etching process), while the semiconductor channel layer (epitaxy layer 310) remains unetched. It is certain that, at least in some cases, the removal of the dummy layer (epitaxy layer 308) can partially etch the top and / or bottom surfaces of the epitaxial layer 310 (semiconductor channel layer) within the channel region of device 300, such that the semiconductor channel layer can be slightly thinner in the channel region compared to the lightly doped drain region (LDD). The removal of the dummy layer will result in the consumption of the top and / or bottom surfaces of the epitaxial layer 310, and if this consumption occurs, the consumption range can be from about 1 nanometer to about 4 nanometers. In some cases, during the selective etching process that removes the dummy layer, partial consumption of the epitaxial layer 310 may occur due to intermixing of the first component epitaxial layer 308 and the second component epitaxial layer 310 at the interface between the epitaxial layers 308 and 310.

[0045] In some examples, the selective removal of the dummy layer may be referred to as a channel layer release process (e.g., due to releasing the semiconductor channel layer from the dummy layer). A selective etching process can be performed via a trench provided by the removal of the dummy gate electrode. In some embodiments, the selective etching process may include a selective wet etching process. In some cases, the selective wet etching process includes ammonia and / or ozone. As an example only, the selective wet etching process includes tetra-methyl ammonium hydroxide (TMAH). Notably, after the selective removal of the dummy layer (epipolar layer 308), gaps 902 may be formed between adjacent semiconductor channel layers (epipolar layers 310) in the channel region. For example, gaps 902 may serve as multiple first portions of epipolar layer 310 exposed between opposing concave contours 904 of capping layer 502 and inner spacer 602, while multiple second portions of epipolar layer 310 remain covered by capping layer 502 and inner spacer 602. As will be described in more detail below, multiple portions of the gate structure of device 300 will be formed within gap 902.

[0046] Following the selective removal of the dummy layer (epitaxy layer 308), method 200 proceeds to block 218, where a wafer trimming process may be performed. See also Figure 9 as well as Figure 10A / 10B / 10C, ​​in the embodiment of block 218, a wafer trimming process may be optionally performed after the channel layer release process (block 216) and before the formation of the gate structure (block 220). In some embodiments, the optional wafer trimming process of block 218 includes etching the top and bottom surfaces of the epitaxial layer 310 (semiconductor channel layer) of the second component within the channel region of device 300, such that the semiconductor channel layer can be slightly thinned in the channel region compared to the lightly doped drain region (LDD). By combining the removal of the dummy layer (as discussed above) and (if performed) the optional wafer trimming process, the consumption range of the top and bottom surfaces of the epitaxial layer 310 can be from about 1 nanometer to about 4 nanometers. The consumption of the top and bottom surfaces of the epitaxial layer 310 is schematically illustrated by the slightly concave top and bottom surfaces 1002 of the epitaxial layer 310. Figure 10A In / 10B / 10C, ​​due to slight erosion of the top and bottom surfaces of the epitaxial layer 310 of the second component, the epitaxial layer 310 now has a thickness 'b1' within the channel region (e.g., below the gate stack 316), where the thickness 'b1' is less than the initial thickness 'b' of the epitaxial layer 310 within the channel region. Notably, at this stage, the thickness 'c' in the lightly doped drain region can be greater than the thickness 'b1' within the channel region, thereby contributing to providing an H-shaped (or dog-bone shaped) semiconductor channel layer. In some embodiments, the wafer trimming process is performed using a dry etching process, a wet etching process, and / or a combination thereof. In some cases, the wafer trimming process may include etching using a standard cleaning 1 (SC-1) solution, a solution of ozone (O3), ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2) and water (H2O), hydrofluoric acid (HF), diluted hydrofluoric acid, and / or fluorine (F2)-based etching. In some examples, fluorine-based etching may include F2 remote plasma etching.

[0047] It is worth noting that in some embodiments, the optional die trimming process of block 218 also etches the surface of capping layer 502 exposed along the lateral sides of gap 902, and in some cases, at least a portion of the underlying inner spacer 602 may also be etched, such that the optional die trimming process exposes the surface 1004 of the inner spacer 602. In various embodiments, different amounts of etching of capping layer 502 along the lateral sides of gap 902 and different amounts of etching of the underlying inner spacer 602 after the optional die trimming process result in different profiles of the exposed surface 1004, as discussed below. Generally, in various examples, the optional die trimming process may result in capping layer 502 being laterally recessed relative to inner spacer 602 (e.g., along a plane parallel to epitaxial layer 310), inner spacer 602 being laterally recessed relative to capping layer 502 (e.g., along a plane parallel to epitaxial layer 310), or capping layer 502 and inner spacer 602 being laterally recessed by substantially the same amount. For example, the trimming process of block 218 may result in the exposed surface 1004 having a... Figure 10A The concave contour shown in the figure, such as Figure 10B The convex profile shown in the drawing, or as... Figure 10C The outline shown is essentially flat (vertical). Some outlines contain convex surfaces (e.g., as...). Figure 10B In embodiments illustrated, only the central portion of the capping layer 502 along the lateral sidewalls of the gap 902 can be removed, exposing only the central portion of the underlying inner spacer 602. Therefore, in some examples, the exposed central portion of the underlying inner spacer 602 may protrude along a plane parallel to the epitaxial layer 310 into the gap 902 beyond the capping layer 502. In some embodiments containing concave profiles (e.g., as shown in the illustration), Figure 10A (as shown) or a flat (vertical) outline (e.g., as shown) Figure 10C In the illustrated embodiment, the exposed portion of the lower inner spacer 602 does not protrude along a plane parallel to the epitaxial layer 310 beyond the gap 902 of the capping layer 502. In some embodiments, and depending on the type of profile of the exposed surface, the slightly concave top and bottom surfaces 1002 of the epitaxial layer 310 may extend to or beyond the boundary of the channel region of the device 300. In various embodiments, and depending on optional wafer trimming processes, the lower inner spacer 602 alone, or a combination of the capping layer 502 and the inner spacer 602, provides different profiles of the exposed surface 1004, as discussed above.

[0048] During subsequent processes, multiple portions of the gate structure may be formed in the gap 902 and between adjacent epitaxial layers 310, such that the portion of the gate structure formed in the gap 902 contacts the slightly recessed top and bottom surfaces 1002 of the epitaxial layer 310 and the exposed surface 1004 of the inner spacer 602. In some embodiments, an optional wafer trimming process of block 218 may be performed to remove the mixed layers (mixed epitaxial layers 308 and 310) at the interface between epitaxial layers 308 and 310, thereby enhancing device performance. More notably, in various embodiments, in some examples, the optional wafer trimming process of block 218 may be skipped if the initial thickness 'b' of epitaxial layer 310 is sufficiently thin (e.g., according to device performance requirements) and / or there are substantially no mixed layers (mixed epitaxial layers 308 and 310) at the interface between epitaxial layers 308 and 310. If the optional wafer trimming process is skipped, in some embodiments, multiple portions of the gate structure subsequently formed in the gap 902 contact the top and bottom surfaces of the epitaxial layer 310 (semiconductor channel layer) and the surface of the capping layer 502 exposed along the lateral side of the gap 902.

[0049] Method 200 proceeds to block 220, forming a gate structure. The gate structure may comprise a high-dielectric-constant / metal gate stack, but may also be other components. In some embodiments, the gate structure may form a gate associated with the multi-channels provided by the multiple semiconductor channel layers exposed in the channel region of device 300 (exposed epitaxial layers 310, now having gaps 902 between epitaxial layers 310). See also Figure 11A In the example of / 11B / 11C, in the embodiment of block 220, a gate dielectric 1102 is deposited on the exposed surface of the epitaxial layer 310 (semiconductor channel layer), encompassing the first exposed portion of the epitaxial layer 310 within the gap 902 and the exposed surface 1004 opposite the inner spacer 602. In some embodiments, the gate dielectric 1102 has a total thickness of about 1 nanometer to about 5 nanometers. In various embodiments, the gate dielectric 1102 includes an interfacial layer (IL) and a high-k dielectric layer formed above the interfacial layer. The high-k dielectric layer, as used and discussed in this disclosure, comprises a dielectric material having a high dielectric constant, such as a dielectric material having a dielectric constant greater than that of thermally oxidized silicon (dielectric constant about 3.9).

[0050] In some embodiments, the interface layer (IL) may comprise a dielectric material such as silicon oxide (SiO2), HfSiO, or silicon oxynitride (SiON). In some examples, a high-k dielectric layer may comprise hafnium oxide (HfO2). Alternatively, the high-k dielectric layer may comprise other high-k dielectric materials such as TiO2, HfZrO, Ta2O3, HfSiO4, ZrO2, ZrSiO2, LaO, AlO, ZrO, TiO, Ta2O5, Y2O3, SrTiO3 (STO), BaTiO3 (BTO), BaZrO, HfZrO, HfLaO, HfSiO, LaSiO, AlSiO, HfTaO, HfTiO, (Ba,Sr)TiO3 (BST), Al2O3, Si3N4, silicon oxynitride (SiON), combinations thereof, or other suitable materials. In various embodiments, the gate dielectric 1102 may be formed by thermal oxidation, atomic layer deposition (ALD), physical vapor deposition (PVD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), and / or other suitable methods.

[0051] See also Figure 11A In the example of / 11B / 11C, in a further embodiment of block 220, a metal gate comprising a metal layer 1104 is formed over the gate dielectric 1102 (e.g., over the interface layer (IL) and over the high dielectric constant dielectric layer). The metal layer 1104 may comprise a metal, a metal alloy, or a metal silicide. Additionally, the formation of the gate dielectric / metal gate stack may include deposition to form various gate materials, one or more substrates, and one or more chemical mechanical polishing (CMP) processes to remove excess gate material, thereby planarizing the top surface of the device 300.

[0052] In some embodiments, metal layer 1104 may comprise a single-layer structure or alternatively a multilayer structure, such as a metal layer having a selected work function to enhance device performance (work function metal layer), a substrate, a wetting layer, an adhesion layer, a metal alloy, or various combinations of metal silicides. For example, metal layer 1104 may comprise Ti, Ag, Al, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, TiN, TaN, Ru, Mo, Al, WN, Cu, W, Re, Ir, Co, Ni, other suitable metallic materials, or combinations thereof. In various embodiments, metal layer 1104 may be formed by atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), electron beam evaporation, or other suitable processes. Furthermore, metal layer 1104 may be formed separately for N-type transistors and P-type transistors, as different metal layers may be used for N-type transistors and P-type transistors. Furthermore, the metal layer 1104 may provide an N-type work function or a P-type work function, and may be used as the gate electrode of a transistor (e.g., a fully wound gate transistor). In at least some embodiments, the metal layer 1104 may comprise a polysilicon layer. Regarding the apparatus illustrated and discussed in this disclosure, the gate structure includes multiple portions of the epitaxial layer 310 intersecting each of the second components, each providing a semiconductor channel layer for the fully wound gate transistor.

[0053] In various examples, the shapes of the gate dielectric 1102 and the metal layer 1104 of the final structure of device 300 may vary, for example, based on the surface profile along the lateral side of gap 902 produced by an optional wafer trimming process of block 218, as seen above. Figure 10A Discussion of / 10B / 10C. For example, if the wafer trimming process results in a concave profile (drawn in... Figure 10A In the middle), the gate dielectric 1102 and the metal layer 1104 will also have concave profiles on their respective lateral sides, such as... Figure 11A As illustrated. Alternatively, if the trimming process results in a convex profile (illustrated in... Figure 10B In the middle), the gate dielectric 1102 and the metal layer 1104 will also have convex profiles on their respective lateral sides, such as... Figure 11B As illustrated. Furthermore, if the wafer trimming process results in a flat (vertical) profile (illustrated in...), Figure 10C In the middle), the gate dielectric 1102 and the metal layer 1104 will also have flat (vertical) profiles on their respective lateral sides, such as Figure 11C drawn.

[0054] Generally, the semiconductor device 300 can be further processed to form various components and areas known in the art to which this disclosure pertains. For example, further processes can form various contacts / vias / wires and multilayer interconnect features (e.g., metal layers and interlayer dielectrics) on the substrate 304, configured to connect various components to form a functional circuit, which may include one or more multi-gate devices (e.g., one or more fully wound gate transistors). In a further example, the multilayer interconnect may include vertical interconnects, such as vias or contacts, and horizontal interconnects, such as metal wires. The various interconnect components can be made of various conductive materials, including copper, tungsten, and / or silicides. In one example, damascene and / or dual damascene processes can be used to form a copper-related multilayer interconnect structure. In addition, additional process steps may be implemented before, during, and after method 200, and some of the process steps described above may be modified, replaced, or removed depending on the various embodiments of method 200.

[0055] As an additional example, see again Figure 11B The diagram illustrates that after the formation of the gate dielectric 1102 / metal layer 1104, a hole 1105 may exist in the corner region of the gate dielectric 1102 / metal layer 1104 adjacent to the capping layer 502, the inner spacer 602, and the epitaxial layer 310 (semiconductor channel layer). In some alternative embodiments, during the formation of the gate dielectric 1102, the gate dielectric 1102 may be deposited such that multiple regions potentially capable of forming holes 1105 are instead filled by the gate dielectric 1102, such as... Figure 12 As illustrated. Therefore. Figure 12 The device 300 does not include the hole 1105. It is worth noting that for devices with other profiles on opposite lateral sides (e.g., as...), Figure 11A as well as Figure 11C As illustrated, a similar gate dielectric 1102 deposition can also be performed to fill any potential voids.

[0056] The description provided in this disclosure discloses various methods and structures for providing multi-gate devices (e.g., providing gate-wound (GAA) transistors) with H-shaped (or dog-bone) semiconductor channel layers. In some examples, devices fabricated according to this disclosure provide better current diffusion in the lightly doped drain region (LDD), which in turn reduces parasitic resistances. Stronger strain efficiency from source / drain stress sources is also provided in at least some embodiments. Furthermore, various embodiments provide good short-channel control by maintaining a thin semiconductor channel layer. In some embodiments, it is possible to have a thin semiconductor channel layer thickness in an epitaxially grown superlattice, with slight (or no) wafer trimming during gate replacement, thereby improving the uniformity of the semiconductor channel layer thickness. Additionally, in some embodiments, a thinner semiconductor channel layer thickness may correspond to a thicker dummy layer thickness, where a thicker dummy layer helps facilitate dummy layer removal during gate replacement and improves the filling of metal gate gaps or the patterning of multi-work-function metals. At least some aspects of the various embodiments and advantages discussed in this disclosure are achieved by using a Si capping layer formed after dummy layer etching and before the formation of the inner spacers. In some examples, the Si capping layer can also help prevent damage to the inner spacers and the source / drain during the dummy layer removal process. In some cases, an additional Si capping layer may help to have a thinner semiconductor channel layer beneath the gate sidewall spacers, which also helps to provide an H-shaped (or dog-bone shaped) semiconductor channel layer. Those skilled in the art to which this disclosure pertains will readily understand that the various methods and structures described herein can be applied to a variety of other semiconductor devices to advantageously achieve similar benefits from these other devices without departing from the scope of this disclosure. For example, a fully wound gate device manufactured according to the method described in this disclosure can be used to form other types of devices and circuits, such as memory devices (e.g., for static random access memory (SRAM), dynamic random access memory (DRAM), etc.), logic circuits, or other types of electronic devices and / or circuits.

[0057] Therefore, one embodiment of this disclosure describes a method of manufacturing a semiconductor device, including providing a fin extending from a substrate, wherein the fin includes an epitaxial layer stack having a plurality of semiconductor channel layers interspersed by a plurality of dummy layers. In some embodiments, the method of manufacturing this semiconductor device further includes removing a portion of the epitaxial layer stack within a source / drain region of the semiconductor device to form a trench in the source / drain region, the trench exposing the semiconductor channel layers and a plurality of lateral surfaces of the dummy layers. After forming the trench, the method of manufacturing this semiconductor device further includes performing a dummy layer etching process to laterally etch a plurality of ends of the dummy layers and form a plurality of first grooves along the sidewalls of the trench. In some embodiments, the method of manufacturing this semiconductor device further includes conformally forming a capping layer along those lateral surfaces exposed by the semiconductor channel layers and within those first grooves.

[0058] In some embodiments, the capping layer described in the method of manufacturing this semiconductor device comprises a silicon (Si) layer. In some embodiments, the capping layer described in the method of manufacturing this semiconductor device comprises a first material composition that is the same as a second material composition of the semiconductor channel layer. In some embodiments, the capping layer described in the method of manufacturing this semiconductor device increases the effective thickness of the semiconductor channel layer in the lightly doped drain (LDD) region of the semiconductor device. In some embodiments, the dummy layer etching process described in the method of manufacturing this semiconductor device consumes a first thickness of the semiconductor channel layer in the lightly doped drain region of the semiconductor device, and wherein the capping layer has a second thickness less than or equal to the first thickness. In some embodiments, the thickness ratio between a semiconductor channel layer and a dummy layer of the semiconductor channel layer in the method of manufacturing this semiconductor device is about 1 / 2 to about 1 / 5. In some embodiments, the method of manufacturing this semiconductor device further includes, after forming the capping layer, forming internal spacers over the capping layer within those first grooves, wherein the capping layer formed on those lateral surfaces of the semiconductor channel layer remains exposed, and after forming the internal spacers, epitaxially growing source / drain components in the source / drain regions. In some embodiments, the method of manufacturing this semiconductor device further includes performing a lateral wafer trimming process after forming internal spacers and before epitaxially growing source / drain components. The lateral wafer trimming process etches capping layers on those lateral surfaces of the semiconductor channel layers and on both the plurality of ends of the semiconductor channel layers to form a plurality of second grooves along the sidewalls of a trench. In some embodiments, the method of manufacturing this semiconductor device further includes performing a channel release process after epitaxially growing source / drain components to remove the dummy layer and form a plurality of gaps between a plurality of adjacent semiconductor channel layers of the semiconductor channel layers, and forming at least a portion of a gate structure within those gaps. In some embodiments, the method of manufacturing this semiconductor device further includes performing a wafer trimming process after performing the channel release process and before forming the at least a portion of the gate structure within those gaps to remove a plurality of portions of the top and bottom surfaces of each semiconductor channel layer in the channel region of the semiconductor device, wherein after the wafer trimming process, the effective thickness of the semiconductor channel layer in the lightly doped drain region of the semiconductor device is greater than the thickness of the semiconductor channel layer in the channel region of the semiconductor device.

[0059] In another embodiment, a method of manufacturing a semiconductor device is discussed, comprising providing a fin structure comprising a plurality of epitaxial layers of a first component interpenetrated by a plurality of epitaxial layers of a second component, wherein the epitaxial layers of the first component are at least twice as thick as the epitaxial layers of the second component. In some embodiments, the method of manufacturing this semiconductor device further comprises forming a dummy gate over the fin structure and forming spacer layers on a plurality of sidewalls of the dummy gate. In some embodiments, the method of manufacturing this semiconductor device further comprises etching a plurality of lateral ends of the epitaxial layers of the first component to form a plurality of recesses disposed below the spacer layers and between a plurality of adjacent epitaxial layers of the second component. In some embodiments, the method of manufacturing this semiconductor device further comprises forming a silicon (Si) capping layer on opposite ends of the epitaxial layers of the second component and within the recesses.

[0060] In some embodiments, the epitaxial layers of the second component described in the method of manufacturing this semiconductor device comprise a region below the spacer layer that includes a lightly doped drain region, wherein a silicon capping layer increases the effective thickness of the epitaxial layers of the second component in the lightly doped drain region. In some embodiments, the method of manufacturing this semiconductor device further includes, after forming the silicon layer, forming an inner spacer on the capping layer within those recesses, and after forming the inner spacer, forming source / drain components in the source / drain region adjacent to the dummy gate. In some embodiments, the method of manufacturing this semiconductor device further includes, after forming the inner spacer and before forming the source / drain components, etching the silicon capping layer on both the opposing ends of the epitaxial layers of the second component and the plurality of ends of the epitaxial layers of the second component, reducing the distance between the source / drain components and the channel regions of the epitaxial layers of the second component. In some embodiments, the method of manufacturing this semiconductor device further includes, after forming the source / drain components, removing both the dummy gate and the epitaxial layers of the first component to form a plurality of gaps between a plurality of adjacent epitaxial layers of the epitaxial layers of the second component, and forming a high-dielectric-constant / metal gate stack within those gaps. In some embodiments, the method of manufacturing this semiconductor device describes removing the epitaxial layers of the first component and also removing portions of the top and bottom surfaces of each of the epitaxial layers of the second component in the channel region, such that the channel region thickness of the epitaxial layers of the second component is less than the thickness of the lightly doped drain region of the epitaxial layers of the second component.

[0061] In another embodiment, a semiconductor device is discussed, comprising fins extending from a substrate, wherein the fins include a plurality of semiconductor channel layers, and each of the semiconductor channel layers includes a channel region and a lightly doped drain region. In some embodiments, the semiconductor device further includes a capping layer surrounding the lightly doped drain region of each of the semiconductor channel layers. In various examples, the semiconductor device further includes a plurality of inner spacers disposed between a plurality of first portions of the capping layer, the first portions of the capping layer being disposed in the lightly doped drain regions of a plurality of adjacent semiconductor channel layers of the semiconductor channel layers. In some embodiments, a first thickness of the semiconductor channel layer in the lightly doped drain region, combined with a second thickness of the capping layer, provides an effective thickness of the semiconductor channel layer in the lightly doped drain region, and wherein the effective thickness is greater than a third thickness of the semiconductor channel layer in the channel region.

[0062] In some embodiments, the semiconductor device further includes a portion of a gate structure disposed between multiple channel regions of multiple adjacent semiconductor channel layers, wherein inner spacers are further disposed on both sides of the portion of the gate structure, and multiple source / drain components disposed on both sides of the gate structure and contacting multiple second portions of a capping layer, the second portions of the capping layer being disposed on multiple lateral surfaces of each semiconductor channel layer. In some embodiments, the capping layer described in this semiconductor device comprises a silicon (Si) layer. In some embodiments, the semiconductor device further includes vias disposed between the source / drain components and at least one adjacent inner spacer.

[0063] The foregoing outlines features of several embodiments to enable those skilled in the art to better understand the viewpoints of the embodiments described herein. Those skilled in the art will understand that other processes and structures can be easily designed or modified based on the embodiments described herein to achieve the same purpose and / or advantages as the embodiments described herein. Those skilled in the art will also understand that such equivalent structures do not depart from the spirit and scope of this disclosure, and various changes, substitutions, and replacements can be made without departing from the spirit and scope of this disclosure. Therefore, the scope of protection of this disclosure shall be determined by the appended claims.

Claims

1. A method for manufacturing a semiconductor device, comprising: A fin extending from a substrate is provided, wherein the fin includes an epitaxial layer stack having a plurality of semiconductor channel layers interspersed by a plurality of dummy layers; A portion of the epitaxial layer stack within a source / drain region of the semiconductor device is removed to form a trench in the source / drain region, the trench exposing multiple lateral surfaces of the semiconductor channel layer and the dummy layer; After the trench is formed, a dummy layer etching process is performed to laterally etch multiple ends of the dummy layer and form multiple first grooves along one sidewall of the trench, wherein the dummy layer etching process consumes a first thickness of the semiconductor channel layer in a lightly doped drain region of the semiconductor device. as well as A capping layer is compliantly formed along the lateral surface exposed by the semiconductor channel layer and within the first groove, wherein the capping layer has a second thickness less than or equal to the first thickness.

2. The method of manufacturing a semiconductor device as claimed in claim 1, wherein the capping layer comprises a silicon layer.

3. The method of manufacturing a semiconductor device as claimed in claim 1, wherein the capping layer includes a first material component, the first material component being the same as a second material component of the semiconductor channel layer.

4. The method of manufacturing a semiconductor device as claimed in claim 1, wherein the capping layer increases an effective thickness of the semiconductor channel layer in a lightly doped drain region of the semiconductor device.

5. The method of manufacturing a semiconductor device as claimed in claim 1, wherein the thickness ratio between a semiconductor channel layer of the semiconductor channel layer and a dummy layer of the dummy layer is 1 / 2 to 1 / 5.

6. The method for manufacturing a semiconductor device as claimed in claim 1, further comprising: After the capping layer is formed, an inner spacer is formed above the capping layer within the first groove, wherein the capping layer formed on the lateral surface of the semiconductor channel layer remains exposed; and After the inner spacer is formed, a source / drain component is epitaxially grown in the source / drain region.

7. The method of manufacturing a semiconductor device as claimed in claim 6, further comprising: After the inner spacer is formed and before the source / drain component is epitaxially grown, a lateral trimming process is performed to etch the capping layer on the lateral surface of the semiconductor channel layer and on both the multiple ends of the semiconductor channel layer to form a multiple second groove along the sidewall of the trench.

8. The method of manufacturing a semiconductor device as claimed in claim 6, further comprising: After epitaxially growing the source / drain component, a channel release process is performed to remove the dummy layer and form multiple gaps between multiple adjacent semiconductor channel layers of the semiconductor channel layer; as well as At least a portion of a gate structure is formed within the gap.

9. The method of manufacturing a semiconductor device as claimed in claim 8, further comprising: After the channel release process is performed and before the formation of at least a portion of the gate structure within the gap, a trimming process is performed to remove portions of the top and bottom surfaces of each of the semiconductor channel layers in a channel region of the semiconductor device, wherein after the trimming process, an effective thickness of the semiconductor channel layer in a lightly doped drain region of the semiconductor device is greater than a thickness of the semiconductor channel layer in the channel region of the semiconductor device.

10. A method for manufacturing a semiconductor device, comprising: A fin structure is provided, comprising a plurality of epitaxial layers of a first component interpenetrated by a plurality of epitaxial layers of a second component, wherein the epitaxial layers of the first component are at least twice as thick as the epitaxial layers of the second component; A dummy gate is formed above the fin structure and a spacer layer is formed on the multiple sidewalls of the dummy gate; The multiple lateral ends of the epitaxial layer of the first component are etched to form a multiple groove, the groove being disposed below the spacer layer and between a multiple adjacent epitaxial layers of the second component; as well as A silicon capping layer is formed on the opposite ends of the epitaxial layer of the second component and within the groove, wherein the epitaxial layer of the second component is disposed in a region below the spacer layer including a lightly doped drain region, and wherein the silicon capping layer increases an effective thickness of the epitaxial layer of the second component in the lightly doped drain region.

11. The method of manufacturing a semiconductor device as claimed in claim 10, further comprising: After the silicon layer is formed, an inner spacer is formed on the capping layer within the groove; as well as After the inner spacer is formed, a source / drain component is formed in a source / drain region adjacent to the dummy gate.

12. The method of manufacturing a semiconductor device as claimed in claim 11, further comprising: After the inner spacer is formed and before the source / drain component is formed, the silicon capping layer on both the opposite ends of the epitaxial layer of the second component and the plurality of ends of the epitaxial layer of the second component is etched to reduce a distance between the source / drain component and a channel region of the epitaxial layer of the second component.

13. The method of manufacturing a semiconductor device as claimed in claim 11, further comprising: After the source / drain component is formed, both the dummy gate and the epitaxial layer of the first component are removed to form a plurality of gaps between a plurality of adjacent epitaxial layers of the epitaxial layer of the second component. as well as A high dielectric constant / metal gate is formed within these gaps.

14. The method of manufacturing a semiconductor device as claimed in claim 13, wherein removing the epitaxial layer of the first component also removes a plurality of portions of the top and bottom surfaces of each of the epitaxial layers of the second component in a channel region, such that the thickness of a channel region of the epitaxial layer of the second component is less than the thickness of a lightly doped drain region of the epitaxial layer of the second component.

15. A semiconductor device, comprising: A fin extending from a substrate, wherein the fin includes a plurality of semiconductor channel layers, and wherein each of the semiconductor channel layers includes a channel region and a lightly doped drain region. A capping layer surrounds the lightly doped drain region of each semiconductor channel layer; as well as Multiple inner spacers are disposed between multiple first portions of the capping layer, and the first portions of the capping layer are disposed in the lightly doped drain regions of multiple adjacent semiconductor channel layers of the semiconductor channel layer; A first thickness of the semiconductor channel layer in the lightly doped drain region, combined with a second thickness of the capping layer, provides an effective thickness of the semiconductor channel layer in the lightly doped drain region, wherein the effective thickness is greater than a third thickness of the semiconductor channel layer in the channel region.

16. The semiconductor device of claim 15, further comprising: A portion of a gate structure is disposed between multiple channel regions of multiple adjacent semiconductor channel layers of the semiconductor channel layer, wherein the inner spacer is further disposed on both sides of the portion of the gate structure; as well as Multiple source / drain components are disposed on both sides of the gate structure and in contact with multiple second portions of the capping layer, wherein the second portions of the capping layer are disposed on multiple lateral surfaces of each semiconductor channel layer.

17. The semiconductor device of claim 15, wherein the capping layer comprises a silicon layer.

18. The semiconductor device of claim 16, further comprising: A hole is provided between the source / drain component and at least one adjacent inner spacer.

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