Semiconductor structure

Abstract

A semiconductor structure includes a first substrate and a second substrate adjacent to the first substrate, the first substrate having a first side with a first interconnect structure, the second substrate having a second side opposite the first side with a second interconnect structure. The semiconductor structure further includes a connection region including the first interconnect structure and the second interconnect structure. The first interconnect structure and the second interconnect structure are electrically connected to an upper surface of the connection region.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more specifically, to a semiconductor structure. Background Technology

[0002] When a large substrate is cut into smaller sizes using partitioning technology, the signals that were originally interconnected between layers in the large substrate are broken and cannot be linked. Therefore, a redesign using an RDL (Redistribution Layer) is necessary. Figure 1 As shown, the routing of RDL 12 is based on the final number of I / Os. The routing is carried out by evenly distributing the routing across each layer. If the partition technology is used to cut the original large-size substrate 10, then all the RDL 12s of each layer can only be laid out on the top layer and then connected in series to maintain the original design function.

[0003] Currently, the RDL wiring on the substrate is evenly distributed across all layers. If there is no solution to the problem of RDL wiring being broken when using partition technology, then this technology has not been applied to the design of large-size substrates. Summary of the Invention

[0004] To address the aforementioned problems in related technologies, this invention proposes a semiconductor structure that avoids the issue in existing methods where signals can only be connected in series via RDL layout to the top layer.

[0005] According to an embodiment of the present invention, a semiconductor structure is provided, comprising a first substrate and a second substrate adjacent to the first substrate. The first substrate has a first interconnect structure on a first side, and the second substrate has a second side opposite to the first side, also having a second interconnect structure. The semiconductor structure further includes a connection region, which contains the first interconnect structure and the second interconnect structure. The first interconnect structure and the second interconnect structure are electrically connected to the upper surface of the connection region.

[0006] According to an embodiment of the present invention, the semiconductor structure further includes a third interconnect structure that extends above the upper surface of the connection region and electrically connects the first interconnect structure and the second interconnect structure.

[0007] According to an embodiment of the present invention, the semiconductor structure further includes an insulating material located between the first substrate and the second substrate within the connection region, thereby isolating the first substrate from the second substrate.

[0008] According to an embodiment of the present invention, each of the first interconnect structure and the second interconnect structure includes a plurality of vertically stacked through-holes.

[0009] According to an embodiment of the present invention, the first interconnect structure or the second interconnect structure includes: a first through hole; an interconnect line connected to the top surface of the first through hole; and a second through hole, the bottom surface of which is connected to the interconnect line, wherein the first through hole and the second through hole are laterally offset.

[0010] According to an embodiment of the present invention, the first substrate or the second substrate further includes: a first circuit layer located in the region outside the connection region; and a second circuit layer located in the region outside the connection region and above the first circuit layer. The circuit density in the second circuit layer is greater than the circuit density in the first circuit layer.

[0011] According to an embodiment of the present invention, the upper surface of the first substrate or the upper surface of the second substrate is the chip side for connecting the chip.

[0012] According to an embodiment of the present invention, the width of the region where the first interconnect structure is located within the connection region is not greater than 100 μm, or the width of the region where the second interconnect structure is located within the connection region is not greater than 100 μm.

[0013] According to an embodiment of the present invention, the width of the connection area is no greater than 400 μm.

[0014] According to an embodiment of the present invention, the first interconnect structure or the second interconnect structure is spaced apart from the lower surface of the connection region. Attached Figure Description

[0015] The various aspects of the invention can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard industrial practice, the various components are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0016] Figure 1 It is a cross-sectional view of an existing semiconductor structure.

[0017] Figure 2 This is a cross-sectional view of a semiconductor structure according to an embodiment of the present invention.

[0018] Figure 3 These are top views and cross-sectional views of the connection area according to an embodiment of the present invention.

[0019] Figure 4 These are top views and cross-sectional views of the connection area according to another embodiment of the present invention. Detailed Implementation

[0020] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of elements and arrangements will be described below to simplify the invention. These are merely examples and are not intended to limit the invention. For example, in the following description, forming a first component above or on a second component can include embodiments where the first and second components are in direct contact, or embodiments where an additional component is formed between the first and second components such that the first and second components are not in direct contact. Furthermore, reference numerals and / or letters may be repeated throughout the various instances. Such repetition is for brevity and clarity only and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0021] Figure 2 This is a cross-sectional view of a semiconductor structure according to an embodiment of the present invention. Figure 2 As shown, the semiconductor structure includes a first substrate 110 and a second substrate 120 adjacent to the first substrate 110. A first interconnect structure 112 is provided on a first side 111 of the first substrate 110 adjacent to the second substrate 120. A second side 121 of the second substrate 120 is opposite to the first side 111 of the first substrate 110, and a second interconnect structure 122 is provided on the second side 121. A connection region 130 is provided between the first substrate 110 and the second substrate 120. The connection region 130 includes the first interconnect structure 112 and the second interconnect structure 122. The first interconnect structure 112 and the second interconnect structure 122 are electrically connected on the upper surface of the connection region 130. For example, all signals cut off by adjacent first substrates 110 and second substrates 120 during the partitioning process can be electrically connected to the first interconnect structure 112 and the second interconnect structure 122 in this connection region 130, and then interconnected on the upper surface of the connection region 130 through the first interconnect structure 112 and the second interconnect structure 122. This avoids the problem in existing methods where signals can only be connected in series via RDL layout to the top layer. At the same time, large-size substrates using partitioning processes can maintain high yield and improve substrate warpage.

[0022] Continue to refer to Figure 2 As shown, in one embodiment, the first interconnect structure 112 and the second interconnect structure 122 are electrically connected via a third interconnect structure 125, which extends laterally above the upper surface of the connection region 130. In other embodiments, the first interconnect structure 112 and the second interconnect structure 122 may also be electrically connected above the connection region 130 in other applicable ways.

[0023] An insulating material is also disposed in the connection region 130 between the first substrate 110 and the second substrate 120 to isolate the first substrate 110 and the second substrate 120 from each other. A third interconnect structure 125 spans this insulating material on the upper surface of the connection region 130 (see [link]). Figure 3 and Figure 4 In some embodiments, the width of the region within the connection region 130 where the first interconnect structure 112 is located (the distance from the edge of the connection region 130 adjacent to the first substrate 110 to the insulating material) is not greater than 100 μm, that is, the width of the portion of the first substrate 110 configured as the connection region 130 is not greater than 100 μm. The width of the region within the connection region 130 where the second interconnect structure 122 is located is not greater than 100 μm. In some embodiments, the width of the connection region 130 is not greater than 400 μm.

[0024] The first interconnect structure 112 and the second interconnect structure 122 may be spaced apart from the lower surface of the connection region 130. That is, only the cut-off signal is routed to the upper surface of the first substrate 110 and the second substrate 120 via the first interconnect structure 112 or the second interconnect structure 122. In some embodiments, the first substrate 110 and the second substrate 120 each have a core 124. The cut-off lines between the core 124 and the lower surface may also be connected to the first interconnect structure 112 or the second interconnect structure 122 and similarly connected to the upper surface of the connection region 130, while the first interconnect structure 112 and the second interconnect structure 122 are spaced apart from the lower surface of the connection region 130.

[0025] The first substrate 110 and the second substrate 120 may each include a first circuit layer 131 located outside the connection region 130 and a second circuit layer 132 located above the first circuit layer 131. The circuit density in the second circuit layer 132 is greater than the circuit density in the first circuit layer 131. In one embodiment, the uppermost second circuit layer 132 is the topmost layer of either the first substrate 110 or the second substrate 120. The upper surface of the first substrate 110 and the upper surface of the second substrate 120 may be the chip side for connecting chips, while the lower surface may be, for example, the solder ball side for connecting solder balls. On the other hand, for the circuit layer below the core board 124, it is not necessary to increase the circuit density or reduce the circuit size. Thus, as Figure 2As shown, in the semiconductor structure of the present invention, the area above the core plate 124 can be referred to as the dense circuit region, and the area below the core plate 124 can be referred to as the sparse circuit region. The present invention modifies the wiring, using high-density and small-size circuits in the last layer on the chip side of the first substrate 110 and the second substrate 120, while decreasing the density and increasing the size of the circuits in subsequent layers. This configuration ensures that the partitioned substrates have the same function. However, the residual copper content of each layer can still be maintained within the range of 70% to 80%. In some embodiments, the size of the circuits in the topmost layer on the chip side can be approximately 10 μm, the size of the circuits in the bottom layer on the chip side can be approximately 25 μm, and the size of the circuits on the lower surface (solder ball side) of the first substrate 110 or the second substrate 120 can be approximately 25 μm.

[0026] Figure 3 These are, respectively, a top view and a cross-sectional view of the connection area 130 according to an embodiment of the present invention. Figure 3 As shown, each of the first interconnect structure 112 and the second interconnect structure 122 may include a plurality of vertically stacked through-holes 1121. Therefore, in Figure 3 In the top view, multiple through holes 1121 overlap each other. The number of stacked through holes 1121 can be arbitrary.

[0027] Figure 4 These are, respectively, a top view and a cross-sectional view of the connection area 130 according to another embodiment of the present invention. Figure 4 As shown, each of the first interconnect structure 112 or the second interconnect structure 122 can be provided with a plurality of vias arranged in a staged manner. The plurality of vias includes a first via 1121 and a second via 1122, which are electrically connected to each other by a laterally offset interconnect line 1123. Specifically, the bottom surface of the interconnect line 1123 is connected to the top surface of the first via 1121, and the second via 1122 is laterally offset from the first via 1121 and connected to the top surface of the interconnect line 1123. Similarly, more first vias 1121, second vias 1122, and interconnect lines 1123 can be provided in this manner.

[0028] The foregoing summary outlines features of several embodiments that enable those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art should understand that other processes and structures can be readily designed or modified based on this invention to achieve the same objectives and / or benefits as the embodiments described herein. Those skilled in the art should also recognize that these equivalent structures do not depart from the spirit and scope of the invention, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of the invention.

Claims

1. A semiconductor structure, characterized in that, include: A first substrate, wherein a first side of the first substrate has a first interconnect structure; A second substrate is adjacent to the first substrate, and the second substrate has a second side opposite to the first side, and the second side has a second interconnection structure. The connection region includes the first interconnect structure and the second interconnect structure; The first interconnect structure and the second interconnect structure are electrically connected to the upper surface of the connection region. Wherein, the first substrate or the second substrate further includes: Multiple line layers are stacked vertically in sequence and located in the region outside the connection area. Among the multiple line layers, the topmost line layer, which is closest to the connection area, has the highest line density and the smallest line size. The line density of each line layer below the topmost line layer decreases and the line size increases layer by layer.

2. The semiconductor structure according to claim 1, characterized in that, Also includes: A third interconnect structure extends above the upper surface of the connection region and electrically connects the first interconnect structure and the second interconnect structure.

3. The semiconductor structure according to claim 1, characterized in that, Also includes: An insulating material is located between the first substrate and the second substrate within the connection area, thereby isolating the first substrate from the second substrate.

4. The semiconductor structure according to claim 1, characterized in that, Each of the first interconnect structure and the second interconnect structure includes a plurality of vertically stacked through-holes.

5. The semiconductor structure according to claim 1, characterized in that, The first interconnect structure or the second interconnect structure includes: First through hole; Interconnecting lines are connected to the top surface of the first through hole; The second through hole has its bottom surface connected to the interconnect line, and the first through hole and the second through hole are laterally offset.

6. The semiconductor structure according to claim 1, characterized in that, The first substrate or the second substrate further includes a core board.

7. The semiconductor structure according to claim 1, characterized in that, The upper surface of the first substrate or the upper surface of the second substrate is the chip side for connecting the chip.

8. The semiconductor structure according to claim 1, characterized in that, The width of the region where the first interconnect structure is located within the connection area is no greater than 100 μm, or the width of the region where the second interconnect structure is located within the connection area is no greater than 100 μm.

9. The semiconductor structure according to claim 1, characterized in that, The width of the connection area is no greater than 400μm.

10. The semiconductor structure according to claim 1, characterized in that, The first interconnect structure or the second interconnect structure is spaced apart from the lower surface of the connection region.

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