Chipset and method of manufacturing the same

Abstract

This invention provides a chipset and its manufacturing method. The chipset includes a first circuit layer, multiple first bare dies, multiple input / output bare dies, and a top logic bare die. The multiple first bare dies include multiple first bonding components. The multiple input / output bare dies include multiple second bonding components. The top logic bare die includes multiple third bonding components. The multiple first bare dies and the multiple input / output bare dies are directly bonded to the multiple third bonding components of the top logic bare die via the multiple first bonding components and the multiple second bonding components in a pad-to-pad manner. Furthermore, the multiple first bare dies and the multiple input / output bare dies are respectively encapsulated on the first circuit layer by multiple first bumps. Therefore, the chipset of this invention can achieve high computing power and high manufacturing yield.

Description

Technical Field

[0001] This invention relates to a semiconductor device, and more particularly to a chipset and its manufacturing method. Background Technology

[0002] For traditional chipsets, the logic chips and input / output chips in a traditional chipset usually need to be connected by interface circuits, such as die-to-die (D2D) interface circuits and high-bandwidth memory (HBM) physical interface circuits. Therefore, as chip design is developing towards high-bandwidth and high-density chips, the chip area (or chip volume) of traditional chipsets is often affected by the increase in the number of these connection interface circuits, resulting in the chip area of ​​traditional chipsets being too large and having high power consumption. Summary of the Invention

[0003] According to an embodiment of the present invention, the chipset of the present invention includes a first circuit layer, a plurality of first bare dies, a plurality of input / output bare dies, and a top logic bare die. The plurality of first bare dies include a plurality of first bonding components. The plurality of input / output bare dies include a plurality of second bonding components. The top logic bare die includes a plurality of third bonding components. The plurality of first bare dies and the plurality of input / output bare dies are directly bonded to the plurality of third bonding components of the top logic bare die via the plurality of first bonding components and the plurality of second bonding components in a pad-to-pad manner. The plurality of first bare dies and the plurality of input / output bare dies are respectively encapsulated on the first circuit layer by a plurality of first bumps.

[0004] According to an embodiment of the present invention, the method for manufacturing a chipset of the present invention includes the following steps: forming a plurality of first bare dies, a plurality of input / output bare dies, and a top logic bare die; directly bonding a plurality of first bonding components of the plurality of first bare dies and a plurality of second bonding components of the plurality of input / output bare dies to a plurality of third bonding components of the top logic bare die in a pad-to-pad manner; and encapsulating the plurality of first bare dies and the plurality of input / output bare dies on a first circuit layer by a plurality of first bumps.

[0005] Based on the above, the chipset and its manufacturing method of the present invention can effectively increase the density of bare dies and chips.

[0006] To make the above features and advantages of the present invention more apparent and understandable, specific embodiments are described below in conjunction with the accompanying drawings. Attached Figure Description

[0007] Figure 1 This is a top view of the structure of a chipset according to an embodiment of the present invention;

[0008] Figure 2This is a side view of the structure of a chipset according to an embodiment of the present invention;

[0009] Figure 3 This is a perspective view of the chipset structure according to an embodiment of the present invention;

[0010] Figure 4 This is a side view of the packaged structure of a chipset according to an embodiment of the present invention;

[0011] Figure 5 This is a side view of the packaged structure of a chipset according to another embodiment of the present invention;

[0012] Figure 6 This is a flowchart of a chipset manufacturing method according to an embodiment of the present invention;

[0013] Figure 7 This is a side view of the input / output bare die structure according to an embodiment of the present invention;

[0014] Figure 8A as well as Figure 8B These are side views of the structural changes of the first bare die during the manufacturing process according to an embodiment of the present invention;

[0015] Figure 9 This is a side view of the top logic bare die structure according to an embodiment of the present invention;

[0016] Figures 10A to 10C These are side views of the structural changes of a chipset during the manufacturing process according to an embodiment of the present invention.

[0017] Figure 11 This is a side view of the circuit layer structure according to an embodiment of the present invention;

[0018] Figures 12A to 12D These are side views of the structural changes of a chipset during the manufacturing process according to another embodiment of the present invention;

[0019] Figure 13 This is a structural side view of the redistribution layer according to another embodiment of the present invention;

[0020] Figures 14A to 14D These are side views showing the structural changes of a chipset during the manufacturing process, representing another embodiment of the present invention. Detailed Implementation

[0021] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element symbols are used in the drawings and description to denote the same or similar parts.

[0022] Figure 1 This is a top view of the chipset according to an embodiment of the present invention. (Reference) Figure 1The chipset 100 includes a top logic die 110, a plurality of first dies 120, a plurality of input / output dies (I / O dies) 130, a plurality of second dies 140, and a circuit layer 150. In this embodiment, the first dies 120 and the I / O dies 130 are disposed on the top logic die 110, and the plurality of I / O dies 130 may be disposed along the edge of the top logic die 110 to surround the plurality of first dies 120. The top logic die 110 and the second dies 140 are disposed on the circuit layer 150, and the plurality of second dies 140 may be disposed on both sides or at least one side of the top logic die 110.

[0023] In this embodiment, the multiple input / output bare crystals 130 each include multiple input / output circuits (ports) 131, and the input / output bare crystals 130 can be electrically connected to the second bare crystal 140 through the input / output circuits 131 and the lines on the line layer 150 to communicate.

[0024] In this embodiment, the first die 120 is a chiplet, and may include a logic chip and / or a memory chip, wherein the memory chip may be a static random-access memory (SRAM) chip. The second die 140 may include a high-bandwidth memory (HBM) chip.

[0025] In this embodiment, the top logic die 110, the first die 120, and the input / output die 130 are manufactured using different process nodes. In one embodiment, the minimum linewidth of the process nodes for the first die 120 and the input / output die 130 is greater than or equal to the minimum linewidth of the process node for the top logic die 110. In another embodiment, the minimum linewidth of the process node for the top logic die 110 may, for example, be less than or equal to 5 nanometers (nm). The minimum linewidth of the process node for the first die 120 may, for example, be between 5 nm and 7 nm. The minimum linewidth of the process node for the input / output die 130 may, for example, be greater than or equal to 5 nm.

[0026] In this embodiment, since the first die 120 and the input / output die 130 are electrically connected through the circuitry in the top logic die 110, the configuration of die-to-die input / output circuitry and wiring between the first die 120 and the input / output die 130 can be effectively reduced, thereby increasing the number of first dies 120 (i.e., increasing logic density). As a result, the chipset 100 of this embodiment can achieve higher computing power and higher manufacturing yield (because die-to-die circuitry and wiring manufacturing is saved).

[0027] Figure 2 This is a side view of the chipset structure according to an embodiment of the present invention. (Reference) Figure 2 The top logic die 110 includes an active circuit 111 and a bonding assembly 112. The active circuit 111 is disposed on a side close to the first die 120 and the input / output die 130. The first die 120 includes an active circuit 121, a bonding assembly 122, a through-silicon via (TSV) 123, and a bump 124. The active circuit 121 is disposed on a side close to the top logic die 110. The input / output die 130 includes an active circuit 131, a bonding assembly 132, a through-silicon via 133, and a bump 134. The active circuit 131 is disposed on a side close to the top logic die 110. In this embodiment, the active circuits 111, 121, and 131 may, for example, each include circuits composed of multiple transistors and lines. Bumps 124 and 134 can be micro bumps (μbump, micro bump), solder balls, or solder balls.

[0028] In this embodiment, the first die 120 and the input / output die 130 are directly bonded to the bonding assembly 112 of the top logic die 110 via bonding assemblies 122 and 132 in a pad-to-pad manner, respectively. Furthermore, the first die 120 and the input / output die 130 are respectively encapsulated by bumps 124 and 134 on a surface such as... Figure 1 On the circuit layer 150 shown. In this embodiment, each of the bonding assemblies 112, 122, and 132 may include a bonding pad, a pillar, and a metal pad, wherein the bonding pad is used to connect (directly contact) with the bonding pad of another bonding assembly, the pillar is used to connect the bonding pad and the metal pad, and the metal pad is used to connect to internal circuitry. The bonding pads between two bonding assemblies may be joined in a hybrid bonding manner.

[0029] In this embodiment, the active circuits 121 and 131 of the first die 120 and the input / output die 130 are electrically connected to the circuit layer 150 via through-silicon vias 123 and 133 and bumps 124 and 134. Through-silicon via 123 connects to the active circuit 121. Through-silicon via 133 connects to the active circuit 131. Through-silicon vias 123 and 133 connect to bumps 124 and 134, respectively. Furthermore, the active circuits 121 and 131 of the first die 120 and the input / output die 130 can be electrically connected and communicate via bonding components 112, 122, and 132. Therefore, the components in this embodiment can effectively save on the configuration of die-to-die input / output circuits and lines between the first die 120 and the input / output die 130.

[0030] Figure 3 This is a perspective view of a chipset according to an embodiment of the present invention. (Reference) Figure 3 This embodiment uses a first die 320 and an input / output die 330 to illustrate the arrangement on the top logic die 310. In this embodiment, the top logic die 310 may have multiple tiny I / O circuits 312 and mesh lines or network on chip (NoC) metal traces 315 disposed on the surface adjacent to the first die 320 and the input / output die 330, wherein the metal traces 315 connect the tiny I / O circuits 312. The top logic die 310 includes tiny I / O circuits 322, and the tiny I / O circuits 322 of the first die 320 are electrically connected to the corresponding tiny I / O circuits 312 of the top logic die 310 through the bonding components of the first die 320 and the corresponding bonding components of the top logic die 310. The input / output die 330 includes a micro input / output circuit 332, and the micro input / output circuit 332 of the input / output die 330 is electrically connected to another corresponding micro input / output circuit 312 of the top logic die 310 through the bonding components of the input / output die 330 and the corresponding bonding components of the top logic die 310. In this embodiment, the other side of the input / output die 330 may also include an input / output circuit 335, and the input / output circuit 335 is used to electrically connect to the lines on the line layer through bumps.

[0031] Figure 4 This is a side view of the packaged structure of a chipset according to an embodiment of the present invention. (Reference) Figure 4The chipset 400 includes a top logic die 410, a first die 420, an input / output die 430, a second die 440, and circuit layers 450 and 460. In this embodiment, the first die 420 and the input / output die 430 are disposed on the top logic die 410 in a pad-to-pad manner using multiple bonding components. The first die 420, the input / output die 430, and the second die 440 are encapsulated on one side of the circuit layer 460 by multiple bumps 401. The bumps 401 can be microbumps. The circuit layer 460 can be an interposer. The first die 420, the input / output die 430, and the second die 440 are electrically connected and communicate with each other through the bumps 401 and the circuit layer 460. The other side of the circuit layer 460 is encapsulated on one side of the circuit layer 450 by multiple bumps 402. The circuit layer 450 may be, for example, a chip substrate, a package substrate, or a circuit substrate, and multiple bumps 403 may be provided on the other side of the circuit layer 450. Bumps 402 and 403 may be solder balls or solder ball bumps, respectively. For example, the multiple bumps 402 may be formed by a controlled collapse chip connection (C4) process technology, and the multiple bumps 403 may be formed by a ball grid array (BGA) process technology, but the present invention is not limited thereto. The chipset 400 may be further packaged onto other circuit substrates via the bumps 403.

[0032] Figure 5 This is a side view of the packaged structure of a chipset according to another embodiment of the present invention. (See reference) Figure 5The chipset 500 includes a top logic die 510, a first die 520, an input / output die 530, a second die 540, a circuit layer 550, and a redistribution layer (RDL) 560. In this embodiment, the first die 520 and the input / output die 530 can be disposed on the top logic die 510 in a pad-to-pad manner using multiple bonding components. The first die 520, the input / output die 530, and the second die 540 can be packaged on one side of the circuit layer 550. Specifically, the first die 520, the input / output die 530, and the second die 540 are each packaged on the circuit layer 550 using a flip-chip method. The redistribution layer 560 can be disposed on the side of the first die 520, the input / output die 530, and the second die 540 closest to the circuit layer 550. The first die 520, the input / output die 530, and the second die 540 can be electrically connected to multiple bumps 502 on the side of the redistribution layer 560 near the circuit layer 550 via multiple metal traces 501, and are electrically connected to multiple bumps 503 via the circuit layer 550. The redistribution layer 560 can be packaged on one side of the circuit layer 550 via multiple bumps 502. The circuit layer 550 can be, for example, a chip substrate, a package substrate, or a circuit board, and multiple bumps 503 can be disposed on the other side of the circuit layer 550. Bumps 502 and 503 can be solder balls or solder ball bumps, respectively. For example, the multiple bumps 502 can be formed by the controlled collapse chip connection (C4) process technology, and the multiple bumps 503 can be formed by the ball grid array (BGA) process technology, but the present invention is not limited thereto. The chipset 500 can be further packaged onto other circuit boards via bumps 503. In addition, the redistribution layer 560 can be packaged and electrically connected to the first die 520, the input / output die 530 and the second die 540 via metal traces and microbumps (not shown).

[0033] Figure 6 This is a flowchart illustrating a method for manufacturing a chipset according to an embodiment of the present invention. (See also...) Figure 1 , Figure 2 as well as Figure 6The chipset 100 can be manufactured using various corresponding manufacturing equipment and according to the following steps S610 to S630. In step S610, a plurality of first dies 120, a plurality of input / output dies 130, and a top logic die 110 are formed. In step S620, a plurality of first bonding components (bonding components 122) of the plurality of first dies 120 and a plurality of second bonding components (bonding components 132) of the plurality of input / output dies 130 are directly bonded to a plurality of third bonding components (bonding components 112) of the top logic die 110 in a pad-to-pad manner. In step S630, the plurality of first dies 120 and the plurality of input / output dies 130 are packaged on a first circuit layer (circuit layer 150) by a plurality of first bumps (bumps 124, 134). Therefore, the manufacturing method of this embodiment can effectively save on die-to-die circuit and line manufacturing, and achieve a higher manufacturing yield. Furthermore, the implementation of each step will be further described below by structural descriptions of several embodiments.

[0034] Figure 7 This is a side view of the input / output bare die structure according to an embodiment of the present invention. Corresponding to step S610 above, as follows... Figure 7 As shown, an input / output die 730 can be formed. The input / output die 730 includes a device layer 730A and a substrate layer 730B. Specifically, metal traces, through-silicon vias 733, driving circuits 735, and related input / output circuits can be formed on the substrate layer 730B of the input / output die 730. An oxide passivation layer is then formed to cover the metal traces, through-silicon vias 733, driving circuits 735, and related logic circuits to form the device layer 730A. Next, a plurality of bonding components 732 can be formed on the surface of the device layer 730A on the side away from the substrate layer 730B, and an oxide passivation layer is again formed around the plurality of bonding components 732, wherein the bonding surfaces of the plurality of bonding components 732 are at the same height as the surface of the device layer 730A and are exposed.

[0035] Figure 8A as well as Figure 8B These are side views showing the structural changes of the first bare die during the manufacturing process according to an embodiment of the present invention. Corresponding to step S610 above, as... Figure 8A As shown, a first bare die 820 can be formed. The first bare die 820 includes a device layer 820A and a substrate layer 820B. Specifically, metal traces, through-silicon vias 823, driving circuits 825, and related input / output circuits can be formed on the substrate layer 820B of the first bare die 820, and an oxide passivation layer is formed to cover the metal traces, through-silicon vias 823, driving circuits 825, and related logic circuits to form a device layer 830A. For example... Figure 8BAs shown, a plurality of bonding components 822 can be formed on the surface of the device layer 820A on the side away from the substrate layer 820B, and an oxide passivation layer is formed again around the plurality of bonding components 822, wherein the bonding surfaces of the plurality of bonding components 822 are at the same height as the surface of the device layer 820A and exposed.

[0036] Figure 9 This is a side view of the top logic bare die structure according to an embodiment of the present invention. Corresponding to step S610 above, as... Figure 9 As shown, a top logic die 910 can be formed. The top logic die 910 includes a device layer 910A and a substrate layer 910B. Specifically, metal traces, driving circuits 915, and related input / output circuits can be formed on the substrate layer 910B of the top logic die 910, and an oxide passivation layer is formed to cover the metal traces, driving circuits 915, and related logic circuits to form the device layer 910A. Next, a plurality of bonding components 912 can be formed on the surface of the device layer 910A on the side away from the substrate layer 910B, and an oxide passivation layer is again formed around the plurality of bonding components 912, wherein the bonding surfaces of the plurality of bonding components 912 are at the same height as the surface of the device layer 910A and exposed.

[0037] Figures 10A to 10C These are side views showing structural changes during the manufacturing process of a chipset according to an embodiment of the present invention. Corresponding to step S620 above, as... Figure 10A As shown, the above Figure 7 , 8A The plurality of input / output dies 730, the plurality of first dies 820, and the top logic die 910 formed in embodiments 8B and 9 are combined. Specifically, the plurality of bonding components 822 of the plurality of first dies 820 and the plurality of bonding components 732 of the plurality of input / output dies 730 are directly bonded to the plurality of bonding components 912 of the top logic die 910 in a pad-to-pad manner. Furthermore, the gaps between the plurality of input / output dies 730 and the plurality of first dies 820 can be filled with a passivation layer, wherein the passivation layer can be an organic material or an oxide. Figure 10B As shown, the substrate layers 730B and 820B of the input / output die 730 and the first die 820 can be polished to expose the multiple through-silicon vias 733 and 823 of the input / output die 730 and the first die 820. Figure 10C As shown, multiple metal traces 1001 and multiple (micro)bumps 1002 can be formed to connect to the multiple through-silicon vias 733 and 823 exposed on the input / output die 730 and the first die 820, respectively, and to complete the fabrication of the chipset 1000.

[0038] Figure 11This is a side view of the circuit layer structure according to an embodiment of the present invention. Corresponding to step S630 above, in one embodiment, as shown... Figure 11 As shown, a circuit layer 1100 can be formed. The circuit layer 1100 is an interposer and includes a substrate layer 1100A and a device layer 1100B. Specifically, a plurality of through-silicon vias 1103 can be formed on the substrate layer 1100A of the circuit layer 1100, penetrating the substrate layer 1100A, and a plurality of deep trench capacitors (DTCs) 1105 can be formed on the side of the substrate layer 1100A adjacent to the device layer 1100B. Next, metal traces 1101 can be formed to connect the plurality of deep trench capacitors 1105 and the plurality of through-silicon vias 1103, and an oxide passivation layer is formed to cover the metal traces 1101, the plurality of deep trench capacitors 1105, and the plurality of through-silicon vias 1103 to form the device layer 1100B. Next, metal traces 1102 and (micro)bumps 1104 are formed to expose the surface of the device layer 1100B away from the substrate layer 1100A, and the fabrication of the circuit layer 1100 is completed.

[0039] Figures 12A to 12D These are side views showing structural changes in a chipset during manufacturing, according to another embodiment of the present invention. Corresponding to step S630 above, in one embodiment, as... Figure 12A As shown, the above Figure 10C , 11 In this embodiment, the chipset 1000 and the circuit layer 1100 are combined. Specifically, the chipset 1000 (including a top logic die, multiple first dies, and multiple input / output dies) is packaged on the circuit layer 1100 via multiple bumps 1002 and / or multiple bumps 1104, and a chip 1210 is packaged on the circuit layer 1100 via multiple (micro)bumps 1213 on at least one side of the chipset 1000. The chip 1210 includes a die 1211 and metal traces 1212 formed on one side of the die 1211, wherein the chip 1210 may be a high-bandwidth memory (HBM) chip. The chip 1210 is electrically connected to the circuit layer 1100 via the metal traces 1212 and the bumps 1213, enabling the chipset 1000 to communicate with the chip 1210 through the circuit layer 1100.

[0040] Next, as Figure 12B As shown, underfill material 1201 is filled into the gap between chipset 1000 and circuit layer 1100, and into the gap between chip 1210 and circuit layer 1100, and molding material 1202 is filled into the space between chipset 1000 and chip 1210. Next, as... Figure 12CAs shown, a temporary carrier board 1203 is formed on the side of the chipset 1000 and the chip 1210 away from the circuit layer 1100, respectively, to fix the chipset 1000, the chip 1210, and the circuit layer 1100. Next, as... Figure 12D As shown, metal traces 1204 and multiple bumps 1205 are formed to connect multiple through-silicon vias 1103 in the substrate layer 1100A of the circuit layer 1100. The temporary carrier 1203 is removed and diced to complete the packaging process of the chipset 1200. Furthermore, the chipset 1200 can be further packaged using multiple bumps 1205 to the aforementioned... Figure 4 The circuit layer 450 is shown. The circuit layer 450 can be, for example, a chip substrate, a packaging substrate, or a circuit board, and multiple bumps (i.e., ...) can be provided on the other side of the circuit layer 450. Figure 4 The multiple bumps 403 shown are used for further encapsulation onto other circuit boards. For example, multiple bumps 1205 (i.e. Figure 4 The multiple bumps 402 shown can be formed by the process technology of Controlled Collapse ChipConnection (C4), and the multiple bumps on the other side of the circuit layer 450 (i.e. Figure 4 The multiple bumps 403 shown can be formed by the process technology of ball grid array (BGA) packaging, but the present invention is not limited thereto.

[0041] Figure 13 This is a structural side view of the redistribution layer according to another embodiment of the present invention. Corresponding to step S630 above, in another embodiment, such as... Figure 13 As shown, a redistribution layer 1300A can be formed. Specifically, a temporary carrier board 1300B can be formed first, and then the redistribution layer 1300A can be formed over the temporary carrier board 1300B using a fan-out packaging technique. For this purpose, an oxide passivation layer can be formed to cover the metal traces 1301 to form the redistribution layer 1300A, wherein at least a portion of the metal traces 1301 is exposed on the surface of the redistribution layer 1300A, thus completing the fabrication of the redistribution layer 1300A. For example, the portion of the metal traces 1301 exposed on the surface of the redistribution layer 1300A can be a microbump.

[0042] Figures 14A to 14D These are side views showing structural changes during the manufacturing process of a chipset according to another embodiment of the present invention. Corresponding to step S630 above, in another embodiment, such as... Figure 14A As shown, the above Figure 10C , 13The chipset 1000 and the assembly 1300 consisting of a redistribution layer 1300A and a temporary carrier 1300B are combined in the embodiment. Specifically, the chipset 1000 (including a top logic die, a plurality of first dies, and a plurality of input / output dies) is packaged on the assembly 1300 via a plurality of bumps 1002, and a chip 1210 is packaged on the assembly 1300 via a plurality of (micro)bumps 1213 on at least one side of the chipset 1000. The chip 1210 includes a die 1211 and metal traces 1212 formed on one side of the die 1211, wherein the chip 1210 may be a high-bandwidth memory chip. The chip 1210 is electrically connected to the redistribution layer 1300A via the metal traces 1212 and the bumps 1213, enabling the chipset 1000 to communicate with the chip 1210 through the redistribution layer 1300A.

[0043] Next, as Figure 14B As shown, bottom filler material 1401 is filled into the gap between chipset 1000 and assembly 1300, and into the gap between chip 1210 and assembly 1300, and encapsulating material 1402 is filled into the space between chipset 1000 and chip 1210. Next, as... Figure 14C As shown, a temporary carrier 1403 is formed on the side of the chipset 1000 and the chip 1210 away from the redistribution layer 1300A, respectively, to fix the chipset 1000, the chip 1210, and the assembly 1300. Then, the temporary carrier 1300B of the assembly 1300 is removed, leaving the redistribution layer 1300A. Next, as... Figure 14D As shown, metal traces 1404 and multiple bumps 1405 are formed to connect to the redistribution layer 1300A and complete the packaging process of the chipset 1400. Furthermore, the chipset 1400 can also be packaged to the aforementioned configuration using multiple bumps 1405. Figure 5 The circuit layer 550 is shown. The circuit layer 550 can be, for example, a chip substrate, a packaging substrate, or a circuit board, and multiple bumps (i.e., ...) can be provided on the other side of the circuit layer 550. Figure 5 The multiple bumps 503 shown are used for further encapsulation onto other circuit substrates. For example, the chipset 1400 can be packaged on the circuit layer 550 in a flip-chip package manner, with multiple bumps 1405 (i.e., Figure 5 The multiple bumps 502 shown can be formed by the process technology of Controlled Collapse Chip Connection (C4), and the multiple bumps on the other side of the circuit layer 550 (i.e. Figure 5 The multiple bumps 503 shown can be formed by the process technology of ball grid array (BGA) packaging, but the present invention is not limited thereto.

[0044] In summary, the chipset and its manufacturing method of the present invention can directly bond one side of multiple first bare dies (each including logic chips and / or memory chips) and multiple input / output chips to the top logic bare die using a pad-to-pad method, thereby saving on bare-die circuit configuration. Furthermore, the other side of the multiple first bare dies and multiple input / output chips of the chipset of the present invention can also be electrically connected to multiple second bare dies of the chipset (each including high-bandwidth memory chips) via a circuit layer, further saving on bare-die circuit configuration. Therefore, the chipset and its manufacturing method of the present invention simultaneously utilize 2.5D packaging technology and 3D packaging technology to achieve high logic density structural characteristics, and can achieve high computing power and high manufacturing yield.

[0045] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A chipset, characterized in that, include: First line layer; Multiple first bare dies, including multiple first bonded components; Multiple input / output bare dies, including multiple second bonding components; as well as Top logic bare die, including multiple third-bonded components, The plurality of first bare dies and the plurality of input / output bare dies are respectively directly bonded to the plurality of third bonding components of the top logic bare die by the plurality of first bonding components and the plurality of second bonding components in a pad-to-pad manner, and the plurality of first bare dies and the plurality of input / output bare dies are respectively encapsulated on the first circuit layer by the plurality of first bumps; Each of the plurality of first bare dies further includes a first substrate layer, a first through-silicon via (TSV), and a first active circuit. The first TSV is embedded in the first substrate layer and connected to the first active circuit and the first line layer. The first active circuit is disposed on the side of the first substrate layer near the top logic bare die and connected to a corresponding first bonding component. Each of the plurality of input / output bare dies further includes a second substrate layer, a second through-silicon via (TSV), and a second active circuit. The second TSV is embedded in the second substrate layer and connected to the second active circuit and the first line layer. The second active circuit is disposed on the side of the second substrate layer near the top logic bare die and connected to a corresponding second bonding component. The top logic die also includes a third substrate layer and a third active circuit. The third active circuit is located on the side of the third substrate layer near the plurality of first dies and the plurality of input / output dies, and is connected to the plurality of third bonding components. as well as The plurality of first bare dies and the plurality of input / output bare dies are electrically connected to each other through lines in the top logic bare die, and are respectively connected to the first line layer through a plurality of first through-silicon vias and a plurality of second through-silicon vias.

2. The chipset according to claim 1, characterized in that, The plurality of first bare dies, the plurality of input / output bare dies, and the top logic bare die are manufactured using processes at different process nodes.

3. The chipset according to claim 1, characterized in that, The minimum linewidth of the process nodes of the plurality of first bare dies and the plurality of input / output bare dies is greater than or equal to the minimum linewidth of the process node of the top logic bare die.

4. The chipset according to claim 1, characterized in that, The plurality of first bare dies each include a logic chip and / or a memory chip, and the pads are bonded together using a hybrid bonding method.

5. The chipset according to claim 1, characterized in that, Also includes: Multiple second bare dies, each including a high-bandwidth memory chip, The plurality of second bare dies are packaged on the first circuit layer by a plurality of second bumps, and the plurality of first bare dies and the plurality of input / output bare dies are electrically connected to the plurality of second bare dies by the plurality of first bumps, the first circuit layer and the plurality of second bumps, respectively.

6. The chipset according to claim 5, characterized in that, Also includes: The second circuit layer, wherein the first circuit layer is an interposer, and the first circuit layer is encapsulated on the second circuit layer by a plurality of third bumps.

7. The chipset according to claim 6, characterized in that, The plurality of first bumps and the plurality of second bumps are micro bumps, and the plurality of third bumps are solder ball or solder ball bumps.

8. The chipset according to claim 5, characterized in that, The plurality of first bumps and the plurality of second bumps are respectively solder balls or solder ball bumps, and the plurality of second bare dies are respectively packaged on the first circuit layer in a flip-chip package manner.

9. The chipset according to claim 8, characterized in that, Also includes: A redistribution layer is disposed on the side of the plurality of first bare dies, the plurality of input / output bare dies, and the plurality of second bare dies near the first circuit layer, wherein the plurality of first bare dies, the plurality of input / output bare dies, and the plurality of second bare dies are respectively connected to the plurality of first bumps and the plurality of second bumps through the redistribution layer.

10. The chipset according to claim 1, characterized in that, The plurality of first bare dies and the plurality of input / output bare dies include a plurality of first micro input / output circuits corresponding to a portion of the plurality of first bonding components and a portion of the plurality of second bonding components, respectively, and the top logic bare die includes a plurality of second micro input / output circuits corresponding to a portion of the plurality of third bonding components.

11. The chipset according to claim 10, characterized in that, The plurality of first micro input / output circuits communicate with the plurality of second micro input / output circuits through a portion of the plurality of first bonding components, a portion of the plurality of second bonding components, and a portion of the plurality of third bonding components, and another portion of the plurality of first bonding components, another portion of the plurality of second bonding components, and another portion of the plurality of third bonding components are respectively used to transmit power signals.

12. The chipset according to claim 1, characterized in that, The plurality of first through-silicon vias and the plurality of second through-silicon vias are respectively connected to the plurality of first bumps, and are connected to the first circuit layer through the plurality of first bumps.

13. A method for manufacturing a chipset, comprising: This results in the formation of multiple first bare dies, multiple input / output bare dies, and a top logic bare die; The plurality of first bonding components of the plurality of first bare dies and the plurality of second bonding components of the plurality of input / output bare dies are directly bonded to the plurality of third bonding components of the top logic bare die in a pad-to-pad manner; and The plurality of first bare dies and the plurality of input / output bare dies are encapsulated on the first circuit layer by a plurality of first bumps. Each of the plurality of first bare dies further includes a first substrate layer, a first through-silicon via (TSV), and a first active circuit. The first TSV is embedded in the first substrate layer and connected to the first active circuit and the first line layer. The first active circuit is disposed on the side of the first substrate layer near the top logic bare die and connected to a corresponding first bonding component. Each of the plurality of input / output bare dies further includes a second substrate layer, a second through-silicon via (TSV), and a second active circuit. The second TSV is embedded in the second substrate layer and connected to the second active circuit and the first line layer. The second active circuit is disposed on the side of the second substrate layer near the top logic bare die and connected to a corresponding second bonding component. The top logic die also includes a third substrate layer and a third active circuit. The third active circuit is located on the side of the third substrate layer near the plurality of first dies and the plurality of input / output dies, and is connected to the plurality of third bonding components. as well as The plurality of first bare dies and the plurality of input / output bare dies are electrically connected to each other through lines in the top logic bare die, and are respectively connected to the first line layer through a plurality of first through-silicon vias and a plurality of second through-silicon vias.

14. The manufacturing method according to claim 13, characterized in that, The plurality of first bare dies, the plurality of input / output bare dies, and the top logic bare die are manufactured using processes at different process nodes.

15. The manufacturing method according to claim 13, characterized in that, The minimum linewidth of the process nodes of the plurality of first bare dies and the plurality of input / output bare dies is greater than or equal to the minimum linewidth of the process node of the top logic bare die.

16. The manufacturing method according to claim 13, characterized in that, The plurality of first bare dies each include a logic chip and / or a memory chip, and the pads are bonded together using a hybrid bonding method.

17. The manufacturing method according to claim 13, characterized in that, Also includes: Multiple second bare dies are formed, wherein each of the multiple second bare dies comprises a high-bandwidth memory chip; as well as The plurality of second bare dies are encapsulated on the first circuit layer by a plurality of second bumps. The plurality of first bare dies and the plurality of input / output bare dies are electrically connected to the plurality of second bare dies through the plurality of first bumps, the first circuit layer and the plurality of second bumps, respectively.

18. The manufacturing method according to claim 17, characterized in that, Also includes: Forming a second line layer; as well as The first circuit layer is encapsulated on the second circuit layer by multiple third bumps. The first circuit layer is an intermediary board. The plurality of first bumps and the plurality of second bumps are micro bumps, and the plurality of third bumps are solder ball or solder ball bumps.

19. The manufacturing method according to claim 17, characterized in that, Also includes: A redistribution layer is formed on one side of the plurality of first bare dies, the plurality of input / output bare dies, and the plurality of second bare dies near the first circuit layer, wherein the plurality of first bare dies, the plurality of input / output bare dies, and the plurality of second bare dies are respectively connected to the plurality of first bumps and the plurality of second bumps through the redistribution layer. The plurality of first bumps and the plurality of second bumps are respectively solder balls or solder ball bumps, and the plurality of second bare dies are respectively packaged on the first circuit layer in a flip-chip package manner.

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