Fan-out wafer level chip packaging method and packaging structure thereof

Abstract

The application provides a fan-out wafer-level chip packaging method and a packaging structure thereof. The packaging method comprises the following steps: obtaining a wafer to be processed; preparing at least one first redistribution layer and at least one first protective layer on the wafer to be processed to obtain a structure to be molded; performing molding processing on the structure to be molded to obtain a structure to be prepared; preparing at least one second redistribution layer and at least one second protective layer on the structure to be prepared to obtain a first structure to be cut; and performing cutting processing on the first structure to be cut to obtain a packaged fan-out wafer-level chip. According to the application, the multiple redistribution layers can be arranged in an array on a small product, the packaging chip can meet the demand for lightness and thinness, the chip back can be protected, and the hidden cracks and other hidden damages can be reduced, so that the packaging structure and the whole machine can be reduced. In addition, the heat dissipation performance of the packaging chip can be improved, and the electromagnetic shielding capability can be improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a packaging method and packaging structure for a fan-out wafer-level chip. Background Technology

[0002] Wafer-level packaging (WLP) is a packaging method that involves packaging and then dicing the wafer. It follows the wafer fabrication process used in integrated circuit chip manufacturing plants, completing the packaging process on the entire wafer before dicing to obtain a large number of finished chips in a single process. Compared to traditional packaging, it offers advantages such as high packaging efficiency, smaller and thinner chip size after packaging, higher input / output density, and better electrical performance. WLP is mainly divided into two types: fan-in and fan-out. Traditional WLP mostly uses fan-in packaging, applied to integrated circuits (ICs) with a relatively small number of pins. As wafer fabrication technology has advanced from tens of micrometers to nanometers, chip sizes are becoming smaller and the input / output density on the chip surface is becoming higher. To adapt to relatively outdated substrate manufacturing processes and surface packaging structures, fan-out packaging has become increasingly widely used and developed.

[0003] Existing fan-out packaging technology has the following disadvantages:

[0004] (1) Highly integrated and multifunctional miniaturized products cannot achieve the array arrangement of solder balls through a single redistribution layer, which makes the existing fan-out packaging process unable to meet the performance requirements of some high-end products.

[0005] (2) The packaging process of grinding before cutting results in a thicker chip after grinding, which cannot meet the product requirements of lightweight and thinner design.

[0006] (3) The back of the chip after cutting is not protected, which can easily cause hidden cracks and other dark damage during the Pick & Place process. Severe dark damage will be detected during the post-packaging test, resulting in the scrapping of the entire plastic package. If the dark damage is not detected during the post-packaging test, it may cause the scrapping of the whole machine.

[0007] (4) The plastic layer on the side of the encapsulation away from the chip is thicker, resulting in poor heat dissipation of the chip. Summary of the Invention

[0008] This application provides a packaging method and structure for a fan-out wafer-level chip. By setting multiple redistribution layers, solder balls can be arranged in an orderly manner on miniaturized products, meeting the requirements for lightweight and thinner packaged chips. It also protects the back of the chip, reduces hidden cracks and other defects, and consequently reduces the scrap of the packaged structure and the entire device. Furthermore, it improves the heat dissipation performance of the packaged chip and enhances its electromagnetic shielding capability.

[0009] This application provides a packaging method for a fan-out wafer-level chip, including:

[0010] Obtain the wafer to be processed;

[0011] At least one first redistribution layer and at least one first protective layer are fabricated on the wafer to be processed to obtain the structure to be molded; the number of first redistribution layers and the number of first protective layers are equal, and the first protective layer covers a part of the area of ​​the first redistribution layer;

[0012] The structure to be encapsulated is encapsulated to obtain the structure to be prepared.

[0013] At least one second rewiring layer and at least one second protective layer are fabricated on the structure to be fabricated to obtain a first structure to be cut; the second rewiring layer is connected to the first rewiring layer, the number of the second rewiring layer and the number of the second protective layer are equal, and the second protective layer covers a part of the area of ​​the second rewiring layer.

[0014] The first structure to be cut is cut to obtain a packaged fan-out wafer-level chip.

[0015] Furthermore, the wafer to be processed includes a first surface and a second surface, which are disposed opposite to each other;

[0016] At least one first redistribution layer and at least one first protective layer are fabricated on the wafer to be processed to obtain the structure to be molded, including:

[0017] At least one first redistribution layer and at least one first protective layer are prepared on the first surface of the wafer to be processed to obtain the second structure to be cut.

[0018] The second structure to be cut is cut to obtain a set of chips to be packaged.

[0019] Each chip in the chip assembly to be packaged is placed upside down on the carrier, so that the first protective layer is connected to the adhesive layer, resulting in the structure to be molded; the carrier includes an adhesive layer and a support layer, with the adhesive layer disposed on the support layer.

[0020] Furthermore, the structure to be molded is molded to obtain the structure to be prepared, including:

[0021] The structure to be encapsulated is encapsulated to form an encapsulation layer on the second surface and side surface of each chip to be encapsulated;

[0022] The first protective layer of the structure to be encapsulated is peeled off to obtain the structure to be prepared.

[0023] Further, at least one second redistribution layer and at least one second protective layer are fabricated on the structure to be fabricated to obtain the first structure to be cut, including:

[0024] At least one second redistribution layer and at least one second protective layer are prepared on the first protective layer of the structure to be prepared to obtain the structure to be polished.

[0025] The second surface of the structure to be polished is polished to obtain the structure to be sputtered.

[0026] A metal layer is sputtered onto the structure to be sputtered to obtain the first structure to be cut.

[0027] Further, the second surface of the structure to be polished is polished to obtain the structure to be sputtered, including:

[0028] The second surface of the structure to be polished is polished so that the thickness of the encapsulation layer on the second surface of the structure to be polished is within a preset thickness range, thus obtaining the structure to be sputtered.

[0029] Further, at least one second redistribution layer and at least one second protective layer are fabricated on the structure to be fabricated to obtain the first structure to be cut, including:

[0030] At least one second redistribution layer, at least one second protective layer, and a bump under-metallization layer are prepared on the first protective layer of the structure to be prepared.

[0031] Ball reflow processing is performed on the metallization layer under the bump to obtain the first structure to be cut; the first structure to be cut has multiple target solder balls, which are distributed in an array on the first structure to be cut.

[0032] Further, at least one first redistribution layer and at least one first protective layer are prepared on the first surface of the wafer to be processed to obtain a second structure to be diced, including:

[0033] At least one first interconnect layer and at least one first protective layer are prepared on the first surface of the wafer to be processed by photolithography, sputtering and electroplating.

[0034] The first wiring layer is made of copper and aluminum.

[0035] The materials for the first protective layer include polyimide and benzocyclobutene.

[0036] Furthermore, after cutting the second structure to be cut to obtain the chip assembly to be packaged, the process also includes:

[0037] A protective layer is sprayed onto the second surface of each chip in the chip assembly to be packaged.

[0038] Positioning points are set on the second surface of each chip to be packaged in the chip set;

[0039] Each chip in the chip assembly to be packaged is placed upside down on the carrier, so that the first protective layer and the adhesive layer are connected, resulting in the structure to be molded, including:

[0040] Based on the positioning points on the second surface of each packaged chip, each chip in the packaged chip set is inverted on the carrier, so that the first protective layer and the adhesive layer are connected to obtain the structure to be encapsulated.

[0041] Further, the first protective layer of the structure to be encapsulated is peeled off to obtain the structure to be prepared, including:

[0042] Based on the pressure-sensitive properties of the adhesive layer, the structure to be encapsulated is subjected to pressure treatment, causing the first protective layer of the structure to be encapsulated to peel off along the adhesive layer and the support layer, thereby obtaining the structure to be prepared; or;

[0043] Based on the heat-sensitive properties of the adhesive layer, the structure to be encapsulated is heated to cause the adhesive layer and support layer to peel off along the first protective layer of the structure to be encapsulated, thus obtaining the structure to be prepared.

[0044] Accordingly, this application provides a packaging structure for a fan-out wafer-level chip, the structure of which is the structure obtained by the above-described packaging method for a fan-out wafer-level chip;

[0045] Fan-out wafer-level chip packaging structures include:

[0046] The wafer to be processed has a first surface and a second surface.

[0047] At least one first super-wiring layer and at least one first protective layer are disposed on the first surface of the wafer to be processed; the number of first super-wiring layers and the number of first protective layers are equal, and the first protective layer covers a portion of the first super-wiring layer.

[0048] At least one second wiring layer and at least one second protective layer are disposed on the first protective layer; the second wiring layer is connected to the first wiring layer, the number of second wiring layers is equal to the number of second protective layers, and the second protective layer covers a portion of the second wiring layer.

[0049] The embodiments of this application have the following beneficial effects:

[0050] This application discloses a packaging method and structure for a fan-out wafer-level chip. The packaging method includes obtaining a wafer to be processed; fabricating at least one first redistribution layer and at least one first protective layer on the wafer to be processed to obtain a structure to be molded; the number of first redistribution layers and the number of first protective layers are equal, and the first protective layer covers a portion of the first redistribution layer; molding the structure to be molded to obtain a structure to be fabricated; fabricating at least one second redistribution layer and at least one second protective layer on the structure to be fabricated to obtain a first structure to be diced; the second redistribution layer is connected to the first redistribution layer, the number of second redistribution layers and the number of second protective layers are equal, and the second protective layer covers a portion of the second redistribution layer; and dicing the first structure to be diced to obtain a packaged fan-out wafer-level chip. Based on this application embodiment, by setting multiple redistribution layers, the solder balls can be arranged in an orderly manner on miniaturized products. By dicing the second structure to be diced to obtain a set of chips to be packaged, the requirements for lightweight and thin packaged chips can be met. By spraying a protective layer onto the second surface of each chip to be packaged, the back side of the chip can be protected during subsequent sorting and inversion processes, reducing hidden cracks and other defects, thereby reducing the scrap of the package structure and the entire package. Furthermore, by inverting each chip to be packaged onto a carrier for overall molding, grinding followed by cutting can be performed during subsequent packaging processes to further meet the requirements for lightweight and thinner packaged chips. Sputtering a metal layer onto the structure to be sputtered can improve the heat dissipation performance of the packaged chip and enhance its electromagnetic shielding capability. Attached Figure Description

[0051] To more clearly illustrate the technical solutions and advantages in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0052] Figure 1 This is a schematic flowchart of a fan-out wafer-level chip packaging method provided in an embodiment of this application;

[0053] Figure 2 This is a schematic diagram of a fan-out wafer-level chip packaging structure provided in an embodiment of this application.

[0054] Reference numerals: 201-Wafer to be processed, 203-First redistribution layer, 205-First protective layer, 207-Second redistribution layer, 209-Second protective layer, 211-Metal layer. Detailed Implementation

[0055] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings. Obviously, the described embodiments are merely one embodiment of this application, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.

[0056] The term "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of this application. In the description of the embodiments of this application, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. Furthermore, the terms "first," "second," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. In addition, the terms "comprising," "having," and "being," and any variations thereof, are intended to cover non-exclusive inclusion.

[0057] The following describes a specific embodiment of a fan-out wafer-level chip packaging method according to this application. Figure 1 This is a flowchart illustrating a fan-out wafer-level chip packaging method provided in an embodiment of this application. This specification provides the method operation steps shown in the embodiments or flowcharts, but based on conventional or non-inventive labor, more or fewer operation steps may be included. The order of steps listed in the embodiments is merely one of many execution orders and does not represent the only execution order. In actual execution, the methods can be executed in the order shown in the embodiments or drawings, or in parallel (e.g., in a parallel processor or multi-threaded processing environment).

[0058] Specific examples Figure 1 As shown, the packaging method for fan-out wafer-level chips may include:

[0059] S101: Obtain the wafer to be processed.

[0060] In this embodiment, the wafer to be processed may include a first surface and a second surface, which may be disposed opposite to each other. For example, the first surface may be the front side, and the second surface may be the back side. The front side may be the side of the wafer to be processed that has the pad surface.

[0061] S103: Prepare at least one first overlay layer and at least one first protective layer on the wafer to be processed to obtain the structure to be molded; the number of first overlay layers and the number of first protective layers are equal, and the first protective layer covers part of the area of ​​the first overlay layer.

[0062] In this embodiment, at least one first redistribution layer and at least one first protective layer can be prepared on the first surface of the wafer to be processed to obtain a second structure to be diced. The second structure to be diced can be diced to obtain a chip assembly to be packaged. Then, each chip to be packaged in the chip assembly can be inverted on a carrier, so that the first protective layer and the adhesive layer are connected to obtain a structure to be molded. The carrier may include an adhesive layer and a support layer, and the adhesive layer may be disposed on the support layer. The conventional operation of existing packaging processes is to grind first and then diced. This makes it impossible to grind to a very thin thickness, otherwise the wafer is easily cracked during the post-grinding process. However, by using the dicing-before-grinding (DBG) process, the wafer is first diced to a thickness below the target grinding thickness, and then separated into individual chips by the grinding process, which can prepare ultra-thin chips. By dicing the second structure to be diced to obtain a chip assembly to be packaged, the requirements for lightweight and thin packaged chips can be met.

[0063] In one optional embodiment, a redistribution layer and a protective layer can be prepared on the front side of the wafer to be processed, which has pads, using photolithography, sputtering, and electroplating. The pads are then positioned appropriately to obtain a second structure to be diced. The second structure can then be diced along the dicing path on its front side to obtain a chip assembly to be packaged. Optionally, the material of the first redistribution layer can be copper, aluminum, or other conductive metals; this embodiment does not specifically limit the material. The material of the first protective layer can be polyimide, benzocyclobutene, or other insulating materials; this embodiment does not specifically limit the material. The support layer can be glass, a carrier wafer, or other substrates with supporting properties; this embodiment does not specifically limit the material. Furthermore, the wafer to be processed can be automatically separated into multiple individual chips by grinding after dicing.

[0064] In this embodiment, after obtaining the chip assembly to be packaged, a protective layer can be sprayed onto the second surface of each chip in the assembly, and positioning points can be set on the second surface of each chip. Then, each chip can be inverted onto a carrier, so that the first protective layer and the adhesive layer are connected, resulting in a structure to be molded. By spraying a protective layer onto the second surface of each chip, the back side of the chip can be protected during subsequent sorting and inversion, reducing hidden cracks and other defects, thereby reducing the scrap of the packaged structure and the entire machine. Furthermore, by inverting each chip onto the carrier for overall molding, grinding and cutting can be performed before packaging to further meet the requirements for lightweight and thinner packaged chips.

[0065] In one alternative implementation, photoresist can be sprayed onto the back of a single chip, and then exposed and developed using a photomask to ensure a firm bond between the cured photoresist and the back of the chip. Simultaneously, PIN origins can be formed at the pin locations of the single chip as positioning points. Furthermore, a pick-and-place device can be used to adhere the pad surface of the single chip to a carrier wafer with an adhesion layer.

[0066] S105: Perform plastic sealing treatment on the structure to be sealed to obtain the structure to be prepared.

[0067] In this embodiment, the structure to be encapsulated can be encapsulated to form a plastic encapsulation layer on the second surface and side surface of each chip to be encapsulated. Then, the first protective layer of the structure to be encapsulated can be peeled off to obtain the structure to be prepared.

[0068] In this embodiment, the structure to be encapsulated can be processed according to the characteristics of the adhesive layer, so that the adhesive layer and the support layer detach from the structure to be encapsulated. The adhesive layer can have pressure-sensitive properties or thermal properties.

[0069] In one alternative implementation, pressure can be applied to the structure to be encapsulated based on the pressure-sensitive properties of the adhesive layer, causing the first protective layer of the structure to be encapsulated to peel off along the adhesive layer and the support layer, thereby obtaining the structure to be prepared.

[0070] In another alternative implementation, the structure to be molded can be heated based on the thermal properties of the adhesive layer, causing the first protective layer of the structure to be molded to peel off along the adhesive layer and the support layer, thus obtaining the structure to be prepared.

[0071] S107: At least one second rewiring layer and at least one second protective layer are prepared on the structure to be prepared to obtain a first structure to be cut; the second rewiring layer is connected to the first rewiring layer, the number of the second rewiring layer and the number of the second protective layer are equal, and the second protective layer covers part of the area of ​​the second rewiring layer.

[0072] In this embodiment, at least one second redistribution layer and at least one second protective layer can be fabricated on the first protective layer of the structure to be fabricated to obtain the structure to be polished. The second surface of the structure to be polished can then be polished to obtain the structure to be sputtered. A metal layer can then be sputtered onto the structure to be sputtered to obtain the first structure to be cut. By sputtering a metal layer onto the structure to be sputtered, the heat dissipation performance of the packaged chip and the electromagnetic shielding capability can be improved.

[0073] In this embodiment, at least one second redistribution layer, at least one second protective layer, and a metallization layer under the bump can be fabricated on the first protective layer of the structure to be fabricated. Then, a ball-mounting and reflowing process can be performed on the metallization layer under the bump to obtain the first structure to be cut. The first structure to be cut has multiple target solder balls, which are distributed in an array on the first structure to be cut. By setting multiple redistribution layers, the solder balls can be arranged in an orderly manner on miniaturized products.

[0074] In this embodiment, multiple first redistribution layers and multiple first protective layers can be fabricated only on the wafer to be processed to obtain the structure to be molded. A second redistribution layer and a second protective layer are then fabricated on the structure to be fabricated to obtain the first structure to be diced. That is, multiple redistribution layers can be fabricated only inside the chip, which can improve the reliability of the packaged chip, increase molding efficiency, and reduce packaging costs. Alternatively, multiple redistribution layers and multiple protective layers can be omitted from the wafer to be processed to obtain the structure to be molded. Only the second redistribution layer and the second protective layer are fabricated on the structure to be fabricated to obtain the first structure to be diced. That is, multiple redistribution layers and multiple protective layers can be fabricated only outside the chip, which can widen the area for subsequent solder ball fabrication, allowing for the aligned arrangement of solder balls in miniaturized products.

[0075] In one optional embodiment, a redistribution layer and a protective layer can be prepared on the first protective layer of the structure to be prepared, such that the redistribution layer is connected to at least a portion of the redistribution layer in S103, to obtain the structure to be polished. Then, the back side of the structure to be polished can be ground to obtain the structure to be sputtered. A heat sink can be formed on the back side of the structure to be sputtered using a step-by-step sputtering method to obtain the first structure to be cut. Optionally, the material of the second redistribution layer can be copper, aluminum, or other metal materials with conductive properties; this application embodiment does not specifically limit the material. The material of the second protective layer can be polyimide, benzocyclobutene, or other materials with insulating properties; this application embodiment does not specifically limit the material.

[0076] In this embodiment, the second surface of the structure to be polished can be polished so that the thickness of the encapsulation layer on the second surface of the structure to be polished is within a preset thickness range, thereby obtaining the structure to be sputtered.

[0077] In one optional implementation, the back side of the structure to be polished can be polished so that the thickness of the molding compound on the back side of the structure to be polished is within a pre-set thickness range, thus obtaining the structure to be sputtered. By retaining part of the molding compound, the heat dissipation performance of the packaged chip can be improved while protecting the chip.

[0078] In another alternative implementation, the back side of the structure to be polished can be polished to completely remove the plastic encapsulation layer, resulting in the structure to be sputtered. By removing the plastic encapsulation layer, the heat dissipation performance of the packaged chip can be further improved.

[0079] S109: The first structure to be cut is cut to obtain a packaged fan-out wafer-level chip.

[0080] In this embodiment of the application, the first structure to be cut can be cut along the cutting path on the front side of the first structure to be cut to obtain a packaged fan-out wafer-level chip.

[0081] The fan-out wafer-level chip packaging method provided in this application, by setting multiple redistribution layers, enables the orderly arrangement of solder balls on miniaturized products. By cutting the second dicing structure to obtain a collection of chips to be packaged, the requirements for lightweight and thinner packaged chips can be met. By spraying a protective layer onto the second surface of each chip to be packaged, the back side of the chip can be protected during subsequent sorting and inversion processes, reducing hidden cracks and other defects, thereby reducing the scrap of the packaged structure and the entire machine. Furthermore, by inverting each chip to be packaged on a carrier for overall molding, grinding followed by cutting can be performed during subsequent packaging processes to further meet the requirements for lightweight and thinner packaged chips. By sputtering a metal layer onto the sputtering structure, the heat dissipation performance of the packaged chip and the electromagnetic shielding capability can be improved.

[0082] This application also provides a fan-out wafer-level chip packaging structure. Figure 2 This is a schematic diagram of a fan-out wafer-level chip packaging structure provided in an embodiment of this application.

[0083] In this embodiment, the packaging structure of the fan-out wafer-level chip can be based on the structure obtained by the above-described packaging method for the fan-out wafer-level chip. The packaging structure of the fan-out wafer-level chip may include a wafer to be processed, at least one first multi-level wiring layer, at least one first protective layer, at least one second multi-level wiring layer, and at least one second protective layer. The wafer to be processed may have a first surface and a second surface. At least one first multi-level wiring layer and at least one first protective layer may be disposed on the first surface of the wafer to be processed. The number of first multi-level wiring layers is equal to the number of first protective layers, and the first protective layer covers a portion of the first multi-level wiring layer. At least one second multi-level wiring layer and at least one second protective layer may be disposed on the first protective layer. The second multi-level wiring layer is connected to the first multi-level wiring layer. The number of second multi-level wiring layers is equal to the number of second protective layers, and the second protective layer covers a portion of the second multi-level wiring layer.

[0084] In this embodiment, the material of the first redistribution layer can be copper, aluminum, or other conductive metals; this embodiment does not impose specific limitations. The material of the first protective layer can be polyimide, benzocyclobutene, or other insulating materials; this embodiment does not impose specific limitations. The material of the second redistribution layer can be copper, aluminum, or other conductive metals; this embodiment does not impose specific limitations. The material of the second protective layer can be polyimide, benzocyclobutene, or other insulating materials; this embodiment does not impose specific limitations.

[0085] In this embodiment of the application, the packaging structure of the fan-out wafer-level chip may include a metal layer. The metal layer may be disposed on the second surface of the wafer to be processed. The metal layer may serve as a heat dissipation layer to improve heat dissipation performance, or as a shielding layer to improve electromagnetic shielding capability.

[0086] In this embodiment of the application, the packaging structure of the fan-out wafer-level chip may include a metallization layer under the bump, and a plurality of target solder balls distributed in an array may be provided on the metallization layer under the bump.

[0087] like Figure 2 As shown, in one optional embodiment, the fan-out wafer-level chip packaging structure may include a wafer to be processed 201, a first redistribution layer 203, a first protective layer 205, a second redistribution layer 207, a second protective layer 209, and a metal layer 211. The wafer to be processed may have a first surface and a second surface. The first redistribution layer and the first protective layer may be disposed on the first surface of the wafer to be processed, with the first protective layer covering a portion of the first redistribution layer. The second redistribution layer and the second protective layer may be disposed on the first protective layer, with the second redistribution layer connected to the first redistribution layer, and the second protective layer covering a portion of the second redistribution layer. The metal layer may be disposed on the second surface of the wafer to be processed.

[0088] The structural and method embodiments in this application are based on the same application concept.

[0089] The fan-out wafer-level chip packaging structure provided in this application has multiple redistribution layers, enabling the neat arrangement of solder balls in miniaturized products. This meets the requirements for lightweight and thinner packaged chips, reduces hidden cracks and other defects, and consequently reduces the scrap of packaged structures and the entire device. Furthermore, it improves the heat dissipation performance of the packaged chip.

[0090] As can be seen from the embodiments of the fan-out wafer-level chip packaging method or packaging structure provided in this application, the packaging method includes obtaining a wafer to be processed; preparing at least one first redistribution layer and at least one first protective layer on the wafer to be processed to obtain a structure to be molded; the number of first redistribution layers and the number of first protective layers are equal, and the first protective layer covers a portion of the first redistribution layer; molding the structure to be molded to obtain a structure to be prepared; preparing at least one second redistribution layer and at least one second protective layer on the structure to be prepared to obtain a first structure to be diced; the second redistribution layer is connected to the first redistribution layer, the number of second redistribution layers and the number of second protective layers are equal, and the second protective layer covers a portion of the second redistribution layer; dicing the first structure to be diced to obtain a packaged fan-out wafer-level chip. Based on the embodiments of this application, by setting multiple redistribution layers, the solder balls can be arranged in an orderly manner on miniaturized products. By dicing the second structure to be diced to obtain a set of chips to be packaged, the requirements for lightweight and thin packaged chips can be met. By spraying a protective layer onto the second surface of each chip to be packaged, the back side of the chip can be protected during subsequent sorting and inversion processes, reducing hidden cracks and other defects, thereby reducing the scrap of the package structure and the entire package. Furthermore, by inverting each chip to be packaged onto a carrier for overall molding, grinding followed by cutting can be performed during subsequent packaging processes to further meet the requirements for lightweight and thinner packaged chips. Sputtering a metal layer onto the structure to be sputtered can improve the heat dissipation performance of the packaged chip and enhance its electromagnetic shielding capability.

[0091] In this invention, unless otherwise explicitly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the connection within two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0092] It should be noted that the order of the embodiments described above is merely for descriptive purposes and does not represent the superiority or inferiority of the embodiments. Furthermore, while this specification describes specific embodiments, other embodiments are also within the scope of the appended claims. In some cases, the actions or steps described in the claims can be performed in the order shown in different embodiments and still achieve the desired results. Additionally, the processes depicted in the drawings do not necessarily require a specific order or sequence of connections to achieve the desired results; in some implementations, parallel processing of multiple tasks is possible or may be advantageous.

[0093] The various embodiments in this specification are described in a progressive manner. Similar or identical parts between embodiments can be referred to interchangeably. Each embodiment focuses on its differences from other embodiments. In particular, structural embodiments are described simply because they are based on similarities to method embodiments; relevant details can be found in the descriptions of the method embodiments.

[0094] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A packaging method for a fan-out wafer-level chip, characterized in that, include: Obtain the wafer to be processed; At least one first redistribution layer and at least one first protective layer are fabricated on the wafer to be processed to obtain a chip assembly to be packaged. A protective layer is sprayed onto the second surface of each chip in the chip set to be packaged, and positioning points are set. Based on the positioning points on the second surface of each chip, each chip in the chip set to be packaged is inverted on a carrier to obtain a molding structure. The number of the first redistribution layers is equal to the number of the first protective layers, and the first protective layer covers a portion of the first redistribution layer. The structure to be encapsulated is encapsulated to obtain the structure to be prepared; At least one second redistribution layer and at least one second protective layer are prepared on the first protective layer of the structure to be prepared to obtain the structure to be polished; the second redistribution layer is connected to the first redistribution layer, the number of the second redistribution layer and the number of the second protective layer are equal, and the second protective layer covers a part of the second redistribution layer; The back side of the structure to be polished is polished so that the thickness of the encapsulation layer on the back side of the structure to be polished is within a preset thickness range, and part of the encapsulation layer is retained to obtain the structure to be sputtered. A metal layer is sputtered onto the structure to be sputtered to obtain a first structure to be cut. The first structure to be cut is cut to obtain a packaged fan-out wafer-level chip.

2. The method according to claim 1, characterized in that, The wafer to be processed includes a first surface and a second surface, which are disposed opposite to each other; the carrier includes an adhesive layer and a support layer, with the adhesive layer disposed on the support layer; the first protective layer is connected to the adhesive layer. The process involves fabricating at least one first redistribution layer and at least one first protective layer on the wafer to be processed to obtain the assembly of chips to be packaged, including: At least one first redistribution layer and at least one first protective layer are prepared on the first surface of the wafer to be processed to obtain a second structure to be cut. The second structure to be cut is cut to obtain the chip assembly to be packaged.

3. The method according to claim 2, characterized in that, The process of molding the structure to be molded to obtain the structure to be prepared includes: The structure to be encapsulated is encapsulated to form an encapsulation layer on the second surface and side surface of each chip to be encapsulated. The first protective layer of the structure to be encapsulated is peeled off to obtain the structure to be prepared.

4. The method according to claim 1, characterized in that, The process of preparing at least one second redistribution layer and at least one second protective layer on the first protective layer of the structure to be prepared, to obtain the structure to be polished, includes: At least one second redistribution layer, at least one second protective layer, and a metallization layer under the bump are prepared on the first protective layer of the structure to be prepared. A ball-mounting reflow process is performed on the metallization layer under the bump to obtain the first structure to be cut; the first structure to be cut has a plurality of target solder balls, which are distributed in an array on the first structure to be cut.

5. The method according to claim 2, characterized in that, The process of fabricating at least one first redistribution layer and at least one first protective layer on the first surface of the wafer to be processed to obtain a second structure to be diced includes: At least one first redistribution layer and at least one first protective layer are prepared on the first surface of the wafer to be processed using photolithography, sputtering, and electroplating. The material of the first wiring layer is copper or aluminum; The materials of the first protective layer include polyimide and benzocyclobutene.

6. The method according to claim 3, characterized in that, The process of peeling off the first protective layer along the structure to be encapsulated to obtain the structure to be prepared includes: Based on the pressure-sensitive properties of the adhesive layer, the structure to be encapsulated is subjected to pressure treatment, causing the first protective layer of the structure to be encapsulated to peel off along the adhesive layer and the support layer, thereby obtaining the structure to be prepared; or; Based on the thermally sensitive properties of the adhesive layer, the structure to be encapsulated is heated to cause the first protective layer of the structure to be encapsulated to peel off along the adhesive layer and the support layer, thereby obtaining the structure to be prepared.

7. A fan-out wafer-level chip packaging structure, characterized in that, The structure of the fan-out wafer-level chip is obtained based on the packaging method of the fan-out wafer-level chip according to claim 1; The packaging structure of the fan-out wafer-level chip includes: The wafer to be processed has a first surface and a second surface. At least one first redistribution layer and at least one first protective layer are disposed on the first surface of the wafer to be processed; the number of the first redistribution layers and the number of the first protective layers are equal, and the first protective layer covers a portion of the first redistribution layer. At least one second rewiring layer and at least one second protective layer are disposed on the first protective layer; the second rewiring layer is connected to the first rewiring layer, the number of second rewiring layers is equal to the number of second protective layers, and the second protective layer covers a portion of the second rewiring layer.

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