Semiconductor structure and method of forming the same

Abstract

A semiconductor structure and a forming method thereof, the structure comprising: a substrate, the substrate comprising a substrate and a fin protruding from the substrate, the substrate comprising a first device region and a second device region in a direction perpendicular to the extending direction of the fin, the device working voltage of the second device region being greater than that of the first device region, the fin height of the first device region and the second device region being equal; an isolation layer on the substrate exposed by the fin, the isolation layer covering part of the sidewall of the fin, and the top of the isolation layer of the second device region being higher than that of the first device region; a first gate oxide layer in the second device region and conformally covering the fin exposed by the isolation layer; and a second gate oxide layer in the first device region and conformally covering the fin exposed by the isolation layer, and the thickness of the second gate oxide layer being less than that of the first gate oxide layer. The top of the isolation layer of the second device region being higher than that of the first device region improves the filling performance of the gate structure in the second device region.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and more particularly to a semiconductor structure and a method for forming the same. Background Technology

[0002] As semiconductor process technology advances, semiconductor process nodes are shrinking in accordance with Moore's Law. To accommodate this shrinking process node, the channel length of MOSFETs is also continuously shortening. However, as the channel length decreases, the distance between the source and drain also decreases, resulting in poorer gate control over the channel and increasing the difficulty of pinching off the channel with the gate voltage. This makes subthreshold leakage, also known as short-channel effects (SCE), more likely to occur.

[0003] Therefore, in order to better adapt to the requirements of proportionally shrinking device dimensions, semiconductor processes have gradually begun to transition from planar MOSFETs to three-dimensional transistors with higher efficiency, such as Fin Field-Effect Transistors (FinFETs). In FinFETs, the gate can control the ultra-thin body (fin) from at least both sides. Compared with planar MOSFETs, the gate has stronger control over the channel and can effectively suppress short-channel effects. Moreover, FinFETs have better compatibility with existing integrated circuit manufacturing compared to other devices.

[0004] Furthermore, semiconductor devices are mainly classified into core devices and input / output (I / O) devices according to their functions. Typically, the operating voltage of I / O devices is much higher than that of core devices. The higher the operating voltage, the thicker the gate oxide layer deposited on the fins. Moreover, as the spacing between the fins of semiconductor devices becomes smaller, the filling performance of the gate structure is affected to some extent during the formation of the gate structure on the I / O device region. Summary of the Invention

[0005] The problem addressed by the embodiments of the present invention is to provide a semiconductor structure and a method for forming the same, thereby improving the electrical performance of the semiconductor structure.

[0006] To address the aforementioned problems, embodiments of the present invention provide a semiconductor structure comprising: a substrate, the substrate including a base and fins protruding from the base, and in a direction perpendicular to the extending direction of the fins, the substrate including a first device region and a second device region, wherein the device operating voltage of the second device region is greater than the device operating voltage of the first device region, and the fins of the first and second device regions have equal heights; an isolation layer located on the substrate where the fins are exposed, the isolation layer covering a portion of the sidewalls of the fins, and the top of the isolation layer in the second device region being higher than the top of the isolation layer in the first device region; a first gate oxide layer located in the second device region and conformally covering the fins exposed in the isolation layer; a second gate oxide layer located in the first device region and conformally covering the fins exposed in the isolation layer, and the thickness of the second gate oxide layer being less than the thickness of the first gate oxide layer; and a gate structure spanning the fins of the first and second device regions and covering the first and second gate oxide layers.

[0007] Accordingly, embodiments of the present invention also provide a method for forming a semiconductor structure, comprising: providing a substrate, including a substrate and a plurality of discrete fins located on the substrate, wherein the substrate includes a first device region and a second device region along a direction perpendicular to the extension direction of the fins, the device operating voltage of the second device region is greater than the device operating voltage of the first device region, and the fins of the first device region and the second device region have equal heights; forming a first isolation layer on the substrate of the first device region, the first isolation layer covering a portion of the sidewalls of the fins; forming a second isolation layer on the substrate of the second device region, the second isolation layer covering a portion of the sidewalls of the fins, and the top surface of the second isolation layer being higher than the top surface of the first isolation layer; forming a first gate oxide layer conformally covering the fins exposed to the second isolation layer in the second device region; forming a second gate oxide layer conformally covering the fins exposed to the first isolation layer in the first device region, and the thickness of the second gate oxide layer being less than the thickness of the first gate oxide layer; and forming a gate structure spanning the fins and covering the first gate oxide layer and the second gate oxide layer in the first device region and the second device region.

[0008] Compared with the prior art, the technical solution of the embodiments of the present invention has the following advantages:

[0009] In the semiconductor structure disclosed in this embodiment of the invention, the substrate includes an adjacent first device region and a second device region. The substrate includes a substrate and a fin protruding from the substrate. An isolation layer is located on the substrate exposed by the fin, and the top of the isolation layer in the second device region is higher than the top of the isolation layer in the first device region. A first gate oxide layer is located in the second device region and conformally covers the fin exposed by the isolation layer. A second gate oxide layer is located in the first device region and conformally covers the fin exposed by the isolation layer. The thickness of the second gate oxide layer is less than the thickness of the first gate oxide layer. A gate structure spans the fins of the first and second device regions and covers the first and second gate oxide layers. When the device is working, since the operating voltage of the second device region is greater than that of the first device region, the thickness of the first gate oxide layer is greater than that of the second gate oxide layer. In this embodiment of the invention, by making the top of the isolation layer of the second device region higher than the top of the isolation layer of the first device region, the height of the fins exposed in the isolation layer in the second device region is reduced, thereby reducing the aspect ratio between the first gate oxide layers in the second device region. Therefore, even if the thickness of the first gate oxide layer is greater than that of the second gate oxide layer, the filling performance of the gate structure in the second device region is improved during the formation of the gate structure, thereby improving the performance of the semiconductor.

[0010] In the semiconductor structure formation method disclosed in this embodiment of the invention, the substrate includes an adjacent first device region and a second device region, wherein the device operating voltage of the second device region is greater than that of the first device region. The substrate includes a substrate and a fin protruding from the substrate. A first isolation layer is formed on the substrate of the first device region, and the first isolation layer covers a portion of the sidewalls of the fin. A second isolation layer is formed on the substrate of the second device region, and the second isolation layer covers a portion of the sidewalls of the fin. The top surface of the second isolation layer is higher than the top surface of the first isolation layer. Then, in the second device region, a first gate oxide layer is formed conformally covering the fin exposed to the second isolation layer. In the first device region, a second gate oxide layer is formed conformally covering the fin exposed to the first isolation layer. The thickness of the second gate oxide layer is less than that of the first gate oxide layer. Finally, in the first and second device regions, a gate structure is formed that spans the fin and covers the first and second gate oxide layers. When the device is working, since the operating voltage of the second device region is greater than that of the first device region, the thickness of the first gate oxide layer is greater than that of the second gate oxide layer. In this embodiment of the invention, by making the top of the isolation layer of the second device region higher than the top of the isolation layer of the first device region, the height of the fins exposed in the isolation layer in the second device region is reduced, thereby reducing the aspect ratio between the first gate oxide layers in the second device region. Therefore, even if the thickness of the first gate oxide layer is greater than that of the second gate oxide layer, the filling performance of the gate structure in the second device region is improved during the formation of the gate structure, thereby improving the performance of the semiconductor. Attached Figure Description

[0011] Figures 1 to 3 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0012] Figure 4 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention;

[0013] Figures 5 to 16 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention. Detailed Implementation

[0014] Currently, the performance of semiconductor structures still needs improvement. This paper analyzes the reasons why the performance of semiconductor structures needs further improvement, using one method for forming a semiconductor structure as an example. Figures 1 to 3 This is a schematic diagram of the structure corresponding to each step in a method for forming a semiconductor structure.

[0015] refer to Figure 1A substrate is provided, the substrate including a substrate 10 and a plurality of discrete fins 12 located on the substrate 10. An isolation layer 11 is formed on the substrate 10 where the fins 12 are exposed. The isolation layer 11 covers part of the sidewalls of the fins 12 in a direction perpendicular to the extension direction of the fins 12. The substrate includes a first device region 10A, a second device region 10B and a third device region 10C. The device operating voltages of the first device region 10A, the second device region 10B and the third device region 10C increase sequentially. The heights of the fins 12 in the first device region 10A, the second device region 10B and the third device region 10C are equal. A first gate oxide layer 13 is formed on the substrate to conformally cover the fins 12.

[0016] refer to Figure 2 The first gate oxide layer 13 of the first device region 10A and the second device region 10B is removed, while the first gate oxide layer 13 of the third device region 10C is retained. After removing the first gate oxide layer 13 of the first device region 10A and the second device region 10B, a second gate oxide layer 14 is formed in the first device region 10A and the second device region 10B to conformally cover the fin 12. The thickness of the first gate oxide layer 13 is greater than the thickness of the second gate oxide layer 14.

[0017] refer to Figure 3 A third gate oxide layer 15 is formed to conformally cover the first gate oxide layer 13 and the second gate oxide layer 14; after the third gate oxide layer 15 is formed, the third gate oxide layer 15 and the second gate oxide layer 14 of the first device region 10A are removed until the fin 12 of the first device region 10A is exposed.

[0018] The first gate oxide layer 13 and the third gate oxide layer 15 of the third device region 10C are used to form the gate dielectric layer of the third device region 10C, and the second gate oxide layer 14 and the third gate oxide layer 15 of the second device region 10B are used to form the gate dielectric layer of the second device region 10B.

[0019] Research has shown that the higher the operating voltage of the device region, the greater the thickness of the gate dielectric layer deposited on the fins of that device region. Figure 3 As shown, the device operating voltage of the third device region 10C is greater than that of the second device region 10B, which results in the gate dielectric layer thickness of the third device region 10C being greater than that of the second device region 10B. Since the spacing between adjacent fins 12 becomes smaller, the aspect ratio between the gate dielectric layers of the third device region 10C becomes larger. This increases the difficulty of filling the device gate structure during the subsequent formation of the device gate structure in the third device region 10C, which in turn easily leads to a decrease in the performance of the semiconductor structure.

[0020] To address the aforementioned technical problem, embodiments of the present invention provide a method for fabricating a semiconductor structure, comprising: providing a substrate, including a substrate and a plurality of discrete fins located on the substrate, wherein the substrate includes a first device region and a second device region along a direction perpendicular to the extension direction of the fins, the device operating voltage of the second device region being greater than the device operating voltage of the first device region, and the fins of the first device region and the second device region having equal heights; forming a first isolation layer on the substrate of the first device region, the first isolation layer covering a portion of the sidewalls of the fins; forming a second isolation layer on the substrate of the second device region, the second isolation layer covering a portion of the sidewalls of the fins, and the top surface of the second isolation layer being higher than the top surface of the first isolation layer; forming a first gate oxide layer conformally covering the fins exposed to the second isolation layer in the second device region; forming a second gate oxide layer conformally covering the fins exposed to the first isolation layer in the first device region, and the thickness of the second gate oxide layer being less than the thickness of the first gate oxide layer; and forming a gate structure spanning the fins and covering the first gate oxide layer and the second gate oxide layer in the first device region and the second device region.

[0021] In the embodiment of the present invention, the substrate includes an adjacent first device region and a second device region, wherein the device operating voltage of the second device region is greater than that of the first device region. The substrate includes a substrate and a fin protruding from the substrate. A first isolation layer is formed on the substrate of the first device region, and the first isolation layer covers a portion of the sidewalls of the fin. A second isolation layer is formed on the substrate of the second device region, and the second isolation layer covers a portion of the sidewalls of the fin. The top surface of the second isolation layer is higher than the top surface of the first isolation layer. Then, in the second device region, a first gate oxide layer is formed conformally covering the fin exposed to the second isolation layer. In the first device region, a second gate oxide layer is formed conformally covering the fin exposed to the first isolation layer. The thickness of the second gate oxide layer is less than the thickness of the first gate oxide layer. Finally, in the first and second device regions, a gate structure is formed that spans the fin and covers the first and second gate oxide layers. When the device is working, since the operating voltage of the second device region is greater than that of the first device region, the thickness of the first gate oxide layer is greater than that of the second gate oxide layer. In this embodiment of the invention, by making the top of the isolation layer of the second device region higher than the top of the isolation layer of the first device region, the height of the fins exposed in the isolation layer in the second device region is reduced, thereby reducing the aspect ratio between the first gate oxide layers in the second device region. Therefore, even if the thickness of the first gate oxide layer is greater than that of the second gate oxide layer, the filling performance of the gate structure in the second device region is improved during the formation of the gate structure, thereby improving the performance of the semiconductor.

[0022] To make the above-mentioned objects, features and advantages of the embodiments of the present invention more apparent and understandable, the specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0023] Figure 4 This is a schematic diagram of a semiconductor structure according to an embodiment of the present invention.

[0024] The semiconductor structure includes: a substrate, the substrate including a substrate 200 and fins 201 protruding from the substrate 200 in a direction perpendicular to the extending direction of the fins 201; the substrate including a first device region 200B and a second device region 200C; the device operating voltage of the second device region 200C being greater than the device operating voltage of the first device region 200B; and the heights of the fins 201 of the first device region 200B and the second device region 200C being equal; and an isolation layer 203 located on the substrate 200 exposed by the fins 201, the isolation layer 203 covering a portion of the sidewalls of the fins 201, and the isolation layer 203 covering the second device region 200C. The top of the release layer 203 is higher than the top of the isolation layer 203 of the first device region 200B; the first gate oxide layer 204 is located in the second device region 200C and conformally covers the fins 201 exposed by the isolation layer 203; the second gate oxide layer 206 is located in the first device region 200B and conformally covers the fins 201 exposed by the isolation layer 203, and the thickness of the second gate oxide layer 206 is less than the thickness of the first gate oxide layer 204; the gate structure 240 spans the fins 201 of the first device region 200B and the second device region 200C, and covers the first gate oxide layer 204 and the second gate oxide layer 206.

[0025] When the device is operating, since the operating voltage of the second device region 200C is greater than that of the first device region 200B, the thickness of the first gate oxide layer 204 is greater than that of the second gate oxide layer 206. Compared with the scheme where the top of the isolation layer 203 of the second device region 200C is flush with the top of the isolation layer 203 of the first device region 200B, this embodiment of the invention reduces the height of the fins 201 exposed in the isolation layer 203 of the second device region 200C by making the top of the isolation layer 203 of the second device region 200C higher than that of the isolation layer 203 of the first device region 200B. This reduces the aspect ratio between the first gate oxide layers 204 of the second device region 200C. Therefore, even though the thickness of the first gate oxide layer 204 is greater than that of the second gate oxide layer 206, the filling performance of the gate structure 240 in the second device region 200C is improved during the formation of the gate structure 240, thereby improving the performance of the semiconductor.

[0026] In this embodiment, the substrate is used to form a fin field-effect transistor (FinFET). The substrate includes a substrate 200 and fins 201 protruding from the substrate 200.

[0027] In this embodiment, the substrate 200 is a silicon substrate. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, etc., and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, etc.

[0028] In this embodiment, the material of the fin 201 is the same as the material of the substrate 200, and the material of the fin 201 is silicon. In other embodiments, the material of the fin may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide.

[0029] In this embodiment, the substrate includes a first device region 200B and a second device region 200C, wherein the device operating voltage of the second device region 200C is greater than the device operating voltage of the first device region 200B. Correspondingly, the gate dielectric layer thickness of the second device region 200C is greater than the gate dielectric layer thickness of the first device region 200B.

[0030] Specifically, both the first device area 200B and the second device area 200C are used to form input / output (I / O) devices.

[0031] In this embodiment, the substrate further includes a third device region 200A, wherein the device operating voltage of the third device region 200A is lower than the device operating voltage of the first device region 200B. Correspondingly, the gate dielectric layer thickness in the third device region 200A is less than the gate dielectric layer thickness in the first device region 200B.

[0032] Specifically, the third device region 200A is used to form a core device.

[0033] In this embodiment, the fins 201 of the first device region 200B, the second device region 200C, and the third device region 200A are all of equal height.

[0034] In this embodiment, the top of the isolation layer 203 of the third device region 200A is flush with the top of the isolation layer 203 of the first device region 200B.

[0035] In this embodiment, the isolation layer 203 is located on the substrate 200 exposed by the fin 201, the isolation layer 203 covers part of the sidewall of the fin 201, and the top of the isolation layer 203 of the second device region 200C is higher than the top of the isolation layer 203 of the first device region 200B.

[0036] The isolation layer 203 is used to isolate adjacent devices. The material of the isolation layer 203 can be silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the material of the isolation layer 203 is silicon oxide.

[0037] In this embodiment, the top of the isolation layer 203 of the second device region 200C is higher than the top of the isolation layer 203 of the first device region 200B. By reducing the height of the fins 201 exposed in the isolation layer 203 in the second device region 200C, the aspect ratio between the first gate oxide layers 204 in the second device region 200C is reduced. Therefore, even if the thickness of the first gate oxide layer 204 is greater than the thickness of the second gate oxide layer, the filling performance of the gate structure 240 in the second device region 200C is improved during the formation of the gate structure 240, thereby improving the performance of the semiconductor.

[0038] In this embodiment, the top of the isolation layer 203 of the second device region 200C is 5 nanometers to 20 nanometers higher than the top of the isolation layer 203 of the first device region 200B.

[0039] It should be noted that the top of the isolation layer 203 of the second device region 200C should not be too large or too small compared to the top of the isolation layer 203 of the first device region 200B. If the top of the isolation layer 203 in the second device region 200C is significantly higher than the top of the isolation layer 203 in the first device region 200B, then even if the height of the exposed fins 201 in the isolation layer 203 of the second device region 200C meets the process requirements, the height of the exposed fins 201 in the isolation layer 203 of the first device region 200B will be excessively high. This will increase the aspect ratio between the first gate oxide layers 204 in the first device region 200B, affecting the filling effect of the gate structure 240 and consequently the performance of the semiconductor structure. Conversely, if the top of the isolation layer 203 in the second device region 200C is significantly higher than the top of the isolation layer 203 in the first device region 200B, the aspect ratio between the first gate oxide layers 204 in the second device region 200C will still be large, affecting the filling effect of the gate structure 240 and consequently the performance of the semiconductor structure. Therefore, in this embodiment, the top of the isolation layer 203 of the second device region 200C is 5 nanometers to 20 nanometers higher than the top of the isolation layer 203 of the first device region 200B.

[0040] It should be noted that the height of the exposed fins 201 in the isolation layer 203 of the second device region 200C should not be too large or too small. If the height of the exposed fins 201 in the isolation layer 203 of the second device region 200C is too large, it will easily lead to a large depth-to-width ratio between the first gate oxide layers 204 during the formation of the gate structure 240 in the second device region 200C, increasing the difficulty of filling the gate structure 240 and thus affecting the performance of the semiconductor device. If the height of the exposed fins 201 in the isolation layer 203 of the second device region 200C is too small, it will easily lead to insufficient space for forming the gate structure 240, thereby reducing the control capability of the gate structure 240 over the channel. Moreover, if the height of the fins 201 covered by the gate structure 240 is also too small, the carrier flux in the exposed fins 201 in the isolation layer 203 will be too small, thus affecting the performance of the semiconductor device. Therefore, in this embodiment, the height of the fin 201 exposed by the isolation layer 203 of the second device region 200C is 40 nanometers to 50 nanometers.

[0041] In this embodiment, the first gate oxide layer 204 is located in the second device region 200C and conformally covers the fin 201 of the isolation layer 203. The second gate oxide layer 206 is located in the first device region 200B and conformally covers the fin 201 of the isolation layer 203.

[0042] Generally, the higher the operating voltage of a semiconductor device, the thicker the gate oxide layer exposed on the fins of the isolation layer. In this embodiment, the device operating voltage of the second device region 200C is greater than the device operating voltage of the first device region 200B. Therefore, the thickness of the gate oxide layer in the first device region 200B is less than the thickness of the gate oxide layer in the second device region 200C.

[0043] Accordingly, in this embodiment, the thickness of the second gate oxide layer 206 in the first device region 200B is less than the thickness of the first gate oxide layer 204 in the second device region 200C.

[0044] The second gate oxide layer 206 provides the process basis for the device operating voltage required by the semiconductor device in the first device region 200B, and the first gate oxide layer 204 provides the process basis for the higher device operating voltage required by the semiconductor device in the second device region 200C.

[0045] In this embodiment, the first gate oxide layer 204 also conformally covers the top of the isolation layer 203 of the second device region 200C. Accordingly, the first gate oxide layer 204 is formed by a deposition process.

[0046] In this embodiment, the second gate oxide layer 206 conformally covers only the fin 201 exposed in the isolation layer 203. Accordingly, the second gate oxide layer 206 is formed by an oxidation process.

[0047] In this embodiment, the semiconductor structure further includes a third gate oxide layer 207, located between the gate structure 240 and the first gate oxide layer 204, and between the gate structure 240 and the second gate oxide layer 206.

[0048] In the first device region 200B, the third gate oxide layer 207 and the second gate oxide layer 206 constitute the gate oxide layer of the first device region 200B, and the third gate oxide layer 207 and the second gate oxide layer 206 together provide the process basis for the device operating voltage required by the first device region 200B.

[0049] In the second device region 200C, the third gate oxide layer 207 and the first gate oxide layer 204 constitute the gate oxide layer of the second device region 200C. The third gate oxide layer 207 and the first gate oxide layer 204 together provide the process basis for the device operating voltage required by the second device region 200C.

[0050] It should be noted that the second gate oxide layer 206 is formed by a thermal oxidation process. In order to ensure that the device operating voltage of the first device region 200B meets the process requirements, the third gate oxide layer 207 needs to be formed on the first device region 200B.

[0051] In this embodiment, the third gate oxide layer 207 also conformally covers the top of the isolation layer 203. Accordingly, the third gate oxide layer 207 is formed by a deposition process.

[0052] It should be noted that the thickness of the first gate oxide layer 204 should not be too large or too small. If the thickness of the first gate oxide layer 204 is too large, given a fixed gate dielectric layer thickness in the second device region 200C, it can easily lead to an insufficient thickness of the third gate oxide layer 207 in the second device region 200C, which in turn leads to an insufficient thickness of the third gate oxide layer 207 in the first device region 200B. Consequently, this affects the device operating voltage in the first device region 200B, failing to meet process requirements. Furthermore, if the thickness of the first gate oxide layer 204 is too large, it can also easily cause the process of forming the first gate oxide layer 204 to affect the fin 20. Excessive loss in fin 201 will affect the linewidth of fin 201, thus impacting the electrical performance of the semiconductor. If the thickness of the first gate oxide layer 204 is too small, given a fixed gate dielectric layer thickness in the second device region 200C, the thickness of the third gate oxide layer 207 in the second device region 200C may become excessive, consequently leading to an excessively large thickness of the third gate oxide layer 207 in the first device region 200B. This, in turn, affects the device operating voltage in the first device region 200B, failing to meet process requirements and thus impacting the electrical performance of the semiconductor. Therefore, in this embodiment, the thickness of the first gate oxide layer 204 is 8 nanometers to 15 nanometers.

[0053] It should be noted that the thickness of the second gate oxide layer 206 should not be too large or too small. If the thickness of the second gate oxide layer 206 is too large, given a fixed thickness of the gate dielectric layer in the first device region 200B, it can easily lead to an insufficient thickness of the third gate oxide layer 207 in the first device region 200B, which in turn leads to an insufficient thickness of the third gate oxide layer 207 in the second device region 200C. Consequently, this affects the device operating voltage in the second device region 200C, failing to meet process requirements and thus impacting the electrical performance of the semiconductor. Conversely, if the thickness of the second gate oxide layer 206 is too small, given a fixed thickness of the gate dielectric layer in the first device region 200B, it can easily lead to an excessive thickness of the third gate oxide layer 207 in the first device region 200B, which in turn leads to an excessive thickness of the third gate oxide layer 207 in the second device region 200C. Consequently, this affects the device operating voltage in the second device region 200C, failing to meet process requirements and thus impacting the electrical performance of the semiconductor. Therefore, in this embodiment, the thickness of the second gate oxide layer 206 is 20 nanometers to 35 nanometers.

[0054] In this embodiment, the gate structure 240 spans the fin 201 of the first device region 200B and the second device region 200C, and covers the first gate oxide layer 204 and the second gate oxide layer 206.

[0055] The gate structure 240 is used to control the opening or closing of the conductive channel when the device is in operation.

[0056] In this embodiment, the gate structure 240 includes a metal gate structure. As the critical dimensions of devices continue to shrink, the use of a metal gate structure helps to improve the short-channel effect.

[0057] In this embodiment, the gate structure 240 includes a high-k gate dielectric layer 213 that conformally covers the fin 201 and the isolation layer 203, a work function layer 212 that conformally covers the high-k gate dielectric layer 213, and a gate electrode layer 216 that conformally covers the work function layer 212.

[0058] The high-k gate dielectric layer 213 is made of a high-k dielectric material, which refers to a dielectric material with a relative permittivity greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer 213 can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc.

[0059] In this embodiment, in the first device region 200B, the second gate oxide layer 206, the third gate oxide layer 207, and the high-k gate dielectric layer 213 constitute the gate dielectric layer of the first device region 200B; in the second device region 200C, the first gate oxide layer 204, the third gate oxide layer 207, and the high-k gate dielectric layer 213 constitute the gate dielectric layer of the second device region 200C; and in the third device region 200A, the high-k gate dielectric layer 213 constitutes the gate dielectric layer of the third device region 200A.

[0060] As the device operating voltages of the second device region 200C, the first device region 200B, and the third device region 200A decrease sequentially, the gate dielectric layer thicknesses of the second device region 200C, the first device region 200B, and the third device region 200A decrease sequentially.

[0061] The work function layer 212 is used to adjust the threshold voltage of the formed transistor. When forming a PMOS transistor, the work function layer 212 is a P-type work function layer, and the material of the P-type work function layer includes one or more of TiN, TaN, TaSiN, TaAlN, and TiAlN; when forming an NMOS transistor, the work function layer 212 is an N-type work function layer, and the material of the N-type work function layer includes one or more of TiAl, Mo, MoN, AlN, and TiAlC.

[0062] The gate electrode layer 216 is used to bring out the electrical properties of the gate structure 240. In this embodiment, the material of the gate electrode layer 216 is Al, Cu, Ag, Au, Pt, Ni, Ti, or W.

[0063] It should be noted that the gate structure 240 also spans the fin 201 of the third device region 200A and covers part of the top and part of the sidewall of the fin 201.

[0064] It should also be noted that the metal gate structure is usually a stacked structure, including at least a high-k gate dielectric layer 213, a work function layer 212, and a gate electrode layer 216. Depending on the requirements of the device's electrical performance, the number of work function layers 212 may also be multiple. This places high demands on the filling capability of the gate structure 240 between the gate oxide layers. Therefore, in this embodiment, by making the top of the isolation layer 203 of the second device region 200C higher than the top of the isolation layer 203 of the first device region 200B, the height of the fins 201 exposed in the isolation layer 203 in the second device region 200C is reduced, thereby reducing the aspect ratio between the first gate oxide layers 204 in the second device region 200C. As a result, the filling performance of the gate structure 240 in the second device region 200C is significantly improved.

[0065] In this embodiment, the semiconductor structure further includes an interlayer dielectric layer 210 located on the substrate 200 exposed by the gate structure 240, and the interlayer dielectric layer 210 covers the sidewall of the gate structure 240.

[0066] The interlayer dielectric layer 210 is used to isolate adjacent devices. The material of the interlayer dielectric layer 210 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In this embodiment, the material of the interlayer dielectric layer 210 is silicon oxide.

[0067] In this embodiment, the semiconductor structure further includes a sidewall 209 located on the sidewall of the gate structure 240. The sidewall 209 can be a single-layer structure or a multilayer structure, and the material of the sidewall 209 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the sidewall 209 is a single-layer structure, and the material of the sidewall 209 is silicon nitride.

[0068] Accordingly, the present invention also provides a method for forming a semiconductor structure, with reference to... Figures 5 to 16 This is a schematic diagram of the structure corresponding to each step in one embodiment of the semiconductor structure formation method of the present invention.

[0069] refer to Figure 5A substrate is provided, including a substrate 100 and a plurality of discrete fins 101 located on the substrate 100. In a direction perpendicular to the extension direction of the fins 101, the substrate includes a first device region 100B and a second device region 100C, the device operating voltage of the second device region 100C is greater than the device operating voltage of the first device region 100B, and the fins 101 of the first device region 100B and the second device region 100C have the same height.

[0070] The substrate is used to provide a process platform for subsequent process manufacturing.

[0071] In this embodiment, the substrate is used to form a fin field-effect transistor (FinFET). The substrate includes a substrate 100 and fins 101 protruding from the substrate 100.

[0072] In this embodiment, the substrate 100 is a silicon substrate. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide, etc., and the substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, etc.

[0073] In this embodiment, the material of the fin 101 is the same as the material of the substrate 100, and the material of the fin 101 is silicon. In other embodiments, the material of the fin may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium ionide.

[0074] In this embodiment, the substrate includes a first device region 100B and a second device region 100C, wherein the device operating voltage of the second device region 100C is greater than the device operating voltage of the first device region 100B. Accordingly, the thickness of the gate dielectric layer formed in the second device region 100C is greater than the thickness of the gate dielectric layer formed in the first device region 100B.

[0075] Specifically, both the first device area 100B and the second device area 100C are used to form input / output (I / O) devices.

[0076] It should be noted that, in the step of providing the substrate, the substrate further includes a third device region 100A, the device operating voltage of the third device region 100A being lower than the device operating voltage of the first device region 100B.

[0077] The third device area 100A provides a process platform for subsequent process manufacturing.

[0078] The operating voltage of the third device region 100A is less than the operating voltage of the first device region 100B. Correspondingly, the thickness of the gate dielectric layer formed in the third device region 100A is less than the thickness of the gate dielectric layer formed in the first device region 100B.

[0079] Specifically, the third device region 100A is used to form a core device.

[0080] In this embodiment, the fins 101 of the first device region 100B, the second device region 100C, and the third device region 100A are all of equal height.

[0081] refer to Figure 6 A second isolation layer 103 is formed on the substrate 100 of the second device region 100C, and the second isolation layer 103 covers part of the sidewall of the fin 101.

[0082] The second isolation layer 103 provides the technological basis for the subsequent formation of the first isolation layer.

[0083] Secondly, the second isolation layer 103 is also used to isolate adjacent devices. The material of the second isolation layer 103 can be silicon oxide, silicon nitride, or silicon oxynitride. In this embodiment, the material of the second isolation layer 103 is silicon oxide.

[0084] It should be noted that in this embodiment, after the second isolation layer 103 is formed, the first isolation layer is formed on the first device region 100B. Therefore, in the step of forming the second isolation layer 103 on the substrate 100 of the second device region 100C, the second isolation layer 103 is also formed on the substrate 100 of the first device region 100B.

[0085] The second isolation layer 103 is formed on the substrate 100 of the first device region 100B, providing a process basis for the subsequent formation of the first isolation layer in the first device region 100B. Specifically, the first isolation layer can be formed by removing a portion of the thickness of the second isolation layer 103 in the first device region 100B.

[0086] In this embodiment, in the step of forming the second isolation layer 103 on the substrate 100 of the second device region 100C, the second isolation layer 103 is also formed on the substrate 100 of the third device region 100A.

[0087] The second isolation layer 103 is also formed on the substrate 100 of the third device region 100A, providing a process basis for the subsequent formation of the first isolation layer in the third device region 100A.

[0088] The height of the fin 101 exposed by the second isolation layer 103 is 40 nanometers to 50 nanometers.

[0089] It should be noted that the height of the exposed fin 101 of the second isolation layer 103 should not be too large or too small. The operating voltage of the second device region 100C is relatively high; therefore, the gate oxide layer thickness of the second device region 100C is relatively large. If the height of the exposed fin 101 of the second isolation layer 103 is too large, it will easily lead to a large depth-to-width ratio between the first gate oxide layers of the second device region 100C during the subsequent formation of the gate structure, increasing the difficulty of filling the gate structure and thus affecting the performance of the semiconductor device. If the height of the exposed fin 101 of the second isolation layer 103 is too small, it will easily lead to insufficient space for the subsequent formation of the gate structure, thereby reducing the gate structure's control over the channel. Moreover, if the height of the fin 101 covered by the gate structure is also too small, the carrier flux in the exposed fin 101 of the second isolation layer 103 will be too small, thus affecting the performance of the semiconductor device. Therefore, in this embodiment, the height of the exposed fin 101 of the second isolation layer 103 is 40 nanometers to 50 nanometers.

[0090] refer to Figure 7 In the second device region 100C, a first gate oxide layer 104 is formed to conformally cover the fin 101 exposed to the second isolation layer 103.

[0091] Generally, the higher the operating voltage of a semiconductor device, the thicker the gate oxide layer exposed on the fins of the isolation layer. In this embodiment, the device operating voltage of the second device region 100C is greater than that of the first device region 100B. Therefore, a first gate oxide layer 104 is formed in the second device region 100C to provide a process basis for the second device region 100C to require a higher device operating voltage.

[0092] In this embodiment, the first gate oxide layer 104 is formed using a deposition process.

[0093] By employing a deposition process, the formation of the first gate oxide layer 104 is reduced, thereby reducing the consumption of the fins 101 in the first device region 100B and the third device region 100A, and thus reducing the impact on the linewidth dimensions of the fins 101 in the first device region 100B and the third device region 100A.

[0094] Specifically, the first gate oxide layer 104 is formed using atomic layer deposition (ALD). ALD involves multiple ALD cycles, which improves the thickness uniformity of the first gate oxide layer 104, enabling it to conformally cover the top and sidewalls of the fin 101 and the top of the second isolation layer 103. Furthermore, ALD offers good gap-filling performance and step coverage, correspondingly improving the conformal coverage capability of the first gate oxide layer 104. In other embodiments, the first gate oxide layer can also be formed using chemical vapor deposition (CVD).

[0095] In this embodiment, the thickness of the first gate oxide layer 104 is 8 nanometers to 15 nanometers.

[0096] It should be noted that the subsequent process also includes: forming a second gate oxide layer conformally covering the fins exposed on the first isolation layer in the first device region 100B, and then forming a third gate oxide layer conformally covering the first gate oxide layer 104 and the second gate oxide layer. In the first device region 100B, the second gate oxide layer and the third gate oxide layer constitute the gate oxide layer of the first device region 100B. In the second device region 100C, the first gate oxide layer 104 and the third gate oxide layer constitute the gate oxide layer of the second device region 100C. Therefore, the thickness of the first gate oxide layer 104 should not be too large or too small. If the thickness of the first gate oxide layer 104 is too large, given a fixed thickness of the gate dielectric layer in the second device region 100C, the thickness of the third gate oxide layer in the second device region 100C will easily become too small, consequently resulting in an insufficient thickness of the third gate oxide layer in the first device region 100B. This will affect the device operating voltage of the first device region 100B, failing to meet process requirements and thus impacting the electrical performance of the semiconductor. Conversely, if the thickness of the first gate oxide layer 104 is too small, given a fixed thickness of the gate dielectric layer in the second device region 100C, the thickness of the third gate oxide layer in the second device region 100C will easily become too large, consequently resulting in an excessive thickness of the third gate oxide layer in the first device region 100B. This will also affect the device operating voltage of the first device region 100B, failing to meet process requirements and thus impacting the electrical performance of the semiconductor. Therefore, in this embodiment, the thickness of the first gate oxide layer 104 is 8 nanometers to 15 nanometers.

[0097] In this embodiment, during the step of forming the first gate oxide layer 104, the first gate oxide layer 104 conformally covers the fin portion 101 and the second isolation layer 103.

[0098] In this case, the first gate oxide layer 104 of the first device region 100B and the third device region 100A can be removed to avoid affecting the operating voltage of the devices formed in the first device region 100B and the third device region 100A.

[0099] refer to Figure 8 After forming the first gate oxide layer 104 and before removing a portion of the thickness of the second isolation layer 103 in the first device region 100B, the method further includes: forming a mask layer 105 in the second device region 100C covering the first gate oxide layer 104; using the mask layer 105 as a mask, removing the first gate oxide layer 104 in the first device region 100B to expose the fin 101 and the second isolation layer 103.

[0100] The mask layer 105 also provides a masking function during the subsequent removal of a portion of the thickness of the second isolation layer 103 in the first device region 100B.

[0101] In this embodiment, the material of the mask layer 105 is one or more of titanium nitride (TiN), tantalum nitride (TaN), titanium oxide (TiOx), tantalum oxide, and tungsten-carbon composite material.

[0102] In this embodiment, a dry etching process is used to remove the first gate oxide layer 104 in the first device region 100B.

[0103] refer to Figure 9 A first isolation layer 130 is formed on the substrate 100 of the first device region 100B. The first isolation layer 130 covers part of the sidewall of the fin 101, and the top surface of the second isolation layer 103 is higher than the top surface of the first isolation layer 130.

[0104] When the device is operating, since the operating voltage of the second device region 100C is greater than that of the first device region 100B, the thickness of the first gate oxide layer 104 is greater than that of the second gate oxide layer. In this embodiment, by making the top of the second isolation layer 103 of the second device region 100C higher than the top of the first isolation layer 130 of the first device region 100B, the height of the fins 101 exposed in the second isolation layer 103 in the second device region 100C is reduced, thereby reducing the aspect ratio between the first gate oxide layers 104 in the second device region 100C. Therefore, even though the thickness of the first gate oxide layer 104 is greater than that of the second gate oxide layer, the filling performance of the gate structure in the second device region 100C is improved during the subsequent formation of the gate structure, thereby improving the performance of the semiconductor.

[0105] In this embodiment, the top of the second isolation layer 103 of the second device region 100C is 5 nanometers to 20 nanometers above the top of the first isolation layer 130 of the first device region 100B.

[0106] It should be noted that the difference in height between the top of the second isolation layer 103 in the second device region 100C and the top of the first isolation layer 130 in the first device region 100B should not be too large or too small. If the difference in height between the top of the second isolation layer 103 in the second device region 100C and the top of the first isolation layer 130 in the first device region 100B is too large, then even if the height of the exposed fin 101 of the second isolation layer 103 in the second device region 100C meets the process requirements, it may lead to an excessively large height of the exposed fin 101 of the isolation layer 103 in the first device region 100B. This would increase the aspect ratio between the first gate oxide layers 104 in the first device region 100B, affecting the filling effect of the subsequently formed gate structure and thus affecting the performance of the semiconductor structure. Conversely, if the difference in height between the top of the second isolation layer 103 in the second device region 100C and the top of the first isolation layer 130 in the first device region 100B is too small, then the aspect ratio between the first gate oxide layers 104 in the second device region 100C would still be large, thus affecting the filling effect of the subsequent gate structure and thus affecting the performance of the semiconductor structure. Therefore, in this embodiment, the top of the second isolation layer 103 of the second device region 100C is 5 nanometers to 20 nanometers above the top of the first isolation layer 130 of the first device region 100B.

[0107] In this embodiment, the step of forming a first isolation layer 130 on the substrate 100 of the first device region 100B includes: removing a portion of the thickness of the second isolation layer 103 in the first device region 100B, with the remaining second isolation layer 103 serving as the first isolation layer 130.

[0108] Specifically, a portion of the thickness of the second isolation layer 103 in the first device region 100B is removed to form the first isolation layer 130, thereby increasing the height of the fin 101 exposed in the first isolation layer 130 in the first device region 100B, increasing the carrier flux in the first device region 100B, and improving the structural performance of the semiconductor.

[0109] It should be noted that after the first gate oxide layer 104 is formed, a portion of the thickness of the second isolation layer 103 in the first device region 100B is removed to form the first isolation layer 130.

[0110] In this embodiment, in the step of removing a portion of the thickness of the second isolation layer 103 in the first device region 100B, the formed mask layer 105 is used as a mask.

[0111] In this embodiment, a dry etching process is used to remove a portion of the thickness of the second isolation layer 103 in the first device region 100B.

[0112] The dry etching process is an anisotropic dry etching process. Anisotropic dry etching has the characteristics of anisotropic etching, and its longitudinal etching rate is much greater than its transverse etching rate. It can obtain a fairly accurate pattern transformation, so while etching away part of the thickness of the second isolation layer 103, it is beneficial to accurately control the morphology of the second isolation layer 103 and the first isolation layer 130.

[0113] It should be noted that in this embodiment, the mask layer 105 is used as a mask in both the steps of forming the first isolation layer 130 and removing the first gate oxide layer 104 in the second device region 100C, so that a single photomask and a single photolithography process can be shared, simplifying the process steps and reducing the process cost.

[0114] In this embodiment, after removing a portion of the thickness of the second isolation layer 103 in the first device region 100B and before forming the second gate oxide layer, the method further includes removing the mask layer 105.

[0115] Specifically, removing the mask layer 105 provides space for the subsequent formation of a gate structure on the substrate 100.

[0116] It should also be noted that, in the step of forming the first isolation layer on the substrate 100 of the first device region 100B, the first isolation layer is also formed on the substrate of the third device region 100A. Therefore, in the step of removing a portion of the thickness of the second isolation layer 103 in the first device region 100B, a portion of the thickness of the second isolation layer 103 in the third device region 100A is also removed.

[0117] refer to Figure 10 In the first device region 100B, a second gate oxide layer 106 is formed to conformally cover the fin 101 exposed in the first isolation layer 130, the thickness of the second gate oxide layer 106 being less than the thickness of the first gate oxide layer 104.

[0118] The second gate oxide layer 106 provides the process basis for the device operating voltage required by the first device region 100B.

[0119] It should be noted that the device operating voltage of the first device region 100B is lower than the device operating voltage of the second device region 100C. Therefore, the thickness of the gate oxide layer in the first device region 100B is less than the thickness of the gate oxide layer in the second device region 100C. Accordingly, in this embodiment, the thickness of the second gate oxide layer 106 in the first device region 100B is less than the thickness of the first gate oxide layer 104 in the second device region 100C.

[0120] In this embodiment, the second gate oxide layer 106 is formed using an oxidation process.

[0121] Specifically, the second gate oxide layer 106 formed by the oxidation process has good density. Moreover, since the oxidation process only oxidizes the exposed fins 101, and the first gate oxide layer 104 in the second device region 100C covers the fins 101, the second gate oxide layer 106 is selectively formed on the surface of the fins 101 in the first device region 100B without covering the first gate oxide layer 104. Therefore, there is no need to remove the second gate oxide layer 106 in the second device region 100C in the future.

[0122] In this embodiment, the thickness of the second gate oxide layer 106 is 20 nanometers to 35 nanometers.

[0123] It should be noted that subsequent processes also include: forming a third gate oxide layer conformally covering the first gate oxide layer 104 and the second gate oxide layer 106. In the first device region 100B, the second gate oxide layer 106 and the third gate oxide layer constitute the gate oxide layer of the first device region 100B. In the second device region 100C, the first gate oxide layer 104 and the third gate oxide layer constitute the gate oxide layer of the second device region 100C. Therefore, the thickness of the second gate oxide layer 106 should not be too large or too small. If the thickness of the second gate oxide layer 106 is too large, given a fixed thickness of the gate dielectric layer in the first device region 100B, the thickness of the third gate oxide layer in the first device region 100B will easily become too small, consequently resulting in an insufficient thickness of the third gate oxide layer in the second device region 100C. This will affect the device operating voltage of the second device region 100C, failing to meet process requirements and thus impacting the electrical performance of the semiconductor. Conversely, if the thickness of the second gate oxide layer 106 is too small, given a fixed thickness of the gate dielectric layer in the first device region 100B, the thickness of the third gate oxide layer in the first device region 100B will easily become too large, consequently resulting in an excessive thickness of the third gate oxide layer in the second device region 100C. This will also affect the device operating voltage of the second device region 100C, failing to meet process requirements and thus impacting the electrical performance of the semiconductor. Therefore, in this embodiment, the thickness of the second gate oxide layer 106 is 20 nanometers to 35 nanometers.

[0124] In this embodiment, during the step of forming the second gate oxide layer 106, the second gate oxide layer 106 also conformally covers the third device region 100A exposed to the fin 101 of the first isolation layer 130.

[0125] refer to Figures 11 to 16 In the first device region 100B and the second device region 100C, a gate structure 140 is formed that spans the fin 101 and covers the first gate oxide layer 104 and the second gate oxide layer 106. Figure 16 (As shown).

[0126] In this embodiment, the gate structure 140 includes a metal gate structure. As the critical dimensions of devices continue to shrink, the use of a metal gate structure helps to improve the short-channel effect.

[0127] The gate structure 140 is used to control the opening or closing of the conductive channel when the device is in operation.

[0128] In this embodiment, the step of forming the gate structure 140 includes: as follows Figure 13 As shown, a gate opening 111 is formed on the substrate 100, spanning the fin 101; as Figure 15As shown, a high-k gate dielectric layer 113 conformally covers the fin 101, and a work function layer 112 conformally covers the high-k gate dielectric layer 113, both formed in the gate opening 111; Figure 16 As shown, a gate electrode layer 116 is formed to conformally cover the work function layer 112.

[0129] The high-k gate dielectric layer 113 is made of a high-k dielectric material, which refers to a dielectric material with a relative permittivity greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer 113 can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc.

[0130] In this embodiment, in the first device region 100B, the second gate oxide layer 106, the third gate oxide layer 107, and the high-k gate dielectric layer 113 constitute the gate dielectric layer of the first device region 100B; in the second device region 100C, the first gate oxide layer 104, the third gate oxide layer 107, and the high-k gate dielectric layer 113 constitute the gate dielectric layer of the second device region 100C; and in the third device region 100A, the high-k gate dielectric layer 113 constitutes the gate dielectric layer of the third device region 100A.

[0131] As the device operating voltages of the second device region 100C, the first device region 100B, and the third device region 100A decrease sequentially, the gate dielectric layer thicknesses of the second device region 100C, the first device region 100B, and the third device region 100A decrease sequentially.

[0132] The work function layer 112 is used to adjust the threshold voltage of the formed transistor. When forming a PMOS transistor, the work function layer 112 is a P-type work function layer, and the material of the P-type work function layer includes one or more of TiN, TaN, TaSiN, TaAlN, and TiAlN; when forming an NMOS transistor, the work function layer 112 is an N-type work function layer, and the material of the N-type work function layer includes one or more of TiAl, Mo, MoN, AlN, and TiAlC.

[0133] The gate electrode layer 116 is used to bring out the electrical properties of the device gate structure 140. In this embodiment, the material of the gate electrode layer 116 is Al, Cu, Ag, Au, Pt, Ni, Ti, or W.

[0134] In this embodiment, during the step of forming the gate structure 140, the gate structure 140 also spans the fin 101 of the third device region 100A.

[0135] refer to Figure 14Before forming the gate structure 140, the method further includes: removing the second gate oxide layer 106 in the third device region 100A to expose the fin 101.

[0136] Specifically, the device operating voltage of the third device region 100A is relatively low, and the second gate oxide layer 106 does not need to be formed in the third device region 100A. Therefore, before forming the gate structure 140, the second gate oxide layer 106 in the third device region 100A is removed to expose the fin 101.

[0137] In this embodiment, a dry etching process is used to remove the second gate oxide layer 106 in the third device region 100A.

[0138] The dry etching process is an anisotropic dry etching process. Anisotropic dry etching has the characteristics of anisotropic etching, and its longitudinal etching rate is much greater than its lateral etching rate, which can obtain a fairly accurate pattern transformation. Therefore, while etching away the second gate oxide layer 106, it is also beneficial to accurately control the morphology of the second gate oxide layer 106 in the first device region 100B.

[0139] refer to Figure 12 After the first gate oxide layer 104 and the second gate oxide layer 106 are formed, and before the second gate oxide layer 106 in the third device region 100A is removed, the method further includes: forming a pseudo gate structure 108 that spans the fin 101 and covers the first gate oxide layer 104 and the second gate oxide layer 106.

[0140] The pseudo-gate structure 108 occupies the space required to form the gate structure 140.

[0141] In this embodiment, the gate structure 140 is formed by forming a high-k last metalgatelast after forming a high-k last gate dielectric layer.

[0142] In this embodiment, the dummy gate structure 108 is made of amorphous silicon. In other embodiments, the dummy gate structure is made of polycrystalline silicon. In other embodiments, the dummy gate structure may also be made of silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, silicon carbonitride, or amorphous carbon.

[0143] In this embodiment, the method further includes forming an interlayer dielectric layer 110 on the substrate 100 exposed by the dummy gate structure 108, wherein the interlayer dielectric layer 110 covers the sidewall of the dummy gate structure 108.

[0144] The interlayer dielectric layer 110 is used to isolate adjacent devices. The material of the interlayer dielectric layer 110 is an insulating material, such as one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. In this embodiment, the material of the interlayer dielectric layer 110 is silicon oxide.

[0145] In this embodiment, after forming the pseudo-gate structure 108 and before forming the interlayer dielectric layer 110, the method further includes: forming a sidewall 109 on the sidewall of the pseudo-gate structure 108.

[0146] The sidewall 109 is used to protect the sidewalls of the gate structure 140. The sidewall 109 can be a single-layer structure or a multilayer structure, and the material of the sidewall 109 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbonitride, silicon carbonitride, silicon oxynitride, silicon oxynitride, boron nitride, and boron carbonitride. In this embodiment, the sidewall 109 is a single-layer structure, and the material of the sidewall 109 is silicon nitride.

[0147] refer to Figure 13 Remove the pseudo-gate structure 108 and form a gate opening 111 in the interlayer dielectric layer 110.

[0148] The gate opening 111 provides a spatial location for forming the gate structure 140.

[0149] In this embodiment, one or both of dry etching and wet etching processes are used to remove the pseudo gate structure 108.

[0150] refer to Figure 14 After removing the pseudo-gate structure 108 and before forming the gate structure 140, the second gate oxide layer 106 in the third device region 100A is removed.

[0151] Specifically, the device operating voltage of the third device region 100A is relatively small, and the second gate oxide layer 106 does not need to be formed in the third device region 100A. Therefore, after removing the pseudo gate structure 108 and before forming the gate structure 140, the process further includes: first removing the second gate oxide layer 106 in the third device region 100A to expose the fin 101.

[0152] It should be noted that after removing the second gate oxide layer 106 in the third device region 100A, the gate structure 140 is formed at the location of the dummy gate structure 108 (i.e., in the gate opening 111).

[0153] refer to Figure 11After forming the second gate oxide layer 106 and before forming the gate structure 140, the method further includes: forming a third gate oxide layer 107 that conformally covers the first gate oxide layer 104 and the second gate oxide layer 106.

[0154] The third gate oxide layer 107 provides the process basis for the device operating voltage required by the device region.

[0155] In this embodiment, the third gate oxide layer 107 is formed using an atomic layer deposition process.

[0156] It should be noted that the second gate oxide layer 106 is formed by a thermal oxidation process. In order to ensure that the device operating voltage of the first device region 100B meets the process requirements, the third gate oxide layer 107 needs to be formed on the first device region 100B.

[0157] Therefore, in this embodiment, before forming the gate structure 140, the method further includes removing the third gate oxide layer 107 in the third device region 100A.

[0158] Specifically, after removing the dummy gate structure 108 and before forming the gate structure 140, the third gate oxide layer 107 in the third device region 100A is removed.

[0159] It should be noted that in this embodiment, after the second isolation layer 103 is formed, the first gate oxide layer 104 is formed, followed by the formation of the first isolation layer 130. In this embodiment, on the one hand, the process of forming the second isolation layer 103 and the first isolation layer 130 is simplified, and on the other hand, the second isolation layer 103 is an integral structure, which helps to ensure the performance of the second isolation layer 103.

[0160] In other embodiments, depending on process requirements, a second isolation layer 103 may be formed after the first isolation layer 130 is formed, followed by the formation of a first gate oxide layer 104 and a second gate oxide layer 106.

[0161] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that, include: The substrate includes a substrate and fins protruding from the substrate. In a direction perpendicular to the extension direction of the fins, the substrate includes a first device region and a second device region, wherein the device operating voltage of the second device region is greater than the device operating voltage of the first device region, and the fins of the first device region and the second device region have equal heights. An isolation layer is located on the substrate exposed by the fin, the isolation layer covers a portion of the sidewall of the fin, and the top of the isolation layer in the second device region is higher than the top of the isolation layer in the first device region; A first gate oxide layer is located in the second device region and conformally covers the fins exposed in the isolation layer; the first gate oxide layer also conformally covers the top of the isolation layer in the second device region. A second gate oxide layer is located in the first device region and conformally covers the fin exposed in the isolation layer, and the thickness of the second gate oxide layer is less than the thickness of the first gate oxide layer. A third gate oxide layer is located between the gate structure and the first gate oxide layer, and between the gate structure and the second gate oxide layer, wherein the third gate oxide layer conformally covers the top of the isolation layer; in the first device region, the second gate oxide layer and the third gate oxide layer constitute the gate oxide layer of the first device region; in the second device region, the third gate oxide layer and the first gate oxide layer constitute the gate oxide layer of the second device region. A gate structure that spans the fins of the first and second device regions and covers the first and second gate oxide layers.

2. The semiconductor structure as described in claim 1, characterized in that, The gate structure includes a metal gate structure.

3. The semiconductor structure as described in claim 1, characterized in that, The thickness of the first gate oxide layer is 8 nanometers to 15 nanometers, and the thickness of the second gate oxide layer is 20 nanometers to 35 nanometers.

4. The semiconductor structure as described in claim 1, characterized in that, The height of the fin exposed by the isolation layer in the second device region is 40 nanometers to 50 nanometers.

5. The semiconductor structure as described in claim 1, characterized in that, The top of the isolation layer in the second device region is 5 nanometers to 20 nanometers higher than the top of the isolation layer in the first device region.

6. The semiconductor structure as described in claim 1, characterized in that, The substrate further includes a third device region, wherein the device operating voltage of the third device region is lower than the device operating voltage of the first device region; The top of the isolation layer of the third device region is flush with the top of the isolation layer of the first device region; The gate structure also spans the fin of the third device region and covers part of the top and part of the sidewalls of the fin.

7. A method for forming a semiconductor structure, characterized in that, include: A substrate is provided, including a substrate and a plurality of discrete fins located on the substrate. In a direction perpendicular to the extension direction of the fins, the substrate includes a first device region and a second device region, wherein the device operating voltage of the second device region is greater than the device operating voltage of the first device region, and the fins of the first device region and the second device region have equal heights. A first isolation layer is formed on the substrate of the first device region, and the first isolation layer covers a portion of the sidewall of the fin; A second isolation layer is formed on the substrate of the second device region, the second isolation layer covers part of the sidewall of the fin, and the top surface of the second isolation layer is higher than the top surface of the first isolation layer; In the second device region, a first gate oxide layer is formed to conformally cover the fins exposed to the second isolation layer; In the first device region, a second gate oxide layer is formed to conformally cover the fins exposed in the first isolation layer, and the thickness of the second gate oxide layer is less than the thickness of the first gate oxide layer; A third gate oxide layer is formed to conformally cover the first gate oxide layer and the second gate oxide layer; in the first device region, the second gate oxide layer and the third gate oxide layer constitute the gate oxide layer of the first device region; in the second device region, the third gate oxide layer and the first gate oxide layer constitute the gate oxide layer of the second device region. In the first device region and the second device region, a gate structure is formed that spans the fin and covers the first gate oxide layer and the second gate oxide layer.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, After the second isolation layer is formed, the first isolation layer is formed; In the step of forming a second isolation layer on the substrate of the second device region, the second isolation layer is also formed on the substrate of the first device region; The step of forming a first isolation layer on the substrate of the first device region includes: removing a portion of the thickness of the second isolation layer in the first device region, leaving the remaining second isolation layer as the first isolation layer.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, After the first gate oxide layer is formed, a portion of the second isolation layer in the first device region is removed to form the first isolation layer.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, In the step of forming the first gate oxide layer, the first gate oxide layer conformally covers the fin and the second isolation layer; After forming the first gate oxide layer and before removing a portion of the second isolation layer in the first device region, the method further includes: forming a mask layer covering the first gate oxide layer in the second device region; using the mask layer as a mask, removing the first gate oxide layer in the first device region to expose the fin and the second isolation layer; In the step of removing a portion of the thickness of the second isolation layer in the first device region, the mask layer is used as a mask; Before forming the second gate oxide layer after removing a portion of the second isolation layer in the first device region, the method further includes removing the mask layer.

11. The method for forming a semiconductor structure as described in claim 8, characterized in that, A dry etching process is used to remove a portion of the second isolation layer in the first device region.

12. The method for forming a semiconductor structure as described in claim 7, characterized in that, The gate structure includes a metal gate structure.

13. The method for forming a semiconductor structure as described in claim 7 or 9, characterized in that, The first gate oxide layer is formed using atomic layer deposition (ALD) and the second gate oxide layer is formed using an oxidation process.

14. The method for forming a semiconductor structure as described in claim 7, characterized in that, In the step of providing the substrate, the substrate further includes a third device region, wherein the device operating voltage of the third device region is lower than the device operating voltage of the first device region; In the step of forming a first isolation layer on the substrate of the first device region, the first isolation layer is also formed on the substrate of the third device region; In the step of forming the second gate oxide layer, the second gate oxide layer also conformally covers the fins exposed in the first isolation layer in the third device region; Before forming the gate structure, the method further includes: removing the second gate oxide layer in the third device region to expose the fin; In the step of forming the gate structure, the gate structure also spans the fin of the third device region.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, After forming the first gate oxide layer and the second gate oxide layer, and before removing the second gate oxide layer in the third device region, the method further includes: forming a pseudo-gate structure that spans the fin and covers the first gate oxide layer and the second gate oxide layer; After removing the dummy gate structure and before forming the gate structure, the second gate oxide layer in the third device region is removed; After removing the second gate oxide layer in the third device region, the gate structure is formed at the location of the dummy gate structure.

16. The method for forming a semiconductor structure as described in claim 7, characterized in that, The thickness of the first gate oxide layer is 8 nanometers to 15 nanometers, and the thickness of the second gate oxide layer is 20 nanometers to 35 nanometers.

17. The method for forming a semiconductor structure as claimed in claim 7, wherein the height of the exposed fin of the second isolation layer is 40 nanometers to 50 nanometers.

18. The method for forming a semiconductor structure as described in claim 7, characterized in that, The top of the second isolation layer of the second device region is 5 nanometers to 20 nanometers higher than the top of the first isolation layer of the first device region.

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