3D Memory Chip

Abstract

Embodiments of the present application provide a 3D storage chip, which solves the problems of large parasitic resistance and capacitance of existing storage chips, high manufacturing cost, large RC delay, high power consumption, and poor heat dissipation caused by the use of through-silicon via technology. The above 3D storage chip includes a storage part and a control part stacked on each other, and the storage part and the control part are connected by a hybrid bonding method. Among them, the hybrid bonding method is to connect the connection pads of the storage part and the connection pads of the control part through a metal conductor. The storage part is provided with a storage array, and the functional circuits of the storage chip are arranged in the control part.

Description

Technical Field

[0001] The embodiments of the present invention relate to the technical field of memories, and more particularly, to a 3D memory chip. Background Art

[0002] Currently, memory chips, especially DRAM memory chips, are mainly divided into planar DRAMs and three-dimensional stacked DRAMs formed using 3DS (3-Dimensional Stack) technology.

[0003] For planar DRAMs, reference can be made to Figure 1 the example of a planar DRAM shown. The memory array part (Bank1 - Bank4) and the control circuit are on one chip. The memory array part usually contains memory cells, and the control circuit usually includes functional circuits such as decoding circuits, data writing circuits, and data reading circuits.

[0004] Due to manufacturing process limitations, especially those of the storage capacitor, planar DRAMs have large parasitic resistance capacitances in the memory chips, which affect the processing performance of the functional circuits in the memory chips. Therefore, they have the defects of slow speed, high power consumption, and poor ability to process data in parallel.

[0005] In three-dimensional stacked DRAMs, a relatively common method is to connect the various memory parts based on TSV (Through-Silicon-Via) technology. The various memory layers can be stacked through TSV technology, and there will be intervals such as metal layers between the layers. The most typical examples are HBM (High Bandwidth Memory) and HMC (Hybrid Memory Cube). However, both HBM and HMC use silicon interposers, so the cost is very high, and there are also problems of large RC delay, high power consumption, and poor heat dissipation. Summary of the Invention

[0006] A series of simplified concepts are introduced in the Summary of the Invention section, which will be further elaborated in detail in the Detailed Description section. The Summary of the Invention section of the embodiments of the present application does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the protection scope of the claimed technical solution.

[0007] The embodiments of the present application provide a 3D memory chip, which solves the problems of large parasitic resistance capacitance in existing memory chips, high manufacturing cost, large RC delay, high power consumption, and poor heat dissipation caused by using through-silicon-via technology.

[0008] To at least partially solve the above problems, in a first aspect, embodiments of the present application provide a 3D storage chip, which may include:

[0009] A storage part and a control part stacked on each other, the storage part and the control part are connected by a hybrid bonding method, wherein the hybrid bonding method is to connect the connection pads of the storage part and the connection pads of the control part through a metal conductor, the control part includes a control part chip, the storage part includes a storage part chip, and the control part chip and / or the storage part chip includes a metal layer via component provided in a chip metal layer, wherein the holes in the metal layer via component are non-through holes;

[0010] The metal layer via component includes a first conductor, a second conductor close to the substrate layer, and a conductor connection hole. A conductor connection hole is provided between the first conductor and the second conductor, and the second conductor is connected to the first conductor through the conductor connection hole so that signals can be transmitted to the first conductor through the substrate layer;

[0011] The storage part is provided with a storage array and a sense amplifier, and the functional circuits of the storage chip are provided in the control part;

[0012] The functional circuit includes a SRAM repair unit circuit, and the SRAM repair unit circuit is used to replace the failed storage cells in the storage array to repair the storage array.

[0013] In a second possible implementation manner of the first aspect, the storage part is further provided with a sense amplifier;

[0014] Other functional circuits of the storage chip are provided in the control part.

[0015] In a third possible implementation manner of the first aspect, the storage part is further provided with a row-column decoding circuit;

[0016] Other functional circuits of the storage chip are provided in the control part.

[0017] In a fourth possible implementation manner of the first aspect, the storage part is further provided with a storage part power supply circuit;

[0018] Other functional circuits of the storage chip are provided in the control part.

[0019] In a fifth possible implementation manner of the first aspect, the functional circuit includes an arithmetic function module.

[0020] In a sixth possible implementation manner of the first aspect, the arithmetic function module is a CPU or a GPU.

[0021] In the seventh possible implementation of the first aspect, the control part includes a control part chip, the storage part includes a storage part chip, the control part chip and / or the storage part chip includes a metal layer via component disposed in a chip metal layer, and the connection pad is disposed on a first conductor member in the metal layer via component that is away from the substrate layer.

[0022] In the eighth possible implementation of the first aspect, the first conductor member is the connection pad.

[0023] In the ninth possible implementation of the first aspect, the metal layer via component further includes a second conductor member close to the substrate layer;

[0024] The substrate layer includes a substrate via hole that communicates with the second conductor member, and the connection pad is disposed on the second conductor member.

[0025] In the tenth possible implementation of the first aspect, a conductor connection hole is provided between the first conductor member and the second conductor member, and the second conductor member is connected to the first conductor member through the conductor connection hole so that a signal can be transmitted through the substrate layer to the first conductor member.

[0026] In the eleventh possible implementation of the first aspect, the second conductor member is the connection pad.

[0027] In the twelfth possible implementation of the first aspect, the substrate via hole is filled with a filling conductor layer, the connection pad is disposed on a side of the filling conductor layer away from the metal layer, and the connection pad is connected to the second conductor member through the filling conductor layer.

[0028] In the thirteenth possible implementation of the first aspect, the shape of the connection pad matches the shape of the first conductor member and / or the second conductor member.

[0029] In the fourteenth possible implementation of the first aspect, the shape of the connection pad is circular or polygonal.

[0030] In the fifteenth possible implementation of the first aspect, the connection pad is also used for bonding of the storage chip package leads.

[0031] In the sixteenth possible implementation of the first aspect, the storage part includes two or more than three storage part chips; and / or,

[0032] The control part includes two or more than three control part chips.

[0033] In the seventeenth possible implementation of the first aspect, the hybrid bonding method is to connect the connection pads of the storage part chip and the connection pads of the control part chip through a metal conductor.

[0034] In the eighteenth possible implementation of the first aspect, the storage part chips are connected to each other through the hybrid bonding method; and / or,

[0035] The control part chips are connected to each other through the hybrid bonding method.

[0036] In the nineteenth possible implementation of the first aspect, the storage part includes two or more storage part chips with storage arrays of the same capacity; and / or,

[0037] The storage part includes two or more storage part chips with storage arrays of different capacities.

[0038] In the twentieth possible implementation of the first aspect, the two or more storage part chips are arranged on the same plane, and each storage part chip is independent of each other.

[0039] In the twenty-first possible implementation of the first aspect, the stacking directions of two or more of the storage part chips are the same.

[0040] In the twenty-second possible implementation of the first aspect, at least one volatile storage chip and one non-volatile storage chip are included in two or more of the storage part chips.

[0041] In the twenty-third possible implementation of the first aspect, the volatile storage chip is a DRAM chip, and the non-volatile storage chip is a NAND flash chip.

[0042] In the twenty-fourth possible implementation of the first aspect, two or more of the storage part chips are stacked, and the adjacent storage part chips and the control part chips are connected through the hybrid bonding method.

[0043] In the twenty-fifth possible implementation of the first aspect, two or more of the control part chips are stacked, and the adjacent storage part chips and the control part chips are connected through the hybrid bonding method.

[0044] In the twenty-sixth possible implementation of the first aspect, at least one of the control part chips is stacked between two or more of the storage part chips at intervals, and the number of storage part chips on both sides of the control part chip is the same.

[0045] In the twenty-seventh possible implementation manner of the first aspect, two or more of the storage part chips are stacked without intervals.

[0046] In the twenty-eighth possible implementation manner of the first aspect, two or more of the control part chips include at least one analog function circuit chip and at least one digital function circuit chip, wherein the analog function circuit chip is only provided with an analog function circuit, and the digital function circuit chip is only provided with a digital function circuit.

[0047] In the twenty-ninth possible implementation manner of the first aspect, among the two or more of the storage part chips, there are two adjacent storage part chips with the same orientation.

[0048] In the thirtieth possible implementation manner of the first aspect, among the two or more of the control part chips, there are two adjacent control part chips with the same orientation.

[0049] In the thirty-first possible implementation manner of the first aspect, among the two or more of the storage part chips, there are two adjacent storage part chips arranged facing each other.

[0050] In the thirty-second possible implementation manner of the first aspect, among the two or more of the control part chips, there are two adjacent control part chips arranged facing each other.

[0051] In the thirty-third possible implementation manner of the first aspect, the adjacent storage part chip and the control part chip are connected by a hybrid bonding method.

[0052] Compared with the prior art, the 3D storage chip provided in the embodiment of the present invention has at least the following beneficial effects:

[0053] The 3D storage chip provided by the embodiment of the present invention includes a storage part and a control part that are stacked on top of each other, and the storage part and the control part are connected by a hybrid bonding method. Among them, the hybrid bonding method is to connect the connection pads of the storage part and the connection pads of the control part through a metal conductor. The storage part is provided with a storage array, and the functional circuits of the storage chip are arranged in the control part. By expanding a single storage chip into two parts, namely a storage part and a control part that are stacked on top of each other, and setting functional circuits and storage arrays with different manufacturing processes or requirements in different parts. Since there is no need for a driving interface circuit or module (PHY) between the two parts of the chip, namely the storage part chip and the control part chip that make up the same storage chip, the chip density of the stacked storage chips can be made very high, and the parasitic parameters (parasitic resistance value, parasitic capacitance value) of the hybrid bonding between the storage part chip and the control part chip that make up the storage chip are very small. Therefore, the RC delay is small, and furthermore, there is no loss in the data transmission speed, and high-bandwidth data transmission of the storage chip can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings:

[0055] Figure 1 It is a schematic structural diagram of a planar DRAM in some examples;

[0056] Figure 2 It is a schematic structural diagram of a 3D storage chip provided by the embodiment of the present invention;

[0057] Figure 3 It is a schematic structural diagram of a single chip in a 3D storage chip provided by the embodiment of the present invention;

[0058] Figure 4a It is a schematic structural diagram of another single chip in a 3D storage chip provided by the embodiment of the present invention;

[0059] Figure 4b It is a schematic structural diagram of yet another single chip in a 3D storage chip provided by the embodiment of the present invention;

[0060] Figure 5 It is a schematic structural diagram of a 3D storage chip with multiple storage parts provided by the embodiment of the present invention;

[0061] Figure 6 It is a schematic structural diagram of another 3D storage chip with multiple storage parts provided by the embodiment of the present invention;

[0062] Figure 7 Schematic structural diagram of another 3D storage chip with multiple storage parts provided by an embodiment of the present invention;

[0063] Figure 8 Schematic structural diagram of a 3D storage chip with multiple control parts provided by an embodiment of the present invention;

[0064] Figure 9 Schematic structural diagram of another 3D storage chip with multiple control parts provided by an embodiment of the present invention. Detailed implementation manners

[0065] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments, so that those skilled in the art can implement it according to the description in the specification.

[0066] It should be understood that terms such as "having", "including", and "comprising" used herein do not exclude the presence or addition of one or more other elements or their combinations.

[0067] In addition, it should be noted that unless otherwise clearly defined and limited, the terms "arranged" and "connected" should be understood in a broad sense. For example, it can be a fixed connection or a detachable connection; it can be directly connected or indirectly connected through an intermediate medium; it can be integrally connected or the communication inside two elements. It can also be that signal transmission and data communication can be carried out between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to specific situations.

[0068] Currently, in order to obtain higher bandwidth, traditional TSV structures are usually used to connect HBM chips and HMC chips of each storage part. Among them, the HBM chip stacks multiple DDR double data rate synchronous dynamic random storage part chips and a PLD (Programmable Logic Device) together and then packages them with the GPU, and realizes chip-to-chip connection by bonding through-silicon vias and micro-bumps, realizing a large-capacity and high-bit-width DDR combined array. The HMC chip stacks multiple DRAM layers on a basic logic layer, and realizes the best combination of logic and DRAM processes in a heterogeneous package. The DRAM layer only processes data, while the logic layer processes all control functions in the HMC.

[0069] However, it is very difficult to achieve a stacking structure of dozens of layers. The implementation difficulty is high, and due to immature technology, there are also problems such as high operating risk and poor stability. Moreover, both HBM and HMC use silicon interposers, so the cost is very high and the shipment volume is extremely limited. In addition, since there is a large number of DRAMs stacked and packaged together with the GPU, it will also seriously affect its heat dissipation performance.

[0070] In view of the above problems, the embodiments of the present application provide a 3D storage chip, which solves the problems of high manufacturing cost, poor circuit flexibility, high operating risk, poor stability, large RC delay, and high power consumption brought by existing planar storage chips or stacked storage chips implemented by technologies such as through-silicon via technology.

[0071] Figure 2 The following is a schematic structural diagram of a 3D storage chip provided by an embodiment of the present invention. As Figure 2 shown, the above 3D storage chip may include:

[0072] A control part 100 and a storage part 200 that are stacked on each other. The storage part 200 is connected to the control part 100 by a hybrid bonding method. Among them, the hybrid bonding method is to connect the connection pads of the storage part 200 and the connection pads of the control part 100 through a metal conductor. Exemplarily, the metal conductor is a metal conductor connection hole structure. The storage part is provided with a storage array, and the functional circuits of the storage chip are arranged in the control part.

[0073] In some examples, the control part 100 and the storage part 200 may be separate planar chips or wafers respectively. For example, it may be stacked planar chips (C2C, Chip to Chip), that is, 3D chips stacked up and down; it may also be stacked wafers (W2W, wafer to wafer), which after being cut, form 3D chips stacked up and down.

[0074] In some examples, the above hybrid bonding method may adopt that both ends of the metal conductor 300 are respectively connected to the connection pads (Connect Pad) on the storage part 200 and the control part 100.

[0075] Exemplarily, the control part may include a control part chip, the storage part may include a storage part chip, the control part chip and / or the storage part chip may include a metal layer via component arranged in the chip metal layer, the connection pad is arranged on the first conductor part far from the substrate layer in the metal layer via component, and the connection pad may also be arranged on one side far from the metal layer in the substrate via.

[0076] As Figure 3As shown, in some examples, the control section 100 and the storage section 200 can be planar chips or wafers. Therefore, when the control section 100 and the storage section 200 are separately manufactured and produced, they can include a substrate layer 20 and a metal layer 10, which can also be referred to as a device layer and a metal wiring layer. The metal layer 10 can include a first surface and a second surface that are oppositely arranged. The second surface of the above-mentioned metal layer 10 is disposed on the above-mentioned substrate layer 20. A metal layer via component can be disposed within the metal layer 10. The above-mentioned metal layer via component can include: a first conductor 11, a second conductor 12, and a conductor connection hole. The above-mentioned first conductor 11 can be formed on the first surface of the above-mentioned metal layer 10. The above-mentioned second conductor 12 can be formed on the second surface of the above-mentioned metal layer 10. For ease of explanation, the surface on the side where the substrate layer of the chip is located can be referred to as the reverse side or the back side of the chip; the surface on the side where the metal layer is located can be referred to as the front side of the chip. A connection pad can be disposed on the front or back side of the storage section 200 or the control section 100. The above-mentioned connection pad can be used for hybrid bonding between the control section 100 and the storage section 200 or for bonding of the package leads of the above-mentioned storage chip.

[0077] Exemplarily, with reference to Figure 3 , it can be understood that the connection pad disposed on the front surface of the control section chip or the storage section chip is disposed on the first conductor 11 of the above-mentioned metal layer via component.

[0078] Exemplarily, the shape of the above-mentioned connection pad can match the shape of the above-mentioned first conductor and / or the above-mentioned second conductor to satisfy sufficient contact between the connection pad and the metal conductor during hybrid bonding. Exemplarily, the shape of the above-mentioned connection pad can be rectangular or circular, or can be other polygons or other shapes, which are not limited herein.

[0079] Exemplarily, the above-mentioned connection pad can also be the above-mentioned first conductor. It can be understood that the first conductor represented by the top metal in the above-mentioned metal layer can be directly used as the above-mentioned connection pad. The above-mentioned connection pad can also be used for hybrid bonding and can further simplify the chip manufacturing process.

[0080] According to some embodiments, as Figure 4a shown, the above-mentioned substrate layer 20 can include a substrate via 21. The above-mentioned substrate via 21 communicates with the above-mentioned second conductor 12. The above-mentioned connection pad can be disposed on the above-mentioned second conductor 12.

[0081] Exemplarily, a conductor connection hole is disposed between the above-mentioned first conductor and the above-mentioned second conductor. The above-mentioned second conductor is connected to the above-mentioned first conductor through the above-mentioned conductor connection hole so that a signal can be transmitted to the above-mentioned first conductor through the above-mentioned substrate layer.

[0082] Exemplarily, the connection pads may be disposed on the back surface of the control section chip or the storage section chip. A hole is dug in the substrate layer from the back surface of the chip to form the above-mentioned substrate through-hole to the second conductor member represented by the bottommost metal of the metal layer, and then connection pads are disposed on the bottommost metal. The first conductor member represented by the bottommost metal and the topmost metal of the metal layer may be connected through conductor connection holes, so that signals can be transmitted from the second conductor member in the above-mentioned substrate layer to the above-mentioned first conductor member.

[0083] Exemplarily, there are two ways to dispose the connection pads on the bottommost metal:

[0084] The first way may refer to Figure 4a , and the bottommost metal can be directly set as the connection pad.

[0085] The second way may refer to Figure 4b , after filling the substrate through-hole 21 with a conductor, a connection pad 23 is disposed on the back surface of the chip with metal. Here, the connection pad 23 is connected to the second conductor member 12 represented by the bottommost metal through the filling conductor layer 22 filled in the substrate through-hole 21. After the connection pad 23 at the bottom of the substrate through-hole is connected to the second conductor member 12 through the filling conductor layer 22, it can be connected to the first conductor member through the conductor connection hole, so that signals can be transmitted from the above-mentioned substrate layer 20 to the topmost metal of the above-mentioned metal layer 10, thereby enabling the signals to connect the entire chip.

[0086] Exemplarily, the form of the connection pad disposed on the second conductor member in the bottommost metal or the form of the connection pad connected to the second conductor member through the filling conductor layer may be the same as the shape of the first conductor member or the connection pad in the topmost metal, which is also used to ensure sufficient contact between the connection pad and the metal conductor during hybrid bonding. Exemplarily, the shape of the above-mentioned connection pad may be rectangular or circular, or may be other polygons or other shapes, which are not limited herein. For example, when the above-mentioned connection pad is on the front surface of the above-mentioned storage section or the above-mentioned control section, the connection pad is disposed on the topmost metal. When the above-mentioned connection pad is on the back surface of the above-mentioned storage section or the above-mentioned control section, the above-mentioned connection pad is directly or indirectly connected to the bottommost metal through the filling conductor layer, and the connection pads on both sides can be circular with the same size.

[0087] It should be noted that the purpose of setting the connection pad is to facilitate the connection between the chip and the metal conductor in the hybrid bonding. When the connection pad is set on the front side of the chip, it is connected to the topmost metal of the metal via component in the metal layer. Among them, the topmost metal can be directly set in the form of a connection pad; when the connection pad is set on the back side of the chip, it is connected to the bottommost metal of the metal layer. Because setting the connection pad on the back side of the chip requires substrate digging, relatively speaking, when the chip is not in the middle position of the stacked chips, it is relatively easier and more reliable to set the connection pad on the topmost metal for hybrid bonding.

[0088] Exemplarily, the above storage part includes two or more than two of the above storage part chips, and the above storage part chips are connected to each other by a hybrid bonding method; and / or, the control part may include two or more than two of the above control part chips, and the above control part chips are connected to each other by a hybrid bonding method. Among them, the stacking methods between the control part chips, between the storage part chips, and between the control part and the storage part chips can have various forms, which are not limited herein.

[0089] Specifically, the storage part and the control part of the above 3D storage chip are connected by a hybrid bonding method. Because the RC parasitic parameters of the hybrid bonding are very small, there is no need for a drive interface circuit or module (PHY) between the two chips of the storage part and the control part. Further, the circuit modules in the original planar DRAM can be flexibly placed in the storage part or the control part according to needs; even the storage part can be extended to a stack of multiple storage function chips, so that the chip density of the stacked storage chips can be made very high. The parasitic parameters (parasitic resistance value, parasitic capacitance value) of the hybrid bonding connecting the storage part chips and the control part are very small. Therefore, the RC delay is small, and thus the data transmission speed is not lost, and high-bandwidth data transmission of the storage chip can be realized.

[0090] Combined with the above examples, referring to Figure 2 , on the side surface of the storage part 200 connected to the control part 100 among the above mutually stacked control part 100 and storage part 200, connection pads can be provided for hybrid bonding, that is, in the way of growing the metal conductor for hybrid bonding on the above connection pads. Correspondingly, connection pads are also provided on the side surface of the control part 100 connected to the storage part 200 for hybrid bonding, that is, in the way of growing the metal conductor for hybrid bonding on the above connection pads. Through the metal conductor for hybrid bonding, the above control part 100 and storage part 200 are connected and data communication is carried out.

[0091] Exemplarily, the foregoing connection pads may be disposed on the front or back surface of the storage portion 200 or the control portion 100. In some examples, the mutually stacked control portion 100 and storage portion 200 may be face-to-face, that is, the front surface of the chip of the control portion 100 faces the front surface of the chip of the storage portion 200, and the front surfaces of the chips of the two portions are connected by a hybrid bonding method, and the back surface of the chip of the control portion 100 and the back surface of the chip of the storage portion 200 are on the outside. In this way, it is only necessary to provide connection pads on the topmost metal of the control portion 100 and the storage portion 200 for hybrid bonding and connect them with the metal conductor 300. As described above, since it is easier and more reliable to provide connection pads on the topmost metal for hybrid bonding. Therefore, it is preferably to use the face-to-face method for hybrid bonding, and the manufactured 3D storage chip has higher reliability and better yield.

[0092] In some examples, since the foregoing connection pads are also used for the bonding of the leads of the storage chip package, after the mutually stacked control portion 100 and storage portion 200 are connected by the metal conductor 300 of hybrid bonding, connection pads may also be provided on the side of the storage portion chip and / or the control portion chip in the mutually stacked control portion 100 and storage portion 200 that faces away from the metal conductor, wherein the foregoing connection pads may be used to lead out the package pin connections for the packaging of the 3D chip.

[0093] It should be noted that the holes in the metal layer via components on the foregoing storage portion and the foregoing control portion are non-through holes. When packaging the chip, different from the traditional TSV, although signals can be transmitted through the entire chip, the holes on the chip do not need to penetrate the entire chip. The foregoing connection pads may be used to lead out the pin connections, and after the storage chip is packaged, it can be connected to an external circuit through the pin leads led out from the foregoing connection pads to serve as a functional unit and cooperate with the integrated circuit connected thereto to realize the overall function on its own electronic device.

[0094] After the 3D storage chip is split into a mutually stacked storage portion and a control portion, the foregoing examples have described in detail the hybrid bonding method between the storage portion and the control portion and the via structure for ensuring data transmission within a single chip. The following will specifically describe the respective function allocations of the storage portion and the control portion in the foregoing 3D storage chip in combination with some examples.

[0095] According to some embodiments, the above-mentioned 3D storage chip may include a storage part and a control part stacked on each other. The storage part and the control part are connected by a hybrid bonding method. Among them, the hybrid bonding method may be to connect the connection pads of the storage part and the connection pads of the control part through metal conductors. The storage part is provided with a storage array, and the functional circuits of the storage chip are arranged in the control part.

[0096] In some examples, the above-mentioned storage part may be provided with the most basic storage units, for example, a storage array. And the functional circuits of the above-mentioned 3D storage chip may be arranged on the control part.

[0097] Exemplarily, the above-mentioned functional circuits may include a row-column decoding circuit, a power supply circuit, a data processing circuit, and an interface circuit. In the above-mentioned 3D storage chip, when reading data from the storage part, the control part receives the command related to reading data. After the row-column decoding circuit decodes the address, the data in the corresponding storage array in the storage part is selected. The data enters the control part from the storage part, and then in the control part, the data is read out through the driving of the interface circuit and the clock control of the data processing circuit. In the above-mentioned 3D storage chip, when writing data to the storage part, the data is written into the storage array of the storage part after being driven by the interface circuit and distributed by the data lines of the data processing circuit in the control part, so that the basic functions of the storage chip can be fully realized.

[0098] Because the smallest storage unit (Memory Cell) in the storage array of the above-mentioned storage part uses a special process capable of storing data, its manufacturing process is very complex and difficult to control. Placing the storage array in the storage part can ensure the consistency of the process, and because other circuits have been placed in the control part, the particularity of its process will not affect other circuits.

[0099] According to some embodiments, the above-mentioned functional circuits may further include an SRAM repair unit circuit, and the SRAM repair unit circuit is used to replace the failed storage units in the storage array to repair the storage array. Usually, redundant units are arranged in the storage array for the purpose of repairing the failed units in the storage array. In the present invention, the functional circuits may further include an SRAM repair unit circuit for replacing the redundant units in the storage array. The advantage of this is that the control part can use a logic process to manufacture a better-performing SRAM circuit, and use the SRAM circuit to repair the failed units in the storage array.

[0100] According to some embodiments, the control part can use a special logic process, and the logic process can also meet the performance requirements of some analog circuits, so that it is not affected by the special process of the storage unit. The logic process can well enable other circuits including row and column decoding circuits, power supply circuits, data processing circuits, interface circuits and SRAM repair unit circuits to perform better. For example, pure digital logic such as row and column decoding circuits and data processing circuits can achieve higher data frequency and bandwidth using logic processes, and may also save power consumption.

[0101] According to some embodiments, in the above-mentioned storage chip, the above-mentioned storage part is provided with a storage array and a sense amplifier, and other functional circuits of the above-mentioned storage chip are provided in the above-mentioned control part. When the above-mentioned storage part is read out, the control part receives the above-mentioned command related to the data reading, and the above-mentioned row and column decoding circuit decodes the address, and then selects the data in the corresponding storage array in the storage part, and the data enters the control part after being amplified by the sense amplifier from the storage part, and then the data is read out in the control part through the driving of the interface circuit and the clock control of the data processing circuit. Because the storage unit in the storage array uses a special process that can store data, its manufacturing process is very complicated and difficult to control. Placing it and the sense amplifier in the storage part can ensure the consistency of the process, and because other circuits have been placed in the control part, the particularity of its process will not affect other circuits. At the same time, the sense amplifier is directly connected to the storage unit in the storage array, and the sense amplifier and the storage unit are placed in the same chip as the storage part to ensure the matching of data reading, and the data reading accuracy is higher.

[0102] According to some embodiments, the storage part may also be provided with a row-column decoding circuit, and other functional circuits of the storage chip are provided in the control part. Here, the row-column decoding circuit is added to the storage part. It can be understood that in the storage part, the row-column decoding circuit will frequently operate and control the storage array, and is closely connected with the storage array, and there are many connections between them. Placing the row-column decoding circuit in the storage part can effectively reduce the mixed bonding connections between the storage part and the control part, reduce the complexity of 3D chip manufacturing and improve the yield. At the same time, placing the row-column decoding circuit and the storage array together can reduce the error caused by process mismatch.

[0103] Exemplarily, the above storage part is further provided with a storage part power supply circuit, and other functional circuits of the above storage chip are arranged in the above control part. Specifically, when data is read and written and during other necessary operations, the above storage array and the above sense amplifier consume a large amount of power. The storage part power supply circuit with a basic power supply unit circuit required by the storage array and the sense amplifier is placed in the storage part, and the basic power supply function can well meet the power requirement of the functional circuits in the storage part during data read and write operations. The stability and reliability of the above storage part during operation are improved.

[0104] It should be noted that while the above power supply circuit is arranged in the storage part, the above control part can also be provided with a basic control part power supply circuit in the same way, and the above two power supply circuits can supply power to the storage part and the control part respectively. Of course, in the scheme where the above power supply circuit is arranged in the storage part, the power supply circuit in the control part can be omitted, and instead, when the control part needs to be powered, the power supply circuit of the storage part can be reused. In this scheme, since the above storage part is provided with a power supply circuit for power supply, the technical effect of improving the stability and reliability of the storage part is still achieved.

[0105] The above control part can be understood as the control part in a general storage chip. Although it can perform operations such as row and column decoding and simple data processing, it does not have an arithmetic function. Correspondingly, in some examples, the control part of the above storage chip can be not limited to only the control functions of a general storage chip, but can also include other more powerful logic functions. For example, the control part can be extended to a processor.

[0106] According to some embodiments, in the above 3D storage chip, an arithmetic function module can also be arranged in the above control part. The above operation function module can be a CPU (Central Processing Unit / Processor, central processor) or a GPU (Graphics Processing Unit, graphics processor). In this way, the data in the above storage part can be directly subjected to data arithmetic processing in the above control part. Since the above control part and the above storage part are connected by a hybrid bonding method and the parasitic parameters of signal transmission between them are small, the system composed of them can overcome storage obstacles and greatly improve the data processing ability.

[0107] It should be noted that the above storage part and control part in the 3D storage chip can still adopt Figure 2The hybrid bonding method shown above enables signal transmission in the planar chip of the 3D storage chip to be achieved through the above-mentioned chip via scheme that does not penetrate the entire chip. There is no need to set through-silicon vias. Instead, only substrate vias are opened on the substrate, and metal layer via components are opened within the metal layer, significantly reducing the diameter and length of the vias, thereby reducing the process difficulty of etching, the area occupied by the metal layer, the parasitic resistance and capacitance parameters, shortening the preparation cycle of chip units, and reducing production costs.

[0108] In the scheme of splitting the 3D storage chip into stacked storage and control parts, the above examples have elaborated in detail on the hybrid bonding method between the storage and control parts, the via structure for ensuring data transmission within a single chip, and the respective functional allocations of the storage and control parts. Next, the stacking method of the stacked storage and control parts in the 3D chip will be specifically described.

[0109] As Figure 2 shown, the above 3D storage chip may include:

[0110] Stacked control part 100 and storage part 200, where the above storage part 200 is connected to the above control part 100 through hybrid bonding. Among them, the above storage part may include two or more storage part chips, and / or, the above control part may include two or more control part chips. For example, the above 3D storage chip may include a storage part composed of three storage part chips and a control part composed of one control part chip, or, the above 3D storage chip may include a storage part composed of one storage part chip and a control part composed of three control part chips, or, the above 3D storage chip may include a storage part composed of three storage part chips and a control part composed of three control part chips. Here, the control part chip or storage part chip refers to a single chip (Die) or a wafer, where the chip refers to a 2D planar chip and the wafer refers to a 2D planar wafer. After the above storage part and control part are connected by the hybrid bonding method, various combination methods can be formed.

[0111] The storage part and control part of the above 3D storage chip are connected by the hybrid bonding method. As two parts of the chip of the same storage chip, there is no need for a drive interface circuit or module (PHY) between them. Further, the chip density of the stacked storage chips can be made very high, enabling more chips to be stacked. The parasitic parameters (parasitic resistance value, parasitic capacitance value) of the hybrid bonding connecting the storage part and control part are very small. Therefore, the RC delay is small, and thus there is no loss in data transmission speed, enabling high-bandwidth data transmission of the storage chip.

[0112] Exemplarily, the above storage part chip and / or the above control part chip can be connected by a hybrid bonding method. The above hybrid bonding method can be to connect the connection pads of the above storage part and the connection pads of the above control part through a metal conductor. The above storage part can be regarded as the chip mainly used for storage function among the multiple stacked chips of the 3D storage chip, and the above control part can be regarded as the chip mainly used for control function among the multiple stacked chips of the 3D storage chip.

[0113] According to some embodiments, in the above storage chip, in addition to the storage part chip and the control part chip can be connected by the above hybrid bonding method, the above storage part chips can also be connected by the hybrid bonding method, and the above control part chips can also be connected by the hybrid bonding method.

[0114] In some examples, the above storage part includes two or more storage part chips with storage arrays of the same capacity; and / or, the above storage part includes two or more storage part chips with storage arrays of different capacities.

[0115] According to some embodiments, two or more storage part chips can be arranged on the same plane, and each of the above storage part chips is independent. The storage part chips here can be storage units with storage arrays, and these storage units can be respectively connected to the above control part through a hybrid bonding method with a metal conductor. Among the multiple storage units in the chips on the same plane here, there can be no physical connection relationship, that is, they are not connected by pin wires or metal conductors.

[0116] Figure 5 This is a schematic structural diagram of a 3D storage chip with multiple storage units provided by an embodiment of the present invention. Having multiple storage units here means that the storage part has multiple storage units in the chips on the same plane. As Figure 5 shown, the above storage part can include a first storage unit, a second storage unit up to an nth storage unit, and the above n storage units can be respectively connected to the above control part through hybrid bonding with a metal conductor. There can be no physical connection relationship among the above n storage units, that is, the above n storage units are not connected by pin wires or metal conductors, but the above n storage units are not stacked on top of each other, but are arranged on the same plane in terms of position.

[0117] Specifically, the surface of one side of the n storage units connected to the control part is provided with a connection pad for connecting with the metal conductor in the hybrid bonding, and then a metal conductor (hybrid bonding) is grown on the connection pad. Correspondingly, the surface of one side of the control part connected to the n storage units can also be provided with a connection pad, and then connected through the metal conductor of the hybrid bonding, so that the control part and the n storage units are respectively connected and perform data communication. With this structure, it is relatively easy for the control part to control the storage part, and the reliability is relatively high. The n storage units can be storage arrays of the same capacity (or different capacities), independent of each other. Exemplarily, the independent storage units can replace each other when necessary. The advantage of this is that if a storage unit fails and malfunctions, other storage units can be replaced as redundant units, thereby improving the reliability of the entire 3D storage chip.

[0118] For example, see Figure 5 , a control part composed of a planar chip and multiple storage units are used as a planar storage part. As mentioned above, because setting connection pads on the back of the chip requires digging holes in the substrate, it is relatively easier and more reliable to set connection pads on the top metal layer for hybrid bonding. Therefore, the storage part and the control part preferably use a face-to-face hybrid bonding method, that is, the front side of the chip of the control part 100 and the front side of the chip of the storage part 200 are opposite, and the front sides of the chips of the two parts are connected by hybrid bonding, and the back side of the chip of the control part 100 and the back side of the chip of the storage part 200 are on the outside.

[0119] According to some embodiments, in the above-mentioned memory chip, the above-mentioned two or more memory part chips are stacked, and two adjacent chips are connected by hybrid bonding. It can be understood that not only the memory part chip and the control part chip can be connected by hybrid bonding, but also the memory part chip and the memory part chip can be connected by hybrid bonding. When the above-mentioned two or more memory part chips are stacked and two adjacent chips are connected by hybrid bonding, the above-mentioned memory chip solution can have multiple situations, and of course each situation also has corresponding functions and characteristics.

[0120] Exemplarily, two or more of the above-mentioned storage part chips can be stacked without any interval. Figure 6 A schematic structural diagram of another 3D memory chip having multiple memory parts provided by an embodiment of the present invention, such as Figure 6As shown, the control part of the above storage chip may include a control part chip 110, and the control part chip has the functions of data and signal processing. The storage part of the above storage chip may include a first storage part chip 210 and a second storage part chip 220. The control part chip 110, the first storage part chip 210, and the second storage part chip 220 are stacked in sequence from top to bottom. The above first storage part chip 210 and the second storage part chip 220 are stacked with the above control part chip 110. Specifically, a connection pad is provided on one surface of the above first storage part chip 210 connected to the above control part chip 110 for connection with the metal conductor in the hybrid bonding. Then, a metal conductor is grown on the above connection pad to form a hybrid bonding method. Correspondingly, a connection pad may also be provided on one surface of the control part chip 110 connected to the above first storage part chip 210 for connection with the metal conductor in the hybrid bonding. Then, a metal conductor is grown on the above metal pad to connect the above control part chip 110 and the above storage part chip 210 and conduct data communication in a hybrid bonding manner.

[0121] Here, it should be noted that as described above, since it is relatively easier and more reliable to set the connection pad on the topmost metal of the chip for hybrid bonding, the front of the control part chip 110 faces the first storage part chip 210. Correspondingly, since the above storage part chip 210 also needs to be continuously connected to the above storage part chip 220, the second storage part chip 220 is also set to face the first storage part chip 210 on the front. That is, connection pads are provided on the fronts of the control part chip 110 and the second storage part chip 220 for connection with the metal conductor in the hybrid bonding.

[0122] For the first storage part chip 210 placed between the control part chip 110 and the second storage part chip 220, since its front and back need to be connected to the control part chip 110 and the second storage part chip 220 by means of hybrid bonding, its front orientation can be placed according to the situation. However, in order to ensure the consistency between the first storage part chip 210 and the second storage part chip 220, generally, the front orientations of the first storage part chip 210 and the second storage part chip 220 are preferably the same. In this way, the consistency between the first storage part chip 210 and the second storage part chip 220 will be very good. Relatively speaking, for the entire 3D chip, the matching between the first storage part chip 210 and the second storage part chip 220 of the storage part will be very good. Thus, the reliability of the manufactured chip, the reliability of the chip operation, and the reliability of data reading and writing will be very good.

[0123] It can be understood that the above storage part can be a stack of multiple storage part chips. The above storage chips have the advantages of convenient extended storage capacity and simple form. When the above storage part is a stack of multiple storage part chips, the multiple storage part chips are stacked in the same direction, that is, the fronts of the multiple storage part chips are all facing up or all facing down.

[0124] Exemplarily, the multiple storage part chips stacked in the above storage part can be the same chips or different chips. When the multiple storage part chips stacked in the above storage part are different chips, it can include at least one volatile storage chip, for example: DRAM storage chip, and at least one non-volatile storage chip, for example: NAND flash storage chip. The advantage of this is that it can ensure the data access speed through the DRAM storage chip, and at the same time, through the NAND flash storage chip, ensure that the data on the non-volatile storage chip will not be lost when the chip loses power.

[0125] According to some embodiments, in the above storage chip, at least one of the control part chips is stacked between two or more of the above storage part chips at intervals, and the number of storage part chips on both sides of the control part chip is the same. Specifically, Figure 7 is a schematic structural diagram of another 3D storage chip with multiple storage parts provided by an embodiment of the present invention, as Figure 7 shown, the control part of the above storage chip can include a control part chip 110, and the control part chip has the function of data and signal processing. The above storage part can include a first storage part chip 210 and a second storage part chip 220. The above storage chip can also form other structures. For example, the control part chip 110 of the control part is arranged between the first storage part chip 210 and the second storage part chip 220.

[0126] Specifically, a connection pad is provided on the surface of the side where the first storage part chip 210 is connected to the control part chip 110, and then a metal conductor is grown on the connection pad to form a hybrid bonding. Correspondingly, a connection pad can also be provided on the surface where the control part chip 110 is connected to the first storage part chip 210, and then a metal conductor is grown on the connection pad to form a hybrid bonding, so that the control part chip 110 and the first storage part chip 210 are connected and data communication is performed. Correspondingly, since the control part chip 110 needs to continue to connect to the second storage part chip 220, a connection pad needs to be provided on the side of the control part chip 110 away from the metal conductor, and then a metal conductor is grown on the connection pad to form a hybrid bonding, and then the second storage part chip 220 is continued to be connected by hybrid bonding to form a chip stacking structure. The storage chip has the advantages of convenient storage capacity expansion, simple form and good symmetry. It should be noted that the above storage part is not limited to having the first storage part chip 210 and the second storage part chip 220, and may also have more storage part chips and continue to form a chip stacking structure.

[0127] Similarly, the above-mentioned storage chip has the advantages of convenient expansion of storage capacity and simple form. The multiple storage part chips stacked in the above-mentioned storage part can be the same chip or different storage chips. When the multiple storage part chips stacked in the above-mentioned storage part are different chips, at least one of them can be a volatile storage chip, such as a DRAM storage chip, and at least one other can be a non-volatile storage chip, such as a NAND flash storage chip. The advantage of this is that the data access speed can be guaranteed through the DRAM storage chip, and the data on the non-volatile storage chip can be ensured not to be lost when the chip loses power through the NAND flash storage chip.

[0128] According to some embodiments, in the above-mentioned memory chip, the above-mentioned two or more control part chips are stacked and arranged, and two adjacent chips are connected by metal conductors in a mixed bonding manner. When the above-mentioned two or more control part chips are stacked and arranged, and two adjacent chips are connected by metal conductors, the above-mentioned memory chip solution can exist in multiple situations, and of course each situation also has corresponding functions and characteristics.

[0129] Exemplarily, among the above-mentioned storage chips, two or more of the above-mentioned control part chips may include at least one analog function circuit chip and at least one digital function circuit chip, wherein the above-mentioned analog function circuit chip is only provided with analog function circuits, and the above-mentioned digital function circuit chip is only provided with digital function circuits.Figure 8 Schematic structural diagram of a 3D storage chip with multiple control parts provided by an embodiment of the present invention, as Figure 8 shown, the storage part of the above storage chip may include a storage part chip 210. The control part of the above storage chip may include a first control part chip 110 and a second control part chip 120. The first control part chip 110 has the function of data and signal processing, and the second control part chip 120 has the function of power supply. The first control part chip 110 and the second control part chip 120 are stacked with the above storage part chip 210. The first control part chip 110, the second control part chip 120, and the storage part chip 210 are stacked in sequence from top to bottom.

[0130] Specifically, a connection pad is provided on the surface of the second control part chip 120 connected to the storage part chip 210 for connection with the metal conductor in the hybrid bonding, and then a metal conductor is grown on the above connection pad to form a hybrid bonding; correspondingly, a connection pad may also be provided on the surface of the storage part chip 210 connected to the second control part chip 120 for connection with the metal conductor in the hybrid bonding, and then a metal conductor is grown on the above connection pad to form a hybrid bonding. So that the second control part chip 120 and the storage part chip 210 are connected and data communication is carried out. Correspondingly, since the second control part chip 120 also needs to continue to be connected to the first control part chip 110, a connection pad is provided on the side of the second control part chip 120 facing away from the storage part chip 210 for connection with the metal conductor in the hybrid bonding, and then a metal conductor (hybrid bonding) is grown on the above connection pad; and it is continuously connected to the control part chip 110 by the above hybrid bonding method to form a chip stack structure.

[0131] It should be noted that the above storage part is not limited to the storage part chip 210, and the control part is not limited to the first control part chip 110 and the second control part chip 120. There may also be more control part chips and continue to form a chip stack structure. Since the control part of the above storage chip is divided into multiple chips, the analog function and the digital function can be set separately, so that the control part can be compatible with the analog function process and the digital function process, and can combine the advantages of each process and have stronger performance.

[0132] Similarly, in addition to the way that the first control part chip 110, the storage part chip 210, and the second control part chip 220 are stacked in sequence from top to bottom as shown in Figure 8 , it may also be other ways, and their stacking order is not limited.

[0133] The storage part chip 210 of the above storage part may be provided with the most basic storage units, for example, a storage array. And the functional circuits of the above storage chip may be provided in the above control part chips 110 and 120. The functional circuits of the control part chip 110 may include: a row and column decoding circuit, a data processing circuit, and an interface circuit. The functional circuits of the control part chip 120 may include: a power supply circuit. In the above storage chip, when reading data from the above storage part, the control part receives the command related to the read data, and after the row and column decoding circuit decodes the address, the data in the corresponding storage array in the storage part is selected. The data enters the control part from the storage part, and then in the control part, the data is read out through the driving of the interface circuit and the clock control of the data processing circuit. In the above storage chip, when writing data to the above storage part, after the data is driven by the interface circuit and distributed by the data lines of the data processing circuit in the above control part, it is written into the storage array of the above storage part, so that the basic functions of the storage chip can be fully realized. Since the storage units in the storage array use a special process capable of storing data, its manufacturing process is very complex and difficult to control. Placing the storage array in the storage part can ensure the consistency of the process, and because the other circuits have been placed in the control part, the particularity of its process will not affect the other circuits.

[0134] Figure 9 FIG. is a schematic structural diagram of another 3D storage chip with multiple control parts provided by an embodiment of the present invention, as Figure 9As shown, the control part of the memory chip may include a memory chip 210. The control part of the memory chip may include a first control chip 110 and a second control chip 120. The first control chip 110 may have the function of data and signal processing, and the second control chip 120 may have the function of power supply. The first control chip 110 and the second control chip 120 are stacked with the memory chip 210. Specifically, a connection pad is provided on the surface of one side of the second control chip 120 connected to the memory chip 210 for connecting with the metal conductor in the hybrid bonding, and then a metal conductor is grown on the connection pad to form a hybrid bonding. Correspondingly, a connection pad may also be provided on the surface of one side of the memory chip 210 connected to the second control chip 120 for connecting with the metal conductor in the hybrid bonding, and then a metal conductor is grown on the connection pad to form a hybrid bonding. The second control chip 120 and the memory chip 210 are connected and data communication is performed. Accordingly, since the storage part chip 210 needs to continue to be connected to the first control part chip 110, it is necessary to set a connection pad on the side of the storage part chip 210 away from the metal conductor for connecting with the metal conductor in the hybrid bonding, and then grow the metal conductor on the connection pad to form a hybrid bonding, and continue to connect with the first control part chip 110 through hybrid bonding to form a chip stacking structure. It should be noted that the storage part is not limited to the storage part chip 210, and the control part is not limited to having control part chips 210 and 220, and can also have more control part chips and continue to form a chip stacking structure. Since the control part of the storage chip is divided into multiple chips, analog functional circuits and digital functional circuits can be set separately, so that the control part can be compatible with analog functional processes and digital functional processes, and can combine the advantages of each process to achieve stronger performance.

[0135] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral one; it can be a mechanical connection, an electrical connection, or communication with each other; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0136] Although the embodiments of the present invention have been disclosed as above, they are not limited to the applications listed in the specification and embodiments. It can be fully applied to various fields suitable for the present invention. For those skilled in the art, additional modifications can be easily achieved. Therefore, without departing from the general concept defined by the claims and their equivalents, the present invention is not limited to the specific details and the examples shown and described herein.

Claims

1. A 3D storage chip, characterized in that, it includes: A storage part and a control part stacked on each other, the storage part and the control part are connected by a hybrid bonding method, wherein the hybrid bonding method is to connect the connection pads of the storage part and the connection pads of the control part through a metal conductor, the control part includes a control part chip, the storage part includes a storage part chip, and the control part chip and / or the storage part chip includes a metal layer via component provided in the chip metal layer, wherein the holes in the metal layer via component are non-through holes; The metal layer via component includes a first conductor, a second conductor close to the substrate layer, and a conductor connection hole. A conductor connection hole is provided between the first conductor and the second conductor, and the second conductor is connected to the first conductor through the conductor connection hole so that signals can be transmitted to the first conductor through the substrate layer; The storage part is provided with a storage array and a sense amplifier, and the functional circuits of the storage chip are arranged in the control part; The functional circuit includes a SRAM repair unit circuit, and the SRAM repair unit circuit is used to replace the failed storage cells in the storage array to repair the storage array.

2. The storage chip according to claim 1, characterized in that, The storage part is also provided with a sense amplifier; Other functional circuits of the storage chip are arranged in the control part.

3. The storage chip according to claim 1, characterized in that, The functional circuit includes an arithmetic function module.

4. The storage chip according to claim 1, characterized in that, The control part includes a control part chip, the storage part includes a storage part chip, the control part chip and / or the storage part chip includes a metal layer via component provided in the chip metal layer, and the connection pad is arranged on the first conductor away from the substrate layer in the metal layer via component.

5. The storage chip according to claim 1, characterized in that, The connection pad is also used for bonding the package leads of the storage chip.

6. The storage chip according to claim 1, characterized in that, The storage part includes two or more than three storage part chips; and / or, The control part includes two or more than three control part chips.

7. The storage chip according to claim 6, characterized in that, The hybrid bonding method is to connect the connection pads of the storage part chips and the connection pads of the control part chips through a metal conductor.

8. The storage chip according to claim 6, characterized in that, The storage part chips are connected by a hybrid bonding method; and / or, The control part chips are connected by a hybrid bonding method.

9. The storage chip according to claim 6, characterized in that, The storage part includes two or more than three storage part chips with storage arrays of the same capacity; and / or, The storage part includes two or more than three storage part chips with storage arrays of different capacities.

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