Static random access memory of 3D stacked device and method for manufacturing the same

Abstract

A semiconductor device and a method for manufacturing the same are provided. The semiconductor device includes a static random access memory (SRAM), which includes a plurality of transistors arranged in a first layer and a second layer. The first layer includes a first shared gate of a first transistor among the plurality of transistors and a second shared gate of a second transistor. The second layer is arranged above the first layer and includes a third shared gate of a third transistor and a fourth shared gate of a fourth transistor among the plurality of transistors. The third shared gate is arranged above the first shared gate, and the fourth shared gate is arranged above the second shared gate. The SRAM further includes a first shared contact, a second shared contact, a first cross-connection contact connecting the fourth shared gate and the first shared contact, and a second cross-connection contact connecting the third shared gate and the second shared contact.

Description

Technical Field

[0001] One or more embodiments of the present disclosure relate to semiconductor devices, and more particularly, to static random access memory (SRAM) cells in 3D stacked devices. Background Art

[0002] The size of transistors continues to shrink to maintain scaled-down logic circuits in electronic devices. However, due to physical limitations faced by the continuous reduction in the size of transistors, planar structured transistors have evolved into all-around gate structures, such as FinFET and MBCFET, in order to concentrate more transistors within a certain area size and to exercise more control over the channel and gate of the transistor. Since the technology of reducing the size of a single transistor has its limitations, three-dimensional forms have been studied, in which transistors are stacked vertically into a 3D structure to provide higher transistor integration density.

[0003] Static random access memory (SRAM) is a random access memory composed of transistors and is one of the most basic elements in cache memory. Therefore, the circuit and physical structure of SRAM have been studied to strictly optimize the surface density and performance. Generally, the SRAM circuit consists of two (2) n-type metal oxide semiconductor (NMOS) transistors and two (2) p-type metal oxide semiconductor (PMOS) transistors for two inverters on one plane and two NMOS transistors for transmission gate transistors. However, the planar structure of SRAM requires more space to install transistors (for example, four NMOS transistors and two PMOS transistors), thereby increasing the size of the chip.

[0004] Thus, one or more layouts for 3D stacked SRAM devices including active cross-connect contacts are provided to optimize the areal density and performance of the SRAM. Summary of the invention

[0005] According to one or more embodiments, a semiconductor device including a static random access memory (SRAM) is provided, which includes: a plurality of transistors arranged in a first layer and a second layer, the first layer including a first shared gate of a first transistor and a second shared gate of the second transistor among the plurality of transistors, the second layer being arranged above the first layer and including a third shared gate of a third transistor and a fourth shared gate of a fourth transistor among the plurality of transistors, wherein the third shared gate is arranged above the first shared gate and the fourth shared gate is arranged above the second shared gate; a first shared contact and a second shared contact; a first cross-connection contact connecting the fourth shared gate and the first shared contact; and a second cross-connection contact connecting the third shared gate and the second shared contact.

[0006] According to one or more embodiments, a method for manufacturing a three-dimensional (3D) stacked static random access memory (SRAM) is provided. The method includes: providing a first metal gate as a first layer; providing a second metal gate as a second layer, the second layer being disposed above the first layer; performing a gate cut through the first metal gate and the second metal gate; removing a portion of the second metal gate to form a first groove; filling the first groove with a first dielectric material; and providing a cross-connection contact on a portion of the first dielectric material and the second metal gate.

[0007] According to one or more embodiments, a semiconductor device is provided, which includes a static random access memory (SRAM) cell, the SRAM cell having two n-type metal oxide semiconductor (NMOS) transistors and two p-type metal oxide semiconductor (PMOS) transistors, the SRAM cell including: an upper layer, including the two PMOS transistors; a lower layer, including the two NMOS transistors; a first shared contact and a second shared contact; a first cross-connection contact, connecting the gate of a first PMOS transistor of the two PMOS transistors to the first shared contact; and a second cross-connection contact, connecting the gate of a second PMOS transistor of the two PMOS transistors to the second shared contact. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The above and other aspects, features and advantages of certain embodiments of the present disclosure will become more apparent through the following description in conjunction with the accompanying drawings, in which:

[0009] Figure 1 is a diagram showing an example of an SRAM circuit;

[0010] Figure 2 is a diagram showing a cross-sectional view of a 3D stacked SRAM circuit according to an embodiment;

[0011] Figure 3 is a diagram showing a top view of an example SRAM layout;

[0012] Figure 4A It is shown Figure 3 An illustration of a top view of a first layer of a 3D stacked SRAM is shown;

[0013] Figure 4B It is shown Figure 3 An illustration of a top view of a second layer of a 3D stacked SRAM is shown;

[0014] Figure 5A is a diagram showing a top view of a first layer of a 3D stacked SRAM according to an embodiment;

[0015] Figure 5Bis a diagram showing a top view of a second layer of a 3D stacked SRAM according to an embodiment;

[0016] Fig. 6A is a diagram showing a top view of a first layer of a 3D stacked SRAM according to an embodiment;

[0017] Figure 6B is a diagram showing a top view of a second layer of a 3D stacked SRAM according to an embodiment;

[0018] Figure 6C is a diagram showing a method of Figure 6B FIG. 1 is a diagram of a cross-sectional view of a 3D stacked SRAM taken along line BB′ in FIG. 1 ;

[0019] Figure 7 is a diagram showing a schematic plan view of a semiconductor module according to an embodiment;

[0020] Figure 8 is a schematic block diagram of an electronic system according to an embodiment; and

[0021] Fig. 9 is a flowchart illustrating a method of manufacturing a three-dimensional (3D) stacked SRAM according to an embodiment. DETAILED DESCRIPTION

[0022] One or more embodiments will be described in detail below with reference to the accompanying drawings.

[0023] The embodiments described here are all example embodiments, therefore, the inventive concept is not limited thereto, but can be implemented in various other forms. It is not excluded that each embodiment provided in the following description is associated with one or more features of another example or another embodiment, which is also provided here or is not provided here but is consistent with the inventive concept. For example, even if the matter described in a specific example or embodiment is not described in different examples or embodiments, unless otherwise stated in its description, the matter can be understood to be related to or combined with different examples or embodiments. In addition, it should be understood that all descriptions of the principles, aspects, examples and embodiments of the inventive concept are intended to cover their structural and functional equivalents. In addition, these equivalents should be understood to include not only currently well-known equivalents, but also equivalents developed in the future, that is, all devices invented to perform the same function, regardless of their structure. For example, the MOSFET described here can adopt transistors of different types or forms, as long as the inventive concept can be applied to it.

[0024] It will be understood that when an element, component, layer, pattern, structure, region, etc. (hereinafter collectively referred to as an "element") of a semiconductor device is referred to as being "on" another element of the semiconductor device, "above" another element of the semiconductor device, "above" another element of the semiconductor device, "below" another element of the semiconductor device, "below" another element of the semiconductor device, "below" another element of the semiconductor device, "connected to" or "coupled to" another element of the semiconductor device, it may be directly located on, above, above, below, below, below, connected to or coupled to the other element, or there may be intervening elements(s). Conversely, when an element of a semiconductor device is referred to as being "directly on" another element of the semiconductor device, "directly above" another element of the semiconductor device, "directly on" another element of the semiconductor device, "directly below" another element of the semiconductor device, "directly below" another element of the semiconductor device, "directly below" another element of the semiconductor device, "directly below" another element of the semiconductor device, "directly connected to" or "directly coupled to" another element of the semiconductor device, there are no intervening elements. Throughout this disclosure, like numbers refer to like elements.

[0025] For ease of description, spatial relationship terms, such as "above", "above", "up", "below", "under", "below", "below", "below", etc., may be used herein to describe the relationship between one element and other (multiple) elements as shown in the figure. It will be understood that the spatial relationship terms are intended to cover different orientations of the semiconductor device in use or operation in addition to the orientation depicted in the figure. For example, if the semiconductor device in the figure is flipped, the elements described as "below" or "below" other elements will be oriented "above" the other elements. Therefore, the term "below" can include both above and below orientations. The semiconductor device can be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relationship descriptors used herein are interpreted accordingly.

[0026] As used herein, expressions such as "at least one of," when following a list of elements, modify the entire list of elements and do not modify the individual elements in the list. For example, the expression "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c. Here, when the term "same" is used to compare the size of two or more elements, the term can encompass "substantially the same" sizes.

[0027] It will be understood that although the terms first, second, third, fourth, etc. can be used to describe various elements here, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teachings of the present invention, the first element discussed below can be referred to as the second element.

[0028] It will also be understood that even if a certain step or operation of manufacturing a device or structure of the present invention is described later than another step or operation, the step or operation may be performed earlier than the other step or operation unless the step or operation is described as being performed after the other step or operation.

[0029] One or more embodiments are described herein with reference to cross-sectional views as schematic diagrams of embodiments (and intermediate structures). Therefore, variations in the illustrated shapes due to, for example, manufacturing techniques and / or tolerances can be expected. Therefore, one or more embodiments should not be interpreted as being limited to the specific shapes of the regions shown here, but will include shape deviations, for example, caused by manufacturing. For example, an implanted region shown as a rectangle will typically have circular or curved features and / or a gradient of implant concentration at its edge, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may cause some implantation to occur in the region between the buried region and the surface through which the implantation is performed. Therefore, the regions shown in the figures are schematic in nature, and their shapes are not intended to illustrate the actual shape of the region of the device and are not intended to limit the scope of the inventive concept. In addition, in the accompanying drawings, the sizes and relative sizes of the layers and regions may be exaggerated for clarity.

[0030] For the sake of brevity, conventional elements of semiconductor devices may or may not be described in detail here. However, even if an element is described or illustrated in a semiconductor device in the present disclosure, the element may not be included in the claimed semiconductor device unless the element is stated to be included in the claimed semiconductor device.

[0031] Figure 1 is a diagram showing an example of an SRAM circuit.

[0032] SRAM is a type of random access memory that uses latch circuits to store one or more bits. Figure 1, a typical SRAM circuit 100 is composed of six metal oxide semiconductor field effect transistors (MOSFETs) (e.g., pull-up transistors PU1 110a and PU2 110b, pull-down transistors PD1 120a and PD2 120b, and transmission gate transistors PG1 130a and PG2 130b). Each bit in the SRAM is stored on four transistors (i.e., PU1 110a, PD1 120a, PU2 110b, and PD2 120b) that form two cross-coupled inverters. For example, PU1 110a and PD1 120a can be one inverter, and PU2 110b and PD2 120b can be another inverter. The two transmission gate transistors (i.e., PG1 130a and PG2 130b) are used to control access to the memory cell (i.e., the two cross-coupled inverters) during read and write operations.

[0033] During a read operation, the word line WL can be set high (i.e., logic state "1") to activate access to the memory cell by PG1 130a and PG2 130b. By activating the word line WL, the value (i.e., "0" or "1") in the memory cell can be read through the bit line BL and / or the complementary bit line BLB. For example, if a logic state "1" is stored in the memory cell and when the word line WL turns on PG1 130a and PG2 130b, the bit line BL can read "1" and the complementary bit line BLB can read "0". During a write operation, for example, if an instruction to write "1" in a memory cell is to be executed, the word line WL can be set high to turn on PG1 130a and PG2 130b, and the bit line BL can be set to a high voltage to overwrite the value "0" stored in the memory cell. Therefore, one or more bits can be stored and accessed in the SRAM.

[0034] Figure 2 is a diagram showing a cross-sectional view of an SRAM circuit according to an embodiment.

[0035] Reference Figure 2, the SRAM circuit 200 may be constructed such that the first pull-down transistor PD1 220a, the second pull-down transistor PD2 220b, the first pass-gate transistor PG1 230a, and the second pass-gate transistor PG2 230b are located on a first layer F1 (also referred to as a "lower layer" and / or a "first layer"), and the first pull-up transistor PU1 210a and the second pull-up transistor PU2 210b are located on a second layer F2 (also referred to as an "upper layer" and / or a "second layer"). Here, the second layer F2 is located above the first layer F1. In other words, the PU1 210a and PU2 210b transistors may be arranged above the PD1 220a, PD2 220b, PG1 230a, and PG2 230b transistors. For example, PU1 210a and PU2 210b may be arranged directly above PD1 220a and PD2 220b, respectively, and each of PG1 230a and PG2 230b may be arranged adjacent to one side of PD1 220a and PD2 220b. That is, for example, PG1 230a may be arranged adjacent to PD1 220a, and PG2 230b may be arranged adjacent to PD2 220b, wherein PG1 230a and PG2 230b are arranged opposite to each other with respect to PD1 220a and PD2 220b therebetween. However, one or more embodiments are not limited thereto, and various arrangements of transistors may be used.

[0036] In addition, PD1 220a, PD2 220b, PG1 230a, and PG2 230b may be n-type metal oxide semiconductor (NMOS) transistors, and PU1 210a and PU2 210b may be p-type metal oxide semiconductor (PMOS) transistors. However, one or more embodiments are not limited thereto, and other transistors and / or other circuit configurations may be used. In addition, as Figure 2 As shown, PU1 210a and PU2 210b may be connected to a voltage source Vdd, and PD1 220a and PD2 220b may be connected to a voltage source Vss.

[0037] according to Figure 2 The SRAM circuit 200 shown can reduce the size of the area required to place all transistors used in the SRAM circuit while maintaining the performance and functionality of the SRAM by placing pull-up transistors (e.g., two (2) PMOS transistors) above the pull-down transistors and the pass-gate transistors (e.g., four (4) NMOS transistors).

[0038] Figure 3 is a diagram showing a top view of an example SRAM layout.

[0039] Reference Figure 3, the SRAM circuit may include a first pull-up transistor PU1 310a, a second pull-up transistor PU2 310b, a first pull-down transistor PD1 320a, a second pull-down transistor PD2 320b, a first pass-gate transistor PG1 330a, and a second pass-gate transistor PG2 330b. Similar to Figure 2 In the SRAM circuit 200 shown, PU1 310a and PD1 320a are connected to form an inverter, and PU2 310b and PD2 320b are connected to form another inverter. Here, the gate of PU1 310a and the gate of PU2 310b are connected to the gate of PD1 320a and the gate of PD2 320b, respectively. The source of PU1 310a and the source of PU2 310b are connected to the voltage source VDD through contacts C2 and C3, respectively. Each drain of PU1 310a and PU2 310b can be connected to a node 350. That is, the drain of PU1 310a can be connected to one of the nodes 350 through the second cross-connection contact 340b and thus connected to the source of PG2 330b, and the drain of PU2 310b can be connected to the other of the nodes 350 through the first cross-connection contact 340a and thus connected to the source of PG1 330a. Each gate of PG1 330a and PG2 330b is connected to a word line, and the drain of PG1 330a and the drain of PG2 330b are connected to the bit line BL and the complementary bit line BLB through contacts C1 and C4, respectively. The source of PG1 330a is connected to the drain of PU1 310a, wherein the drain of PU1 310a is connected to the source of PD1 320a. Similarly, the source of PG2 330b is connected to the drain of PU2 310b, wherein the drain of PU2 310b is connected to the source of PD2 320b. PD1 320a and PD2 320b are also connected to a voltage source VSS. Here, PU1 310a and PU2 310b may be PMOS transistors, and PD1 320a, PD2 320b, PG1 330a, and PG2 330b may be NMOS transistors.

[0040] Figure 3 The SRAM circuit shown can be divided into a first layer and a second layer in the 3D stacked SRAM, wherein the second layer is located above the first layer. Figure 4A and Figure 4B Describe it in more detail.

[0041] Figure 4A It is shown Figure 3 Illustration of a top view of a first layer of a 3D stacked SRAM is shown.

[0042] Reference Figure 4A, the first layer F1 of the 3D stacked SRAM may include a first pull-down transistor PD1 420a, a second pull-down transistor PD2 420b, a first pass-gate transistor PG1 430a, a second pass-gate transistor PG2 430b, and a node 450. As described above with reference to Figure 3 As described above, PG1 430a and PD1 420a may be connected via contact C1 connected to one of nodes 450 (hereinafter referred to as the "first node"). Similarly, PG2 430b and PD2 420b may be connected via contact C4 connected to another of nodes 450 (hereinafter referred to as the "second node").

[0043] Figure 4B It is shown Figure 3 Illustration of a top view of the second layer of the 3D stacked SRAM shown.

[0044] Reference Figure 4B , the second layer F2 of the 3D stacked SRAM may include a first pull-up transistor PU1 410a, a second pull-up transistor PU2 410b, and a node 450. The node 450 may extend vertically from the first layer F1 to the second layer F2. That is, the node 450 may extend in the z direction (i.e., the direction of entering and exiting the paper). The first node may be connected to the contact C1 ( Figure 4A The second node may be connected to contact C4 ( Figure 4A ) and contact C3 to form a second inverter including PU2 410b and PD2 420b. Therefore, node 450 (e.g., the first node and the second node) forms a first inverter and a second inverter. In addition, the first node and the second node are connected to PU2 410b and PU1 410a in the upper layer through the first cross-connection contact 440a and the second cross-connection contact 440b, respectively. Specifically, the first node can be connected to PU2 410b through the first cross-connection contact 440a, and the second node can be connected to PU1 410a through the second cross-connection contact 440b, thereby connecting PU1 410a and PU2 410b set in the upper layer to PD1 420a and PD2 420b set in the lower layer, respectively, and forming a cross-connection inverter to be used as a memory cell of the SRAM.

[0045] However, Figure 3 , Figure 4A and Figure 4BThe SRAM circuit shown is simply divided into an upper layer and a lower layer, and more than one gate cutting operation may be required to separate the gate of each transistor during the manufacture of the SRAM. Gate cutting may include, for example, depositing a dielectric material to insulate the gate of the transistor. The dielectric material may include, for example, silicon oxide, silicon nitride, carbon nitride, aluminum nitride, etc. However, the dielectric material is not limited thereto, but may include any other material capable of insulating the gate of the transistor from other conductors.

[0046] Figure 5A is a diagram showing a top view of a first layer of a 3D stacked SRAM according to an embodiment. Here, the first layer of the 3D stacked SRAM structure according to this embodiment is similar to Figure 4A Therefore, for the sake of brevity of description, descriptions of the same or similar elements provided above may be omitted.

[0047] Reference Figure 5A , the first layer F1 of the 3D stacked SRAM may include a first pull-down transistor PD1 520a, a second pull-down transistor PD2 520b, a first pass-gate transistor PG1 530a, a second pass-gate transistor PG2 530b, and a node 550. As described above with reference to Figure 4A As described above, PG1 530a and PD1 520a may be connected via contact C1, wherein the contact C1 is connected to one of the nodes 550 (referred to as a "first node"). Similarly, PG2 530b and PD2 520b may be connected via contact C4, wherein the contact C4 is connected to another of the nodes 550 (referred to as a "second node"). In addition, each gate of PG1 530a and PG2 530b may be connected to a word line WL 570. Each drain of PG1 530a and PG2 530b may be connected to a corresponding bit line. For example, the drain of PG1 530a may be connected to a bit line BL, and the drain of PG2 530b may be connected to a complementary bit line BLB. Here, PD1 520a and PD2 520b and PG1 530a and PG2 530b may be NMOS transistors.

[0048] Figure 5B is a diagram illustrating a top view of a second layer of a 3D stacked SRAM according to an embodiment.

[0049] Reference Figure 5B, the second layer F2 of the 3D stacked SRAM may include a first pull-up transistor PU1 510a, a second pull-up transistor PU2 510b, a first dummy gate 590a, a second dummy gate 590b, and a node 550. The node 550 may extend vertically from the first layer F1 to the second layer F2. That is, the node 550 may extend in the z direction (i.e., the direction of entering and exiting the paper). The first node may be connected to the contact C1 ( Figure 5A The second node may be connected to contact C4 (as shown) and contact C2 to form a first inverter including PU1 510a and PD1 520a. Figure 5A 510b and PD2 520b are connected to each other through a first cross-connection contact 540a and a second cross-connection contact 540b. Specifically, the first node can be connected to the gate of PU2 510b through the first cross-connection contact 540a, and the second node can be connected to the gate of PU1 510a through the second cross-connection contact 540b, thereby connecting PU1 510a and PU2 510b disposed in the upper layer to PD1 520a and PD2 520b disposed in the lower layer, and forming a cross-connection inverter to be used as a storage unit of the SRAM.

[0050] However, the first cross-linking contact 540a and the second cross-linking contact 540b according to an embodiment may be diagonally disposed to connect PU1 510a and PU2 510b to the corresponding node 550. Specifically, the first cross-linking contact 540a may be diagonally disposed (e.g., relative to the direction in which the gate and / or the first node of PU2 510b extend) to connect PU2 510b to the first node. Similarly, the second cross-linking contact 540b may be diagonally disposed (e.g., relative to the direction in which the gate and / or the second node of PU1 510a extend) to connect PU1 510a to the second node. Here, a portion of the first cross-linking contact 540a may be in contact with the first dummy gate 590a and a portion of the second cross-linking contact 540b may be in contact with the second dummy gate 590b. Such a configuration, for example, the first cross-connection contact 540a contacts the first dummy gate 590a, may cause a short circuit in the first inverter because the first cross-connection contact 540a may connect PU2 510b, the first dummy gate 590a, and the first node connected to PD1 520a and PG1 530a in the lower layer. Similarly, the second cross-connection contact 540b in contact with the second dummy gate 590b may cause the same problem as described above. Therefore, the first inverter and the second inverter may fail, making the memory cell of the SRAM inoperable. Therefore, it is necessary to separate the first dummy gate 590a and the second dummy gate 590b from the first cross-connection contact 540a and the second cross-connection contact 540b, respectively. The following will refer to FIG. 6A to FIG. 6C A more detailed description of the fabrication process for separating the dummy gate from the cross-connect contacts is described.

[0051] Fig. 6A is a diagram showing a top view of a first layer of a 3D stacked SRAM according to an embodiment.

[0052] Reference Fig. 6A , on the first layer F1 (ie, the lower layer), the 3D stacked SRAM circuit may include an active region 601, a first pull-down transistor PD1 620a, a second pull-down transistor PD2 620b, a first pass-gate transistor PG1 630a, a second pass-gate transistor PG2 630b, a shared contact (CNT) 650, and a word line 670. Fig. 6A In the example, the shared gate is the gate of PD1 620a and PD2 620b, respectively. Fig. 6A It can be seen that the shared gates of the first pass-gate transistor PG1 630a and the second pull-down transistor PD2 620b are collinear, and the shared gates of the second pass-gate transistor PG2 630b and the first pull-down transistor PD1 620a are collinear. Fig. 6AThe shared gates in the embodiment will be referred to as “first shared gate 620a” and “second shared gate 620b” hereinafter. In addition, the shared CNT 650 may correspond to the shared gates in the embodiment described above. Figures 3 to 5B Nodes 350, 450 and / or 550 described above, and active region 601 may correspond to Figures 3 to 5B Contacts C1 to C4 are described.

[0053] On the first layer F1, the active region 601 may be connected to each of PG1 630a, PG2 630b, the first shared gate 620a, and the second shared gate 620b. The shared CNT 650 may be disposed between PG1 630a and the first shared gate 620a and between the second shared gate 620b and PG2 630b. The word line 670 may be connected to the gates of PG1 630a and PG2 630b. Here, a gate cutting process may be performed to separate the second shared gate 620b from the gate of PG1 630a. For example, a recess may be formed in the gates of the second shared gate 620b and PG1 630a, and a dielectric 604 may be filled in the recess. Similarly, the dielectric 604 may separate the gates of the first shared gate 620a and PG2 630b. This will be described below with reference to Figure 6B and Figure 6C The dielectric 604 is described in more detail.

[0054] Figure 6B is a diagram illustrating a top view of a second layer of a 3D stacked SRAM according to an embodiment.

[0055] Reference Figure 6B , on the second layer F2 (ie, upper layer), the 3D stacked SRAM circuit may include a first pull-up transistor PU1 610a, a second pull-up transistor PU2 610b, a first dummy gate 690a, a second dummy gate 690b, and a shared CNT 650. The shared CNT may extend vertically from the first layer F1 to the second layer F2. Figure 6B The shared gate in may represent the gate of PU1 610a and the gate of PU2 610b. Figure 6B The shared gates in will be referred to as “third shared gate 610a” and “fourth shared gate 610b”. Furthermore, the third shared gate 610a and the fourth shared gate 610b may be used interchangeably with PU1 610a and PU2 610b.

[0056] The active region 601 may be connected to the first dummy gate 690 a , the second dummy gate 690 b , the third shared gate 610 a , and the fourth shared gate 610 b . Figure 6B The active region 601 in Figure 6CThe second active region 601b shown in FIG. 6 is disposed above the first active region 601a. Figure 6C As shown, the active regions 601a and 601b are separated by a dielectric material so that the first active region 601a connected to the first and second shared gates 620a and 620b is separated from the second active region 601b connected to the third and fourth shared gates 610a and 610b.

[0057] The shared CNT 650 may connect the active regions 601 to form a first inverter including PU1 610a and PD1 620a. The shared CNT 650 may also connect the active regions 601 to form a second inverter including PU2 610b and PD2 620b. Thus, the shared CNT 650 (eg, corresponding to Figures 3 to 5B The first node and the second node in the circuit) form a first inverter and a second inverter.

[0058] The shared CNT 650 is connected to the fourth shared gate 610b and the third shared gate 610a at the upper layer through the first cross-connection contact 640a and the second cross-connection contact 640b, respectively. Specifically, the third shared gate 610a can be connected to one of the shared CNTs 650 through the second cross-connection contact 640b, and the fourth shared gate 610b can be connected to the other of the shared CNTs 650 through the first cross-connection contact 640a, thereby connecting PU1 610a and PU2 610b disposed at the upper layer to PD1 620a and PD2 620b disposed at the lower layer, respectively, and forming a cross-connection inverter to be used as a memory cell of the SRAM.

[0059] According to an embodiment, the first cross-linking contact 640a and the second cross-linking contact 640b may be disposed obliquely to connect the third shared gate 610a and the fourth shared gate 610b to the corresponding shared CNT 650. In other words, the first cross-linking contact 640a may be disposed obliquely to connect the fourth shared gate 610b to one of the shared CNTs 650 (e.g., Figure 6B Similarly, the second cross-connection contact 640b may be disposed obliquely to connect the third shared gate 610a to another one of the CNTs 650 (eg, Figure 6B shared CNT 650 on the right side of the diagram).

[0060] When the first cross-connection contact 640a and the second cross-connection contact 640b are arranged to connect the corresponding shared gate and the shared CNT, a portion of the first cross-connection contact 640a may touch the first dummy gate 690a or contact the first dummy gate 690a, and a portion of the second cross-connection contact 640b may touch the second dummy gate 690b or contact the second dummy gate 690b. Such a configuration, for example, the first cross-connection contact 640a contacts the first dummy gate 690a, which may cause a short circuit in the first inverter, because the first cross-connection contact 640a may connect the fourth shared gate 610b, the first dummy gate 690a, and the shared CNT 650 connected to the first shared gate 620a and PG1 630a in the lower layer. Similarly, the second cross-connection contact 640b in contact with the second dummy gate 690b may cause the same problem as above. Therefore, the first inverter and the second inverter may fail, making the memory cell of the SRAM inoperable. Therefore, one may wish to separate the first and second dummy gates 690a and 690b from the first and second cross-linking contacts 640a and 640b, respectively.

[0061] In addition, gate cutting may be performed on the second layer F2 to separate the first dummy gate 690a and PU2 610b. In addition, the same gate cutting may separate the second dummy gate 690b and PU1 610a. Figure 6C Gate cutting is described in more detail.

[0062] Figure 6C is a diagram showing a method of Figure 6B Schematic diagram of a cross-sectional view of a 3D stacked SRAM taken along line BB′ in FIG.

[0063] Reference Figure 6C , the first active region 601a may be disposed on the silicon substrate. Alternatively, the first active region 601a may be formed so as to be combined with the silicon substrate. For example, the first active region 601a may include a silicon substrate extending in a horizontal direction and a protrusion protruding from a top surface of the silicon substrate in a vertical direction. A first dielectric 602 for separating or isolating the silicon substrate from a metal gate may be disposed on the first active region 601a. ​​The gate of PD2 620b and the gate of PG1 630a may be disposed on the first dielectric 602. Although not in Figure 6C620a and PG1 630b. Although the gate of PD2 620b and the gate of PG1 630a are described separately for the purpose of illustration, it is understood that the gate of PD2 620b and the gate of PG1 630a can be formed of the same metal material, such as aluminum (Al), tungsten (W), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti) or an alloy thereof. However, the material of the metal gate is not limited thereto, but may include any other material capable of conducting electricity. The gate of PD2 620b and the gate of PG1 630a may be connected to the protrusion of the first active region 601a.

[0064] In addition, the first dummy gate 690a and the gate of PU2 610b may be disposed above the gate of PG1 630a and the gate of PD2 620b, respectively. The first dummy gate 690a and the gate of PU2 610b may be connected to the second active region 601b. Here, the second active region 601b is separated from the first active region 601a by a second dielectric 603 disposed between the first active region 601a and the second active region 601b.

[0065] As mentioned above about Fig. 6A and Figure 6B As described, gate cutting may be performed on the gate of the first layer F1 and the gate of the second layer F2. That is, the dielectric 604 formed by performing a single gate cutting may separate the second shared gate 620b and the gate of PG1 630a, and may separate the fourth shared gate 610b and the first dummy gate 690a. Figure 6C Although not shown in the figure, the dielectric 604 may separate the first shared gate 620a and the gates of PG2 630b, and separate the third shared gate 610a and the second dummy gate 690b. The dielectric 604 may be performed by filling the region C with a dielectric material.

[0066] A portion of the first dummy gate 690a (similarly, the second dummy gate 690b) may be removed by etching the first dummy gate 690a to form a groove, and then the third dielectric 606 may be filled in the groove where the portion of the first dummy gate 690a is removed. In this way, the portion on the first dummy gate 690a may be insulated. Thereafter, the first cross-connection contact 640a may be disposed so that the first cross-connection contact 640a contacts the fourth shared gate 610b and a portion of the third dielectric 606. Because the third dielectric 606 is used to insulate or separate the first dummy gate 690a from being connected to the fourth shared gate 610b through the first cross-connection contact 640a, the first cross-connection contact 640a may only connect the fourth shared gate 610b to the shared CNT 650 (e.g., Figure 6B ) while keeping the first dummy gate 690a intact. In addition, it should be understood that the above structure and process can be similarly applied to the second dummy gate 690b, the second cross-connection contact 640b, the third shared gate 610a and the shared CNT 650. For example, the second dummy gate 690b can include a third dielectric 606 thereon.

[0067] In addition, a fourth dielectric 605 for covering the metal gate may be provided on a portion of the first dummy gate 690a and the fourth shared gate 610b. The fourth dielectric 605 may be provided adjacent to each side surface of the first cross-connection contact 640a. In addition, a word line 670 may be provided on the top of a portion of the first dummy gate 690a (where the first dummy gate 690a is not replaced by the third dielectric 606). The first cross-connection contact 640a may be insulated or separated from the word line 670 by the fourth dielectric 605. It should be understood that the above structure and process may be similarly applied to the second dummy gate 690b, the second cross-connection contact 640b, the third shared gate 610a and the shared CNT 650. For example, the fourth dielectric 605 may also be provided on a portion of the second dummy gate 690b and the third shared gate 610a.

[0068] By performing only a single gate cut to cut the gates disposed on the first layer F1 and the second layer F2, the complexity of manufacturing a 3D stacked SRAM can be significantly reduced. In addition, because it is difficult to perfectly or cleanly etch the dummy gates 690a and 690b to connect only the shared gates 610a and 610b with the shared CNT 650 using the cross-connection contacts 640a and 640b, respectively, by placing the third dielectric 606 in the grooves formed in the dummy gates 690a and 690b, the cross-connection contacts 640a and 640b can be disposed without touching the dummy gates 690a and 690b.

[0069] Figure 7is a diagram showing a schematic plan view of a semiconductor module according to an embodiment.

[0070] Reference Figure 7 , a semiconductor module 700 according to an embodiment may include a processor 720 and a semiconductor device 730 mounted on a module substrate 710. The processor 720 and / or the semiconductor device 730 may include one or more 3D stacked SRAMs described in one or more embodiments.

[0071] Figure 8 is a schematic block diagram of an electronic system according to an embodiment.

[0072] Reference Figure 8 , an electronic system 800 according to an embodiment may include a microprocessor 810, a memory 820, and a user interface 830 that perform data communication using a bus 840. The microprocessor 810 may include a central processing unit (CPU) or an application processor (AP). The electronic system 800 may further include a random access memory (RAM) 850 that communicates directly with the microprocessor 810. The microprocessor 810 and / or the RAM 850 may be implemented in a single module or package. The user interface 830 may be used to input data to the electronic system 800, or output data from the electronic system 800. For example, the user interface 830 may include a keyboard, a touch pad, a touch screen, a mouse, a scanner, a voice detector, a liquid crystal display (LCD), a micro light emitting device (LED), an organic light emitting diode (OLED) device, an active matrix light emitting diode (AMOLED) device, a printer, a lighting device, or various other input / output devices without limitation. The memory 820 may store an operation code of the microprocessor 810, data processed by the microprocessor 810, or data received from an external device. The memory 820 may include a memory controller, a hard disk, or a solid state drive (SSD).

[0073] At least the microprocessor 810 , the memory 820 , and / or the RAM 850 in the electronic system 800 may include one or more 3D stacked SRAMs described in one or more embodiments.

[0074] Fig. 9 is a flowchart illustrating a method of manufacturing a three-dimensional (3D) stacked SRAM according to an embodiment.

[0075] In operation S910, a first metal gate may be provided as a first layer on a substrate. Here, the first metal gate may be processed into, for example, Figure 6CThe metal gate before PD2 620 b and PG1 630 a is shown. In addition, a first dielectric 602 may be disposed between the substrate and the first metal gate, and the first metal gate may be disposed on the first dielectric 602 .

[0076] In operation S920, a second metal gate may be provided as a second layer on the first metal gate. Here, the second metal gate may be a metal gate before being processed into, for example, PU2 610b and the first dummy gate 690a. The second metal gate may be formed of the same or different material as the first metal gate.

[0077] In operation S930, gate cutting may be performed on the first metal gate and the second metal gate to separate or insulate PD2 620b and PG1 630a in the first layer and separate or insulate PU2 610b and the first dummy gate 690a in the second layer. Here, a single gate cutting may be performed to cut both the first metal gate and the second metal gate.

[0078] In operation S940, a portion of the second metal gate may be removed to form a groove on the second metal gate. For example, the portion of the second metal gate that is adjacent to the gate cut dielectric 604 ( Figure 6C ) to form a groove on the second metal gate.

[0079] In operation S950 , the groove may be filled with a dielectric material.

[0080] In operation S960, a cross-connection contact may be provided on the second metal gate. Figure 6B and Figure 6C , the first cross-connection contact 640a may be provided obliquely on the fourth shared gate 610b to connect the fourth shared gate 610b with the shared CNT 650. Here, the first cross-connection contact 640a may partially touch or occupy the surface area above the first dummy gate 690a. However, because the first dummy gate 690a is insulated by the dielectric material (e.g., the third dielectric 606) filled in the groove of the second metal gate (e.g., the first dummy gate 690a), the first cross-connection contact 640a may not be electrically connected to the first dummy gate 690a.

[0081] However, the method of manufacturing a three-dimensional (3D) stacked SRAM is not limited to the above embodiments but may include various other methods.

[0082] Some embodiments of the present disclosure have been shown and described above. However, one or more embodiments of the present invention are not limited to the above-mentioned specific embodiments. It is understood that various modifications, substitutions, improvements and equivalences thereof can be made without departing from the spirit and scope of the present disclosure. It should be understood that such modifications, substitutions, improvements and equivalences thereof all fall within the scope of protection of the present invention and should not be construed as departing from the inventive concept or expectation of the present disclosure.

[0083] This application is based on and claims priority to U.S. Provisional Application No. 63 / 143,221 filed with the U.S. Patent and Trademark Office on January 29, 2021, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor device, comprising: A three-dimensional stacked static random access memory comprising a plurality of transistors arranged in a first layer and a second layer; The first layer includes a first shared gate of a first transistor and a second shared gate of a second transistor, the first transistor and the second transistor being disposed diagonally; The second layer is disposed above the first layer and includes a third shared gate of a third transistor and a fourth shared gate of a fourth transistor, and a first dummy gate and a second dummy gate, wherein the third shared gate is disposed above the first shared gate, the fourth shared gate is disposed above the second shared gate, and the first dummy gate and the second dummy gate are disposed diagonally; a first shared contact and a second shared contact, the first shared contact being disposed in the second layer between the first dummy gate and the third shared gate, the second shared contact being disposed in the second layer between the second dummy gate and the fourth shared gate; a first cross-connect contact connecting the fourth shared gate and the first shared contact; as well as a second cross-connect contact connecting the third shared gate and the second shared contact, wherein a third dielectric material is disposed between the first dummy gate and the fourth shared gate, and between the second dummy gate and the third shared gate, wherein a portion of the first dummy gate and a portion of the second dummy gate include a first dielectric material, wherein the first cross-connection contact is disposed over the first dielectric material of the first dummy gate and the fourth shared gate so as to electrically connect only the fourth shared gate and the first shared contact, and The second cross-connection contact is disposed above the first dielectric material of the second dummy gate and the third shared gate, thereby electrically connecting only the third shared gate and the second shared contact.

2. The semiconductor device according to claim 1, wherein the first transistor and the second transistor are pull-down transistors, and Wherein the third transistor and the fourth transistor are pull-up transistors.

3. The semiconductor device according to claim 1, wherein the first cross-linking contact is arranged obliquely with respect to the fourth shared gate and the first shared contact, and The second cross-connection contact is arranged obliquely relative to the third shared gate and the second shared contact.

4. The semiconductor device according to claim 1, wherein the first layer further comprises: a fifth transistor connected to the second shared gate of the second transistor; as well as A sixth transistor is connected to the first shared gate of the first transistor. 5 . The semiconductor device according to claim 4 , wherein a gate of the fifth transistor and a gate of the sixth transistor are connected to a word line. 6 . The semiconductor device according to claim 4 , wherein the first dummy gate is disposed above the gate of the fifth transistor, and the second dummy gate is disposed above the gate of the sixth transistor.

7. The semiconductor device according to claim 4, wherein the fifth transistor and the sixth transistor are transfer gate transistors.

8. The semiconductor device according to claim 1, further comprising: a first active region connected to the first shared gate and the second shared gate, and a second active region connected to the third shared gate and the fourth shared gate, The first active region and the second active region are separated by a second dielectric material disposed between the first active region and the second active region. 9 . The semiconductor device of claim 4 , wherein the third dielectric material is further disposed between the gate of the fifth transistor and the second shared gate, and between the gate of the sixth transistor and the first shared gate.

10. The semiconductor device according to claim 4, wherein the first shared contact is provided in the first layer between the source of the fifth transistor and the first shared gate of the first transistor, and The second shared contact is arranged in the first layer between the source of the sixth transistor and the second shared gate of the second transistor.

11. The semiconductor device of claim 4, wherein the fifth transistor is connected to a bit line and the sixth transistor is connected to a complementary bit line.

12. The semiconductor device according to claim 8, wherein a fourth dielectric material is disposed on a portion of the first dummy gate, the fourth shared gate, and the third dielectric material, and The fourth dielectric material is disposed on a portion of the second dummy gate, the third shared gate, and the third dielectric material.

13. A method for manufacturing a three-dimensional stacked static random access memory, the method comprising: providing a first metal gate as a first layer; providing a second metal gate as a second layer, the second layer being disposed above the first layer and including a first shared contact in the second layer; performing a gate cut through the first metal gate and the second metal gate to form a second groove, and filling the second groove with a second dielectric material, thereby cutting the second metal gate into a separated first dummy gate and a first gate; removing a portion of the first dummy gate adjacent to the first gate to form a first groove; filling the first groove with a first dielectric material; and providing a cross-link contact on a portion of the first dielectric material and the first gate, The first shared contact is at one side of the first dummy gate, and the cross-connection contact is disposed over the first dielectric material and the first gate so as to electrically connect only the first gate and the first shared contact.

14. The method of claim 13, wherein performing the gate cutting through the first metal gate and the second metal gate comprises: A portion of the first metal gate and the second metal gate is removed to form the second groove passing through the first metal gate and the second metal gate.

15. The method of claim 13, wherein the method further comprises: providing a substrate layer disposed below the first layer, wherein the substrate layer includes a first active region connected to the first metal gate and a second active region connected to the second metal gate, and The first active region and the second active region are separated by a third dielectric material.

16. The method of claim 13, further comprising: A fourth dielectric material is provided over the second metal gate and the first dielectric material.

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