Semiconductor device and data storage system including semiconductor device

Abstract

A semiconductor device and a data storage system including the semiconductor device are provided. The semiconductor device includes a substrate having a first region and a second region; gate electrodes stacked in a first direction on the first region, and each including a pad region having an upper surface exposed upward in the second region; a channel structure penetrating the gate electrodes and extending in the first direction; a separation region penetrating the gate electrodes and extending in a second direction; contact plugs each penetrating the pad region of each of the gate electrodes and extending in the first direction; a nitride layer disposed in an outer side of a lowermost first gate electrode among the gate electrodes, spaced apart from the lowermost first gate electrode, and extending horizontally; and a dummy gate electrode disposed between the lowermost first gate electrode and the nitride layer in the second direction and having a first end portion spaced apart from the lowermost first gate electrode.

Description

[0001] Korean Patent Application No. 10-2021-0006784, entitled "Semiconductor Device and Data Storage System Including Semiconductor Device", filed on January 18, 2021, with the Korean Intellectual Property Office, is incorporated herein by reference in its entirety. Technical Field

[0002] The example embodiment relates to a semiconductor device and a data storage system including the semiconductor device. Background Technology

[0003] There is a demand for semiconductor devices capable of storing high-capacity (large-capacity) data in data storage systems. Therefore, measures to increase the data storage capacity of semiconductor devices have been researched. For example, as one method to increase the data storage capacity of semiconductor devices, semiconductor devices comprising three-dimensional memory cells instead of two-dimensional memory cells have been proposed. Summary of the Invention

[0004] The embodiment relates to a semiconductor device, the semiconductor device including a first semiconductor structure and a second semiconductor structure, the first semiconductor structure including a first substrate and circuit devices on the first substrate, the second semiconductor structure disposed on the first semiconductor structure, wherein the second semiconductor structure includes: a second substrate having a first region and a second region; gate electrodes stacked and spaced apart from each other in a first direction in the first region and extending to different lengths in a second direction in the second region, and each gate electrode including a pad region having an upwardly exposed upper surface in the second region; interlayer insulating layers stacked alternately with the gate electrodes; channel structures penetrating the gate electrodes and extending in the first direction, and each channel structure including a channel layer; and separation regions in the first region and The second region penetrates the gate electrode and extends in a second direction; contact plugs, each contact plug penetrating the pad region of each gate electrode in the gate electrode and extending in a first direction into the first semiconductor structure; a first contact plug insulating layer disposed alternately with an interlayer insulating layer below the pad region and surrounding each contact plug in the contact plugs; a through plug extending in a first direction in a third region on the outer side of the second substrate to electrically connect the first semiconductor structure to the second semiconductor structure; a first through plug insulating layer surrounding the through plug at a level lower than the level of the upper surface of the lowermost first gate electrode in the gate electrode; and a first nitride layer contacting the outer surface of the first through plug insulating layer and extending horizontally in the third region.

[0005] The embodiment relates to a semiconductor device, the semiconductor device comprising: a substrate having a first region and a second region; gate electrodes stacked and spaced apart from each other in a first direction in the first region and extending to different lengths in a second direction in the second region, each gate electrode including a pad region having an upwardly exposed upper surface in the second region; a channel structure penetrating the gate electrodes, extending in the first direction, and each channel structure including a channel layer; a separation region penetrating the gate electrodes in the first and second regions and extending in the second direction; contact plugs, each contact plug penetrating the pad region of each gate electrode in the gate electrodes and extending in the first direction; a nitride layer disposed outside the lowermost first gate electrode among the gate electrodes, spaced apart from the lowermost first gate electrode, and extending horizontally; and a dummy gate electrode disposed in the second direction between the lowermost first gate electrode and the nitride layer, and having a first end spaced apart from the lowermost first gate electrode.

[0006] The embodiment relates to a data storage system including a semiconductor memory device and a controller. The semiconductor memory device includes: a first substrate; circuitry on the first substrate; a second substrate having a first region and a second region; gate electrodes stacked and spaced apart from each other in a first direction in the first region and extending to different lengths in a second direction in the second region, each gate electrode including a pad region having an upwardly exposed upper surface in the second region; a channel structure penetrating the gate electrodes and extending in the first direction, each channel structure including a channel layer; a separation region penetrating the gate electrodes in the first and second regions and extending in the second direction; contact plugs, each contact plug penetrating the pad region of each gate electrode and extending in the first direction; a nitride layer disposed outside the lowermost first gate electrode, spaced apart from the lowermost first gate electrode, and extending horizontally; a dummy gate electrode disposed in the second direction between the lowermost first gate electrode and the nitride layer, and having a first end spaced apart from the lowermost first gate electrode; and an input / output pad electrically connected to the circuitry, the controller being electrically connected to the semiconductor memory device via the input / output pad and configured to control the semiconductor memory device. Attached Figure Description

[0007] The features will become clear to those skilled in the art from the detailed description of exemplary embodiments with reference to the accompanying drawings, in which:

[0008] Figure 1 This is a layout diagram illustrating a semiconductor device according to an example embodiment;

[0009] Figure 2 This is a plan view illustrating a semiconductor device according to an example embodiment;

[0010] Figure 3A and Figure 3B This is a cross-sectional view showing a semiconductor device according to an example embodiment;

[0011] Figures 4A to 4C This is an enlarged view showing a portion of a semiconductor device according to an example embodiment;

[0012] Figure 5A and Figure 5B This is an enlarged perspective view showing a portion of a semiconductor device according to an example embodiment;

[0013] Figure 6 This is an enlarged perspective view showing a portion of a semiconductor device according to an example embodiment;

[0014] Figure 7A This is a cross-sectional view showing a semiconductor device according to an example embodiment. Figure 7B This is an enlarged view showing a portion of a semiconductor device according to an example embodiment;

[0015] Figure 8 This is an enlarged view showing a portion of a semiconductor device according to an example embodiment;

[0016] Figure 9 This is a cross-sectional view showing a semiconductor device according to an example embodiment;

[0017] Figure 10 This is a cross-sectional view showing a semiconductor device according to an example embodiment;

[0018] Figure 11 This is a cross-sectional view showing a semiconductor device according to an example embodiment;

[0019] Figure 12 This is a cross-sectional view showing a semiconductor device according to an example embodiment;

[0020] Figures 13A to 13K This is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an example embodiment;

[0021] Figure 14 This is a view illustrating a data storage system including a semiconductor device according to an example embodiment;

[0022] Figure 15 This is a perspective view illustrating a data storage system including a semiconductor device according to an example embodiment; and

[0023] Figure 16 This is a cross-sectional view showing a semiconductor device according to an example embodiment. Detailed Implementation

[0024] Figure 1This is a layout diagram illustrating a semiconductor device according to an example embodiment.

[0025] Reference Figure 1 The semiconductor device 10 may include a first semiconductor structure S1 and a second semiconductor structure S2 stacked in a vertical direction. The first semiconductor structure S1 may be configured as a peripheral circuit structure and may include a row decoder DEC, a page buffer PB, and other peripheral circuits PC. The second semiconductor structure S2 may be configured as a memory cell structure and may include a memory cell array MCA, a first through-interconnect region TR1, and a second through-interconnect region TR2.

[0026] In the first semiconductor structure S1, the row decoder DEC generates and sends word line drive signals by decoding the input address. The page buffer PB is connected to the memory cell array MCA via bit lines and can read data stored in the memory cells. Other peripheral circuitry PC can be configured as a region including control logic and voltage generators, and may include, for example, latch circuitry, cache circuitry, and / or sense amplifiers. The first region R1 may also include a pad region. In this case, the pad region may include electrostatic discharge (ESD) devices or data input / output circuitry.

[0027] At least a portion of the various circuit regions (such as the row decoder DEC, page buffer PB, and other peripheral circuits PC) in the first semiconductor structure S1 can be disposed below the memory cell array MCA of the second semiconductor structure S2. For example, the page buffer PB and / or other peripheral circuits PC can be disposed below the memory cell array MCA to be superimposed on the memory cell array MCA. However, the circuits included in the first semiconductor structure S1 and their arrangement can vary, and therefore, the circuits superimposed on the memory cell array MCA can also vary.

[0028] The second semiconductor structure S2 may have a first region R1, a second region R2, and a third region R3. The first region R1 and the second region R2 may be configured such that a substrate can be disposed therein so that a memory cell array (MCA) can be disposed. The third region R3 may be configured as a region on the outer side of the substrate. The first region R1 may be configured such that memory cells are disposed therein. The second region R2 may be configured such that word lines are electrically connected to circuitry regions (such as a row decoder (DEC), a page buffer (PB), and other peripheral circuitry (PC)) of the first semiconductor structure S1.

[0029] In the second semiconductor structure S2, the memory cell array MCA can be configured to be spaced apart from each other. Figure 1In the example embodiment, four memory cell arrays (MCAs) are provided, but in the example embodiment, the number and arrangement of the memory cell arrays (MCAs) provided on the second semiconductor structure S2 can be varied.

[0030] The first through-interconnect region TR1 and the second through-interconnect region TR2 may include interconnect structures that penetrate the second semiconductor structure S2 and connect to the first semiconductor structure S1. The first through-interconnect region TR1 may be disposed in the memory cell array MCA in the first region R1 at predetermined intervals. For example, the first through-interconnect region TR1 may include an interconnect structure electrically connected to the page buffer PB of the first semiconductor structure S1. The second through-interconnect region TR2 may be disposed in at least one edge region of the memory cell array MCA in the second region R2, and may include interconnect structures (such as contact plugs electrically connected to the row decoder DEC of the first semiconductor structure S1). The number of second through-interconnect regions TR2 may be greater than the number of first through-interconnect regions TR1, but in example embodiments, the shape, number, and position of the first through-interconnect regions TR1 and the second through-interconnect regions TR2 may vary.

[0031] In the second semiconductor structure S2, the nitride layer NL can be retained in the third region R3 within the cell region insulating layer 190 (see...). Figure 3A The neutral / or unit region insulation layer 190 is located below. The nitride layer NL may be retained in the outer edge region of the second region R2, which contacts the third region R3. (See below for reference.) Figures 2 to 3B The construction will be described in more detail.

[0032] Figure 2 This is a plan view illustrating a semiconductor device according to an example embodiment. Figure 3A and Figure 3B This is a cross-sectional view showing a semiconductor device according to an example embodiment. Figure 3A It is along Figure 2 The sectional view taken by line I-I' in the middle. Figure 3B It is along Figure 2 The sectional view taken from line II-II' in the middle. Figures 4A to 4C This is an enlarged view showing a portion of a semiconductor device according to an example embodiment. Figure 4A It is shown Figure 3A A magnified view of region "A" in the image. Figure 4B It is shown Figure 3A A magnified view of region "B" in the image. Figure 4C It is shown Figure 3A An enlarged view of region "C" in the image.

[0033] Reference Figures 2 to 3BThe semiconductor device 100 may include a peripheral circuit region (PERI) and a memory cell region (CELL). The PERI may be a first semiconductor structure including a first substrate 201, and the CELL may be a second semiconductor structure including a second substrate 101. The CELL may be disposed above the PERI. In another embodiment, in an example embodiment, the CELL may be disposed below the PERI.

[0034] The peripheral circuit region PERI may include a first substrate 201, a source / drain region 205 and a device separation layer 210 in the first substrate 201, circuit devices 220 disposed on the first substrate 201, circuit contact plugs 270, circuit interconnects 280 and peripheral region insulating layer 290.

[0035] The first substrate 201 may have an upper surface extending in both the X and Y directions. An active region may be defined on the first substrate 201 by a device separation layer 210. Source / drain regions 205, including impurities, may be disposed within a portion of the active region. The first substrate 201 may comprise a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. The first substrate 201 may be configured as a bulk wafer or an epitaxial layer.

[0036] Circuit device 220 may include planar transistors. Each of circuit devices 220 may include a circuit gate dielectric layer 222, a spacer layer 224, and a circuit gate electrode 225. Source / drain regions 205 may be disposed on both sides of the circuit gate electrode 225 in the first substrate 201.

[0037] A peripheral region insulating layer 290 may be disposed on the circuit device 220 on the first substrate 201. A circuit contact plug 270 may penetrate the peripheral region insulating layer 290 and may be connected to the source / drain region 205. Electrical signals may be applied to the circuit device 220 through the circuit contact plug 270. In an area not shown, the circuit contact plug 270 may also be connected to the circuit gate electrode 225. Circuit interconnects 280 may be connected to the circuit contact plug 270 and may be configured in multiple layers.

[0038] The memory cell region CELL may include a second substrate 101 having a first region R1 and a second region R2, a gate electrode 130 stacked on the second substrate 101, an interlayer insulating layer 120 stacked alternately with the gate electrode 130, a channel structure CH configured to penetrate the stacked structure of the gate electrode 130, a first separation region MS1 ​​and a second separation region MS2 extending through the stacked structure of the gate electrode 130, a contact plug 170 extending through the gate electrode 130 in the second region R2, and a through plug 175 disposed in a third region R3 disposed on the outside of the second substrate 101.

[0039] The memory cell region (CELL) may also include a first contact plug insulating layer 160 and a second contact plug insulating layer 165 surrounding the contact plug 170, a first through plug insulating layer 180 and a second through plug insulating layer 185 surrounding the through plug 175, a first nitride layer 150L and a second nitride layer 150U respectively in contact with the first through plug insulating layer 180 and the second through plug insulating layer 185, and a first dummy gate electrode 131D and a second dummy gate electrode 132D.

[0040] The memory cell region CELL may include a first horizontal conductive layer 102 on a first region R1, a horizontal insulating layer 110 disposed on a second region R2 parallel to the first horizontal conductive layer 102, a second horizontal conductive layer 104 on the first horizontal conductive layer 102 and the horizontal insulating layer 110, a base insulating layer 121 penetrating the second substrate 101, an upper separation region SS penetrating a portion of the stacked structure of the gate electrode 130, a dummy channel structure DCH configured to penetrate the stacked structure of the gate electrode 130 in the second region R2, a cell region insulating layer 190, and a cell interconnect 195.

[0041] The first region R1 of the second substrate 101 can be configured such that gate electrodes 130 can be vertically stacked and a channel structure CH can be provided, and memory cells can be disposed in the first region R1. The second region R2 can be configured such that the gate electrodes 130 can extend to different lengths, and can be configured to electrically connect the memory cells to the peripheral circuit region PERI. The second region R2 can be disposed on at least one end of the first region R1 in at least one direction (e.g., in the X direction).

[0042] The second substrate 101 may have an upper surface extending in both the X and Y directions. The second substrate 101 may include a semiconductor material, such as a group IV semiconductor, a group III-V compound semiconductor, or a group II-VI compound semiconductor. For example, a group IV semiconductor may include silicon, germanium, or silicon-germanium. The second substrate 101 may also include impurities. The second substrate 101 may be configured as a polycrystalline semiconductor layer or an epitaxial layer, such as a polycrystalline silicon layer.

[0043] The first horizontal conductive layer 102 and the second horizontal conductive layer 104 may be stacked sequentially on the upper surface of the first region R1 of the second substrate 101. The first horizontal conductive layer 102 may not extend to the second region R2 of the second substrate 101. The second horizontal conductive layer 104 may extend to the second region R2.

[0044] The first horizontal conductive layer 102 can be used as part of the common source line of the semiconductor device 100, and can be used as the common source line together with the second substrate 101, for example. (Refer to...) Figure 3B In the enlarged view, the first horizontal conductive layer 102 can be directly connected to the channel layer 140 around the channel layer 140.

[0045] The second horizontal conductive layer 104 may contact the second substrate 101 in a region where the first horizontal conductive layer 102 and the horizontal insulating layer 110 are not disposed. The second horizontal conductive layer 104 may be bent in this region to cover the ends of the first horizontal conductive layer 102 and / or the ends of the horizontal insulating layer 110, and may extend onto the second substrate 101.

[0046] The first horizontal conductive layer 102 and the second horizontal conductive layer 104 may comprise semiconductor materials. For example, both the first horizontal conductive layer 102 and the second horizontal conductive layer 104 may comprise polycrystalline silicon. In this case, at least the first horizontal conductive layer 102 may be a doped layer, and the second horizontal conductive layer 104 may be a doped layer or a layer comprising impurities diffused from the first horizontal conductive layer 102. However, the second horizontal conductive layer 104 may be replaced with an insulating layer.

[0047] The horizontal insulating layer 110 may be disposed side-by-side with the first horizontal conductive layer 102 on the second substrate 101 in at least a portion of the second region R2. The horizontal insulating layer 110 may include a first horizontal insulating layer 111 and a second horizontal insulating layer 112 alternately stacked on the second region R2 of the second substrate 101. The horizontal insulating layer 110 may be a layer that remains after a portion of it has been replaced by the first horizontal conductive layer 102 during the process of manufacturing the semiconductor device 100.

[0048] The horizontal insulating layer 110 may include silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride. The first horizontal insulating layer 111 and the second horizontal insulating layer 112 may include different insulating materials. For example, the first horizontal insulating layer 111 may be formed of the same material as the interlayer insulating layer 120, and the second horizontal insulating layer 112 may be formed of a different material than the interlayer insulating layer 120.

[0049] The substrate insulating layer 121 may extend in the Z direction and may penetrate the second substrate 101, the horizontal insulating layer 110, and the second horizontal conductive layer 104 in the second region R2. The substrate insulating layer 121 may be configured to surround each of the contact plugs 170. Thus, the contact plugs 170 connected to different gate electrodes 130 may be electrically isolated from each other. The substrate insulating layer 121 may also be disposed on a third region R3 (outside the second substrate 101). The substrate insulating layer 121 may include, for example, silicon oxide, silicon nitride, silicon carbide, or silicon oxynitride.

[0050] Gate electrodes 130 may be vertically stacked and spaced apart from each other on the second substrate 101, and may form a stacked structure. Gate electrodes 130 may include a lower gate electrode 130L forming the gate of a ground selection transistor, a memory gate electrode 130M forming the gate of a plurality of memory cells, and an upper gate electrode 130U forming the gate of a string selection transistor. The number of memory gate electrodes 130M forming the gate of the memory cells may be determined according to the capacity of the semiconductor device 100. In some example embodiments, the number of each of the upper gate electrode 130U and the lower gate electrode 130L may be 1 to 4 or greater, and may have the same structure as or different from the structure of the memory gate electrode 130M. In some example embodiments, gate electrodes 130 may also include gate electrodes 130 disposed above the upper gate electrode 130U and / or below the lower gate electrode 130L, and forming the gate of an erase transistor in an erase operation utilizing the gate-induced drain leakage (GIDL) phenomenon. Furthermore, a portion of the gate electrode 130 (e.g., the memory gate electrode 130M adjacent to the upper gate electrode 130U or the lower gate electrode 130L) may be a dummy gate electrode.

[0051] The gate electrodes 130 can be vertically stacked and spaced apart on the first region R1, and can extend to different lengths from the first region R1 to the second region R2, forming a stepped structure in a stepped shape. (Refer to...) Figure 3A The gate electrode 130 can form a stepped structure between the gate electrodes 130 in the X direction, and can also have a stepped structure in the Y direction.

[0052] Due to the stepped structure, the lower gate electrode 130 can extend longer than the upper gate electrode 130, such that the gate electrode 130 can have a region exposed upward from the interlayer insulating layer 120, and said region can be referred to as pad region 130P. In each of the gate electrodes 130, pad region 130P can include the end of the gate electrode in the X direction. Pad region 130P can correspond to a portion of the uppermost gate electrode 130 among the gate electrodes 130 that form a stacked structure (e.g., a corresponding stepped structure) in the second region R2 of the second substrate 101. The gate electrode 130 can be connected to the contact plug 170 in the pad region 130P.

[0053] The gate electrode 130 may have an increased thickness in the pad region 130P. The thickness of each of the gate electrodes 130 may be increased in such a way that the level (or "height") of its lower surface may be constant, while the level of its upper surface may be increased. (See reference...) Figure 4A The gate electrode 130 can extend from the first region R1 toward the second region R2 with a first thickness T1, and can be in the region R2. Figure 4A The pad region 130P, marked by the dashed line, has a second thickness T2 that is greater than the first thickness T1. The second thickness T2 can be in the range of about 150% to about 210% of the first thickness T1.

[0054] The gate electrodes 130 can be separated from each other in the Y direction by first separation regions MS1 extending in the X direction. The gate electrodes 130 between a pair of first separation regions MS1 can form a memory block, but the scope of the memory block is not limited thereto. For example, the gate electrodes 130 can include a metallic material such as tungsten (W). In some example embodiments, the gate electrodes 130 can include polycrystalline silicon or metal silicide materials.

[0055] Interlayer insulating layers 120 may be disposed between gate electrodes 130. Similar to gate electrodes 130, interlayer insulating layers 120 may be spaced apart from each other in a direction perpendicular to the upper surface of the second substrate 101 and may extend in the X direction. Interlayer insulating layers 120 may comprise insulating materials such as silicon oxide or silicon nitride.

[0056] The first separation region MS1 ​​and the second separation region MS2 can be configured to penetrate the gate electrode 130 and can extend in the X direction. The first separation region MS1 ​​and the second separation region MS2 can be arranged parallel to each other. The first separation region MS1 ​​and the second separation region MS2 can penetrate the entire gate electrode 130 stacked on the second substrate 101 and can be connected to (e.g., extended to) the second substrate 101. The first separation region MS1 ​​can extend as a single region in the X direction, and the second separation region MS2 can extend intermittently between a pair of first separation regions MS1 or can be provided only in a portion of the region. However, the arrangement order and number of the first separation regions MS1 and the second separation regions MS2 are not limited to... Figure 2 The example shown. (Refer to...) Figure 3B The separation insulating layer 105 can be disposed in the first separation region MS1 ​​and the second separation region MS2. For example, the separation insulating layer 105 may include insulating materials such as silicon oxide, silicon nitride, and silicon oxynitride.

[0057] Reference Figure 2The upper separation region SS can extend in the X direction within the first region R1, between the first separation region MS1 ​​and the second separation region MS2. (Refer to...) Figure 3B The upper separation region SS can separate the three gate electrodes 130, including the upper gate electrode 130U, from each other in the Y direction. However, in the example embodiment, the number of gate electrodes 130 separated by the upper separation region SS can vary. The upper gate electrodes 130U separated by the upper separation region SS can form different string select lines. An upper separation insulating layer 103 can be disposed in the upper separation region SS. For example, the upper separation insulating layer 103 can include an insulating material such as silicon oxide, silicon nitride, or silicon oxynitride.

[0058] Reference Figure 2 Each channel structure CH can form a single memory cell string, and can be spaced apart from each other and can form rows and columns on a first region R1. The channel structure CH can be configured to form a grid pattern, or it can be configured in a zigzag pattern in one direction. The channel structure CH can have a cylindrical shape and can have sloping side surfaces depending on the aspect ratio, the sloping side surfaces having a width that decreases toward the second substrate 101.

[0059] for Figure 3A In the example embodiment shown, the channel structure CH may include a first channel structure CH1 and a second channel structure CH2 stacked vertically. In the channel structure CH, the first channel structure CH1, which penetrates the lower stacked structure of the gate electrode 130, may be connected to the second channel structure CH2, which penetrates the upper stacked structure of the gate electrode 130, and may have a curved portion in the connection region due to width differences. However, the number of channel structures stacked in the Z direction may vary.

[0060] Reference Figure 3B The enlarged view shows that the channel layer 140 can be disposed in the channel structure CH. In the channel structure CH, the channel layer 140 can be formed in an annular shape with the channel-filling insulating layer 147 surrounding it. The channel layer 140 can be connected to the first horizontal conductive layer 102 at the bottom. The channel layer 140 can include a semiconductor material such as polycrystalline silicon or monocrystalline silicon.

[0061] A gate dielectric layer 145 may be disposed between the gate electrode 130 and the channel layer 140. Although not specifically shown, the gate dielectric layer 145 may include a tunneling layer, a charge storage layer, and a barrier layer stacked sequentially from the channel layer 140. The tunneling layer can tunnel charge to the charge storage layer and may include, for example, silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), or combinations thereof. The charge storage layer may be a charge trapping layer or a floating gate conductive layer. The barrier layer may include silicon oxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), a high-k dielectric material, or combinations thereof. In some example embodiments, at least a portion of the gate dielectric layer 145 may extend horizontally along the gate electrode 130. A channel pad 149 may be disposed only on the upper end of the second channel structure CH2. The channel pad 149 may include, for example, doped polysilicon.

[0062] The channel layer 140, gate dielectric layer 145, and channel-filling insulating layer 147 can be interconnected between the first channel structure CH1 and the second channel structure CH2. An upper interlayer insulating layer 125 with a relatively large thickness can be disposed between the first channel structure CH1 and the second channel structure CH2, that is, between the lower stack structure and the upper stack structure. However, the shapes of the interlayer insulating layer 120 and the upper interlayer insulating layer 125 can vary.

[0063] The dummy channel structures (DCHs) can be spaced apart from each other and can form rows and columns in the second region R2. In a plan view, the dummy channel structures (DCHs) can have a larger size than the channel structures (CHs), but the example embodiment is not limited to this. The dummy channel structures (DCHs) can also be located in the portion of the first region R1 adjacent to the second region R2. Unlike the channel structures (CHs), the dummy channel structures (DCHs) may not be electrically connected to the upper interconnect structure and may not form a string of memory cells in the semiconductor device 100.

[0064] The dummy channel structure DCH can have the same structure as the channel structure CH or a different structure. When the dummy channel structure DCH is formed together with the channel structure CH, the dummy channel structure DCH can have the same structure as the channel structure CH. When the dummy channel structure DCH is formed as part of the process for forming contact plug 170, the dummy channel structure DCH can have a different structure from the channel structure CH. In this case, for example, the dummy channel structure DCH can have a structure filled with an insulating material (such as oxide).

[0065] Contact plug 170 can penetrate the uppermost gate electrode 130 and the first contact plug insulating layer 160 disposed below the uppermost gate electrode 130 in the second region R2, and can be connected to the pad region 130P of the gate electrode 130. Contact plug 170 can penetrate at least a portion of the cell region insulating layer 190, and can be connected to each of the upwardly exposed pad regions 130P of the gate electrode 130. Contact plug 170 can penetrate the second substrate 101, the second horizontal conductive layer 104, and the horizontal insulating layer 110 below the gate electrode 130, and can be connected to the circuit interconnect 280 in the peripheral circuit region PERI. Contact plug 170 can be spaced apart from the second substrate 101, the second horizontal conductive layer 104, and the horizontal insulating layer 110 by the substrate insulating layer 121.

[0066] Reference Figure 4A Each of the contact plugs 170 may include a vertical extension 170V extending in the Z direction and a horizontal extension 170H extending horizontally from the vertical extension 170V and contacting the pad region 130P. Due to its aspect ratio, the vertical extension 170V may have a cylindrical shape in which its width decreases toward the second substrate 101. The horizontal extension 170H may be disposed along the circumference of the vertical extension 170V and may extend a first length L1 from the side surface of the vertical extension 170V to the other end. The first length L1 may be shorter than the second length L2 of the underlying first contact plug insulation layer 160.

[0067] Reference Figure 4C The contact plug 170 may be surrounded by a substrate insulating layer 121 to electrically isolate it from the second substrate 101. The region including the lower end of the contact plug 170 may be surrounded by a pad 285 on the circuit interconnect 280. The pad 285 may be configured to protect the circuit interconnect 280 during the manufacturing process of the semiconductor device 100 and may include, for example, a conductive material such as polysilicon.

[0068] The contact plug 170 may include at least one of, for example, tungsten (W), copper (Cu), aluminum (Al), and alloys thereof. In some example embodiments, the contact plug 170 may also include a barrier layer on the sidewalls and bottom surface of the contact hole in which the contact plug 170 is disposed. The barrier layer may include at least one of, for example, titanium (Ti), titanium nitride (TiN), tantalum (Ta), and tantalum nitride (TaN).

[0069] A first contact plug insulating layer 160 may be disposed below the pad region 130P to surround the side surface of the contact plug 170. The inner surface of the first contact plug insulating layer 160 may surround the contact plug 170, and the outer surface of the first contact plug insulating layer 160 may be surrounded by the gate electrode 130. Each of the contact plugs 170 may be physically electrically connected to a single gate electrode 130 and may be electrically decoupled from the gate electrode 130 disposed below that single gate electrode 130 via the first contact plug insulating layer 160.

[0070] A second contact plug insulating layer 165 may be disposed above the pad region 130P to surround a portion of the side surface of the contact plug 170. For example, the second contact plug insulating layer 165 may be configured to surround the contact plug 170 connected to the gate electrode 130 of the lower stack structure. The gate electrode in the upper stack structure gate electrode 130 that is positioned most adjacent to the lower end of the second channel structure CH2 may be referred to as the second gate electrode 132. The second contact plug insulating layer 165 may be disposed at a level corresponding to or similar to the level of the second gate electrode 132. In the given example embodiment, "corresponding level" may refer to a level within a range in which a particular component is disposed. Therefore, the second contact plug insulating layer 165 may be disposed at a level that overlaps with the level on which the second gate electrode 132 is disposed, or at a level similar to the level on which the second gate electrode 132 is disposed. In the given example embodiment, the second contact plug insulating layer 165 may be disposed at a level that is horizontally stacked thereon on which the second gate electrode 132 is disposed, and may be disposed at a level lower than the level of the upper surface of the second gate electrode 132.

[0071] The first contact plug insulating layer 160 and the second contact plug insulating layer 165 may include insulating materials, and may include at least one of silicon oxide, silicon nitride and silicon oxynitride, for example.

[0072] The through-plug 175 can be disposed in a third region R3 of the memory cell region CELL (the third region R3 can be an outer region of the second substrate 101), and can penetrate the cell region insulating layer 190 and extend to the peripheral circuit region PERI. The through-plug 175 can be configured to connect the cell interconnect 195 of the memory cell region CELL to the circuit interconnect 280 of the peripheral circuit region PERI. The through-plug 175 can include a conductive material and can include metallic materials such as tungsten (W), copper (Cu), and aluminum (Al). The through-plug 175 can be formed in the same process as the contact plug 170, can include the same material, and can have the same internal structure.

[0073] The first through-plug insulating layer 180 and the second through-plug insulating layer 185 can be configured to surround the side surfaces of the through-plug 175 in the lower and upper portions, respectively. The first through-plug insulating layer 180 can be disposed in a region corresponding to the lower portion of the gate electrode 130. For example, the first through-plug insulating layer 180 can be disposed at a level corresponding to or similar to the level of the lowermost first gate electrode 131. In the given example embodiment, the first through-plug insulating layer 180 can be disposed at a level lower than the level of the upper surface of the first gate electrode 131.

[0074] The second through-hole plug insulating layer 185 may be disposed at a level substantially the same as the level of the second contact plug insulating layer 165. In the given example embodiments, "substantially the same" means either identical or an example of differences that may occur within the range of deviations in the manufacturing process, and can be interpreted in the same way even when the expression "substantially" is omitted. For example, the second through-hole plug insulating layer 185 may be disposed at a level corresponding to or similar to the level of the second gate electrode 132.

[0075] The first through-plug insulating layer 180 and the second through-plug insulating layer 185 may have substantially the same thickness and / or width, but the example embodiment is not limited thereto. The second through-plug insulating layer 185 may have a thickness substantially the same as that of the second contact plug insulating layer 165. The first through-plug insulating layer 180 and the second through-plug insulating layer 185 may include insulating materials, and may include at least one of, for example, silicon oxide, silicon nitride, and silicon oxynitride.

[0076] The first nitride layer 150L and the second nitride layer 150U can be referenced above. Figure 1 The nitride layer NL is described. The first nitride layer 150L and the second nitride layer 150U may extend parallel to the upper surface of the second substrate 101 in a portion of the second region R2 and in the third region R3. The first nitride layer 150L may contact the outer surface of the first through-hole insulating layer 180 and may extend horizontally along the XY plane at a level corresponding to the level of the first gate electrode 131. The second nitride layer 150U may contact the outer surface of the second through-hole insulating layer 185 and may extend horizontally along the XY plane at a level corresponding to the level of the second gate electrode 132. The first nitride layer 150L and the second nitride layer 150U may be deposited during the manufacturing process to thicken the pad region 130P of the gate electrode 130, and the first nitride layer 150L and the second nitride layer 150U may be retained.

[0077] Reference Figure 4BThe first nitride layer 150L may surround the first through-hole insulating layer 180 and may contact the side surface of the first dummy gate electrode 131D at the end adjacent to the second region R2. The first nitride layer 150L (e.g., its lower surface) may be disposed at a level higher than the level of the upper surface of the second substrate 101. The thickness T4 of the first nitride layer 150L may be substantially the same as the thickness T3 of the first dummy gate electrode 131D and the thickness T5 of the first through-hole insulating layer 180. The thickness T4 of the first nitride layer 150L may have a thickness smaller than the increased second thickness T2 of the first gate electrode 131 in the pad region 130P. For example, the thickness T4 of the first nitride layer 150L may be similar to that of a reference layer. Figure 4A The difference between the second thickness T2 and the first thickness T1 is the same or similar.

[0078] Similarly, the second nitride layer 150U may also surround the second through-hole insulating layer 185 and may contact the second dummy gate electrode 132D at the end adjacent to the second region R2. The second nitride layer 150U may have a thickness substantially the same as that of the first nitride layer 150L and may be described above in relation to the thickness T4 of the first nitride layer 150L.

[0079] The first nitride layer 150L and the second nitride layer 150U may include silicon nitride and may have Si. x N y or Si x N y :H components. (Refer to...) Figure 4B The first nitride layer 150L and the second nitride layer 150U may each comprise two layers 152 and 154 with different compositions and stacked vertically, but the example embodiment is not limited thereto. For example, the lower layer 152 may have a greater thickness than the upper layer 154 and may have a high hydrogen (H) content.

[0080] The first dummy gate electrode 131D and the second dummy gate electrode 132D can be respectively disposed at a level corresponding to the level of the first gate electrode 131 and a level corresponding to the level of the second gate electrode 132. The first dummy gate electrode 131D and the second dummy gate electrode 132D can be respectively configured to be spaced apart from the end of the first gate electrode 131 and the end of the second gate electrode 132 in the X direction by a predetermined distance. The distance can be, for example, about 50 nm or less. Therefore, the first dummy gate electrode 131D and the second dummy gate electrode 132D can be electrically isolated from the first gate electrode 131 and the second gate electrode 132, respectively.

[0081] The first dummy gate electrode 131D and the second dummy gate electrode 132D may each have a first end spaced apart from the end of the first gate electrode 131 and a first end spaced apart from the end of the second gate electrode 132, respectively, and may each have a second end contacting the first nitride layer 150L and a second end contacting the second nitride layer 150U, respectively. In the first dummy gate electrode 131D and the second dummy gate electrode 132D, the positions of the second ends may be the same or similar in the Z direction. The second dummy gate electrode 132D may contact the outer surface of the second contact plug insulating layer 165 and may surround the second contact plug insulating layer 165.

[0082] Reference Figure 2 The outer end of the first dummy gate electrode 131D may have a wavy shape along the end of the first separation region MS1 ​​and the end of the second separation region MS2 in a plan view, and may surround the end. The outer end of the second dummy gate electrode 132D may also be disposed above the outer end of the first dummy gate electrode 131D, and may have the same or similar shape as the first dummy gate electrode 131D.

[0083] The first dummy gate electrode 131D and the second dummy gate electrode 132D may have regions extending outward in the X direction, and extending further than the first separation region MS1 ​​and the second separation region MS2. In the wavy shape, since the first dummy gate electrode 131D and the second dummy gate electrode 132D are formed in regions where a portion of the first nitride layer 150L and the second nitride layer 150U can be removed, the first dummy gate electrode 131D and the second dummy gate electrode 132D may have a shape according to the contour of the etchant injected from the first separation region MS1 ​​and the second separation region MS2.

[0084] As shown above (refer to the reference) Figure 4B Described, the first dummy gate electrode 131D may have a thickness substantially the same as the thickness of the first nitride layer 150L and the thickness of the first through-hole insulating layer 180. The second dummy gate electrode 132D may have a thickness substantially the same as the thickness of the second contact plug insulating layer 165, the thickness of the second nitride layer 150L, ​​and the thickness of the second through-hole insulating layer 185. The first dummy gate electrode 131D and the second dummy gate electrode 132D may have a thickness smaller than the aforementioned first thickness T1 and second thickness T2 of the gate electrode 130 including the first gate electrode 131 and the second gate electrode 132. Furthermore, the first dummy gate electrode 131D and the second dummy gate electrode 132D may be formed of the same material as the gate electrode 130.

[0085] The unit region insulating layer 190 can be configured to cover the second substrate 101, the gate electrode 130 on the second substrate 101, and the peripheral region insulating layer 290. The unit region insulating layer 190 can be formed of an insulating material or can be formed of multiple insulating layers.

[0086] Cell interconnect 195 can form an upper interconnect structure electrically connected to memory cells in the memory cell region CELL. Cell interconnect 195 can connect to contact plug 170 and through plug 175, and can be electrically connected to gate electrode 130 and channel structure CH. In some example embodiments, the number of contact plugs and interconnects forming the upper interconnect structure can vary. Cell interconnect 195 can include metal, and can include, for example, tungsten (W), copper (Cu), aluminum (Al), etc.

[0087] Figure 5A and Figure 5B This is an enlarged perspective view showing a portion of a semiconductor device according to an example embodiment.

[0088] Figure 5A The arrangement of the contact plug 170 and the second dummy gate electrode 132D is shown. For example, Figure 5A A contact plug 170 is shown above the pad region 130P, connected to the gate electrode 130 of the lower stacked structure surrounding the lower first channel structure CH1. The contact plug 170 may be surrounded by a second contact plug insulating layer 165, and the second contact plug insulating layer 165 may be surrounded by a second dummy gate electrode 132D.

[0089] Figure 5B The arrangement of the through-plug 175, the first nitride layer 150L, ​​and the second nitride layer 150U is shown. The through-plug 175 may be surrounded in the lower portion by the first through-plug insulation layer 180, and the first through-plug insulation layer 180 may be surrounded by the first nitride layer 150L. The through-plug 175 may be surrounded in the upper portion by the second through-plug insulation layer 185, and the second through-plug insulation layer 185 may be surrounded by the second nitride layer 150U.

[0090] When comparing contact plug 170 and through plug 175, both elements can be surrounded by an insulating layer, but the layers disposed on the outside of the insulating layer can be different. For example, in contact plug 170, a second dummy gate electrode 132D, which may be a conductive material, can be disposed on the outside of the second contact plug insulating layer 165. In through plug 175, a first nitride layer 150L and a second nitride layer 150U, which may be insulating materials, can be disposed on the outside of the first through plug insulating layer 180 and the second through plug insulating layer 185.

[0091] Figure 6This is an enlarged perspective view showing a portion of a semiconductor device according to an example embodiment.

[0092] Figure 6 It shows the setting with Figure 3A The first gate electrode 131 corresponds to a horizontally positioned portion of the assembly. The first gate electrode 131 may be separated from each other in the Y direction by a first separation region MS1 ​​and a second separation region MS2 in a region including its ends. A first dummy gate electrode 131D may be spaced apart from the first gate electrode 131 and may be a single layer. The first dummy gate electrode 131D may have regions surrounding the ends of the first separation region MS1 ​​and the second separation region MS2, and may have a semi-circular or wavy shape along the ends. A first nitride layer 150L may contact the wavy side surface of the first dummy gate electrode 131D and may extend horizontally. The first nitride layer 150L and the first dummy gate electrode 131D may have a thickness smaller than that of the first gate electrode 131.

[0093] The through-hole plug 175 can penetrate the first nitride layer 150L and can be spaced apart from the first nitride layer 150L by the first through-hole plug insulating layer 180.

[0094] Figure 7A This is a cross-sectional view showing a semiconductor device according to an example embodiment. Figure 7B This is an enlarged view showing a portion of a semiconductor device according to an example embodiment. Figure 7B It is shown Figure 7A An enlarged view of region "B" in the image.

[0095] Reference Figure 7A and Figure 7B In the semiconductor device 100a, the first nitride layer 150L and the second nitride layer 150U disposed thereon are horizontally compatible with... Figure 3A The example embodiments differ from those in the examples. Therefore, the levels of the first dummy gate electrode 131D, the second dummy gate electrode 132D, the second contact plug insulating layer 165, the first through plug insulating layer 180, and the second through plug insulating layer 185 can also be the same as those in the examples. Figure 3A The example implementations are different from those in the text.

[0096] Reference Figure 7A and Figure 7B The first nitride layer 150L can be disposed at a level lower than the lower surface of the first gate electrode 131. The first nitride layer 150L can be configured not to overlap with the first gate electrode 131 in the X direction. For example, the first nitride layer 150L can be configured to contact the upper surface of the second horizontal conductive layer 104 and the upper surface of the substrate insulating layer 121. (Refer to the following...) Figure 13BThe structure described above can be formed when the bottommost interlayer insulating layer 120 is removed from the outside of the sacrificial insulating layer 118 during the process of etching the sacrificial insulating layer 118.

[0097] However, the bottommost interlayer insulation layer 120 may not be completely removed and can be retained with a relatively small thickness. In this case, with Figure 3A Unlike the example embodiments shown, the lower surface of the first nitride layer 150L may not be coplanar with the lower surface of the first gate electrode 131, and may be disposed at a level lower than the level of the lower surface of the first gate electrode 131. According to the example embodiment, unlike the illustrated and given example embodiments, the upper surface of the first nitride layer 150L may be disposed at a level higher than the level of the lower surface of the first gate electrode 131.

[0098] Similarly, the second nitride layer 150U can be disposed at a level lower than the levels of the upper and lower surfaces of the second gate electrode 132. The second nitride layer 150U can be configured so as not to overlap with the second gate electrode 132 in the X direction. For example, the second nitride layer 150U can be disposed within the cell region insulating layer 190. However, a portion of the interlayer insulating layer 120 can also be described as belonging to the cell region insulating layer 190, and the boundary between the interlayer insulating layer 120 and the cell region insulating layer 190 can vary. Furthermore, in the example embodiment, with... Figure 3A Unlike the example embodiment, the lower surface of the second nitride layer 150U may not be coplanar with the lower surface of the second gate electrode 132, and may be disposed at a level lower than the level of the lower surface of the second gate electrode 132. Also unlike the example embodiment, the upper surface of the second nitride layer 150U may be disposed at a level higher than the level of the lower surface of the second gate electrode 132.

[0099] As described above, in the exemplary embodiment, the first nitride layer 150L and the second nitride layer 150U can be disposed at a level corresponding to or lower than the level of each of the first gate electrode 131 and the second gate electrode 132, and the specific arrangement level can vary. Furthermore, in the exemplary embodiment, the relative horizontal relationship between the first nitride layer 150L and the first gate electrode 131 can differ from the relative horizontal relationship between the second nitride layer 150U and the second gate electrode 132. When the level of the first nitride layer 150L changes, the levels of the first dummy gate electrode 131D and the first through-hole insulating layer 180 can also change. When the level of the second nitride layer 150U changes, the levels of the second dummy gate electrode 132D, the second contact plug insulating layer 165, and the second through-hole insulating layer 185 can also change.

[0100] Figure 8This is an enlarged view showing a portion of a semiconductor device according to an example embodiment, and illustrates the relationship with... Figure 3B The region corresponding to region "D" in the diagram.

[0101] Reference Figure 8 In semiconductor device 100b, with Figure 3A and Figure 3B Unlike the example embodiments described above, the memory cell region CELL may not include the first horizontal conductive layer 102 and the second horizontal conductive layer 104 on the second substrate 101. Furthermore, the channel structure CHb may also include an epitaxial layer 107.

[0102] The epitaxial layer 107 can be disposed on the second substrate 101 at the lower end of the channel structure CHb, and can be disposed on the side surface of at least one gate electrode 130. The epitaxial layer 107 can be disposed in a recessed region of the second substrate 101. The level of the lower surface of the epitaxial layer 107 can be higher than the level of the upper surface of the lowermost lower gate electrode 130L, and can be lower than the level of the lower surface of the lower gate electrode 130L disposed above the lowermost lower gate electrode 130L, but the exemplary embodiment is not limited thereto. The epitaxial layer 107 can be connected to the channel layer 140 through its upper surface. A gate insulating layer 141 can also be disposed between the lower gate electrode 130L and the epitaxial layer 107.

[0103] Figure 9 This is a cross-sectional view showing a semiconductor device according to an example embodiment.

[0104] Reference Figure 9 In semiconductor device 100c, with Figure 3A Unlike the example embodiments described, the second nitride layer 150U, the second dummy gate electrode 132D, the second contact plug insulating layer 165, and the second through plug insulating layer 185 may not be provided. Furthermore, the channel structure CHc may have a gradually changing width, rather than a top-and-bottom connection.

[0105] The channel structure CHc in the given example embodiment can be etched in a single process. Figure 13B and Figure 13E The sacrificial insulating layer 118 is formed by the entire lower and upper stacked structures. Therefore, the nitride layer forming the sacrificial pad region 118P can be formed by a single process instead of multiple separate processes. Therefore, since the second nitride layer 150U is not formed separately, the second dummy gate electrode 132D, the second contact plug insulating layer 165, and the second through plug insulating layer 185 do not need to be formed. However, even in this case, the first nitride layer 150L, ​​the first dummy gate electrode 131D, and the first through plug insulating layer 180 can be disposed at a level corresponding to or similar to the level of the first gate electrode 131.

[0106] Figure 10 This is a cross-sectional view showing a semiconductor device according to an example embodiment.

[0107] Reference Figure 10 In semiconductor device 100d, with Figure 3A Unlike the example embodiments described, the first and second through-plug insulating layers 180 and 185 surrounding the through plug 175 may not be provided. The through plug 175 can penetrate the first nitride layer 150L and the second nitride layer 150U, as well as the unit region insulating layer 190, and may include a region surrounded by the first nitride layer 150L and the second nitride layer 150U. This structure can be manufactured by forming the through plug 175 in a process separate from the process of forming the contact plug 170. Therefore, even in this case, a portion of the contact plug 170 may have a region surrounded by the second contact plug insulating layer 165.

[0108] Figure 11 This is a cross-sectional view showing a semiconductor device according to an example embodiment.

[0109] Reference Figure 11 In the semiconductor device 100e, the memory cell region CELL may further include a through interconnect region TR. The through interconnect region TR may correspond to Figure 1 The second through-interconnect region TR2 in the memory cell region 130U can have the same or similar structure as the first through-interconnect region TR1. In addition to the first through-plug 175A, the memory cell region CELL can also include a second through-plug 175B disposed in the through-interconnect region TR. Furthermore, the second contact plug 170B connected to the upper gate electrode 130U can have a shape different from that of the other first contact plugs 170A.

[0110] The through-interconnect region TR may include a second through-plug 175B extending from the top of the memory cell region CELL through the second substrate 101 and in the Z direction. The second through-plug 175B may have the same shape as the first through-plug 175A and may not be connected to the gate electrode 130. The entire gate electrode 130 may be disposed in the through-interconnect region TR up to the uppermost gate electrode 130U, and the uppermost gate electrode 130U may not have a pad region 130P in the through-interconnect region TR. Therefore, the uppermost gate electrode 130U may not have an increased thickness. The second through-plug 175B may be separable from the gate electrode 130 through a first contact plug insulating layer 160. The through-interconnect region TR may be formed by performing a process during the manufacturing process to prevent the retention of the second nitride layer 150U. However, the second nitride layer 150U may not be removed by a separate process and may be removed together with a layer used to stop etching when forming the step portion.

[0111] Unlike the first contact plug 170A, the second contact plug 170B may be configured to connect to the upper gate electrode 130U in the pad region 130P and not penetrate the upper gate electrode 130U. The second contact plug 170B may be configured to be partially recessed into the upper gate electrode 130U, or it may be configured to contact the upper surface of the upper gate electrode 130U.

[0112] Figure 12 This is a cross-sectional view showing a semiconductor device according to an example embodiment.

[0113] Reference Figure 12 The semiconductor device 100f may have a structure in which a peripheral circuit region PERI can be vertically bonded to a memory cell region CELL. In the given example embodiment, the peripheral circuit region PERI may further include a first bonding metal layer 295, and the memory cell region CELL may further include an upper plug 187, a second bonding metal layer 197, and a passivation layer 198 on the second substrate 101. Furthermore, the upper ends of the contact plug 170 and the through plug 175 may be respectively disposed in the second substrate 101 and the substrate insulating layer 121.

[0114] A first bonding metal layer 295 may be disposed on the circuit contact plug 270 and the circuit interconnect 280, and the upper surface of the first bonding metal layer 295 may be exposed to the upper surface of the peripheral circuit region PERI via the peripheral region insulating layer 290. A second bonding metal layer 197 may be disposed below the upper plug 187, and the lower surface of the second bonding metal layer 197 may be exposed to the lower surface of the memory cell region CELL via the cell region insulating layer 190. For example, the first bonding metal layer 295 and the second bonding metal layer 197 may comprise a conductive material such as copper (Cu). In some example embodiments, each of the peripheral region insulating layer 290 and the cell region insulating layer 190 may comprise a bonding dielectric layer surrounding a corresponding one of the first bonding metal layer 295 and the second bonding metal layer 197 and disposed at a predetermined depth from the upper surface. The bonding dielectric layer may comprise at least one of, for example, SiO, SiN, SiCN, SiOC, SiON, and SiOCN. The passivation layer 198 may be disposed on the second substrate 101 to protect the second substrate 101, and may include an insulating material.

[0115] The peripheral circuit region (PERI) and the memory cell region (CELL) can be bonded by bonding a first bonding metal layer 295 to a second bonding metal layer 197 and bonding dielectric layers to each other. The first bonding metal layer 295 and the second bonding metal layer 197 can be, for example, copper (Cu)-copper (Cu) bonding. The bonded dielectric layers can be bonded to each other by dielectric-dielectric bonding, and can be, for example, SiCN-SiCN layers. The peripheral circuit region (PERI) and the memory cell region (CELL) can be bonded by a hybrid bonding method including copper (Cu)-copper (Cu) bonding and dielectric-dielectric bonding.

[0116] The upper ends of the contact plugs 170 may be configured to be electrically isolated from each other within the second substrate 101. In the given example embodiment, the second substrate 101 may include an insulating region 106, and the upper ends of the contact plugs 170 may be disposed within the insulating region 106. However, the second substrate 101 may be in a split form to electrically isolate the contact plugs 170 from each other, instead of including an insulating region 106.

[0117] Figures 13A to 13K This is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an example embodiment.

[0118] Reference Figure 13A A structure including circuit devices 220 and a lower interconnect structure can be formed on the first substrate 201 to form a peripheral circuit region PERI, and a second substrate 101, a horizontal insulating layer 110, a second horizontal conductive layer 104 and a substrate insulating layer 121 can be formed above the peripheral circuit region PERI.

[0119] A device separation layer 210 can be formed in a first substrate 201, and a circuit gate dielectric layer 222 and a circuit gate electrode 225 can be sequentially formed on the first substrate 201. The device separation layer 210 can be formed, for example, by a shallow trench separation (STI) process. The circuit gate dielectric layer 222 and the circuit gate electrode 225 can be formed using atomic layer deposition (ALD) or chemical vapor deposition (CVD). The circuit gate dielectric layer 222 can be formed from silicon oxide, and the circuit gate electrode 225 can be formed from at least one of a polysilicon layer and a metal silicide layer, but the exemplary embodiments are not limited thereto. Subsequently, a spacer layer 224 can be formed on the two sidewalls of the circuit gate dielectric layer 222 and the circuit gate electrode 225, and a source / drain region 205 can be formed in the first substrate 201 at the two sidewalls of the circuit gate dielectric layer 222 and the circuit gate electrode 225. In some exemplary embodiments, the spacer layer 224 can be formed from multiple layers. Subsequently, the source / drain region 205 can be formed by performing an ion implantation process.

[0120] In the underlying interconnect structure, circuit contact plugs 270 can be formed by partially forming a peripheral region insulating layer 290, removing a portion of the peripheral region insulating layer 290 by etching, and filling with conductive material. Circuit interconnects 280 can be formed by depositing conductive material and patterning the conductive material.

[0121] The peripheral region insulating layer 290 may include multiple insulating layers. The peripheral region insulating layer 290 may be partially formed in each process forming the lower interconnect structure and may be partially formed on the uppermost circuit interconnect 280, such that the peripheral region insulating layer 290 can be formed to cover the circuit device 220 and the lower interconnect structure.

[0122] Subsequently, a second substrate 101 can be formed on the peripheral insulating layer 290. The second substrate 101 can be formed of, for example, polysilicon, and can be formed by a CVD process. The polysilicon forming the second substrate 101 may include impurities.

[0123] A first horizontal insulating layer 111 and a second horizontal insulating layer 112 can be alternately stacked on the second substrate 101 to form the horizontal insulating layer 110. This can be achieved through subsequent processes. Figure 3AThe first horizontal conductive layer 102 partially replaces the horizontal insulating layer 110. The first horizontal insulating layer 111 may comprise a material different from that of the second horizontal insulating layer 112. For example, the first horizontal insulating layer 111 may be formed of the same material as the interlayer insulating layer 120, and the second horizontal insulating layer 112 may be formed of the same material as the subsequent sacrificial insulating layer 118. A portion of the horizontal insulating layer 110 may be removed (e.g., in the second region R2 of the second substrate 101) by a patterning process.

[0124] A second horizontal conductive layer 104 may be formed on the horizontal insulating layer 110, and the second horizontal conductive layer 104 may contact the second substrate 101 in the region from which the horizontal insulating layer 110 has been removed. Therefore, the second horizontal conductive layer 104 may be bent along the end of the horizontal insulating layer 110, may cover the end, and may extend onto the second substrate 101.

[0125] The base insulating layer 121 may contain the contact plug 170 for which the second region R2 is to be disposed (see Figure 3A The second substrate 101 is penetrated in the region R1 and the third region R3. The substrate insulating layer 121 can be formed by removing a portion of the second substrate 101, the horizontal insulating layer 110, and the second horizontal conductive layer 104 and filling it with an insulating material. After filling with the insulating material, a planarization process can also be performed using a chemical mechanical polishing (CMP) process. Therefore, the upper surface of the substrate insulating layer 121 can be substantially coplanar with the upper surface of the second horizontal conductive layer 104.

[0126] Reference Figure 13B The sacrificial insulating layer 118 and the interlayer insulating layer 120 can be alternately stacked on the second horizontal conductive layer 104 to form a lower stack structure, a stepped structure can be formed, and a first preliminary nitride layer 150LP can be formed.

[0127] In this process, a first channel structure CH1 (see) can be installed on it. Figure 3A A sacrificial insulating layer 118 and an interlayer insulating layer 120 are formed in the horizontal region. An upper interlayer insulating layer 125 with a relatively large thickness can be formed on the uppermost portion, and an etch stop layer 126 can be formed above the upper interlayer insulating layer 125. A gate electrode 130 (see [link to relevant documentation]) can be used in subsequent processes. Figure 3AThe sacrificial insulating layer 118 is replaced. The sacrificial insulating layer 118 may be formed of a material different from that of the interlayer insulating layer 120, and may be formed of a material that is selectively etched relative to the interlayer insulating layer 120 under predetermined etch conditions. For example, the interlayer insulating layer 120 and the upper interlayer insulating layer 125 may be formed of at least one of silicon oxide and silicon nitride, and the sacrificial insulating layer 118 may be formed of a material different from that of the interlayer insulating layer 120, selected from silicon, silicon oxide, silicon carbide, and silicon nitride. In some example embodiments, the interlayer insulating layers 120 may not have the same thickness. Furthermore, the thicknesses of the interlayer insulating layers 120 and the sacrificial insulating layer 118, as well as their number of layers, may vary from the examples shown. The etch stop layer 126 may be a layer used to protect the structure disposed below when forming the stepped structure, and may be referred to as a hard mask layer.

[0128] Subsequently, in the second region R2, photolithography and etching processes can be repeatedly performed on the sacrificial insulating layer 118 using a mask layer, such that the upper sacrificial insulating layer 118 can extend less than the lower sacrificial insulating layer 118. Therefore, the sacrificial insulating layer 118 can form a stepped structure in predetermined units, and the sacrificial pad region 118P disposed on the uppermost portion of the sacrificial insulating layer 118 can be exposed upwards. This can be achieved by forming the lowermost interlayer insulating layer 120 to extend the same length as the sacrificial insulating layer 118 disposed above the lowermost interlayer insulating layer 120. Figure 7A and Figure 7B The first nitride layer 150L in the example embodiment.

[0129] Subsequently, a first preliminary nitride layer 150LP can be formed on the lower stack structure. The first preliminary nitride layer 150LP can cover the exposed sacrificial pad region 118P along the stepped shape of the lower stack structure, can cover the side surfaces of the steps of the lower stack structure, and can extend onto the lowest interlayer insulating layer 120. The thickness of the first preliminary nitride layer 150LP can be in the range of about 50% to about 110% of the thickness of the sacrificial insulating layer 118, but the exemplary embodiment is not limited thereto.

[0130] Reference Figure 13C The first nitride layer 150L can be formed by partially removing the first preliminary nitride layer 150LP so that it is only retained on the sacrificial pad region 118P.

[0131] The first preliminary nitride layer 150LP can be selectively removed from the side surface of the step in the lower stacked structure. For example, the removal process can be performed after altering the physical properties of the horizontally deposited region of the first preliminary nitride layer 150LP using plasma. Thus, the first preliminary nitride layer 150LP can remain on the sacrificial pad region 118P and the bottommost interlayer insulating layer 120, and a first nitride layer 150L can be formed. On the bottommost interlayer insulating layer 120, the first nitride layer 150L can be spaced apart from the adjacent sacrificial pad region 118P.

[0132] In the given example embodiment, the process for removing the first nitride layer 150L from the outside of the lower stacked structure can be omitted, thereby simplifying the process and improving productivity. Therefore, the first nitride layer 150L on the bottommost interlayer insulating layer 120 can remain in a portion of the second region R2 and the third region R3, and can be included in the semiconductor device 100 (see...). Figure 3A )middle.

[0133] Reference Figure 13D This can form a first channel sacrificial layer 116a that penetrates the underlying stacked structure.

[0134] First, a portion of the lower stacked structure covering the sacrificial insulating layer 118 and the interlayer insulating layer 120 can be formed by the unit region insulating layer 190, and the etch stop layer 126 can be removed by a planarization process.

[0135] Subsequently, it can be connected to the first channel structure CH1 in the first region R1 (see...) Figure 3A A first channel sacrificial layer 116a is formed in the corresponding region. The first channel sacrificial layer 116a can be formed by forming a lower channel via to penetrate the lower stack structure and depositing the material forming the first channel sacrificial layer 116a in the lower channel via. The first channel sacrificial layer 116a may include, for example, polysilicon.

[0136] Reference Figure 13E The sacrificial insulating layer 118 and the interlayer insulating layer 120 that form the upper stacked structure can be alternately stacked on the lower stacked structure, a stepped structure can be formed, and a second nitride layer 150U can be formed.

[0137] In this process, a second channel structure CH2 (see) will be installed on top of it. Figure 3A In the upper region at the level of ), the above reference can be performed in the same way. Figure 13B and Figure 13CThe process described is for the lower stacked structure. Therefore, the second nitride layer 150U can be retained only on the sacrificial pad region 118P and the bottommost interlayer insulating layer 120 of the upper stacked structure. Furthermore, on the bottommost interlayer insulating layer 120 of the upper stacked structure, the second nitride layer 150U can be spaced apart from the adjacent sacrificial pad region 118P. This can be achieved by forming the bottommost interlayer insulating layer 120 of the upper stacked structure to extend the same length as the sacrificial insulating layer 118 disposed above the bottommost interlayer insulating layer 120. Figure 7A and Figure 7B The second nitride layer 150U in the example embodiment.

[0138] In the given example embodiment, the process for removing the second nitride layer 150U from the outside of the upper stacked structure can be omitted, thereby simplifying the process and improving productivity. Therefore, the second nitride layer 150U on the bottommost interlayer insulating layer 120 of the upper stacked structure can be retained in a portion of the second region R2 and the third region R3, and can be included in the semiconductor device 100.

[0139] Reference Figure 13F This can form a second channel sacrificial layer 116b that penetrates the stacked structure.

[0140] This can form part of an upper stacked structure that covers the sacrificial insulation layer 118 and the interlayer insulation layer 120 of the unit region insulation layer 190.

[0141] Subsequently, the second channel sacrificial layer 116b can be formed by forming an upper channel via to penetrate the upper stacked structure and expose the upper end of the first channel sacrificial layer 116a, and depositing a material in the upper channel via to form the second channel sacrificial layer 116b. The second channel sacrificial layer 116b may include, for example, polysilicon.

[0142] Reference Figure 13G It can remove the first channel sacrificial layer 116a and the second channel sacrificial layer 116b, form a channel structure CH, and form an open OH.

[0143] In the upper stacked structure, the upper separation region SS (see [reference]) can be formed by removing a portion of the sacrificial insulation layer 118 and the interlayer insulation layer 120. Figure 3B To form the upper separation region SS, a mask layer can be used to expose the area where the upper separation region SS will be formed. A predetermined number of sacrificial insulating layers 118 and interlayer insulating layers 120 can be removed, and insulating material can be deposited to form the upper separation insulating layer 103 (see...). Figure 3B ).

[0144] The channel structure CH can be formed by forming a channel via by removing the first channel sacrificial layer 116a and the second channel sacrificial layer 116b and filling the channel via. For example, the channel structure CH can be formed by sequentially forming a gate dielectric layer 145, a channel layer 140, a channel-filling insulating layer 147, and a channel pad 149 in the channel via. In this process, at least a portion of the gate dielectric layer 145 extending vertically along the channel layer 140 can be formed. The channel layer 140 can be formed on the gate dielectric layer 145 in the channel structure CH. The channel-filling insulating layer 147 can be formed to fill the channel structure CH and can be an insulating material. For example, the channel pad 149 can be formed from a conductive material (such as polysilicon).

[0145] It can be formed in it Figure 3A An opening OH is formed in the region of the contact plug 170 and through plug 175. Prior to forming the opening OH, a portion of the covering channel structure CH of the cell region insulating layer 190 may also be formed. The opening OH may have a cylindrical hole shape, penetrate the substrate insulating layer 121, and extend to the peripheral circuit region PERI. Although not specifically shown, the opening OH may be formed to expose the pad 285 on the circuit interconnect 280 (see...). Figure 4C A portion of the opening OH can extend through the first nitride layer 150L and the second nitride layer 150U.

[0146] Reference Figure 13H This can partially remove the sacrificial insulating layer 118, the first nitride layer 150L, ​​and the second nitride layer 150U exposed through the opening OH.

[0147] By providing etchant through the opening OH, a predetermined length of the sacrificial insulating layer 118, the first nitride layer 150L, ​​and the second nitride layer 150U can be removed from the circumference of the opening OH, thereby forming a first tunnel portion TL1. The first tunnel portion TL1 can be formed to have a relatively short length in the sacrificial pad region 118P and can be formed to have a relatively long length in the sacrificial insulating layer 118 disposed below the sacrificial pad region 118P.

[0148] For example, firstly, the first tunnel portion TL1 can be formed relatively long in the sacrificial pad region 118P, possibly because the etching rates of the first nitride layer 150L and the second nitride layer 150U can be relatively higher than the etching rate of the sacrificial insulating layer 118. Subsequently, a sacrificial layer can be formed in the opening OH and the first tunnel portion TL1. The sacrificial layer can be formed from a material having an etching rate slower than that of the first nitride layer 150L, ​​the second nitride layer 150U, and the sacrificial insulating layer 118. Subsequently, the sacrificial layer and a portion of the sacrificial insulating layer 118 can be removed. In this case, the sacrificial layer can remain in the uppermost portion, and in the lower portion, the sacrificial layer can be removed, and a portion of the sacrificial insulating layer 118 can be removed. Therefore, the first tunnel portion TL1 can be formed with a relatively short length in the sacrificial pad region 118P.

[0149] Reference Figure 13I The first tunnel portion TL1 and the opening OH can be filled with the initial contact plug insulation layer 160P and the vertical sacrificial layer 191, and the sacrificial insulation layer 118 can be removed to form the second tunnel portion TL2.

[0150] The initial contact plug insulation layer 160P can be retained in subsequent processes, and a first contact plug insulation layer 160 and a second contact plug insulation layer 165, as well as a first through plug insulation layer 180 and a second through plug insulation layer 185, can be formed. The initial contact plug insulation layer 160P can be deposited by, for example, an ALD process. The initial contact plug insulation layer 160P can not completely fill the first tunnel portion TL1 in the uppermost region (the region from which the sacrificial pad region 118P is partially removed) of each of the stepped regions, which has a relatively large thickness, and can completely fill the first tunnel portion TL1 in the lower region and the region from which the first nitride layer 150L and the second nitride layer 150U are removed.

[0151] A vertical sacrificial layer 191 can be formed to fill the remaining space in the opening OH. The vertical sacrificial layer 191 may include a material different from the material of the initial contact plug insulating layer 160P, and may include, for example, polysilicon.

[0152] Subsequently, in the first separation region MS1 ​​(see...) Figure 2 ) and the second separation region MS2 (see Figure 2 An opening is formed in the position of the second substrate 101, which penetrates the sacrificial insulation layer 118 and the interlayer insulation layer 120.

[0153] By forming a sacrificial spacer layer in the opening and performing an etch-back process, the horizontal insulating layer 110 can be selectively removed from the first region R1, and a portion of the exposed gate dielectric layer 145 can also be removed. A first horizontal conductive layer 102 can be formed by depositing a conductive material in the region from which the horizontal insulating layer 110 has been removed, and the sacrificial spacer layer can be removed from the opening. Through this process, the first horizontal conductive layer 102 can be formed in the first region R1.

[0154] For example, wet etching can be used to selectively remove the sacrificial insulating layer 118 relative to the interlayer insulating layer 120, the second horizontal conductive layer 104, and the base insulating layer 121. Thus, a second tunnel portion TL2 can be formed between the interlayer insulating layers 120. In this process, a portion of the first nitride layer 150L and the second nitride layer 150U can also be removed. For example, it can be removed from the interlayer insulating layer 120. Figure 3A The regions corresponding to the first dummy gate electrode 131D and the second dummy gate electrode 132D shown in the figure have the first nitride layer 150L and the second nitride layer 150U removed.

[0155] Reference Figure 13J The gate electrode 130 can be formed by filling the second tunnel portion TL2 with conductive material, the vertical sacrificial layer 191 can be removed, and the initial contact plug insulating layer 160P can be partially removed.

[0156] Before forming the gate electrode 130, a portion of the gate dielectric layer 145 extending vertically along the gate electrode 130 can be formed, and the gate electrode 130, the first dummy gate electrode 131D, and the second dummy gate electrode 132D can be formed. The conductive material forming the gate electrode 130 can fill the second tunnel portion TL2. The conductive material can include metal, polysilicon, or metal silicide. After forming the gate electrode 130, a separation insulating layer 105 (see [link to documentation]) can be formed in the openings formed in the regions of the first separation region MS1 ​​and the second separation region MS2. Figure 3B ).

[0157] The vertical sacrificial layer 191 in the opening OH can be selectively removed. After removing the vertical sacrificial layer 191, the exposed initial contact plug insulating layer 160P can be partially removed. In this case, in the pad region 130P, the initial contact plug insulating layer 160P can be completely removed to allow the formation of the third tunnel portion TL3, and the initial contact plug insulating layer 160P can be retained in the lower portion (e.g., below the pad region 130P) and the first contact plug insulating layer 160 can be formed. In the third tunnel portion TL3, after removing the initial contact plug insulating layer 160P, the exposed gate dielectric layer 145 can also be partially removed to expose the side surface of the gate electrode 130. At the level corresponding to the first nitride layer 150L and the second nitride layer 150U, the initial contact plug insulating layer 160P can be retained, and the second contact plug insulating layer 165, as well as the first through plug insulating layer 180 and the second through plug insulating layer 185, can be formed.

[0158] Reference Figure 13K Contact plug 170 and through plug 175 can be formed by depositing conductive material in the opening OH.

[0159] The padding layer 285 can be removed from the bottom of the opening OH (see [link]). Figure 4C This exposes the circuit interconnects 280, and conductive material can be deposited thereon. Contact plugs 170 and through plugs 175 can be formed together in the same process; therefore, contact plugs 170 and through plugs 175 can have the same structure. Contact plug 170 can be formed to have a horizontally extending portion 170H in the pad region 130P (see...). Figure 4A ), thereby physically and electrically connected to the gate electrode 130.

[0160] Return to reference Figure 3A The semiconductor device 100 can be manufactured by forming a cell interconnect 195 that connects to the upper end of the through plug 175 and the upper end of the contact plug 170.

[0161] Figure 14 This is a view illustrating a data storage system including semiconductor devices according to an example embodiment.

[0162] Reference Figure 14The data storage system 1000 may include a semiconductor device 1100 and a controller 1200 electrically connected to the semiconductor device 1100. The data storage system 1000 may be implemented as a storage device including one or more semiconductor devices 1100, or as an electronic device including a storage device. For example, the data storage system 1000 may be implemented as a solid-state drive (SSD) device, a universal serial bus (USB) device, a computing system, a medical device, or a communication device including one or more semiconductor devices 1100.

[0163] Semiconductor device 1100 can be implemented as a non-volatile memory device, and can be implemented as, for example, as described above. Figures 1 to 12 The NAND flash memory device described herein. Semiconductor device 1100 may include a first semiconductor structure 1100F and a second semiconductor structure 1100S on the first semiconductor structure 1100F. In some example embodiments, the first semiconductor structure 1100F may be disposed on a side of the second semiconductor structure 1100S. The first semiconductor structure 1100F may be configured as a peripheral circuit structure including a decoder circuit 1110, a page buffer 1120, and logic circuitry 1130. The second semiconductor structure 1100S may be configured as a memory cell structure including a bit line BL, a common-source line CSL, a word line WL, a first gate upper line UL1 and a second gate upper line UL2, a first gate lower line LL1 and a second gate lower line LL2, and a memory cell string CSTR between the bit line BL and the common-source line CSL.

[0164] In the second semiconductor structure 1100S, each of the memory cell strings CSTRs may include lower transistors LT1 and LT2 adjacent to the common-source line CSL, upper transistors UT1 and UT2 adjacent to the bit line BL, and a plurality of memory cell transistors MCTs disposed between the lower transistors LT1 and LT2 and the upper transistors UT1 and UT2. In an example embodiment, the number of lower transistors LT1 and LT2 and the number of upper transistors UT1 and UT2 may vary.

[0165] In some example embodiments, upper transistors UT1 and UT2 may include string select transistors, and lower transistors LT1 and LT2 may include ground select transistors. Gate lower lines LL1 and LL2 may be the gate electrodes of lower transistors LT1 and LT2, respectively. Word line WL may be the gate electrode of memory cell transistor MCT, and gate upper lines UL1 and UL2 may be the gate electrodes of upper transistors UT1 and UT2, respectively.

[0166] In some example embodiments, the lower transistors LT1 and LT2 may include a lower erase control transistor LT1 and a ground select transistor LT2 connected in series with each other. The upper transistors UT1 and UT2 may include a string select transistor UT1 and an upper erase control transistor UT2 connected in series with each other. At least one of the lower erase control transistor LT1 and the upper erase control transistor UT2 can be used for an erase operation that erases data stored in the memory cell transistor MCT using the GIDL phenomenon.

[0167] The common-source line CSL, the first lower gate line LL1, the second lower gate line LL2, the word line WL, and the first upper gate line UL1 and the second upper gate line UL2 can be electrically connected to the decoder circuit 1110 via a first interconnect 1115 extending from the first semiconductor structure 1100F to the second semiconductor structure 1100S. The bit line BL can be electrically connected to the page buffer 1120 via a second interconnect 1125 extending from the first semiconductor structure 1100F to the second semiconductor structure 1100S.

[0168] In the first semiconductor structure 1100F, the decoder circuit 1110 and the page buffer 1120 can perform control operations on at least one selected memory cell transistor among a plurality of memory cell transistors (MCTs). The decoder circuit 1110 and the page buffer 1120 can be controlled by the logic circuit 1130. The semiconductor device 1100 can communicate with the controller 1200 via input and output pads (or input / output pads) 1101 electrically connected to the logic circuit 1130. The input and output pads 1101 can be electrically connected to the logic circuit 1130 via input and output interconnects 1135 extending from the first semiconductor structure 1100F to the second semiconductor structure 1100S.

[0169] The controller 1200 may include a processor 1210, a NAND controller 1220, and a host interface (I / F) 1230. In some example embodiments, the data storage system 1000 may include a plurality of semiconductor devices 1100, and in this case, the controller 1200 may control the plurality of semiconductor devices 1100.

[0170] Processor 1210 can control the overall operation of data storage system 1000, including controller 1200. Processor 1210 can operate according to predetermined firmware and can access semiconductor device 1100 by controlling NAND controller 1220. NAND controller 1220 may include NAND interface (I / F) 1221 for processing communication with semiconductor device 1100. Control commands for controlling semiconductor device 1100, data to be written to memory cell transistors (MCTs) of semiconductor device 1100, and data to be read from memory cell transistors (MCTs) of semiconductor device 1100 can be sent through NAND interface 1221. Host interface 1230 provides communication functionality between data storage system 1000 and external host. When a control command is received from external host through host interface 1230, processor 1210 can control semiconductor device 1100 in response to the control command.

[0171] Figure 15 This is a perspective view illustrating a data storage system including semiconductor devices according to an example embodiment.

[0172] Reference Figure 15 The data storage system 2000 according to an example embodiment may include a main substrate 2001, a controller 2002 mounted on the main substrate 2001, one or more semiconductor packages 2003 and DRAM 2004. The semiconductor packages 2003 and DRAM 2004 may be connected to the controller 2002 via interconnect patterns 2005 formed on the main substrate 2001.

[0173] The main substrate 2001 may include a connector 2006, which includes a plurality of pins coupled to an external host. The number and arrangement of the plurality of pins in the connector 2006 may vary depending on the communication interface between the data storage system 2000 and the external host. In some example embodiments, the data storage system 2000 may communicate with the external host via one of Universal Serial Bus (USB), Peripheral Component Interconnect Fast (PCI Fast), Serial Advanced Technology Attachment (SATA), and M-PHY for Universal Flash Memory (UFS). In some example embodiments, the data storage system 2000 may operate with power supplied from the external host via the connector 2006. The data storage system 2000 may also include a power management integrated circuit (PMIC) for distributing power supplied from the external host to the controller 2002 and the semiconductor package 2003.

[0174] The controller 2002 can write data to or read data from the semiconductor package 2003, and can improve the operating speed of the data storage system 2000.

[0175] DRAM 2004 can be configured as a buffer memory to reduce the speed difference between semiconductor package 2003, data storage space, and external host. DRAM 2004 included in data storage system 2000 can also operate as a cache memory and can provide space for temporarily storing data during control operations on semiconductor package 2003. When DRAM 2004 is included in data storage system 2000, controller 2002 may also include a DRAM controller for controlling DRAM 2004, in addition to a NAND controller for controlling semiconductor package 2003.

[0176] Semiconductor package 2003 may include a first semiconductor package 2003a and a second semiconductor package 2003b spaced apart from each other. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may be configured as a semiconductor package including a plurality of semiconductor chips 2200. Each of the first semiconductor package 2003a and the second semiconductor package 2003b may include a package substrate 2100, semiconductor chips 2200 on the package substrate 2100, an adhesive layer 2300 disposed on the lower surface of each of the semiconductor chips 2200, a connection structure 2400 electrically connecting the semiconductor chips 2200 to the package substrate 2100, and a molding layer 2500 covering the semiconductor chips 2200 and the connection structure 2400 on the package substrate 2100.

[0177] The package substrate 2100 can be configured as a printed circuit board including package pads 2130. Each of the semiconductor chips 2200 may include input and output pads 2210. The input and output pads 2210 can be coupled with... Figure 14 The input and output pads 1101 correspond to each other. Each of the semiconductor chips 2200 may include a gate stack structure 3210 and a channel structure 3220. Each of the semiconductor chips 2200 may include a reference. Figures 1 to 12 The semiconductor device described.

[0178] In some example embodiments, the connection structure 2400 may be a bonding wire electrically connecting the input and output pads 2210 to the package pad 2130. Therefore, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other via bonding wires and may be electrically connected to the package pad 2130 of the package substrate 2100. In some example embodiments, in each of the first semiconductor package 2003a and the second semiconductor package 2003b, the semiconductor chips 2200 may be electrically connected to each other via a through-silicon via (TSV, or via-silicon via) connection structure instead of the bonding wire connection structure 2400.

[0179] In some example embodiments, the controller 2002 and the semiconductor chip 2200 may be included in a single package. For example, the controller 2002 and the semiconductor chip 2200 may be mounted on a separate intermediate substrate, different from the main substrate 2001, and the controller 2002 may be connected to the semiconductor chip 2200 via interconnects formed on the intermediate substrate.

[0180] Figure 16 This is a cross-sectional view showing a semiconductor device according to an example embodiment. Figure 16 It shows Figure 15 An example embodiment of the semiconductor package 2003 is shown, and it is illustrated. Figure 15 A cross-sectional view of the semiconductor package 2003 taken along line III-III'.

[0181] Reference Figure 16 In semiconductor package 2003, package substrate 2100 can be configured as a printed circuit board. Package substrate 2100 may include package substrate body portion 2120 and package pad 2130 disposed on the upper surface of package substrate body portion 2120 (see See Figure 15 The package includes a lower pad 2125 disposed on or exposed through the lower surface of the package substrate body portion 2120, and an internal interconnect 2135 within the package substrate body portion 2120 electrically connecting the package upper pad 2130 to the lower pad 2125. The package upper pad 2130 may be electrically connected to a connection structure 2400 (see...). Figure 15 ).like Figure 15 Similarly, the lower pad 2125 can be connected to the interconnect pattern 2005 of the main substrate 2001 of the data storage system 2000 via the conductive connection portion 2800.

[0182] Each of the semiconductor chips 2200 may include a semiconductor substrate 3010 and a first structure 3100 and a second structure 3200 sequentially stacked on the semiconductor substrate 3010. The first structure 3100 may include a peripheral circuit region including a peripheral interconnect 3110. The second structure 3200 may include a common source line 3205, a gate stack structure 3210 on the common source line 3205, a channel structure 3220 penetrating the gate stack structure 3210 and a separation structure (not shown), a bit line 3240 electrically connected to the channel structure 3220, and a word line WL electrically connected to the gate stack structure 3210 (see See). Figure 14 Contact plug 3235. (See reference...) Figures 1 to 12 As described, in each of the semiconductor chips 2200, the first nitride layer 150L and the second nitride layer 150U can be retained in a portion of the second region R2 and the third region R3.

[0183] Each of the semiconductor chips 2200 may include a through-interconnect 3245 electrically connected to the peripheral interconnect 3110 of the first structure 3100 and extending into the second structure 3200. The through-interconnect 3245 may be disposed on the outside of the gate stack structure 3210 and may also be configured to penetrate the gate stack structure 3210. Each of the semiconductor chips 2200 may also include input and output pads 2210 electrically connected to the peripheral interconnect 3110 of the first structure 3100 (see...). Figure 15 ).

[0184] Example embodiments may include a contact plug structure surrounded by a first contact plug insulating layer and a reserved nitride layer for forming a pad region of the gate electrode.

[0185] As described above, the example embodiments can provide semiconductor devices with improved productivity. Example embodiments can provide data storage systems including semiconductor devices with improved productivity.

[0186] Example embodiments have been disclosed herein, and although specific terminology has been used, it is used and interpreted in a general and descriptive sense only, and not for limiting purposes. In some instances, as will be apparent to those skilled in the art, features, characteristics, and / or elements described in connection with particular embodiments may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless specifically indicated otherwise, since the filing of this application. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the spirit and scope of the invention as set forth in the appended claims.

Claims

1. A semiconductor device, the semiconductor device comprising: A first semiconductor structure includes a first substrate and circuit devices on the first substrate; as well as A second semiconductor structure is disposed on the first semiconductor structure, wherein the second semiconductor structure includes: The second substrate has a first region and a second region; Gate electrodes are stacked and spaced apart from each other in a first direction in the first region, extend to different lengths in a second direction in the second region, and each gate electrode in the second region includes a pad region having an upwardly exposed upper surface; Interlayer insulating layers are stacked alternately with the gate electrode; A channel structure that penetrates the gate electrode and extends in the first direction, and each channel structure includes a channel layer; A separation region that penetrates the gate electrode in the first region and the second region and extends in the second direction; Contact plugs, each contact plug penetrating the pad region of each gate electrode in the gate electrode and extending into the first semiconductor structure in the first direction; A first contact plug insulating layer is disposed alternately with the interlayer insulating layer below the pad region of each of the gate electrodes and surrounds each of the contact plugs; Through the plug, extending in the first direction in a third region on the outer side of the second substrate to electrically connect the first semiconductor structure to the second semiconductor structure; A first through-hole insulating layer surrounds the through-hole at a level lower than the level of the upper surface of the lowermost first gate electrode among the gate electrodes; and A first nitride layer contacts the outer surface of the first through-hole insulating layer and extends horizontally in the third region.

2. The semiconductor device according to claim 1, wherein, The first nitride layer is configured to be spaced apart from the lowermost first gate electrode in the second direction.

3. The semiconductor device according to claim 1, wherein, The first nitride layer has a first thickness, and each of the gate electrodes has a second thickness in the pad region that is greater than the first thickness.

4. The semiconductor device according to claim 3, wherein: Each of the gate electrodes has a third thickness, smaller than the second thickness, in a region other than the pad region, and The third thickness is equal to or greater than the first thickness.

5. The semiconductor device according to claim 1, wherein, The second semiconductor structure further includes a first dummy gate electrode, which is spaced apart from the lowermost first gate electrode, disposed at a level corresponding to the level of the first nitride layer, and has a region extending further outward from the separation region in the second direction than the separation region.

6. The semiconductor device according to claim 5, wherein, The first dummy gate electrode is configured to be located at its end in the second direction surrounding the separation region.

7. The semiconductor device according to claim 5, wherein, The first nitride layer is in contact with the side surface of the first dummy gate electrode.

8. The semiconductor device according to claim 1, wherein: Each channel structure in the channel structure includes a first channel structure and a second channel structure stacked in the first direction, and The second semiconductor structure further includes a second contact plug insulating layer that surrounds the contact plug at a level lower than the level of the upper surface of the second gate electrode, which is most adjacent to the lower end of the second channel structure.

9. The semiconductor device according to claim 8, wherein, The second semiconductor structure also includes: A second through-plug insulation layer surrounds the through-plug at a level corresponding to the level of the second contact plug insulation layer; and The second nitride layer contacts the outer surface of the second through-plug insulation layer and extends horizontally.

10. The semiconductor device according to claim 9, wherein, The second semiconductor structure further includes a second dummy gate electrode, which is in contact with the outer surface of the second contact plug insulating layer and with the second nitride layer.

11. The semiconductor device according to claim 1, wherein, Each of the contact plugs includes a vertical extension extending in the first direction and a horizontal extension extending horizontally from the vertical extension to contact the pad region.

12. The semiconductor device according to claim 11, wherein, The length from the side surface of the vertical extension to the end of the horizontal extension is smaller than the length from the side surface of the vertical extension to the end of the first contact plug insulation layer surrounding the vertical extension.

13. The semiconductor device according to claim 1, wherein, The first semiconductor structure further includes a padding layer surrounding the contact plug at the lower end of the contact plug.

14. A semiconductor device, the semiconductor device comprising: The substrate has a first region and a second region; Gate electrodes are stacked and spaced apart from each other in a first direction in the first region, extend to different lengths in a second direction in the second region, and each gate electrode in the second region includes a pad region having an upwardly exposed upper surface; A channel structure that penetrates the gate electrode and extends in the first direction, and each channel structure includes a channel layer; A separation region that penetrates the gate electrode in the first region and the second region and extends in the second direction; Contact plugs, each contact plug penetrating the pad region of each of the gate electrodes and extending in the first direction; A nitride layer is disposed outside the lowermost first gate electrode among the gate electrodes, spaced apart from the lowermost first gate electrode, and extends horizontally; as well as A dummy gate electrode is disposed in the second direction between the lowermost first gate electrode and the nitride layer, and has a first end spaced apart from the lowermost first gate electrode.

15. The semiconductor device according to claim 14, wherein, The dummy gate electrode has a second end that is opposite to the first end in the second direction and in contact with the nitride layer.

16. The semiconductor device according to claim 14, wherein, The dummy gate electrode has a region that extends further outward from the separation region in the second direction than the separation region.

17. The semiconductor device according to claim 14, wherein, The nitride layer is disposed at a level corresponding to or lower than the level of the bottommost first gate electrode.

18. The semiconductor device according to claim 14, wherein, The lower surface of the nitride layer is positioned at a level higher than the upper surface of the substrate.

19. A data storage system, the data storage system comprising: A semiconductor memory device includes: a first substrate; circuit devices on the first substrate; a second substrate having a first region and a second region; gate electrodes stacked and spaced apart from each other in a first direction in the first region and extending to different lengths in a second direction in the second region, each gate electrode including a pad region having an upwardly exposed upper surface in the second region; a channel structure penetrating the gate electrodes and extending in the first direction, each channel structure including a channel layer; a separation region penetrating the gate electrodes in the first and second regions and extending in the second direction; contact plugs, each contact plug penetrating the pad region of each gate electrode and extending in the first direction; a nitride layer disposed outside the lowermost first gate electrode among the gate electrodes, spaced apart from the lowermost first gate electrode, and extending horizontally; a dummy gate electrode disposed between the lowermost first gate electrode and the nitride layer in the second direction, and having a first end spaced apart from the lowermost first gate electrode; and an input / output pad electrically connected to the circuit devices; and The controller is electrically connected to the semiconductor memory device via the input / output pad and is configured to control the semiconductor memory device.

20. The data storage system according to claim 19, wherein: The semiconductor memory device further includes: a through-hole that penetrates the second substrate in a third region on the outer side of the second substrate and extends in the first direction; and a through-hole insulating layer that surrounds the through-hole at a level corresponding to the level of the nitride layer, and The nitride layer is in contact with the outer surface of the through-hole plug insulation layer.

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