Split-gate flash memory cell and method for preparing the same

Abstract

The present invention provides a split-gate flash memory cell and a preparation method thereof, comprising: a substrate; a first split-gate structure and a second split-gate structure, located on the substrate, and both comprising a first floating gate, a second floating gate and an erase gate, the erase gate covering a portion of the top surface of the first floating gate, the second floating gate covering the side of the first floating gate and extending upward to cover the side of the erase gate, and the second floating gate directly contacts the first floating gate; a source line layer, located on the substrate between the first split-gate structure and the second split-gate structure, and two second floating gates respectively covering one side of the source line layer; a source region, located in the substrate below the source line layer, and electrically connected to the source line layer. The present invention can simplify the interconnection process and preparation process, reduce the interconnection contact resistance and help reduce the area of ​​the split-gate flash memory cell.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a split-gate flash memory unit and a preparation method thereof. Background Art

[0002] Flash memory is a non-volatile memory that controls the switching of the gate channel by changing the critical voltage of the transistor or storage unit to achieve the purpose of storing data, so that the data stored in the memory will not disappear due to power outage. Flash memory, as a special structure of electrically erasable and programmable read-only memory, has now occupied most of the market share of non-volatile semiconductor memory and has become the fastest-growing non-volatile semiconductor memory.

[0003] Figure 1 is a cross-sectional diagram of a split-gate flash memory cell. Figure 1 The source region 20' is located in the substrate 10' below the erase gate 30'. The source region 20' and the erase gate 30' are isolated by an oxide layer 40'. The floating gate 50' is located on both sides of the erase gate 30'. In the subsequent interconnection process, a source electrical connector (not shown in the figure) penetrating the erase gate 30' needs to be formed to be electrically connected to the source region 20'. Because the source electrical connector penetrates the erase gate 30', the contact resistance of the electrical connector is large, that is, the interconnection contact resistance is large, and the erase gate 30' needs to be led out through the erase gate electrical connector (not shown in the figure). The interconnection layout is complex and the interconnection process is required to be high. In addition, the device structure generally requires that the source region 20' and the floating gate 50' have a certain width of overlap in the lateral direction as a coupling portion (shown in the dotted box in the figure). The coupling portion is to ensure the coupling coefficient between the source region 20' and the floating gate 50', which is beneficial for programming the split-gate flash memory unit. Therefore, in order to ensure that the source region 20' and the floating gate 50' have a certain width of overlap in the lateral direction, the width of the floating gate 50' cannot be too small, which makes it difficult to reduce the size of the device. Summary of the invention

[0004] The object of the present invention is to provide a split-gate flash memory cell and a preparation method thereof, so as to simplify the interconnection process and the preparation process, reduce the interconnection contact resistance and facilitate the reduction of the area of ​​the split-gate flash memory cell.

[0005] In order to achieve the above object, the present invention provides a split-gate flash memory cell, comprising:

[0006] substrate;

[0007] A first split gate structure and a second split gate structure are located on the substrate and both include a first floating gate, a second floating gate and an erase gate, wherein the erase gate covers a portion of the top surface of the first floating gate, the second floating gate covers the side surface of the first floating gate and extends upward to cover the side surface of the erase gate, and the second floating gate is in direct contact with the first floating gate;

[0008] A source line layer is located on the substrate between the first split gate structure and the second split gate structure, and two second floating gates respectively cover one side of the source line layer;

[0009] The source region is located in the substrate below the source line layer and is electrically connected to the source line layer.

[0010] Optionally, the first split gate structure and the second split gate structure also include a first side wall, which covers the top surface of the erase gate, the remaining top surface of the first floating gate and the side surface of the second floating gate close to the source line layer, and part of the first side wall is located between the erase gate and the second floating gate.

[0011] Optionally, the first split gate structure and the second split gate structure also include a second sidewall and a word line gate, the second sidewall covers the corresponding side of the first floating gate and the erase gate away from the source line layer, and the word line gate covers the surface of the corresponding second sidewall.

[0012] Optionally, two drain regions are further included, each of which is located in the substrate outside each word line gate.

[0013] Optionally, the source line layer is made of polysilicon.

[0014] The present invention also provides a method for preparing a split-gate flash memory unit, comprising:

[0015] providing a substrate; and,

[0016] A first split gate structure and a second split gate structure are formed on the substrate, and both include a first floating gate, a second floating gate and an erase gate, the erase gate covers a portion of the top surface of the first floating gate, the second floating gate covers the side of the first floating gate and extends upward to cover the side of the erase gate, and the second floating gate is in direct contact with the first floating gate, a source line layer is formed on the substrate between the first split gate structure and the second split gate structure, and two second floating gates respectively cover one side of the source line layer, forming a source region in the substrate below the source line layer, and electrically connected to the source line layer.

[0017] Optionally, the step of forming the first floating gate, the erase gate, the source line layer and the source region includes:

[0018] forming a first floating gate material layer, an erase gate material layer and a mask layer in sequence on the substrate;

[0019] Sequentially etching the mask layer, the erase gate material layer, and the first floating gate material layer to form an opening exposing the substrate;

[0020] performing ion implantation on the substrate at the bottom of the opening to form the source region in the substrate at the bottom of the opening;

[0021] Filling the opening with the source line layer, wherein the source line layer is electrically connected to the source region; and

[0022] The mask layer and the first floating gate material layer and the erase gate material layer directly below the mask layer are removed by etching, and the remaining first floating gate material layer on each side of the source line layer is used as a first floating gate, and the remaining erase gate material layer on each side of the source line layer is used as an erase gate.

[0023] Optionally, the step of forming the opening and the second floating gate includes:

[0024] Etching the mask layer to form a first opening exposing the erase gate material layer;

[0025] forming a first sub-spacer on the sidewall of the first opening;

[0026] Using the first sub-spacer as a mask, etching the erase gate material layer to form a second opening exposing the first floating gate material layer;

[0027] forming a second sub-spacer on the sidewall of the second opening, wherein the second sub-spacer covers at least a portion of the surface of the first sub-spacer;

[0028] Using the first sub-spacer and the second sub-spacer as a mask, etching the first floating gate material layer to form a third opening exposing the substrate, wherein the first opening, the second opening and the third opening are connected to form the opening;

[0029] forming a second floating gate on the sidewall of the third opening, wherein the second floating gate covers at least a portion of the surface of the second sub-spacer; and,

[0030] A third sub-spacer is formed on the surface of the second floating gate, and the first sub-spacer, the second sub-spacer and the third sub-spacer constitute a first spacer.

[0031] Optionally, after forming the first floating gate and the erase gate, the method further includes:

[0032] forming a second spacer on a side of each of the erase gates and the first floating gate away from the source line layer; and,

[0033] A word line gate is formed on a surface of each of the second spacers.

[0034] Optionally, after forming the word line gate, the method further includes:

[0035] Ion implantation is performed on the substrate outside each word line gate to form a drain region in the substrate.

[0036] In the split-gate flash memory cell and its preparation method provided by the present invention, the first split-gate structure and the second split-gate structure are located on the substrate, and both include a first floating gate, a second floating gate and an erase gate, the erase gate covers part of the top surface of the first floating gate, the second floating gate covers the side of the first floating gate and extends upward to cover the side of the erase gate, and the second floating gate is in direct contact with the first floating gate; the source line layer is located on the substrate between the first split-gate structure and the second split-gate structure, and the two second floating gates respectively cover one side of the source line layer; the source region is located in the substrate below the source line layer and is electrically connected to the source line layer. In the present invention, erasing is performed through the erase gate above the first floating gate, the source region is electrically connected to the source line layer, and when the interconnection process is performed later, the source region is led out through the source line layer, which can reduce the source contact resistance and simplify the interconnection process and the preparation process; and the second floating gate covers the side of the source line layer, which increases the coupling area between the source line layer and the second floating gate, can reduce the width of the first floating gate, and is conducive to reducing the area of ​​the split-gate flash memory cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 is a cross-sectional schematic diagram of a split-gate flash memory cell;

[0038] Figure 2 A flow chart of a method for preparing a split-gate flash memory cell provided by an embodiment of the present invention;

[0039] Figures 3A to 3H A cross-sectional schematic diagram of corresponding steps in a method for preparing a split-gate flash memory cell provided by an embodiment of the present invention, wherein: Figure 3H A cross-sectional schematic diagram of a split-gate flash memory cell provided by an embodiment of the present invention;

[0040] Wherein, the accompanying drawings are marked as follows:

[0041] 10, 10'-substrate; 21-gate oxide layer; 22-tunneling oxide layer; 23-word line oxide layer; 30-first floating gate material layer; 50', 31-first floating gate; 32-second floating gate; 40-erase gate material layer; 30', 41-erase gate; 50-mask layer; 61-first sub-spacer; 62-second sub-spacer; 63-third sub-spacer; 64-second spacer; 71-first opening; 72-second opening; 73-third opening; 20', 81-source region; 82-drain region; 90-source line layer; 100-word line gate; 40'-oxide layer; T1-first sub-gate structure; T2-second sub-gate structure. DETAILED DESCRIPTION

[0042] The specific implementation of the present invention will be described in more detail below in conjunction with the schematic diagram. The advantages and features of the present invention will become clearer based on the following description. It should be noted that the drawings are all in a very simplified form and are not in exact proportions, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.

[0043] Figure 3H This is a cross-sectional diagram of a split-gate flash memory cell provided in this embodiment. Figure 3H The present embodiment provides a split-gate flash memory cell, comprising: a substrate 10, a first split-gate structure T1, a first split-gate structure T2, a source line layer 90, a source region 81 and a drain region 82, wherein the material of the substrate 10 comprises one or more of silicon, germanium, gallium, nitrogen or carbon.

[0044] The first split gate structure T1 and the second split gate structure T2 are both located on the substrate 10, and both include a first floating gate 31, a second floating gate 32, and an erase gate 41, wherein the erase gate 41 covers a portion of the top surface of the first floating gate 31, the second floating gate 32 covers the side of the first floating gate 31 and extends upward to cover the side of the erase gate 41, the first floating gate 31 is in direct contact with the second floating gate 32, and the first floating gate 31, the second floating gate 32, and the erase gate 41 are all made of polysilicon. In this embodiment, a gate oxide layer 21 is formed between the first floating gate 31 and the second floating gate 32 and the substrate 10; and a tunnel oxide layer 22 is formed between the first floating gate 31 and the erase gate 41.

[0045] Furthermore, the first split gate structure T1 and the second split gate structure T2 also include a first side wall, which covers the top surface of the erase gate 41, the remaining top surface of the first floating gate 31 and the side surface of the second floating gate 32 close to the source line layer 90, and part of the first side wall is located between the erase gate 41 and the second floating gate 32. Specifically, the first side wall includes a first sub-side wall 61, a second sub-side wall 62 and a third sub-side wall 63, wherein the first sub-side wall 61 is located above the erase gate 41, that is, covers the top surface of the erase gate 41; the second sub-side wall 62 covers the side of the erase gate 41 and the tunneling oxide layer 22 close to the source line layer 90 and the remaining top surface of the first floating gate 31, and extends to cover at least part of the surface of the first sub-side wall 61, and part of the second sub-side wall 62 is located between the erase gate 41 and the second floating gate 32; the third sub-side wall 63 covers the side of the second floating gate 32 and the gate oxide layer 21 close to the source line layer 90, and can extend to cover at least part of the surface of the second sub-side wall 62.

[0046] The source line layer 90 is located on the substrate 10 between the first split gate structure T1 and the second split gate structure T2, and the two second floating gates 32 respectively cover one side of the source line layer 90. The two second floating gates 32 and the source line layer 90 have a large relative area (i.e., coupling surface), which can reduce the width of the first floating gate 31 and help reduce the area of ​​the split gate flash memory unit. In this embodiment, the material of the source line layer 90 is preferably polysilicon; and a metal silicide layer (not shown in the figure) is formed on the source line layer 90 to reduce the contact resistance.

[0047] The source region 81 is located in the substrate 10 below the source line layer 90 , and the source region 81 is electrically connected to the source line layer 90 , that is, the source region 81 is in direct contact with the source line layer 90 .

[0048] The first split gate structure T1 and the second split gate structure T2 also include a second sidewall 64, a word line gate 100 and a word line oxide layer 23. The second sidewall 64 covers the corresponding gate oxide layer 21, the first floating gate 31, the tunnel oxide layer 22 and the side of the erase gate 41 away from the source line layer 90 and extends to cover at least part of the surface of the first sub-sidewall 61; the word line oxide layer 23 covers part of the surface of the substrate 10 and part of the surface of the second sidewall 64; the word line gate 100 is located on the word line oxide layer 23 and covers the remaining surface of the corresponding second sidewall 64, and can also extend to cover part of the side of the first sub-sidewall 61 away from the source line layer 90. In this embodiment, the first split gate structure T1 and the second split gate structure T2 are symmetrically arranged with the source line layer 90 as the center. In the figure, for the convenience of illustration, the first split gate structure T1 and the second split gate structure T2 are simply circled with a rectangular virtual frame, wherein the circled part does not mean that all of them belong to the first split gate structure T1 and the second split gate structure T2. For the specific parts included in the first split gate structure T1 and the second split gate structure T2, please refer to the text description of this embodiment.

[0049] Furthermore, two drain regions 82 are included, each located in the substrate 10 outside each word line gate 100, that is, located in the substrate 10 outside the word line gate 100 of the first split gate structure T1 and the word line gate 100 of the second split gate structure T2.

[0050] Furthermore, it also includes a passivation layer, a source electrical connector and an erase gate electrical connector (all not shown in the figures), wherein the passivation layer covers the first sub-gate structure T1, the second sub-gate structure T2, the source line layer 90 and the substrate 10, the source electrical connector penetrates the passivation layer and is electrically connected to the source line layer 90, the erase gate electrical connector penetrates the passivation layer and the first sub-side wall 61 and is electrically connected to the erase gate 41, and in addition, a first floating gate electrical connector, a word line gate electrical connector and a drain region electrical connector (all not shown in the figures) are formed and are electrically connected to the first floating gate 31, the word line gate 100 and the drain region 82 respectively.

[0051] In this embodiment, when the split-gate flash memory cell is erased, the erase gate 41 is connected to a higher positive voltage, and the others are kept at zero potential. Erasing is performed by electron tunneling from the first floating gate 31 and the second floating gate 32 to the erase gate 41, so as to pull electrons out from the first floating gate 31 and the second floating gate 32 through the tunneling oxide layer 22; when the split-gate flash memory cell is read, the word line gate 100 is connected to the power supply voltage VDD, the source region 81 is connected to the read voltage, and the others are kept at zero potential to achieve reading; when the split-gate flash memory cell is written, the word line gate 100 is connected to the power supply voltage VDD, the source region 81 is connected to the write voltage, and the source line layer 90 and the erase gate 41 are connected to a positive voltage to achieve writing.

[0052] In the present embodiment, erasing is performed through the erase gate 41 above the first floating gate 31. During erasing, the erase gate 41 is connected to a high voltage, and erasing is performed through electron tunneling from the first floating gate 31 and the second floating gate 32 to the erase gate 41. The source region 81 is electrically connected to the source line layer 90, that is, the source region 81 is led out through the source line layer 90. When the subsequent interconnection process is performed, it is not necessary to form a source electrical connector that passes through the erase gate 41. The source electrical connector is directly electrically connected to the source line layer 90. On the one hand, the source contact resistance (that is, the interconnection contact resistance) can be reduced. On the other hand, the positions of the source electrical connector and the erase gate electrical connector on the interconnection layout are separated, which can simplify the interconnection process of the source electrical connector and the erase gate electrical connector, as well as the preparation process. In addition, the second floating gate 32 and the source line layer 90 have a larger coupling surface, which can reduce the width of the first floating gate 31, which is conducive to reducing the area of ​​the split-gate flash memory unit.

[0053] In this embodiment, a plurality of split-gate flash memory cells are used to form a split-gate flash memory device, and how the plurality of split-gate flash memory cells are arranged is not limited in this description.

[0054] Figure 2 This is a flow chart of the method for preparing a split-gate flash memory cell provided in this embodiment. Figure 2 This embodiment provides a method for preparing a split-gate flash memory cell, comprising:

[0055] Step S1: providing a substrate; and,

[0056] Step S2: forming a first split gate structure and a second split gate structure on the substrate, and both include a first floating gate, a second floating gate and an erase gate, the erase gate covers a portion of the top surface of the first floating gate, the second floating gate covers the side of the first floating gate and extends upward to cover the side of the erase gate, and the second floating gate is in direct contact with the first floating gate, forming a source line layer on the substrate between the first split gate structure and the second split gate structure, and the two second floating gates respectively cover one side of the source line layer, forming a source region in the substrate below the source line layer, and electrically connected to the source line layer.

[0057] Figures 3A to 3HThe cross-sectional schematic diagram of the corresponding steps in the method for preparing the split-gate flash memory cell provided in this embodiment is shown below in conjunction with Figures 3A to 3H The method for preparing the split-gate flash memory cell provided in this embodiment is described in detail.

[0058] Please refer to Figure 3A , perform step S1: provide a substrate 10, the material of the substrate 10 includes one or more of silicon, germanium, gallium, nitrogen or carbon.

[0059] The step of performing step S2: forming a first split gate structure, a second split gate structure, a source line layer and a source region comprises:

[0060] Please continue to refer to Figure 3A A gate oxide layer 21, a first floating gate material layer 30, a tunnel oxide layer 22, an erase gate material layer 40 and a mask layer 50 are sequentially formed on a substrate 10, wherein the first floating gate material layer 30 and the erase gate material layer 40 are made of polysilicon. In this embodiment, the thicknesses of the gate oxide layer 21, the first floating gate material layer 30, the tunnel oxide layer 22, the erase gate material layer 40 and the mask layer 50 are not limited, and the specific thicknesses depend on actual conditions.

[0061] Then, the mask layer 50, the erase gate material layer 40, the tunnel oxide layer 22, the first floating gate material layer 30 and the gate oxide layer 21 are sequentially etched to form an opening exposing the substrate 10. The steps of forming the opening specifically include:

[0062] Please refer to Figure 3B , the mask layer 50 is etched to form a first opening 71 exposing the erase gate material layer 40 , and a first sub-spacer 61 is formed on a sidewall of the first opening 71 .

[0063] Please refer to Figure 3C , using the first sub-spacer 61 as a mask, the gate material layer 40 and the tunnel oxide layer 22 are etched and erased to form a second opening 72 exposing the first floating gate material layer 30, and a second sub-spacer 62 is formed on the sidewall of the second opening 72, and the second sub-spacer 62 extends to cover at least a portion of the surface of the first sub-spacer 61.

[0064] Please refer to Figure 3D , the first floating gate material layer 30 is etched with the first sub-spacer 61 and the second sub-spacer 62 as masks to form a third opening 73 exposing the substrate 10, and the first opening 71, the second opening 72 and the third opening 73 are connected to form an opening. In this embodiment, due to the existence of the gate oxide layer 21, after etching, the gate oxide layer 21 at the bottom of the third opening 73 is retained (such as Figure 3D), that is, using the first sub-spacer 61 and the second sub-spacer 62 as a mask, the first floating gate material layer 30 is etched to form a third opening 73 exposing the gate oxide layer 21, and then, a second floating gate 32 is formed on the sidewall of the third opening 73, and the second floating gate 32 extends to cover at least a portion of the surface of the second sub-spacer 62; and, ion implantation is performed on the substrate 10 at the bottom of the third opening 73 to form a source region 81 in the substrate 10 at the bottom of the third opening 73.

[0065] Please refer to Figure 3E , firstly etch and remove the gate oxide layer 21 at the bottom of the third opening 73 ( Figure 3E The gate oxide layer 21 at the bottom of the third opening 73 no longer exists in the substrate 10, so that the third opening 73 extends to the surface of the substrate 10. Further, a third sub-spacer 63 is formed on the surface of the second floating gate 32, and the third sub-spacer 63 extends to cover the side surface of the gate oxide layer 21 close to the third opening 73 and at least a portion of the surface of the second sub-spacer 62. The first sub-spacer 61, the second sub-spacer 62 and the third sub-spacer 63 constitute a first spacer.

[0066] Please refer to Figure 3F After the openings are formed, the source line layer 90 is filled in the openings, that is, the source line layer 90 is filled in the first opening 71, the second opening 72 and the third opening 73. The source region 81 is located in the substrate 10 below the source line layer 90. The source region 81 is in direct contact with the source line layer 90 so that the source region 81 is electrically connected to the source line layer 90. In the present embodiment, the material of the source line layer 90 is preferably polysilicon. In the subsequent process, a metal silicide layer is formed on the surface of the source line layer 90, which is beneficial to reduce the contact resistance.

[0067] Please continue to refer to Figure 3F and reference Figure 3G , the mask layer 50 and the erase gate material layer 41, the tunnel oxide layer 22, the first floating gate material layer 30 and the gate oxide layer 21 directly below the mask layer 50 are etched away, and the etching stops at the surface of the substrate 10; after etching, the remaining first floating gate material layer 30 on each side of the source line layer 90 is respectively used as a first floating gate 31, and the remaining erase gate material layer 41 on each side of the source line layer 90 is respectively used as an erase gate 41, and the first floating gate 31 is directly in contact with the second floating gate 32 to be electrically connected.

[0068] Please refer to Figure 3HAfter forming the first floating gate 31 and the erase gate 41, the method further includes: forming a second sidewall 64 on a side of each erase gate 41 and the first floating gate 31 away from the source line layer 90, and the second sidewall 64 covers the side of the tunneling oxide layer 22 and the gate oxide layer 21 away from the source line layer 90 and at least a portion of the side of the first sub-sidewall 61 away from the source line layer 90; forming a word line oxide layer 23 on a portion of the surface of each second sidewall 64, and the word line oxide layer 23 covers a portion of the surface of the substrate 10; and forming a word line gate 100 on the remaining surface of each second sidewall 64, the word line gate 100 is located on the word line oxide layer 23, and can extend to cover a portion of the side of the first sub-sidewall 61 away from the source line layer 90.

[0069] For further information, please refer to Figure 3H After forming the word line gate 100, the method further includes: performing ion implantation on the substrate 10 outside each word line gate 100 to form two drain regions 82 in the substrate 10. Before or after forming the drain region 82, a third spacer (not shown) is formed on the surface of each word line gate 100.

[0070] Furthermore, after forming the drain region 82, a passivation layer (not shown in the figure) is formed to cover the first sub-gate structure T1, the second sub-gate structure T2, the source line layer 90 and the substrate 10, a source electrical connector (not shown in the figure) is formed to penetrate the passivation layer and be electrically connected to the source line layer 90, an erase gate electrical connector (not shown in the figure) is formed to penetrate the passivation layer and the first sub-side wall 61 and be electrically connected to the erase gate 41, and in addition, a first floating gate electrical connector, a word line gate electrical connector and a drain region electrical connector (not shown in the figure) are formed to be electrically connected to the first floating gate 31, the word line gate 100 and the drain region 82, respectively.

[0071] In the present embodiment, erasing is performed through the erase gate 41 above the first floating gate 31. During erasing, the erase gate 41 is connected to a high voltage, and erasing is performed through electron tunneling from the first floating gate 31 and the second floating gate 32 to the erase gate 41. The source region 81 is electrically connected to the source line layer 90, that is, the source region 81 is led out through the source line layer 90. When the subsequent interconnection process is performed, it is not necessary to form a source electrical connector that passes through the erase gate 41. The source electrical connector is directly electrically connected to the source line layer 90. On the one hand, the source contact resistance (that is, the interconnection contact resistance) can be reduced. On the other hand, the positions of the source electrical connector and the erase gate electrical connector on the interconnection layout are separated, which can simplify the interconnection process of the source electrical connector and the erase gate electrical connector, as well as the preparation process. In addition, the second floating gate 32 and the source line layer 90 have a larger coupling surface, which can reduce the width of the first floating gate 31, which is conducive to reducing the area of ​​the split-gate flash memory unit.

[0072] In summary, in the split-gate flash memory cell and its preparation method provided by the present invention, the first split-gate structure and the second split-gate structure are located on the substrate, and both include a first floating gate, a second floating gate and an erase gate, the erase gate covers part of the top surface of the first floating gate, the second floating gate covers the side of the first floating gate and extends upward to cover the side of the erase gate, and the second floating gate is in direct contact with the first floating gate; the source line layer is located on the substrate between the first split-gate structure and the second split-gate structure, and the two second floating gates respectively cover one side of the source line layer; the source region is located in the substrate below the source line layer and is electrically connected to the source line layer. In the present invention, erasing is performed through the erase gate above the first floating gate, the source region is electrically connected to the source line layer, and when the interconnection process is performed later, the source region is led out through the source line layer, which can reduce the source contact resistance (i.e., the interconnection contact resistance), simplify the interconnection process and the preparation process; and the second floating gate covers the side of the source line layer, which increases the coupling area between the source line layer and the second floating gate, can reduce the width of the first floating gate, and is conducive to reducing the area of ​​the split-gate flash memory cell.

[0073] The above is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any technician in the relevant technical field, without departing from the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which does not depart from the content of the technical solution of the present invention and still falls within the protection scope of the present invention.

Claims

1. A split-gate flash memory cell, characterized in that: include: substrate; A first split gate structure and a second split gate structure are located on the substrate and both include a first floating gate, a second floating gate and an erase gate, wherein the erase gate covers a portion of the top surface of the first floating gate, the second floating gate covers the side surface of the first floating gate and extends upward to cover the side surface of the erase gate, and the second floating gate is in direct contact with the first floating gate; A source line layer is located on the substrate between the first split gate structure and the second split gate structure, and two second floating gates respectively cover one side of the source line layer; The source region is located in the substrate below the source line layer and is electrically connected to the source line layer.

2. The split-gate flash memory cell according to claim 1, wherein: The first split gate structure and the second split gate structure also include a first side wall, which covers the top surface of the erase gate, the remaining top surface of the first floating gate and the side surface of the second floating gate close to the source line layer, and part of the first side wall is located between the erase gate and the second floating gate.

3. The split-gate flash memory cell according to claim 1, wherein: The first split gate structure and the second split gate structure also include a second sidewall and a word line gate. The second sidewall covers the corresponding side of the first floating gate and the erase gate away from the source line layer, and the word line gate covers the surface of the corresponding second sidewall.

4. The split-gate flash memory cell according to claim 3, wherein: The invention also comprises two drain regions, which are respectively located in the substrate outside each word line gate.

5. The split-gate flash memory cell according to claim 1, wherein: The material of the source line layer includes polysilicon.

6. A method for preparing a split-gate flash memory cell, characterized in that: include: providing a substrate; as well as, A first split gate structure and a second split gate structure are formed on the substrate, and both include a first floating gate, a second floating gate and an erase gate, the erase gate covers a portion of the top surface of the first floating gate, the second floating gate covers the side of the first floating gate and extends upward to cover the side of the erase gate, and the second floating gate is in direct contact with the first floating gate, a source line layer is formed on the substrate between the first split gate structure and the second split gate structure, and two second floating gates respectively cover one side of the source line layer, forming a source region in the substrate below the source line layer, and electrically connected to the source line layer.

7. The method for preparing a split-gate flash memory cell according to claim 6, wherein: The steps of forming the first floating gate, the erase gate, the source line layer and the source region include: forming a first floating gate material layer, an erase gate material layer and a mask layer in sequence on the substrate; Sequentially etching the mask layer, the erase gate material layer, and the first floating gate material layer to form an opening exposing the substrate; performing ion implantation on the substrate at the bottom of the opening to form the source region in the substrate at the bottom of the opening; Filling the opening with the source line layer, wherein the source line layer is electrically connected to the source region; and The mask layer and the first floating gate material layer and the erase gate material layer directly below the mask layer are removed by etching, and the remaining first floating gate material layer on each side of the source line layer is used as a first floating gate, and the remaining erase gate material layer on each side of the source line layer is used as an erase gate.

8. The method for preparing a split-gate flash memory cell according to claim 7, characterized in that: The step of forming the opening and the second floating gate comprises: Etching the mask layer to form a first opening exposing the erase gate material layer; forming a first sub-spacer on the sidewall of the first opening; Using the first sub-spacer as a mask, etching the erase gate material layer to form a second opening exposing the first floating gate material layer; forming a second sub-spacer on the sidewall of the second opening, wherein the second sub-spacer covers at least a portion of the surface of the first sub-spacer; Using the first sub-spacer and the second sub-spacer as a mask, etching the first floating gate material layer to form a third opening exposing the substrate, wherein the first opening, the second opening and the third opening are connected to form the opening; forming a second floating gate on the sidewall of the third opening, wherein the second floating gate covers at least a portion of the surface of the second sub-spacer; and, A third sub-spacer is formed on the surface of the second floating gate, and the first sub-spacer, the second sub-spacer and the third sub-spacer constitute a first spacer.

9. The method for preparing a split-gate flash memory cell according to claim 7, wherein: After forming the first floating gate and the erase gate, the method further includes: forming a second spacer on a side of each of the erase gates and the first floating gate away from the source line layer; and, A word line gate is formed on a surface of each of the second spacers.

10. The method for preparing a split-gate flash memory cell according to claim 9, wherein: After forming the word line gate, the method further includes: Ion implantation is performed on the substrate outside each word line gate to form a drain region in the substrate.

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