Methods for forming microelectronic devices and related microelectronic devices, memory devices and electronic systems

Abstract

This application relates to methods for forming microelectronic devices and related microelectronic devices, memory devices, and electronic systems. The method for forming a microelectronic device includes forming a microelectronic device structure. The microelectronic device structure includes: a stacked structure having an alternating sequence of conductive and insulating structures; an upper stadium-like structure; a lower stadium-like structure; and a peak region defined between a first stepped structure of the upper stadium-like structure and a second stepped structure of the lower stadium-like structure. The stacked structure further includes: pillar structures extending through the stacked structure; and dielectric structures inserted between adjacent pillar structures within the upper stadium-like structure. The method further includes forming a trench in the peak region of the stacked structure between two dielectric structures on the opposite side of another dielectric structure; and filling the trench with a dielectric material. The trench partially overlaps with the dielectric structure.

Description

[0001] Priority requirements

[0002] This application claims the benefit of the filing date of U.S. Patent Application No. 17 / 153,740, entitled “Methods of Forming Microelectronic Devices, and Related Microelectronic Devices, Memory Devices, and Electronic Systems,” filed January 20, 2021. Technical Field

[0003] In various embodiments, this disclosure generally relates to the field of microelectronic device design and fabrication. More specifically, this disclosure relates to methods of forming microelectronic devices and related microelectronic devices, memory devices, and electronic systems. Background Technology

[0004] A persistent goal of the microelectronics industry is to increase the memory density (e.g., the number of memory cells per memory die) of memory devices, such as non-volatile memory devices (e.g., NAND flash memory devices). One way to increase memory density in non-volatile memory devices is to utilize vertical memory array (also known as “three-dimensional (3D) memory array”) architectures. A conventional vertical memory array comprises vertical memory strings extending through openings in one or more stacks (e.g., stacked structures) containing conductive structures and dielectric material layers. Each vertical memory string may contain at least one selection device series-coupled to a series combination of vertically stacked memory cells. Compared to structures with a conventional planar (e.g., two-dimensional) transistor arrangement, this configuration allows for a greater number of switching devices (e.g., transistors) to be located in cells (i.e., the length and width of the active surface consumed) of the die region by constructing the array upwards (e.g., vertically) on the die.

[0005] A vertical memory array architecture generally comprises a hierarchy of conductive structures in the stack of memory devices (e.g., a stacked structure) and electrical connections between access lines (e.g., word lines), allowing for unique selection of memory cells in the vertical memory array for write, read, or erase operations. One method of forming this electrical connection involves forming a so-called “step” (or “staircase”) structure at the edges (e.g., horizontal ends) of the stack of memory devices. The staircase structure includes individual “steps” defining contact areas of conductive structures, on which conductive contact structures can be positioned to provide electrical access to the conductive structures.

[0006] With advancements in vertical memory array technology, increased memory density is achieved by forming memory devices to enable multiple stack configurations (e.g., dual stacks). For example, in a conventional dual stack configuration, some vertical memory strings reside in an upper stack (e.g., an upper stack structure), and additional vertical memory strings reside in a lower stack (e.g., a lower stack structure) below the upper stack. The vertical memory strings in the upper stack may be electrically coupled to the additional vertical memory strings in the lower stack (e.g., via conductive interconnect structures), or the vertical memory strings in the upper stack may be electrically isolated from the additional vertical memory strings in the lower stack (e.g., via an intermediate dielectric material). Disadvantageously, with increasing feature package density and decreasing fabrication tolerances, conventional memory device fabrication methods and associated configurations introduce undesirable stresses (e.g., access line contacts exceeding etch stress), defects (e.g., access line contact punch-through), and current leakage (e.g., select gate current leakage, access line current leakage), which can degrade the desired memory device performance, reliability, and durability. Summary of the Invention

[0007] Embodiments of this disclosure include a method of forming a microelectronic device. The method includes forming a microelectronic device structure. The microelectronic device structure includes a stacked structure having a vertically alternating sequence of conductive and insulating structures arranged in layers. The stacked structure comprises a stacked structure including a vertically alternating sequence of conductive and insulating structures arranged in layers, the stacked structure being divided into blocks separated from each other by filling trenches. Each block includes an upper stadium-like structure, a lower stadium-like structure, and a peak region between a first stepped structure of the upper stadium-like structure and a second stepped structure of the lower stadium-like structure. The microelectronic device structure further includes a dielectric structure extending parallel through the upper stadium-like structure and into the peak region, the dielectric structure extending vertically through and segmenting some layers of conductive structures to form an upper select gate. The method further includes forming trenches to extend between and partially overlap two dielectric structures in at least the peak region of one or more blocks of the stacked structure, and filling the trenches at least substantially with a dielectric material.

[0008] Additional embodiments of this disclosure include a microelectronic device. The microelectronic device includes a stacked structure comprising a vertically alternating sequence of hierarchically arranged conductive and insulating structures, the stacked structure being divided into blocks separated from each other by filler slots. Each block includes: an upper stadium-like structure including a first stepped structure with a negative slope facing an additional first stepped structure with a positive slope; a lower stadium-like structure including a second stepped structure with a negative slope facing an additional second stepped structure with a positive slope; and a peak region horizontally inserted between the additional first stepped structure of the upper stadium-like structure and the second stepped structure of the lower stadium-like structure. The microelectronic device further includes: a dielectric-filled trench extending horizontally parallel through an upper stadium-like structure and into a peak region, the dielectric-filled trench extending vertically through several layers of conductive structures and physically separating the conductive structures to define an upper select gate for each of the stacked structural blocks; and at least one additional dielectric-filled trench in at least a peak region of one or more blocks of the stacked structure, the at least one additional dielectric-filled trench extending horizontally between two dielectric-filled trenches within the horizontal boundaries of the one or more blocks and partially overlapping the two dielectric-filled trenches.

[0009] Other embodiments of this disclosure include a memory device comprising a stacked structure comprising a vertically alternating sequence of hierarchically arranged conductive and insulating structures. The stacked structure includes an upper segmented stadium-like structure comprising: opposing stepped structures, each step having a step, the step including edges of some layers of the stacked structure; and a bridge structure adjacent to a horizontal boundary of the opposing stepped structures in a first horizontal direction and including portions of some layers, the portions extending from the opposing stepped structures and between the opposing stepped structures in a second horizontal direction orthogonal to the first horizontal direction. The stacked structure further includes: a lower segmented stadium-like structure adjacent to the upper segmented stadium-like structure in the second horizontal direction; and a peak region inserted between the upper and lower segmented stadium-like structures in the second horizontal direction. The memory device further includes: a dielectric fill trench structure extending parallel to the upper stadium-like structure in a second horizontal direction, the dielectric fill trench structure extending vertically through several layers of conductive structures and separating the conductive structures to define an upper select gate; at least one fill trench extending horizontally in the second horizontal direction through the peak region of the stacked structure and reaching the dielectric fill trench structure, the at least one fill trench being inserted between a pair of dielectric fill trenches in a first horizontal direction; and a memory cell string extending vertically through the stacked structure.

[0010] Further embodiments of this disclosure include an electronic system. The electronic system includes an input device; an output device; a processor device operatively coupled to the input device and the output device; and a memory device operatively coupled to the processor device and including a microelectronic device structure. The microelectronic device structure includes a stacked structure comprising a vertically alternating sequence of hierarchically arranged conductive and insulating structures. The stacked structure may include a stadium-like structure having steps, the steps including horizontal ends of a group of drain-select gates between a dielectric-filled trench structure inserted into the stacked structure and a peak region extending horizontally from the uppermost staircase of the stadium-like structure. The memory device further includes a filling trench extending vertically through at least the peak region of the stacked structure, the filling trench electrically isolating a first group of drain-select gates from a second group of drain-select gates. Attached Figure Description

[0011] Figures 1A to 1D These are various views of a microelectronic device at a stage of a method for forming a microelectronic device according to embodiments of the present disclosure;

[0012] Figures 2A to 2C At another stage of the method for forming microelectronic devices Figures 1A to 1D Various views of a microelectronic device;

[0013] Figures 3A to 3C At another stage of the method for forming microelectronic devices Figures 1A to 1D Various views of a microelectronic device;

[0014] Figures 4A to 4C At another stage of the method for forming microelectronic devices Figures 1A to 1D Various views of a microelectronic device;

[0015] Figures 5A to 5C At another stage of the method for forming microelectronic devices Figures 1A to 1D Various views of a microelectronic device;

[0016] Figure 6 This is a partial cross-sectional perspective view of a microelectronic device according to an embodiment of the present disclosure;

[0017] Figure 7 These are schematic block diagrams illustrating electronic systems according to embodiments of the present disclosure; and

[0018] Figure 8 This is a schematic block diagram of a processor-based system according to embodiments of the present disclosure. Detailed Implementation

[0019] The following description provides specific details, such as material composition, shape, and size, to provide a sufficient description of embodiments of this disclosure. However, those skilled in the art will understand that embodiments of this disclosure can be practiced without these specific details. In fact, embodiments of this disclosure can be practiced in conjunction with conventional microelectronic device manufacturing techniques used in the industry. Furthermore, the description provided below does not form a complete process flow for manufacturing microelectronic devices (e.g., memory devices, such as 3D NAND flash memory devices). The structures described below do not form a complete microelectronic device. Only those process actions and structures necessary for understanding embodiments of this disclosure are described in detail below. Additional actions for forming a complete microelectronic device from said structures can be performed using conventional manufacturing techniques.

[0020] The accompanying drawings presented herein are for illustrative purposes only and are not intended to be actual views of any particular material, component, structure, device, or system. The shapes depicted in the drawings are expected to vary due to, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments described herein should not be construed as limited to the specific shapes or areas illustrated, but should include, for example, shape variations caused by manufacturing processes. For instance, areas illustrated or described as box-shaped may have rough and / or non-linear characteristics, and areas illustrated or described as circular may include some rough and / or linear characteristics. Furthermore, acute angles shown may be rounded, and vice versa. Therefore, the areas illustrated in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shape of the areas and do not limit the scope of the claims. The drawings are not necessarily drawn to scale. Additionally, common elements between figures may retain the same numerical designations.

[0021] As used herein, “memory device” means and includes, but is not limited to, microelectronic devices that exhibit memory functionality. In other words, by way of non-limiting example only, the term “memory device” includes not only conventional memory (e.g., conventional volatile memory, such as conventional DRAM; conventional non-volatile memory, such as conventional NAND memory), but also application-specific integrated circuits (ASICs) (e.g., system-on-a-chip (SoC)), combinational logic and memory of microelectronic devices, and graphics processing units (GPUs) incorporating memory.

[0022] As used herein, the terms “vertical,” “longitudinal,” “horizontal,” and “lateral” refer to the principal plane of the structure and are not necessarily defined by the Earth’s gravitational field. A “horizontal” or “lateral” direction is a direction substantially parallel to the principal plane of the structure, while a “vertical” or “longitudinal” direction is a direction substantially perpendicular to the principal plane of the structure. The principal plane of the structure is defined by structural surfaces having a relatively large area compared to the other surfaces of the structure. Referring to the figures, a “horizontal” or “lateral” direction may be perpendicular to the indicated “Z” axis and parallel to the indicated “X” axis and / or parallel to the indicated “Y” axis; and a “vertical” or “longitudinal” direction may be parallel to the indicated “Z” axis, perpendicular to the indicated “X” axis, and perpendicular to the indicated “Y” axis.

[0023] As used herein, features described as “adjacent” to each other (e.g., regions, structures, devices) refer to and include features of the disclosed identifiers (or identifiers) located closest to each other (e.g., closest to each other). Additional features (e.g., additional regions, additional structures, additional devices) of the disclosed identifiers (or identifiers) that do not match “adjacent” features may be positioned between “adjacent” features. In other words, “adjacent” features may be positioned directly adjacent to each other such that no other features intervene between “adjacent” features; or “adjacent” features may be positioned indirectly adjacent to each other such that at least one feature having an identifier other than the identifier associated with at least one “adjacent” feature is located between “adjacent” features. Thus, features described as “vertically adjacent” to each other refer to and include features of the disclosed identifiers (or identifiers) located closest to each other (e.g., vertically closest to each other). Furthermore, features described as “horizontally adjacent” to each other refer to and include features of the disclosed identifiers (or identifiers) located closest to each other (e.g., horizontally closest to each other).

[0024] As used herein, for ease of description, spatially relative terms such as “below,” “under,” “lower,” “bottom,” “above,” “top,” “front,” “back,” “left,” “middle,” and “right” are used to describe the relationship of an element or feature to another element or feature as shown in the figure. Unless otherwise specified, spatially relative terms are intended to cover different orientations of material other than those depicted in the figure. For example, if the material in the figure is reversed, an element described as being “below,” “under,” “below,” or “on the bottom” of another element or feature will be oriented “above” or “on the top” of said other element or feature. Thus, the term “below” may encompass both above and below orientations, depending on the context in which the term is used, as will be apparent to those skilled in the art. Material may be oriented in other ways (e.g., rotated 90 degrees, inverted, flipped), and the spatially relative descriptive terms used herein will be interpreted accordingly.

[0025] As used herein, unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well.

[0026] As used herein, “and / or” includes any and all combinations of one or more of the associated listed items.

[0027] As used herein, the term “configured” refers to the size, shape, material composition, orientation, and arrangement of at least one feature (e.g., at least one structure, at least one area, at least one device) that facilitates the operation of at least one feature in a predetermined manner.

[0028] As used herein, the phrase “coupled to” refers to structures that are operatively connected to each other, such as by direct ohmic connection or by indirect connection (e.g., by means of another structure) electrical connection.

[0029] As used herein, the term "substantially" with respect to a given parameter, property, or condition means and includes the degree to which a given parameter, property, or condition conforms to deviations (such as within acceptable tolerances) as would be understood by one of ordinary skill in the art. As an example, depending on the specific parameter, property, or condition that is substantially satisfied, it may satisfy at least 90.0%, at least 95.0%, at least 99.0%, at least 99.9%, or even 100.0%.

[0030] As used herein, the term "about" or "approximately" when referring to a value for a particular parameter includes that value, and those skilled in the art will understand that deviations from that value are within acceptable tolerances for the particular parameter. For example, "about" or "approximately" may include additional values ​​within 90.0% to 110.0% of the value, such as within 95.0% to 105.0%, 97.5% to 102.5%, 99.0% to 101.0%, 99.5% to 100.5%, or 99.9% to 100.1%.

[0031] As used herein, a material is “selectively etchable” relative to the other material if it exhibits an etch rate at least about five times (5x), such as about ten times (10x), about twenty times (20x), or about forty times (40x) greater than that of another material when exposed to the same etchant (e.g., etchant).

[0032] As used herein, the term "uniform" means that the relative amounts of elements contained in a feature (e.g., material, structure) do not change throughout the different parts of the feature (e.g., different horizontal parts, different vertical parts). Conversely, as used herein, the term "non-uniform" means that the relative amounts of elements contained in a feature (e.g., material, structure) change throughout the different parts of the feature. If a feature is non-uniform, the amounts of one or more elements contained in the feature may change gradually (e.g., abruptly) or may change continuously throughout the different parts of the feature (e.g., gradually, such as linearly or parabolically). A feature may, for example, be formed by and contain a stack of at least two different materials.

[0033] Unless otherwise indicated, the materials described herein may be formed using conventional techniques including, but not limited to, spin coating, blanket coating, chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-enhanced ALD, physical vapor deposition (PVD) (including sputtering, evaporation, ionization PVD, and / or plasma-enhanced CVD), or epitaxial growth. Alternatively, the material may be grown in situ. Depending on the specific material to be formed, the technique used for depositing or growing the material may be selected by those skilled in the art. Unless the context otherwise indicates, material removal may be achieved by any suitable technique including, but not limited to, etching (e.g., dry etching, wet etching, vapor phase etching), ion milling, planarization (e.g., chemical-mechanical planarization), or other known methods. Those skilled in the art may select the etching chemicals and etching conditions used to etch the desired material.

[0034] As used herein, the term "insulating material" includes at least one dielectric oxide material (e.g., silicon oxide (SiO2)). x Phossilicate glass, borosilicate glass, borosilicate-phosphorus glass, fluorosilicate glass, alumina (AlO) x ), Hafnium oxide (HfO) x ), niobium oxide (NbO) x Titanium oxide (TiO) x Zirconium oxide (ZrO) x ), tantalum oxide (TaO) x ) and magnesium oxide (MgO) x One or more of the following), at least one dielectric nitride material (e.g., silicon nitride (SiN) y ()), at least one dielectric oxide nitride material (e.g., silicon oxynitride (SiO) x N y and at least one dielectric carbon oxynitride material (e.g., silicon carbon oxynitride (SiO2)). x C z Ny One or more of the following: . This document contains one or more of the chemical formulas selected from "x", "y", and "z" (e.g., SiO2). x AlO x HfO x NbO x TiO x SiN y SiO x N y SiO x C z N y The chemical formula represents a material containing “x” atoms of one element, “y” atoms of another element, and “z” atoms of an additional element (if present) relative to each atom of another element (e.g., Si, Al, Hf, Nb, Ti). Because chemical formulas represent relative atomic ratios and non-strict chemical structures, insulating structure 162 may include one or more stoichiometric compounds and / or one or more non-stoichiometric compounds, and the values ​​of “x,” “y,” and “z” (if present) may be integers or non-integers. As used herein, the term “non-stoichiometric compound” means and includes compounds composed of an element that cannot be expressed by a ratio of clearly defined natural numbers and violates the law of definite proportions.

[0035] As used herein, the term "conductive material" includes one or more of the following: metals (e.g., tungsten (W), titanium (Ti), molybdenum (Mo), niobium (Nb), vanadium (V), hafnium (Hf), tantalum (Ta), chromium (Cr), zirconium (Zr), iron (Fe), ruthenium (Ru), osmium (Os), cobalt (Co), rhodium (Rh), iridium (Ir), nickel (Ni), palladium (Pa), platinum (Pt), copper (Cu), silver (Ag), gold (Au), aluminum (Al)); alloys (e.g., Co Basic alloys, Fe-based alloys, Ni-based alloys, Fe and Ni-based alloys, Co and Ni-based alloys, Fe and Co-based alloys, Co and Ni and Fe-based alloys, Al-based alloys, Cu-based alloys, Magnesium (Mg)-based alloys, Ti-based alloys, steel, low-carbon steel, stainless steel); containing metallic materials (e.g., metal nitrides, metal silicides, metal carbides, metal oxides); including titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), iridium oxide (IrO). x ), Ruthenium oxide (RuO) x Materials comprising at least one of the following alloys: conductive doped semiconductor materials (e.g., conductive doped polysilicon, conductive doped germanium (Ge), conductive doped silicon germanium (SiGe)); polysilicon; other materials exhibiting conductivity; or combinations thereof.

[0036] Embodiments of this disclosure include microelectronic device structures for microelectronic devices (e.g., memory devices), and related microelectronic devices (e.g., memory devices), electronic systems, and methods. In some embodiments, the microelectronic device structures of this disclosure include a stacked structure having a vertically alternating sequence of hierarchically arranged conductive and insulating structures. The stacked structure further includes: an upper segmented stadium-like structure comprising a first stepped structure with a negative slope facing an additional first stepped structure with a positive slope (e.g., opposite, mirror image); a lower segmented stadium-like structure comprising a second stepped structure with a negative slope facing an additional second stepped structure with a positive slope; and a peak region defined between the additional first stepped structure of the upper segmented stadium-like structure and the second stepped structure of the lower segmented stadium-like structure. The microelectronic device further includes: a support pillar structure extending vertically through the stacked structure; a dielectric fill trench structure inserted between horizontally adjacent support pillar structures within the horizontal boundary of the upper segmented stadium-like structure; and a fill trench extending vertically through at least the peak region of the stacked structure. The fill trench may be formed on the opposite side of another dielectric fill trench structure within the dielectric fill trench structure, between the two dielectric fill trench structures, and may separate a first set of upper select gates and a second set of upper select gates of the upper stadium-like structure within at least a portion of the peak region.

[0037] Trenches filled with dielectric material can provide advantages over other methods attempting to separate a first set of upper select gates (e.g., drain-side select gates (SGD)) from a second set of upper select gates associated with an upper segmented stadium-like structure (e.g., having contact regions therein) within the peak region of the microelectronic device structure. For example, due to the raised bridge portion of the segmented stadium-like structure of the microelectronic device structure, short-circuit paths between the first and second sets of upper select gates may exist in the peak region between the upper segmented stadium-like structure and a horizontally adjacent segmented stadium-like structure below it, and at least one filling trench may interfere with (e.g., remove) these short-circuit paths. For example, a filling trench may be formed in the peak region of the microelectronic device structure between the first and second sets of upper select gates. Because the filling trench extends into the peak region and extends between the first and second sets of upper select gates, it physically and electrically separates portions of the first drain-side SGD and portions of the second set of upper select gates within the peak region. Therefore, the filling trench can remove the short-circuit path between the first set of upper select gates and the second set of upper select gates in the peak region. Thus, the filling trench prevents individual select gates in the first set of upper select gates from short-circuiting with other individual select gates in the second set of upper select gates across the peak region.

[0038] Furthermore, the trenches described herein are superior to forming horizontal barriers within the peak region (e.g., within the peak in a direction parallel to the horizontal length of a given step in a stadium-like structure) to prevent short circuits across the peak region. For example, forming barriers in the aforementioned direction (e.g., patterning in the aforementioned direction) can present challenges in maintaining critical dimensions due to manufacturing limitations, and when patterning in the aforementioned direction results in critical dimensions (e.g., ... Figure 1A As the X-direction increases, the risk of under-etching and over-etching also increases.

[0039] Furthermore, forming trenches does not require the formation of relatively small features. Additionally, typical manufacturing processes do not involve significant structural changes (e.g., processing) within the microelectronic device structure after trench formation. Moreover, trench formation can be relatively precise using eight, ten, fifteen, or more layers of stacked structures.

[0040] As described in more detail below, from Figures 1A to 1D to Figure 2A To 2XC Figures 3A to 3C to Figures 4A to 4C to Figures 5A to 5CThe sequence of descriptions illustrates embodiments of methods for forming microelectronic devices (e.g., memory devices, such as 3D NAND flash memory devices). Microelectronic device structure 100 may, for example, include a portion of a memory device (e.g., a multi-stacking 3D NAND flash memory device, such as a dual-stacking 3D NAND flash memory device). In conjunction with the description provided below, it will be apparent to those skilled in the art that the methods and structures described herein can be used in various devices and electronic systems.

[0041] Figures 1A to 1D Various views of the microelectronic device structure 100 at the stage of forming the microelectronic device are shown. Figure 1A This is a simplified perspective view of a microelectronic device 100 according to an embodiment of the present disclosure. The microelectronic device structure 100 may represent a structure following (e.g., after) one or more so-called “alternate gate” or “gate persistence” processes. For example, the microelectronic device structure 100 may include a structure formed by at least partially replacing a sacrificial material (e.g., a dielectric material, such as a dielectric nitride material) of a sacrificial structure with one or more conductive materials (e.g., at least one metal, such as tungsten (W)). The alternative gate processing action may include selectively removing (e.g., selectively etching and / or digging out) portions of the sacrificial structure of the initial stacked structure by creating slots in the initial stacked structure, and filling the resulting void spaces with a conductive material (e.g., W) to form a conductive structure. As described herein, some conductive structures may be used as access line structures (e.g., word line structures) of the microelectronic device structure 100, while others may be used as select gate structures of the microelectronic device structure 100. At least one lower conductive structure of the resulting modified stacked structure can be used as at least one lower select gate (e.g., at least one source-side select gate (SGS)) of the microelectronic device structure 100. In some embodiments, a single (e.g., only one) conductive structure of the lowest vertical layer of the modified stacked structure is used as a lower select gate (e.g., SGS) of the microelectronic device structure 100. Additionally, an upper conductive structure of the modified stacked structure can be used as an upper select gate (e.g., drain-side select gate (SGD)) of the microelectronic device structure 100. In some embodiments, one or more horizontally adjacent conductive structures of the upper vertical layers of the modified stacked structure are used as upper select gates (e.g., SGDs) of the microelectronic device structure 100.

[0042] like Figure 1A As shown and referenced Figures 1B to 1D The microelectronic device structure 100 may include a stacked structure 152, said stacked structure comprising a vertically alternating sequence of conductive and insulating structures. The microelectronic device structure 100 may also include one or more segmented stepped structures 110. For clarity, Figure 1AOnly a single block 174 of the microelectronic device structure 100 is depicted. Figure 1D Specifically, block 174 of the microelectronic device structure 100 may be included in adjacent trench structures used in alternative gate processes (e.g., first trench structure 157). Figure 1C The microelectronic device structure 100 consists of portions of the structure 100 between two (2) horizontally adjacent slot structures (e.g., the first slot structure 157). Individual (e.g., a single, one) blocks 174 may be inserted between two (2) horizontally adjacent slot structures (e.g., the first slot structure 157). The microelectronic device structure 100 may contain any number of blocks 174 that are horizontally oriented adjacent to each other, such as... Figure 1D As shown herein, the term "segmentation" of one or more stepped structures of the microelectronic device structure 100 refers to a stepped structure of the microelectronic device structure 100 that does not extend uninterruptedly across the entire width of the microelectronic device structure 100 in the X direction. Instead, the stepped structure of the microelectronic device structure 100 may be segmented (e.g., divided) in the X direction by elevated bridge structures 180, 182, and each segment of the stepped structure may be defined between adjacent elevated bridge structures 180, 182. Figure 1A In the diagram, the raised bridge structure 180 is shown as transparent to better showcase the other components of the microelectronic device structure 100. The raised bridge structures 180 and 182 are described in more detail below.

[0043] One or more stepped structures may include steps 111, and the steps 111 of the stepped structure 410 of the microelectronic device structure 100 may serve as contact areas for different layers of conductive material in the stacked structure 152. The steps 111 may be located at the horizontal ends of conductive and insulating structures, with the insulating structures located between adjacent conductive structures.

[0044] The stepped structure 110 may include, for example, a first stadium-style structure 101, a second stadium-style structure 102, a third stadium-style structure 103, and a fourth stadium-style structure 104. Each of the first stadium-style structure 101, the second stadium-style structure 102, the third stadium-style structure 103, and the fourth stadium-style structure 104 may include a step 111, which is at a different height (e.g., vertically in the Z direction) relative to the step 111 of the other one of the first stadium-style structure 101, the second stadium-style structure 102, the third stadium-style structure 103, and the fourth stadium-style structure 104. The first stadium-style structure 101 may include a first stepped structure 101a and an additional first stepped structure 101b; the second stadium-style structure 102 may include a second stepped structure 102a and an additional second stepped structure 102b; the third stadium-style structure 103 may include a third stepped structure 103a and an additional third stepped structure 103b; and the fourth stadium-style structure 104 may include a fourth stepped structure 104a and an additional fourth stepped structure 104b. The first stepped structure 101a, the second stepped structure 102a, the third stepped structure 103a, and the fourth stepped structure 104a may include steps 111 that are opposite to and at the same height as the corresponding additional first stepped structure 101b, additional second stepped structure 102b, additional third stepped structure 103b, and additional fourth stepped structure 104b. Each of the first step structure 101a, the second step structure 102a, the third step structure 103a, and the fourth step structure 104a can individually exhibit a generally negative slope; and each of the additional first step structure 101b, the additional second step structure 102b, the additional third step structure 103b, and the additional fourth step structure 104b can individually exhibit a generally positive slope.

[0045] In some embodiments, the upper selection gate (e.g., SGD) may be located within the boundary (e.g., horizontal boundary, vertical boundary) of the first stadium-like structure 101 of the microelectronic device structure 100. Figure 1A As shown, valley 125 may be located between a first stepped structure 101a and an additional first stepped structure 101b; between a second stepped structure 102a and an additional second stepped structure 102b; between a third stepped structure 103a and an additional third stepped structure 103b; and between a fourth stepped structure 104a and an additional fourth stepped structure 104b. In some embodiments, valley 125 may be made of insulating material 176 ( Figure 1B )filling.

[0046] The area between adjacent stadium-type structures (e.g., first stadium-type structure 101, second stadium-type structure 102, third stadium-type structure 103 and fourth stadium-type structure 104) may include a raised area 140, which may also be referred to as “peak area 140”.

[0047] As mentioned above, the microelectronic device structure 100 includes raised bridge structures 180 and 182. The raised bridge structures 180 and 182 can extend along individual blocks 174 of the microelectronic device structure 100. Figure 1D The elevated bridge structures 180, 182 may extend along the sides of the individual blocks 174, across the relative stepped structures of each stadium-like structure 101, 102, 103, 104 of the microelectronic device structure 100, and extend horizontally (e.g., in the Y direction) between the relative stepped structures. In some embodiments, the elevated bridge structures 180, 182 may include unremoved portions of the stacked structure 152 of the microelectronic device structure 100 (e.g., portions of the stacked structure 152 of the microelectronic device structure 100 that were not removed during the formation of the block 174, and the stadium-like structures 101, 102, 103, 104 within the individual blocks 174). In one or more embodiments, the elevated bridge structures 180, 182 have a relatively uniform height along the longitudinal dimension of the individual blocks 174 of the microelectronic device structure 100.

[0048] As described in more detail below, conductive contact structures and vertical conductive contacts may be formed in the conductive portions of each layer (e.g., each step 111) of the stacked structure 152 of the microelectronic device structure 100.

[0049] According to embodiments of this disclosure, Figure 1B and Figure 1C yes Figure 1A A simplified cross-sectional view of the microelectronic device structure 100, and Figure 1D yes Figure 1A A simplified top view of a portion of the first stadium-style structure 101 of the microelectronic device structure 100. Specifically, Figure 1B Through Figure 1D The cross-section of the microelectronic device structure 100 is taken by the cross-section line BB, and Figure 1C Through Figure 1D The cross-section of the microelectronic device structure 100 is taken by the cross-sectional line CC. Figure 1B In order to clearly show the other components of the microelectronic device structure 100, some components of the microelectronic device structure 100 (e.g., support pillar structure (described)) have been removed. Additionally, Figure 1B and 1C Each representation in Figure 1AThe "slice" of the microelectronic device structure 100 makes it possible to omit the depiction of the components of the microelectronic device structure 100 in the foreground and background.

[0050] Let's refer to each other. Figures 1B to 1D The microelectronic device structure 100 may be formed to include a stacked structure 152, a source layer 154 below the stacked structure 152, and a dielectric structure 156 extending vertically into the stacked structure 152 (e.g., dielectric material deposited within a first trench structure 157 previously manufactured for use during a so-called "alternate gate" or "gate persistence" processing operation). The microelectronic device structure 100 may further include a support pillar structure 151 extending vertically (e.g., in the Z direction) through at least a portion of the microelectronic device structure 100. The support pillar structure 151 is described in more detail below.

[0051] The stacked structure 152 includes a vertically alternating (e.g., in the Z direction) sequence of insulating structures 162 and conductive structures 164 (e.g., gate structures, word lines) arranged in layers 168. Each of the layers 168 of the stacked structure 152 may include at least one of the insulating structures 162 vertically adjacent to at least one of the conductive structures 164. The stacked structure 152 may include a desired number of layers 168. For example, the stacked structure 152 may include more than or equal to ten (10) layers 168, more than or equal to twenty-five (25) layers 168, more than or equal to fifty (50) layers 168, more than or equal to one hundred (100) layers 168, more than or equal to one hundred and fifty (150) layers 168, or more than or equal to two hundred (200) layers 168 of insulating structures 162 and conductive structures 164.

[0052] The insulating structure 162 of the layer 168 of the stacked structure 152 may be formed of and contain at least one electrically insulating material, such as one or more of the insulating materials described above. In some embodiments, the insulating structure 162 is made of SiO2. x (For example, SiO2) is formed and contains the SiO x Each of the insulating structures 162 may individually comprise a substantially uniform distribution of at least one electrically insulating material or a substantially non-uniform distribution of at least one electrically insulating material. In some embodiments, each of the insulating structures 162 is substantially uniform. In other embodiments, at least one of the insulating structures 162 is substantially non-uniform. The insulating structure 162 may be formed, for example, by and comprise a stack (e.g., lamination) of at least two electrically insulating materials. The insulating structure 162 of each layer 168 of the stacked structure 152 may each be substantially planar and may each individually exhibit a desired thickness.

[0053] The conductive structure 164 of each layer 168 of the stacked structure 152 may be formed of and contain a conductive material, such as one or more of the conductive materials described above. For example, as described above, the conductive structure 164 may be formed of and contain tungsten (W). The conductive structure 164 may be substantially uniform or substantially non-uniform. In some embodiments, the conductive structure 164 is substantially uniform. In additional embodiments, the conductive structure 164 is substantially non-uniform. The conductive structure 164 of each layer 168 of the stacked structure 152 may each be substantially planar and may each individually exhibit a desired thickness.

[0054] In some embodiments, the conductive structure 164 may include a conductive liner material surrounding the conductive structure 164, for example, between the conductive structure 164 and the insulating structure 162. For example, the conductive liner material may include a seed material, and the conductive structure 164 may be formed from said seed material. The conductive liner material may be formed of, for example, a metal (e.g., titanium, tantalum), a metal nitride (e.g., tungsten nitride, titanium nitride, tantalum nitride), or another material and may include, for example, a metal (e.g., titanium, tantalum), a metal nitride (e.g., tungsten nitride, titanium nitride, tantalum nitride), or another material. In some embodiments, the conductive liner material includes titanium nitride.

[0055] As described above, at least one lower conductive structure 164 of the stacked structure 152 can be used as at least one lower select gate (e.g., at least one source-side select gate (SGS)) of the microelectronic device structure 100. In some embodiments, a single (e.g., only one) conductive structure 164 of the vertically bottommost layer 168 of the stacked structure 152 is used as a lower select gate (e.g., SGS) of the microelectronic device structure 100. Additionally, the upper conductive structure 164 of the stacked structure 152 can be used as an upper select gate (e.g., SGD) of the microelectronic device structure 100. In some embodiments, the horizontally adjacent conductive structures 164 of the vertically topmost layer 168 of the stacked structure 152 are used as upper select gates (e.g., SGDs) of the microelectronic device structure 100.

[0056] Source layer 154 is vertically positioned below stacked structure 152 (e.g., in the Z direction) and includes at least one source structure 159 (e.g., a source plate). Source structure 159 may be formed of at least one conductive material and includes at least one conductive material, such as one or more of the conductive materials described above. In some embodiments, source layer 154 includes at least one source structure 159 and one or more discrete structures.

[0057] Let's refer to each other. Figures 1A to 1DThe steps 111 (e.g., contact areas) of the stepped structure 110 of the microelectronic device structure 100 may be defined by the horizontal edges (e.g., horizontal ends) of the layers 168. The number of steps 111 included in the stepped structure 110 may be substantially the same as (e.g., equal to) the number of layers 168 in each stack structure 152 or may be different (e.g., less or greater than the number of layers 168 in each stack structure 152). In some embodiments, the steps 111 of the stepped structure 110 are arranged in such a sequence that steps 111 that are directly horizontally adjacent to each other in the X direction correspond to layers 168 of the stack structure 152 that are directly vertically adjacent to each other (e.g., in the Z direction). In an additional embodiment, the steps 111 of the stepped structure 110 are arranged in a random order such that at least some steps 111 of the stepped structure 110 that are directly horizontally adjacent to each other in the X direction correspond to layers 168 of the stack structure 152 that are not directly vertically adjacent to each other (e.g., in the Z direction).

[0058] The height H (e.g., in the Z direction) of the individual step structures 110 between the uppermost and lowermost steps 111 of the step structure 110 can be in the range of about 5.0 μm to about 20.0 μm, for example, from about 5 micrometers (μm) to about 10.0 μm, from about 10.0 μm to about 15.0 μm, or from about 15.0 μm to about 20.0 μm. In some embodiments, the height H is about 13.5 μm. However, this disclosure is not limited thereto, and the height H may differ from those described above.

[0059] Insulating material 176 ( Figure 1A (Not depicted) may be overlaid on the stepped structure 110 and provide electrical insulation between its components. Insulating material 176 may be formed of and comprise one or more of the insulating materials described above with reference to insulating structure 162. In some embodiments, insulating material 176 comprises the same material composition as insulating structure 162. In some embodiments, insulating material 176 comprises silicon dioxide.

[0060] refer to Figure 1D The stacked structure 152 can be divided by a first slot structure 157 in a Y direction orthogonal to the X direction. The first slot structure 157 can extend vertically (e.g., in...). Figure 1AThe first trench structure 157 extends, for example, entirely vertically through the stacked structure 152 and extends, for example, to the source layer 154. The first trench structure 157 can divide the stacked structure 152 (e.g., in the Y direction) into multiple blocks 174. As described above, the first trench structure 157 can be used, for example, to form the conductive structure 164 of the stacked structure 152 through a so-called "alternate gate" or "gate persistence" processing action. As described above, the first trench structure 157 can be filled within a dielectric material and can form a dielectric structure 156. The dielectric material may comprise one or more of the following: at least one dielectric oxide material (e.g., SiO2). x Phossilicate glass, borosilicate glass, borosilicate-phosphorus glass, fluorosilicate glass, AlO x HfO x NbO x TiO x ZrO x TaO x and MgO x One or more of the following), at least one dielectric nitride material (e.g., SiN). y ), and at least one dielectric oxide nitride material (e.g., SiO2). x N y ), or at least one dielectric carbon oxynitride material (e.g., SiO2). x C z N y In some embodiments, the dielectric structure 156 is made of SiO2. x (For example, SiO2) is formed and contains the SiO x .

[0061] Additionally, in one or more embodiments, raised bridge structures 180, 182 may be formed adjacent to the first slot structure 157, the first slot structure defining the boundary of block 174 in the X direction. Furthermore, see also... Figure 1C and 1D The raised bridge structures 180, 182 may include a first set of upper select gates 117A ( Figure 1C The first group of upper select gates 117A and the fourth group of upper select gates 117D are also present. Furthermore, because portions of the first group of upper select gates 117A and the fourth group of upper select gates 117D within the raised bridge structures 180 and 182 remain unremoved, the short-circuit path between the first group of upper select gates 117A and the fourth group of upper select gates 117D can be maintained in the peak region 140. Figure 1A )Inside.

[0062] In some embodiments, at least some (e.g., all) of blocks 174 may be subdivided (in the Y direction) into multiple sub-blocks using a second trench structure 175 located at, for example, the end portion of a stepped structure 110. Within individual blocks 174, the second trench structure 175 may further divide the upper layer 168 of the stacked structure 152 such that the uppermost conductive structure 164 of the upper layer 168 can be used as the upper selected gate of block 174 of the stacked structure 152. For example, as Figure 1C As shown, each of the second groove structures 175 may be formed between adjacent support pillar structures 151 of the individual blocks 174. The second groove structure 175 may extend vertically (e.g., in the Z direction) through one or more (e.g., two or more) of the insulating material 176 and the upper layers 168 of the stacked structure 152. The second groove structure 175 may disrupt (e.g., terminate) the horizontal continuity of the insulating material 176, the insulating structure 162 of the upper layer 168, and the conductive structure 164 of the upper layer 168. The second groove structure 175 may terminate (e.g., end) at the upper surface of the conductive structure 164 of the individual layer 168. For example, the lower vertical boundary of the second groove structure 175 may be substantially coplanar with the upper surface of the conductive structure 164 of the individual layer 168 of the stacked structure 152, such as... Figure 1C As depicted in [the original text]. In other embodiments, the second trench structure 175 terminates within the vertical boundary of the conductive structure 164 of the upper layer 168 of the stacked structure 152. In yet another embodiment, the second trench structure 175 terminates within the vertical boundary of the insulating structure 162 of the upper layer 168 of the stacked structure 152. In some embodiments, each of the second trench structures 175 extends to substantially the same vertical depth as each of the other second trench structures 175. In some embodiments, the second trench structure 175 may include trenches filled within a dielectric material to form a dielectric structure 177. The dielectric material may comprise one or more of the following: SiO2 x Phossilicate glass, borosilicate glass, borosilicate-phosphorus glass, fluorosilicate glass, AlO x HfO x NbO x TiO x ZrO x TaO x MgO x High aspect ratio process (HARP) oxides.

[0063] Additionally, the second trench structure 175 may at least partially define a group of upper select gates (e.g., SGDs) extending in the Z direction. For example, within each block 174, the second trench structure 175 may define at least a first group of upper select gates 117A, a second group of upper select gates 117B, a third group of upper select gates 117C, and a fourth group of upper select gates 117D. Figure 1C As depicted in and according to Figure 1C In the view depicted, in the X direction, a first group of upper select gates 117A may be defined between the leftmost trench structure 157L and its associated dielectric structure 156, and between the leftmost second trench structure 175L and its associated dielectric structure 177; a second group of upper select gates 117B may be defined between the leftmost second trench structure 175L and its associated dielectric structure 177, and between the middle second trench structure 175M and its associated dielectric structure 177; a third group of upper select gates 117C may be defined between the middle second trench structure 175M and its associated dielectric structure 177, and between the rightmost second trench structure 175R and its associated dielectric structure 177; and a fourth group of upper select gates 117D may be defined between the rightmost second trench structure 175R and its associated dielectric structure 177, and between the rightmost trench structure 157R and its associated dielectric structure 156. Although only four groups of upper select gates are described, each block 174 of the stacked structure 152 may contain fewer or more groups of upper select gates. For example, each block 174 may contain six, eight, ten or more groups of upper select gates.

[0064] Common Reference Figure 1C and Figure 1D As described above, the microelectronic device structure 100 may further include a support pillar structure 151, the support pillar structure comprising: a first material 153 extending vertically through the stacked structure 152 and extending to the source layer 154; and a liner material 155 situated on the sidewalls of the first material 153. The liner material 155 may substantially surround (e.g., substantially horizontally and vertically cover) the sidewalls of the first material 153.

[0065] The first material 153 may be formed of and contain at least one conductive material, such as one or more of the conductive materials described above. In some embodiments, the first material 153 of each of the support pillar structures 151 has substantially the same material composition. In other embodiments, the first material 153 is formed of and contains an insulating material. In some such embodiments, the first material 153 may be formed of and contain at least one dielectric material, such as at least one dielectric oxide material (e.g., SiO2). x Phossilicate glass, borosilicate glass, borosilicate-phosphorus glass, fluorosilicate glass, AlO x HfOx NbO x TiO x ZrO x ,TaO x and MgO x One or more of the following), at least one dielectric nitride material (e.g., SiN). y ), and at least one dielectric oxide nitride material (e.g., SiO2). x N y ), and at least one dielectric carbon oxynitride material (e.g., SiO2). x C z N y The first material 153 comprises one or more of the following: SiO2 and amorphous carbon. In some embodiments, the first material 153 comprises SiO2. In some embodiments, such as when the first material 153 comprises an insulating material, the microelectronic device structure 100 may not include a liner material 155 on the sidewall of the first material 153, and the support pillar structure 151 may comprise only the first material 153 (e.g., an insulating material).

[0066] Each support pillar structure 151 may individually exhibit a desired geometry (e.g., size and shape) and spacing. The geometry and spacing of the support pillar structures 151 may be selected at least in part based on the configuration and location of other components of the microelectronic device structure 100 (e.g., steps 111 of the stepped structure 110, conductive contact structures formed to contact the steps 111 of the stepped structure 110, source layers 154). For example, each support pillar structure 151 may have a geometry and spacing that allows it to extend vertically (e.g., in the Z direction) through the stacked structure 152 and physically contact (e.g., ascend) the source layers 154 to facilitate a predetermined function (e.g., electrical interconnection function, support function) of the support pillar structure 151. In other embodiments, the support pillar structure 151 may not include electrical interconnection functionality and primarily (e.g., only) provide support functionality. Each of the support column structures 151 may exhibit substantially the same geometric configuration (e.g., same size and shape) and horizontal spacing (e.g., in the X direction) as each of the other support column structures 151, or at least some support column structures 151 may exhibit different geometric configurations (e.g., one or more different sizes, different shapes) and / or different horizontal spacings than at least some of the other support column structures 151. In some embodiments, the support column structures 151 are at least partially uniformly spaced in the X direction and in the Y direction. In some embodiments, the support column structures 151 are arranged as columns extending in the X direction and rows extending in the Y direction between the first slot structures 157. In other embodiments, the support column structures 151 are at least partially non-uniformly spaced in the X direction.

[0067] The support pillar structure 151 may serve as a support structure during and / or after the formation of one or more components of the microelectronic device structure 100. For example, the support pillar structure 151 may serve as a support structure for forming the conductive structure 164 during the replacement of the sacrificial structure with the conductive structure 164, as described above with reference to the "replacement gate" or "gate persistence" processing operation. The support pillar structure 151 may hinder (e.g., prevent) layer collapse during the selective removal of the sacrificial structure.

[0068] The liner material 155 can be horizontally inserted between each of the first materials 128 of the support column structure 151 and the layers 168 of the stacked structure 152 (including its insulating structure 162 and conductive structure 164). The liner material 155 may be formed of one or more of the following and includes one or more of the following: at least one dielectric oxide material (e.g., SiO2). x Phossilicate glass, borosilicate glass, borosilicate-phosphorus glass, fluorosilicate glass, AlO x HfO x NbO x TiO x ZrO x ,TaO x and MgO x One or more of the following), at least one dielectric nitride material (e.g., SiN). y ), and at least one dielectric oxide nitride material (e.g., SiO2). x N y ), and at least one dielectric carbon oxynitride material (e.g., SiO2). x C z N y The liner material 155 comprises SiO2. In some embodiments, the liner material 155 has a different material composition than the insulating material 176. In other embodiments, the liner material 155 has the same material composition as the insulating material 176. In some embodiments, the liner material 155 comprises a material composition that is substantially removed in response to exposure to etching chemicals formulated and configured to remove silicon nitride.

[0069] Next reference Figures 2A to 2C The mask structure 202 can be formed on the insulating material 176 of the microelectronic device structure 100. Figure 2B and 2C Each representation in Figure 2AA “slice” of the microelectronic device structure 100 is provided, allowing for the omission of depicting the components of the microelectronic device structure 100 in the foreground and background. In some embodiments, the mask structure 202 may at least substantially cover the upper surface of the insulating material 176. The mask structure 202 may be formed of and contain at least one material (e.g., at least one hard mask material) suitable for use as an etching mask to pattern portions of the stacked structure 152 (e.g., portions of layer 168, including portions of insulating structure 162, conductive structure 164, support pillar structure 151, and dielectric structure 177) to form holes (e.g., openings, vias, trenches) extending vertically (e.g., in the Z direction) through portions of the stacked structure 152, as described in further detail below. By means of a non-limiting example, the mask structure 202 may be formed of and contain one or more hard mask materials having etch selectivity relative to one or more materials of the stacked structure 152. In some embodiments, mask structure 202 includes one or more of amorphous carbon and doped amorphous carbon (e.g., boron-doped amorphous carbon, such as comprising at least 1 wt% boron and at least 20 wt% carbon, for example, between about 1 wt% boron and about 40 wt% boron, and between about 99 wt% carbon and about 60 wt% carbon). In additional embodiments, mask structure 202 may comprise one or more of titanium, TiN, or TaN (e.g., a hard mask). In other embodiments, mask structure 202 is a dielectric material. For example, hard mask material 124 may comprise one or more of the above dielectric materials. Mask structure 202 may be homogeneous (e.g., may comprise only one material layer) or non-homogeneous (e.g., may comprise a stack exhibiting at least two different material layers). Additionally, the mask structure 202 can exhibit any thickness that allows the stacked structure 152 to be patterned as desired, for example, a thickness ranging from about 1 nanometer (nm) to about 1000 nm.

[0070] In an additional embodiment, the mask structure 202 may include a photoresist structure. The photoresist structure may be formed of and contain a photoresist material, such as a positive or negative photoresist material. Suitable photoresist materials (e.g., positive or negative photoresist materials) are known in the art and therefore will not be described in detail herein. For example, the photoresist structure may be compatible with 13.7 nm, 157 nm, 193 nm, 248 nm, or 365 nm wavelength systems; with 193 nm wavelength immersion systems; and / or with electron beam lithography systems.

[0071] In one or more embodiments, the mask structure 202 may be formed by one or more of ALD, CVD, PVD, LPCVD, PECVD, another deposition method, or a combination thereof.

[0072] Next reference Figures 3A to 3C A portion of the mask structure 202 can be removed (e.g., etched) to form a patterned mask structure 204, which includes an elongated opening 206 (e.g., a hole, a through hole) extending vertically (e.g., in the Z direction) through it. Figure 3B and 3C Each representation in Figure 3A A "slice" of the microelectronic device structure 100 is provided, allowing for the omission of depicting the components of the microelectronic device structure 100 in the foreground and background. The elongated openings 206 can be configured to reveal a desired horizontal cross-sectional shape and desired horizontal dimensions (e.g., width, length). In some embodiments, each of the elongated openings 206 is configured to reveal an elliptical horizontal cross-sectional shape (e.g., a rectangular cross-sectional shape). The horizontal dimension (e.g., width) of each of the elongated openings 206 in a first horizontal direction (e.g., the X direction) may be smaller than another horizontal dimension (e.g., length) of the elongated opening 206 in a second horizontal direction (e.g., a direction orthogonal to the X direction, such as the Y direction).

[0073] like Figure 3B and 3C As shown, an elongated opening 206 extends vertically (e.g., in the Z direction) from the upper surface of the patterned mask structure 204 to the upper surface of the stacked structure 152 (e.g., the upper surface of the insulating material 176 of the stacked structure 152), completely passing through the patterned mask structure 204. Additionally, the elongated opening 206 may extend in the Y direction over a portion of the microelectronic device structure 100 that includes a lower stadium-like structure (e.g., a second stadium-like structure 102, a third stadium-like structure 103, and a fourth stadium-like structure 104). For example, the elongated opening 206 may extend over a portion of the microelectronic device structure 100 that includes a lower select gate (e.g., SGS) and an intermediate layer select gate.

[0074] Specifically, refer to Figure 3BThe elongated opening 206 may extend horizontally in the Y direction from a portion of the microelectronic device structure 100 including the lower stadium-like structure to at least a portion of the peak region 140 and above at least a portion of the peak region 140, the at least portion of which is formed between the uppermost stadium-like structure (e.g., the first stadium-like structure 101) and the adjacent, relatively vertical lower stadium-like structure of the microelectronic device structure 100 (e.g., the second stadium-like structure 102). Furthermore, in some embodiments, the elongated opening 206 extends above (e.g., horizontally overlaps with) the portion of the uppermost stadium-like structure (e.g., the first stadium-like structure 101) in which the second groove structure 175 and dielectric structure 177 are formed, such as... Figure 3C As shown in the diagram. Specifically, the elongated opening 206 may horizontally overlap (e.g., in a direction perpendicular to it) with a portion of the second groove structure 175 and the dielectric structure. For example, the elongated opening 206 may extend above at least a portion of the uppermost step of the uppermost stadium-like structure (e.g., the first stadium-like structure 101).

[0075] The geometry (e.g., shape, size), horizontal position (e.g., in the X and Y directions), and horizontal spacing of each elongated opening 206 in the patterned mask structure 204 depend at least in part on the geometry, horizontal position, and horizontal spacing of the trenches that will ultimately be formed in the stacked structure 152 using the patterned mask structure 204, as described below regarding Figures 4A to 4C Further detailed description. The geometric configuration, horizontal position, and horizontal spacing of each hole formed in the stacked structure 152, which in turn depends in at least part on the geometric configuration, horizontal position, and horizontal spacing of the structure of the stacked structure 152 (e.g., dielectric structure, conductive structure, and insulating structure), are further described in detail below.

[0076] In some embodiments, the microelectronic device structure 100 may include each block 174 for the stacked structure 152. Figure 1D The elongated opening 206 may also have a width that is substantially the same in the X direction as the distance between the leftmost dielectric structure 177L (e.g., dielectric structure 177 within the leftmost second trench structure 175L) and the rightmost dielectric structure 177R (e.g., dielectric structure 177 within the rightmost second trench structure 175R) of a given block 174.

[0077] Additionally, still refer to Figure 3CThe surface of the patterned mask structure 204 defining the leftmost boundary of a given elongated opening 206 in the X direction may be substantially coplanar with the surfaces of the insulating material 176, insulating structure 162, and conductive structure 164 defining the boundary (e.g., the main surface) of the leftmost second trench structure 175L. For example, the surface of the patterned mask structure 204 defining the leftmost boundary of the given elongated opening 206 may be coplanar with the leftmost or rightmost boundary of the leftmost dielectric structure 177L. In other embodiments, the surface of the patterned mask structure 204 defining the leftmost boundary of the given elongated opening 206 may generally be aligned vertically with a portion of the leftmost dielectric structure 177L. Furthermore, the surface of the patterned mask structure 204 defining the rightmost boundary of the given elongated opening 206 in the X direction may be substantially coplanar with the surfaces of the insulating material 176, insulating structure 162, and conductive structure 164 defining the boundary (e.g., the main surface) of the rightmost second trench structure 175R. For example, the surface of the patterned mask structure 204 defining the rightmost boundary of a given elongated opening 206 may be coplanar with the leftmost or rightmost boundary of the rightmost dielectric structure 177R. In other embodiments, the surface of the patterned mask structure 204 defining the rightmost boundary of a given elongated opening 206 may generally be aligned vertically with a portion of the rightmost dielectric structure 177R. As will be described in more detail below, the elongated opening 206 defined by the patterned mask structure 204 may allow removal of a portion of the stacked structure 152 between the leftmost dielectric structure 177L and the rightmost dielectric structure 177R (e.g., between the first set of upper select gates 117A and the fourth set of upper select gates 117D).

[0078] refer to Figures 4A to 4C A portion of the stacked structure 152 can be removed through the elongated opening 206 to form a trench 208 (e.g., a slot, slit). Figure 4B and 4C Each representation in Figure 4A The "slice" of the microelectronic device structure 100 allows for the omission of depicting the components of the microelectronic device structure 100 in the foreground and background. The trenches 208 can be formed to exhibit a desired horizontal cross-sectional shape and desired horizontal dimensions (e.g., width, length), at least in part due to the elongated horizontal cross-sectional shape of the openings. In some embodiments, each of the trenches 208 is formed to exhibit an elliptical horizontal cross-sectional shape (e.g., a rectangular cross-sectional shape). The horizontal dimension (e.g., width) of each of the trenches 208 in a first horizontal direction (e.g., the X direction) may be smaller than another horizontal dimension (e.g., length) of the trench 122 in a second horizontal direction (e.g., a direction orthogonal to the X direction (e.g., the Y direction)).

[0079] Trench 208 may extend vertically (e.g., in the Z direction) through portions of insulating material 176, upper layer 168 (e.g., upper insulating structure 162 and upper conductive structure 164), support pillar structure 151, and at least portions of one or more dielectric structures 177 of stacked structure 152. Trench 208 may disrupt (e.g., terminate) the horizontal continuity of upper insulating structure 162 and upper conductive structure 164 of upper layer 168 of stacked structure 152. Trench 208 may extend vertically through portions of stacked structure 152 forming upper select gate (SGD) of microelectronic device structure. Specifically, trench 208 may extend vertically through at least a portion of stacked structure 152 forming first stadium-type structure 101. In some embodiments, trench 208 may terminate vertically (e.g., end) at the upper surface of conductive structure 164 of layer 168 of stacked structure 152 forming portions (e.g., upper steps) of second stadium-type structure 102. For example, the lower vertical boundary of trench 208 may be substantially coplanar with the upper surface of the conductive structure 164 of the layer 168 of the stacked structure 152 that forms the upper step of the second stadium-like structure 102, such as... Figure 4B As depicted in [the original text]. In other embodiments, trench 208 may extend at least partially into the conductive structure 164 of layer 168 of the stacked structure 152 and may terminate within the vertical boundary of the conductive structure 144. In some embodiments, each of the trenches 208 extends to substantially the same vertical depth as each of the other trenches 208.

[0080] In some embodiments, the width of each of the trenches 208 may be substantially the same as the width of the corresponding elongated opening 206 described above. Specifically, each of the trenches 208 may have a width in the X direction that is substantially the same as the distance (in the X direction) between the leftmost dielectric structure 177L (e.g., dielectric structure 177 within the leftmost second trench structure 175L) and the rightmost dielectric structure 177R (e.g., dielectric structure 177 within the rightmost second trench structure 175R) of the corresponding block 174. Therefore, the formation of the trenches 208 can remove portions of the second and third sets of upper select gates 117B and 117C between the leftmost dielectric structure 177L and the rightmost dielectric structure 177R (e.g., portions of the second and third sets of upper select gates 117B and 117C between the first set of upper select gates 117A and the fourth set of upper select gates 117D) and the peak region 140 of the microelectronic device structure 100 between the first stadium structure 101 and the second stadium structure. Figure 1A The portion within ) . Therefore, the trench 208 can be located in the peak region 140 ( ) between the first stadium-type structure 101 and the second stadium-type structure 102. Figure 1AThe trench 108 is at least partially horizontally divided (e.g., separated) by a first group of upper select gates 117A and a fourth group of upper select gates 117D. Furthermore, as described above, the trench 208 may partially overlap with the dielectric structure 177 and its associated second trench structure 175 in the Y direction. Additionally, in some embodiments, the trench 108 may not extend through the first step 111 (e.g., the uppermost step) of the first stadium-like structure 101 in the Y direction.

[0081] The trench 208 can be formed using conventional processes not described in detail herein, such as conventional material removal processes (e.g., conventional etching processes, such as conventional dry etching processes) and conventional processing equipment. By means of non-limiting examples, at least a portion of the insulating material 176, the upper layer 168 (e.g., upper insulating structure 162 and upper conductive structure 164), portions of the support pillar structure 151, and one or more dielectric structures 177 of the stacked structure 152 can undergo anisotropic etching (e.g., anisotropic dry etching, such as reactive ion etching (RIE), deep RIE, plasma etching, reactive ion beam etching, and chemically assisted ion beam etching or anisotropic wet etching) to form the trench 208.

[0082] As described in more detail below, trench 208 may be superior to other methods of separating the first set of upper select gates (e.g., the first set of upper select gates 117A) from the fourth set of upper select gates (e.g., the fourth set of upper select gates 117D) of a microelectronic device structure (e.g., microelectronic device structure 100). For example, as described above, due to the raised bridge portions 180, 182 ( Figure 1A and 1D Before trench 208 is formed, short-circuit paths may exist between the first set of upper select gates 117A and the fourth set of upper select gates 117D, and trench 208 can disrupt (e.g., remove) these short-circuit paths. Specifically, in some embodiments, trench 208 is located in the peak region 140 between the first stadium structure 101 and the second stadium structure 102. Figure 1A The trench 208 separates a portion of the first set of upper select gates 117A from the fourth set of upper select gates 117D. Therefore, the trench 208 prevents the upper select gates in the first set of upper select gates 117A and the fourth set of upper select gates 117D from passing through and crossing the peak region 140 between the first stadium-style structure 101 and the second stadium-style structure 102. Figure 1A Short circuit (e.g., leakage current and causing a short circuit).

[0083] refer to Figures 5A to 5C Dielectric material 210 may be formed (e.g., deposited) within trench 208 and above patterned mask structure 204. Figure 5B and5C Each representation in Figure 5A A "slice" of the microelectronic device structure 100 is provided, allowing for the omission of depicting the components of the microelectronic device structure 100 in the foreground and background. Trench 208 may be at least substantially filled with dielectric material 210. In some embodiments, dielectric material 210 comprises a spin-coated dielectric material and can be formed by a spin-coating process. In additional embodiments, dielectric material 210 may be formed using one or more of ALD, CVD, PVD, LPCVD, PECVD, or another deposition method. In some embodiments, dielectric material 210 is formed from and contains at least one dielectric oxide material. For example, dielectric material 210 may contain SiO2. x Phossilicate glass, borosilicate glass, borosilicate-phosphorus glass, fluorosilicate glass, AlO x HfO x NbO x TiO x ZrO x TaO x MgO x and one or more of the high aspect ratio process (HARP) oxides.

[0084] Despite Figures 5A to 5C While not explicitly depicted, in some embodiments, portions of the dielectric material 210 and / or portions of the dielectric material 210 and the patterned mask structure 204 on or above the insulating material 176 may be removed, while retaining additional portions of the dielectric material 210 having the boundaries of the trenches 208. In some embodiments, portions of the dielectric material 210 and / or portions of the dielectric material 210 and the patterned mask structure 204 may be removed by a planarization process (e.g., chemical mechanical planarization (CMP) process). In other embodiments, portions of the dielectric material 210 and / or portions of the dielectric material 210 and the patterned mask structure 204 may be removed by another suitable technique, including but not limited to etching (e.g., dry etching, wet etching, vapor phase etching) or ion etching.

[0085] As will be understood by those skilled in the art, although the microelectronic device structure 100 has been described as having a specific structure, this disclosure is not limited thereto, and the microelectronic device structure 100 may have different geometric configurations and orientations.

[0086] Let's refer to each other. Figures 1A to 5CThe trench 208 and the dielectric material 210 filling the trench 208 are preferable to separating the first set of upper select gates (e.g., the first set of upper select gates 117A) from the fourth set of upper select gates (e.g., the fourth set of upper select gates 117D) of a microelectronic device structure (e.g., microelectronic device structure 100) having a segmented stepped structure (e.g., stepped structure 110), such as a segmented upper stadium-like structure (e.g., the first stadium-like structure 101). For example, as described above, due to the raised bridge portions 180, 182 of the segmented upper stadium-like structure ( Figure 1A and 1D A short-circuit path may exist within the peak region 140 between the first set of upper select gates 117A (e.g., the first set of drain select gates) and the fourth set of upper select gates 117D (e.g., the fourth set of drain select gates). To mitigate this problem, the trench 208 and the dielectric material 210 filling the trench 208 may partially overlap in the Y direction with the second trench structure 175 extending through the first stadium-shaped structure 101 of the microelectronic device structure 100. Therefore, the trench 208 and the dielectric material 210 filling the trench 208 extend within the peak region 140 of the microelectronic device structure 100 between the first set of upper select gates 117A and the fourth set of upper select gates 117D.

[0087] Because trench 208 and dielectric material 210 extend into the peak region 140 between the first stadium-type structure 101 and the second stadium-type structure 102, and because trench 208 and dielectric material 210 extend within the peak region 140 between the first set of upper select gates 117A and the fourth set of upper select gates 117D, trench 208 and dielectric material 210 can extend within the peak region 140 ( Figure 1A Within the first set of upper select gates 117A, a portion is physically separated from the fourth set of upper select gates 117D. Therefore, trench 208 can remove a short-circuit path between the first set of upper select gates 117A and the fourth set of upper select gates 117D within the peak region 140. Thus, trench 208 prevents the gates within the first set of upper select gates 117A and the gates within the fourth set of upper select gates 117D from short-circuiting through and across the peak region 140.

[0088] Furthermore, the trench 208 and dielectric material 210 described herein are superior in the peak region 140 and / or valley 125 ( Figure 1AA barrier is formed within the valley, which extends horizontally in a direction orthogonal (e.g., the X direction) to the direction in which the first groove structure 157 extends to prevent short circuits across the peak region 140. For example, forming barriers and features (e.g., patterning in the X direction) in the X direction presents challenges in maintaining critical dimensions due to manufacturing constraints, and the risk of under-etching and over-etching increases as the critical dimensions for patterning in the X direction increase. When patterning in the Y direction, the aforementioned manufacturing constraints are not a significant issue, as depicted in the figure.

[0089] Furthermore, forming the trench 208 and dielectric material 210 does not require forming relatively small features. Additionally, typical manufacturing processes do not involve significant structural changes within the microelectronic device structure 100 after forming the trench 208 and dielectric material 210. Moreover, forming the trench 208 and dielectric material 210 through eight, ten, fifteen, or more layers 168 of the stacked structure 152 can be relatively accurate.

[0090] Figure 6 This illustration shows a partial cross-sectional perspective view of a portion of a microelectronic device 601 (e.g., a memory device, such as a dual-stack 3D NAND flash memory device) including a microelectronic device structure 600. The microelectronic device structure 600 may be substantially similar to that described in the previous references. Figures 1A to 5C The microelectronic device structure 100 described after the processing stage. For example... Figure 6 As shown, the microelectronic device structure 600 may include a stacked structure 613, which includes features defined for connecting access lines 606 to conductive layers 605 (e.g., conductive layers, conductive plates, such as conductive structure 164). Figures 1A to 5C The segmented stepped structure 620 of the contact area (e.g., stepped structure 110) Figures 1A to 1C The microelectronic device structure 600 may include a vertical string 607 of memory cells 603 coupled in series with each other. The vertical string 607 may extend vertically (e.g., in the Z direction) and perpendicularly to conductors and conductive layers 605, such as data lines 602, source layers 604 (e.g., source structure 159 (e.g., ...)). Figure 1B and 1C The stacked structure 613 can be horizontally divided (e.g., in the Y direction) into multiple blocks 632 (e.g., block 174). The stack includes conductive layers 605, access lines 606, a first select gate 608 (e.g., upper select gate, drain select gate (SGD)), select lines 609, and a second select gate 610 (e.g., lower select gate, source select gate (SGS)). Figure 1D The block is connected by a slot structure 630 (e.g., a first slot structure 157). Figures 1B to 1D They are separated from each other horizontally (e.g., in the Y direction).

[0091] Vertical conductive contacts 611 can electrically couple components to each other, as shown. For example, select line 609 can be electrically coupled to a first select gate 608, and access line 606 can be electrically coupled to conductive layer 605. Microelectronic device 601 may also include a control unit 612 located below the memory array, which may include control logic configured to control various operations of other features of microelectronic device 601 (e.g., vertical strings 607 of memory cells 603). By way of non-limiting examples, control unit 612 may include one or more (e.g., each) of the following: a charge pump (e.g., V... CCP Charge pump, V NEGWL Charge pumps, DVC2 charge pumps), delay-locked loop (DLL) circuit systems (e.g., ring oscillators), V dd The control unit 612 includes a regulator, a driver (e.g., a serial driver), a decoder (e.g., a local stack decoder, a column decoder, a row decoder), a sense amplifier (e.g., an equalization (EQ) amplifier, an isolation (ISO) amplifier, an NMOS sense amplifier (NSA), a PMOS sense amplifier (PSA)), a repair circuit system (e.g., a column repair circuit system, a row repair circuit system), I / O devices (e.g., local I / O devices), a memory test device, a MUX, an error checking and correction (ECC) device, a self-refresh / wear-out equalization device, and other chip / stack control circuit systems. The control unit 612 may be electrically coupled to, for example, a data line 602, a source layer 604, an access line 606, a first select gate 608, and a second select gate 610. In some embodiments, the control unit 612 includes a CMOS (Complementary Metal-Oxide-Semiconductor) circuit system. In such embodiments, the control unit 612 may be characterized by having an "array-under-CMOS" ("CuA") configuration.

[0092] The first select gate 608 may extend horizontally in a first direction (e.g., the X direction) and may be coupled to a corresponding first set of vertical strings 607 of the memory cell 603 at a first end (e.g., the upper end) of the vertical strings 607. The second select gate 610 may be formed in a substantially flat configuration and may be coupled to the vertical strings 607 at a second opposite end (e.g., the lower end) of the vertical strings 607 of the memory cell 603.

[0093] Data lines 602 (e.g., bit lines) may extend horizontally in a second direction (e.g., in the Y direction) at an angle (e.g., perpendicular) to a first direction in which the first select gate 608 extends. Data lines 602 may be coupled at a first end (e.g., the upper end) of a vertical string 607 to a corresponding second set of vertical strings 607. The first set of vertical strings 607 coupled to the corresponding first select gate 608 may share a specific vertical string 607 with the second set of vertical strings 607 coupled to the corresponding data lines 602. Therefore, a specific vertical string 607 may be selected at the intersection of a specific first select gate 608 and a specific data line 602. Thus, the first select gate 608 can be used to select a memory cell 603 of a vertical string 607 of memory cell 603.

[0094] Conductive layer 605 (e.g., word line board), conductive structure 164 (e.g., Figure 1C The conductive layers 605 can extend in the corresponding horizontal plane. The conductive layers 605 can be stacked vertically such that each conductive layer 605 is coupled to all vertical strings 607 of the memory cells 603, and the vertical strings 607 of the memory cells 603 extend vertically through the stack of conductive layers 605. The conductive layers 605 can be coupled to or can form the control gate of the memory cells 603. Each conductive layer 605 can be coupled to one memory cell 603 in a specific vertical string 607 of the memory cells 603.

[0095] The stepped structure 620 can be configured to provide an electrical connection between the access line 606 and the conductive layer 605 via a vertical conductive contact 611. For example, a specific level of the conductive layer 605 can be selected via an access line 606 electrically connected to a corresponding conductive contact 611, which is electrically connected to a specific conductive layer 605.

[0096] Data line 602 can be electrically coupled to vertical string 607 through conductive contact structure 634.

[0097] As described above, referring to the microelectronic device structure 100, insulating material (e.g., insulating material 176) Figure 1B , 1C It can provide electrical isolation between adjacent conductive contacts 611.

[0098] Microelectronic device structures according to embodiments of the present disclosure (e.g., previously referenced) Figures 5A to 5C The microelectronic device structure 100 described, and previous references Figure 6 The microelectronic device structure 600 described herein and the microelectronic device (e.g., previously referenced) Figure 6 The described microelectronic device 601 can be used in embodiments of the electronic systems of this disclosure. For example, Figure 7This is a block diagram of an illustrative electronic system 700 according to embodiments of the present disclosure. Electronic system 700 may include, for example, a computer or computer hardware component, a server or other network-connected hardware component, a cellular phone, a digital camera, a personal digital assistant (PDA), a portable media (e.g., music) player, a Wi-Fi or cellular-enabled tablet computer (e.g., an iPad® or SURFACE® tablet computer), an e-book, and / or a navigation device. Electronic system 700 includes at least one memory device 702. Memory device 702 may include, for example, embodiments of microelectronic device architectures and one or more microelectronic devices previously described herein. Electronic system 700 may further include at least one electronic signal processor device 704 (generally referred to as a “microprocessor”). Electronic signal processor device 704 may optionally include embodiments of microelectronic device architectures and one or more microelectronic devices previously described herein. Although memory device 702 and electronic signal processor device 704 are depicted as... Figure 7 The electronic system 700 may contain two (2) separate devices, but in additional embodiments, a single (e.g., only one) memory / processor device with the functionality of memory device 702 and electronic signal processor device 704 may be included in the electronic system 700. In such embodiments, the memory / processor device may include one or more of the microelectronic device architectures and microelectronic devices previously described herein. The electronic system 700 may further include one or more input devices 706 for inputting information into the electronic system 700 by a user, such as a mouse or other pointing device, keyboard, touchpad, button, or control panel. The electronic system 700 may further include one or more output devices 708 for outputting information (e.g., visual or audio output) to a user, such as one or more of a monitor, display, printer, audio output jack, and speaker. In some embodiments, the input device 706 and output device 708 may include a single touchscreen device for inputting information into the electronic system 700 and outputting visual information to a user. The input device 706 and output device 708 may be in electrical communication with one or more of the memory device 702 and electronic signal processor device 704.

[0099] Therefore, according to embodiments of this disclosure, an electronic system includes an input device, an output device, a processor device operatively coupled to the input device and the output device, and a memory device operatively coupled to the processor device. The memory device includes at least one microelectronic device structure comprising: a stacked structure including layers, each layer including a conductive structure and a dielectric structure vertically adjacent to the conductive structure; trenches extending entirely vertically through the stacked structure and filled with a dielectric material; additional trenches alternating horizontally with the trenches and extending partially vertically through the stacked structure, at least one of the additional trenches having a non-planar horizontal boundary and filled with additional dielectric material; a source layer vertically located below the stacked structure and including a source structure and discrete conductive structures electrically isolated from each other and from the source structures; and conductive pillars extending vertically through the stacked structure to reach the discrete conductive structures of the source layer.

[0100] The methods, structures (e.g., microelectronic device structures 100, 600), devices (e.g., microelectronic device 601), and systems (e.g., electronic system 700) of this disclosure advantageously promote one or more of the following compared to conventional structures, devices, and systems: improved performance, reliability and durability, lower cost, increased component miniaturization, improved pattern quality, and higher package density. By means of non-limiting examples, the methods and configurations of this disclosure can reduce the risk of unwanted current leakage and short circuits (e.g., SGD-SGD current leakage and short circuits) compared to conventional methods and configurations.

[0101] refer to Figure 8 The present invention describes a processor-based system 800. The processor-based system 800 may include various microelectronic devices and microelectronic device structures manufactured according to embodiments of the present disclosure (e.g., microelectronic devices and microelectronic device structures including one or more of microelectronic device 601 or microelectronic device structures 100, 600). The processor-based system 800 may be any of a variety of types, such as a computer, pager, cellular phone, personal memo pad, control circuitry, or other electronic device. The processor-based system 800 may include one or more processors 802 (e.g., microprocessors) to control system functions and request processing in the processor-based system 800. The processor 802 and other sub-components of the processor-based system 800 may include microelectronic devices and microelectronic device structures manufactured according to embodiments of the present disclosure (e.g., microelectronic devices and microelectronic device structures including one or more of microelectronic device 601 or microelectronic device structures 100, 600).

[0102] The processor-based system 800 may include a power supply 804 operatively connected to the processor 802. For example, if the processor-based system 800 is a portable system, the power supply 804 may include one or more of a fuel cell, an energy purification device, a permanent battery, a replaceable battery, and a rechargeable battery. For example, the power supply 804 may also include an AC adapter; thus, the processor-based system 800 can be plugged into a wall outlet. For example, the power supply 804 may also include a DC adapter, allowing the processor-based system 800 to be plugged into a vehicle cigarette lighter or a vehicle power port.

[0103] Various other devices may be coupled to processor 802 depending on the functions performed by processor-based system 800. For example, user interface 806 may be coupled to processor 802. User interface 806 may include input devices such as buttons, switches, keyboards, light pens, mice, digitizers and styluses, touchscreens, voice recognition systems, microphones, or combinations thereof. Display 808 may also be coupled to processor 802. Display 808 may include LCD displays, SED displays, CRT displays, DLP displays, plasma displays, OLED displays, LED displays, 3D projections, audio displays, or combinations thereof. Furthermore, RF subsystem / baseband processor 810 may also be coupled to processor 802. RF subsystem / baseband processor 810 may include antennas coupled to RF receivers and RF transmitters (not shown). Communication port 812 or more may also be coupled to processor 802. For example, communication port 812 may be adapted to couple to one or more peripheral devices 814 (e.g., modem, printer, computer, scanner, or camera) or to a network (e.g., local area network, remote area network, corporate intranet, or Internet).

[0104] Processor 802 can control processor-based system 800 by implementing software programs stored in memory. For example, the software programs may include operating systems, database software, graphics software, word processing software, media editing software, or media playback software. Memory is operatively coupled to processor 802 to store and facilitate the execution of various programs. For example, processor 802 may be coupled to system memory 816, which may include one or more of spin torque transfer magnetic random access memory (STT-MRAM), magnetic random access memory (MRAM), dynamic random access memory (DRAM), static random access memory (SRAM), race memory, and other known memory types. System memory 816 may include volatile memory, non-volatile memory, or combinations thereof. System memory 816 is typically large enough to dynamically store loaded applications and data. In some embodiments, system memory 816 may include semiconductor devices, such as the microelectronic devices and microelectronic device structures described above (e.g., microelectronic device 301 and microelectronic device structures 100, 300), or combinations thereof.

[0105] Processor 802 may also be coupled to non-volatile memory 818, which does not imply that system memory 816 is necessarily volatile. Non-volatile memory 818 may include one or more of STT-MRAM, MRAM, read-only memory (ROM) (e.g., EPROM, resistive read-only memory (RROM)), and flash memory to be used in conjunction with system memory 816. The size of non-volatile memory 818 is typically chosen to be sufficient to store only the necessary operating system, applications, and fixed data. Alternatively, for example, non-volatile memory 818 may include mass storage such as disk drive memory, such as a hybrid drive containing resistive memory, or other types of non-volatile solid-state memory. Non-volatile memory 818 may include microelectronic devices, such as the microelectronic devices and microelectronic device structures described above (e.g., microelectronic device 601 and microelectronic device structures 100, 600), or combinations thereof.

[0106] Embodiments of this disclosure include a method of forming a microelectronic device. The method includes forming a microelectronic device structure. The microelectronic device structure includes a stacked structure having a vertically alternating sequence of conductive and insulating structures arranged in layers. The stacked structure comprises a stacked structure including a vertically alternating sequence of conductive and insulating structures arranged in layers, the stacked structure being divided into blocks separated from each other by filling trenches. Each block includes an upper stadium-like structure, a lower stadium-like structure, and a peak region between a first stepped structure of the upper stadium-like structure and a second stepped structure of the lower stadium-like structure. The microelectronic device structure further includes a dielectric structure extending parallel through the upper stadium-like structure and into the peak region, the dielectric structure extending vertically through and segmenting some layers of conductive structures to form an upper select gate. The method further includes forming trenches to extend between and partially overlap two dielectric structures in at least the peak region of one or more blocks of the stacked structure, and filling the trenches at least substantially with a dielectric material.

[0107] Some embodiments of this disclosure include microelectronic devices. The microelectronic devices include a stacked structure comprising a vertically alternating sequence of conductive and insulating structures arranged in layers, the stacked structure being divided into blocks separated from each other by filler slots. Each block includes: an upper stadium-like structure including a first stepped structure with a negative slope facing an additional first stepped structure with a positive slope; a lower stadium-like structure including a second stepped structure with a negative slope facing an additional second stepped structure with a positive slope; and a peak region horizontally inserted between the additional first stepped structure of the upper stadium-like structure and the second stepped structure of the lower stadium-like structure. The microelectronic device further includes: a dielectric-filled trench extending horizontally parallel through an upper stadium-like structure and into a peak region, the dielectric-filled trench extending vertically through several layers of conductive structures and physically separating the conductive structures to define an upper select gate for each of the stacked structural blocks; and at least one additional dielectric-filled trench in at least a peak region of one or more blocks of the stacked structure, the at least one additional dielectric-filled trench extending horizontally between two dielectric-filled trenches within the horizontal boundaries of the one or more blocks and partially overlapping the two dielectric-filled trenches.

[0108] Additional embodiments of this disclosure include a memory device comprising a stacked structure including a vertically alternating sequence of hierarchically arranged conductive and insulating structures. The stacked structure includes an upper segmented stadium-like structure comprising: opposing stepped structures, each step having a step including edges of some layers of the stacked structure; and a bridge structure adjacent to a horizontal boundary of the opposing stepped structures in a first horizontal direction and including portions of some layers extending from and between the opposing stepped structures in a second horizontal direction orthogonal to the first horizontal direction. The stacked structure further includes: a lower segmented stadium-like structure adjacent to the upper segmented stadium-like structure in the second horizontal direction; and a peak region inserted between the upper and lower segmented stadium-like structures in the second horizontal direction. The memory device further includes: a dielectric fill trench structure extending parallel to the upper stadium-like structure in a second horizontal direction, the dielectric fill trench structure extending vertically through several layers of conductive structures and separating the conductive structures to define an upper select gate; at least one fill trench extending horizontally in the second horizontal direction through the peak region of the stacked structure and reaching the dielectric fill trench structure, the at least one fill trench being inserted between a pair of dielectric fill trenches in a first horizontal direction; and a memory cell string extending vertically through the stacked structure.

[0109] Embodiments of this disclosure include an electronic system. The electronic system includes an input device, an output device, a processor device operatively coupled to the input device and the output device, and a memory device operatively coupled to the processor device and including a microelectronic device architecture. The microelectronic device architecture includes a stacked structure comprising a vertically alternating sequence of hierarchically arranged conductive and insulating structures. The stacked structure may include a stadium-like structure having steps, the steps including a horizontal end of a group of drain-select gates between a dielectric-filled trench structure inserted into the stacked structure and a peak region extending horizontally from the uppermost staircase of the stadium-like structure. The memory device further includes a filling trench extending vertically through at least the peak region of the stacked structure, the filling trench electrically isolating a first group of drain-select gates from a second group of drain-select gates.

[0110] Non-limiting exemplary embodiments may include the following, individually or in combination:

[0111] Example 1. A method of forming a microelectronic device, comprising: forming a microelectronic device structure, the microelectronic device structure comprising: a stacked structure including a vertically alternating sequence of conductive and insulating structures arranged in layers, the stacked structure being divided into blocks separated from each other by filling trenches, each block including: an upper stadium-like structure; a lower stadium-like structure; and a peak region defined between a first stepped structure of the upper stadium-like structure and a second stepped structure of the lower stadium-like structure; a dielectric structure extending parallel through the upper stadium-like structure and into the peak region, the dielectric structure extending vertically through and segmenting some layers of conductive structures to form an upper select gate; forming trenches to extend between and partially overlap the two dielectric structures in at least the peak region of one or more blocks of the stacked structure; and

[0112] The trench is at least substantially filled with a dielectric material.

[0113] Example 2. The method according to Example 1, wherein forming the trench includes removing portions of some of the upper selected gates of the one or more blocks of the stacked structure.

[0114] Example 3. The method according to any one of Examples 1 and 2, wherein forming the trench includes forming the lower vertical boundary of the trench as the lower vertical boundary of the upper selected gate at or below some of the lowermost layers.

[0115] Example 4. The method according to any one of Examples 1 to 3, wherein forming the trench includes forming the width of the trench to be substantially equal to the distance between two of the dielectric structures.

[0116] Example 5. The method according to any one of Examples 1 to 4, wherein forming the trench includes electrically separating the first set of upper select gates from the second set of upper select gates in the peak regions of the one or more of the blocks.

[0117] Example 6. The method according to any one of Examples 1 to 5, wherein forming the trench includes forming the trench to extend vertically through at least eight of the layers of the stacked structure.

[0118] Example 7. The method according to any one of Examples 1 to 6, wherein forming the trench includes: forming a mask material over the stacked structure; forming one or more elongated openings in the mask material to form a patterned mask material; and removing portions of the one or more blocks of the stacked structure through the one or more elongated openings.

[0119] Example 8. The method according to any one of Examples 1 to 7, further comprising a support column structure extending vertically through the stacked structure.

[0120] Example 9. A microelectronic device comprising: a stacked structure including a vertically alternating sequence of conductive and insulating structures arranged in layers, the stacked structure being divided into blocks separated from each other by filling slots, each block comprising: an upper stadium-like structure including a first stepped structure with a negative slope facing an additional first stepped structure with a positive slope; a lower stadium-like structure including a second stepped structure with a negative slope facing an additional second stepped structure with a positive slope; and a peak region horizontally inserted into the additional first stepped structure of the upper stadium-like structure and the lower stadium-like structure. Between the second-step structure; a dielectric-filled trench extending horizontally parallel through the upper stadium-like structure and into the peak region, the dielectric-filled trench extending vertically through several layers of conductive structures and physically separating the conductive structures to define an upper selection gate in each of the blocks of the stacked structure; and at least one additional dielectric-filled trench in at least the peak region of one or more of the blocks of the stacked structure, the at least one additional dielectric-filled trench extending horizontally between two dielectric-filled trenches within the horizontal boundaries of the one or more of the blocks and partially overlapping the two dielectric-filled trenches.

[0121] Example 10. The microelectronic device according to Example 9, wherein the upper stadium-like structure includes an upper segmented stadium, the upper segmented stadium including: a bridge structure adjacent to the horizontal boundary of the first stepped structure in a first horizontal direction and including portions of some of the layers, the portions extending from the first stepped structure and the additional first stepped structure in a second horizontal direction orthogonal to the first horizontal direction and extending between the first stepped structure and the additional first stepped structure.

[0122] Example 11. A microelectronic device according to any one of Examples 9 and 10, wherein the lower stadium-like structure includes a lower segmented stadium-like structure.

[0123] Example 12. A microelectronic device according to any one of Examples 9 to 11, wherein the lowest boundary of the at least one additional dielectric filling trench vertically covers the lowest boundary of the upper stadium-like structure of the one or more blocks of the stacked structure.

[0124] Example 13. A microelectronic device according to any one of Examples 9 to 12, wherein the lowermost boundary of the at least one additional dielectric filling trench vertically covers the uppermost boundary of the lower stadium-like structure of the one or more blocks of the stacked structure.

[0125] Example 14. A microelectronic device according to any one of Examples 9 to 13, further comprising a support column structure extending vertically through the stacked structure.

[0126] Example 15. A microelectronic device according to any one of Examples 9 to 14, wherein the at least one additional dielectric filling trench extends horizontally from and between the relative horizontal boundaries of the two dielectric filling trenches.

[0127] Example 16. A microelectronic device according to any one of Examples 9 to 15, wherein the lower vertical boundary of the filling trench is located at or vertically below the lower vertical boundary of the upper select gate of the lowest layer of the layers.

[0128] Example 17. A microelectronic device according to any one of Examples 9 to 16, wherein some of the layers of the stacked structure include at least eight of the layers of the stacked structure.

[0129] Example 18. A microelectronic device according to any one of Examples 9 to 17, further comprising a source layer below the stacked structure and including a source plate.

[0130] Example 19. A memory device comprising: a stacked structure including a vertically alternating sequence of conductive and insulating structures arranged in layers, the stacked structure further comprising: an upper segmented stadium-like structure including: opposing stepped structures, each stepped structure having a step, the step including edges of some of the layers of the stacked structure; and a bridge structure adjacent to the horizontal boundary of the opposing stepped structures in a first horizontal direction and including portions of the layers, the portions extending from the opposing stepped structures and between the opposing stepped structures in a second horizontal direction orthogonal to the first horizontal direction; and a lower segmented stadium-like structure adjacent to the upper structure in the second horizontal direction. A segmented stadium-like structure; and a peak region inserted in the second horizontal direction between the upper segmented stadium-like structure and the lower segmented stadium-like structure; a dielectric fill trench structure extending parallel through the upper segmented stadium-like structure in the second horizontal direction, the dielectric fill trench structure extending vertically through several layers of conductive structures and separating the conductive structures to define an upper select gate; at least one fill trench extending horizontally in the second horizontal direction through the peak region of the stacked structure and reaching the dielectric fill trench structure, the at least one fill trench inserted in the first horizontal direction between a pair of dielectric fill trench structures; and a memory cell string extending vertically through the stacked structure.

[0131] Example 20. The memory device according to Example 19, wherein the filling trench electrically separates the first set of upper select gates from the second set of upper select gates.

[0132] Example 21. A memory device according to any one of Examples 19 and 20, further comprising a support column structure extending vertically through the stacked structure.

[0133] Example 22. The memory device according to Example 21 further includes: an access line contact structure on the steps of the upper segment stadium-like structure and the lower stadium-like structure; a data line covering the stacked structure; an access line electrically connected to the access line contact structure; and a control device including a CMOS circuit system vertically below a source layer including a source plate and within the horizontal boundary of the support pillar structure, the control device being electrically coupled to the source plate, the data line, and the access line.

[0134] Example 23. A memory device according to any one of Examples 19 to 22, wherein some of the layers of the stacked structure include at least four of the layers of the stacked structure.

[0135] Example 24. An electronic system comprising an input device; an output device; a processor device operatively coupled to the input device and the output device; and a memory device operatively coupled to the processor device and including a microelectronic device structure, the microelectronic device structure comprising: a stacked structure including a vertically alternating sequence of hierarchically arranged conductive and insulating structures, the stacked structure including: a stadium-like structure having steps, the steps including horizontal ends of a group of drain-select gates inserted into dielectric fill trench structures in the stacked structure; and a peak region extending horizontally from the uppermost staircase of the stadium-like structure; and a fill trench extending vertically through at least the peak region of the stacked structure, the fill trench electrically isolating a first of the group of drain-select gates from a second of the group of drain-select gates.

[0136] Example 25. The electronic system according to Example 24, wherein the memory device includes a multi-stack 3D NAND flash memory device.

[0137] While this disclosure is susceptible to various modifications and alternatives, specific embodiments have been illustrated by way of example in the figures and described in detail herein. However, this disclosure is not limited to the specific forms disclosed. In fact, this disclosure covers all modifications, equivalents, and alternatives, as well as their legal equivalents, that fall within the scope of the appended claims.

Claims

1. A method for forming a microelectronic device, comprising: Forming a microelectronic device structure, the microelectronic device structure comprising: A stacked structure comprising a vertically alternating sequence of conductive and insulating structures arranged in layers, the stacked structure being divided into blocks separated from each other by filling slots, each block comprising: The upper stadium-style structure includes a first stepped structure with a negative slope, which faces an additional first stepped structure with a positive slope. The lower stadium-style structure includes a second stepped structure with a negative slope, the second stepped structure facing an additional second stepped structure with a positive slope; and The peak region is horizontally inserted between the additional first tier structure of the upper stadium-like structure and the second tier structure of the lower stadium-like structure; Dielectric-filled trenches extend horizontally and parallel through at least a portion of the upper stadium-like structure and into the peak region, and the dielectric-filled trenches extend vertically through and physically separate the conductive structures of some of the layers to define an upper selected gate in each of the blocks of the stacked structure. At least one additional dielectric filling trench is formed in at least the peak region of one or more blocks in the stacked structure, the at least one additional dielectric filling trench extending horizontally between and partially overlapping the two dielectric filling trenches within the horizontal boundary of the one or more blocks in the block.

2. The method of claim 1, wherein forming the trench comprises removing portions of some of the upper selected gates of the one or more blocks of the stacked structure.

3. The method of claim 1, wherein forming the trench comprises forming the lower vertical boundary of the trench as the lower vertical boundary of the upper selected gate of the lowest level of some of the layers.

4. The method of claim 1, wherein forming the trench comprises forming the width of the trench to be substantially equal to the distance between the two dielectric-filled trenches.

5. The method according to any one of claims 1 to 4, wherein forming the trench includes electrically separating the first set of upper select gates from the second set of upper select gates within the peak regions of the one or more of the blocks.

6. The method according to any one of claims 1 to 4, wherein forming the trench comprises forming the trench to extend vertically through at least eight of the layers of the stacked structure.

7. The method according to any one of claims 1 to 4, wherein forming the trench comprises: A mask material is formed over the stacked structure; One or more elongated openings are formed in the mask material to form a patterned mask material; and Parts of the one or more blocks of the stacked structure are removed through the one or more elongated openings.

8. The method according to any one of claims 1 to 4, further comprising a support column structure extending vertically through the stacked structure.

9. A microelectronic device comprising: A stacked structure comprising a vertically alternating sequence of conductive and insulating structures arranged in layers, the stacked structure being divided into blocks separated from each other by filling slots, each block comprising: The upper stadium-style structure includes a first stepped structure with a negative slope, which faces an additional first stepped structure with a positive slope. The lower stadium-style structure includes a second stepped structure with a negative slope, the second stepped structure facing an additional second stepped structure with a positive slope; and The peak region is horizontally inserted between the additional first tier structure of the upper stadium-like structure and the second tier structure of the lower stadium-like structure; Dielectric-filled trenches extend horizontally parallel through the upper stadium-like structure and into the peak region; the dielectric-filled trenches also extend vertically through some of the conductive structures in the layers and physically separate the conductive structures to define an upper selection gate in each of the blocks of the stacked structure; and At least one additional dielectric fill trench extends horizontally and partially overlaps the two dielectric fill trenches within the horizontal boundaries of the one or more blocks in the stacked structure at least in the peak region of the stacked structure.

10. The microelectronic device of claim 9, wherein the upper stadium-type structure comprises an upper segmented stadium, the upper segmented stadium comprising: A bridge structure that is adjacent to the horizontal boundary of the first stepped structure in a first horizontal direction and includes portions of some of the layers, the portions extending from the first stepped structure and the additional first stepped structure in a second horizontal direction orthogonal to the first horizontal direction and extending between the first stepped structure and the additional first stepped structure.

11. The microelectronic device of claim 9, wherein the lower stadium-like structure comprises a lower segmented stadium-like structure.

12. The microelectronic device according to any one of claims 9 to 11, wherein the lowest boundary of the at least one additional dielectric filling trench vertically overlaps the lowest boundary of the upper stadium-like structure of the one or more blocks of the stacked structure.

13. The microelectronic device according to any one of claims 9 to 11, wherein the lowermost boundary of the at least one additional dielectric filling trench vertically overlaps the uppermost boundary of the lower stadium-like structure of the one or more blocks of the stacked structure.

14. The microelectronic device according to any one of claims 9 to 11, further comprising a support pillar structure extending vertically through the stacked structure.

15. The microelectronic device according to any one of claims 9 to 11, wherein the at least one additional dielectric filling trench extends horizontally from and between the relative horizontal boundaries of the two dielectric filling trenches.

16. The microelectronic device according to any one of claims 9 to 11, wherein the lower vertical boundary of the filling trench is located at or vertically below the lower vertical boundary of the upper select gate of the lowest layer of the layers.

17. The microelectronic device according to any one of claims 9 to 11, wherein some of the layers of the stacked structure include at least eight of the layers of the stacked structure.

18. The microelectronic device according to any one of claims 9 to 11, further comprising a source layer below the stacked structure and including a source plate.

19. A memory device comprising: A stacked structure having a vertically alternating sequence of layered conductive and insulating structures, the stacked structure further comprising: The upper section is a stadium-style structure, which includes: Compared to a stepped structure, each stepped structure has steps that include some of the edges of the layers of the stacked structure; The lower segment stadium-style structure, which is adjacent to the upper segment stadium-style structure in the second horizontal direction, includes: Compared to a stepped structure, each stepped structure has steps at the edges of some of the layers of the stacked structure; A bridge structure, which is adjacent in a first horizontal direction to the horizontal boundary of the relative stepped structure of the upper segment stadium-like structure and the lower segment stadium-like structure and includes portions of some of the layers, the portions extending in a second horizontal direction orthogonal to the first horizontal direction across the relative stepped structure of the upper segment stadium-like structure and the lower segment stadium-like structure and extending between the relative stepped structure of the upper segment stadium-like structure and the lower segment stadium-like structure; The peak region is inserted between the upper segment stadium-like structure and the lower segment stadium-like structure in the second horizontal direction; A dielectric filling trench structure extends parallel to a portion of the upper segmented stadium-like structure in the second horizontal direction, and the dielectric filling trench structure extends vertically through and separates several layers of the conductive structure to define an upper selection gate. At least one filling trench extends horizontally in the second horizontal direction through the peak region of the stacked structure and into the dielectric filling trench structure, the at least one filling trench being inserted between a pair of the dielectric filling trench structures in the first horizontal direction; and A string of memory cells extends vertically through the stacked structure.

20. The memory device of claim 19, wherein the filling trench electrically separates the first set of upper select gates from the second set of upper select gates.

21. The memory device of claim 19, further comprising a support pillar structure extending vertically through the stacked structure.

22. The memory device of claim 21, further comprising: Access line contact structure, which is located on the steps of the upper segment stadium-style structure and the lower segment stadium-style structure; Data cable, which is covered by the stacked structure; Access line, which is electrically connected to the access line contact structure; and A control device includes a CMOS circuit system vertically below a source layer including a source plate and within the horizontal boundary of the support pillar structure, the control device being electrically coupled to the source plate, the data line, and the access line.

23. The memory device according to any one of claims 19 to 22, wherein some of the layers of the stacked structure include at least four of the layers of the stacked structure.

24. An electronic system comprising: Input device; Output device; A processor device operatively coupled to the input device and the output device; and A memory device operatively coupled to the processor device and comprising: A stacked structure comprising a vertically alternating sequence of conductive and insulating structures arranged in layers, the stacked structure further comprising: The upper section is a stadium-style structure, which includes: Compared to the stepped structure, each stepped structure has steps at the edges of some of the layers of the stacked structure; and The lower segment stadium-style structure, which is adjacent to the upper segment stadium-style structure in the second horizontal direction, includes: Compared to a stepped structure, each stepped structure has steps at the edges of some of the layers of the stacked structure; A bridge structure, located in a first horizontal direction adjacent to the horizontal boundaries of the relative stepped structures of the upper and lower segmented stadium structures and including portions of some of the layers, the portions extending in a second horizontal direction orthogonal to the first horizontal direction across the relative stepped structures of the upper and lower segmented stadium structures and extending between the relative stepped structures of the upper and lower segmented stadium structures; and The peak region, which is inserted between the upper segment stadium-like structure and the lower segment stadium-like structure in the second horizontal direction; and A dielectric filling trench structure extends parallel to a portion of the upper segmented stadium-like structure in the second horizontal direction, and the dielectric filling trench structure extends vertically through and separates several layers of the conductive structure to define an upper selection gate. At least one filling trench extends horizontally in the second horizontal direction through the peak region of the stacked structure and into the dielectric filling trench structure, the at least one filling trench being inserted between a pair of the dielectric filling trench structures in the first horizontal direction.

25. The electronic system of claim 24, wherein the memory device comprises a multi-stack 3D NAND flash memory device.

Images