Three-dimensional memory and methods of making the same, memory systems, electronic devices

Abstract

The application provides a three-dimensional memory, a preparation method thereof, a storage system and an electronic device. The preparation method of the three-dimensional memory comprises the following steps: alternately stacking gate layers and sacrifice layers to form a stack structure; forming a channel structure penetrating through the stack structure, the channel structure comprising a blocking layer, a charge capturing layer and a tunneling layer formed in sequence on the inner wall of a channel hole; sequentially removing the sacrifice layers and the part of the blocking layer corresponding to the sacrifice layers to form a sacrifice gap; isolating the part of the charge capturing layer corresponding to the space between adjacent gate layers through the sacrifice gap; forming a gate dielectric layer in the sacrifice gap; and forming an auxiliary conductive layer on the surface of the gate layer close to the gate dielectric layer.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically, to three-dimensional memory and its fabrication methods, memory systems, and electronic devices. Background Technology

[0002] Three-dimensional memory increases storage density by using vertical memory arrays. The fabrication process of three-dimensional memory mainly includes: firstly, forming channel vias in a stacked structure of alternating dielectric and gate layers, and then sequentially depositing functional layers and channel layers in the channel vias to form a channel structure with storage function.

[0003] The functional layer in the channel structure is the key structure for the three-dimensional memory to perform its storage function. Specifically, the functional layer includes a silicon oxide-silicon nitride-silicon oxide (ONO) structure formed sequentially on the outer wall of the channel structure, and each gate layer can contact the corresponding ONO structure functional layer. Furthermore, the gate layer can control the corresponding ONO structure to achieve the storage function by capturing charges.

[0004] In existing technologies, silicon nitride (SiN) layers are used as charge traps to retain charges (holes or electrons) within the trapping layer. However, during storage, the charges stored in the charge traps diffuse axially into the channel structure, reducing the storage reliability of the charge trapping layer corresponding to each gate layer and thus decreasing the retention characteristics of the three-dimensional memory. Improving lateral charge spread within the charge traps is one of the technical problems that those skilled in the art are dedicated to solving. Summary of the Invention

[0005] This application provides a method for fabricating a three-dimensional memory, which includes: alternately stacking gate layers and sacrificial layers to form a stacked structure; forming a channel structure penetrating the stacked structure, the channel structure including a barrier layer, a charge trapping layer and a tunneling layer sequentially formed on the inner wall of the channel hole; sequentially removing the sacrificial layer and the portion of the barrier layer corresponding to the sacrificial layer to form a sacrificial gap; isolating the portion of the charge trapping layer corresponding to the adjacent gate layers through the sacrificial gap; forming a gate dielectric layer within the sacrificial gap; wherein an auxiliary conductive layer is formed on the surface of the gate layer near the gate dielectric layer.

[0006] In one embodiment, isolating a portion of the charge trapping layer corresponding to the adjacent gate layers via the sacrificial gap includes: etching away the portion of the charge trapping layer exposed by the sacrificial gap.

[0007] In one embodiment, the portion of the charge trapping layer exposed by the sacrificial gap is oxidized to form an oxide layer.

[0008] In one embodiment, the gate layer includes a first conductive layer, a semiconductor layer, and a second conductive layer stacked sequentially, and the gate layer and the sacrificial layer are alternately stacked to form a stacked structure, including: alternately stacking the first conductive layer, the semiconductor layer, the second conductive layer, and the sacrificial layer to form a stacked structure.

[0009] In one embodiment, the method includes performing an annealing process on the gate layer to form an auxiliary conductive layer on the surface of the gate layer adjacent to the gate dielectric layer.

[0010] In one embodiment, the method further includes filling an oxide layer in the area exposed by removing the charge trapping layer.

[0011] In one embodiment, the method further includes forming a conductive layer on the surface of the gate layer exposed to the sacrificial gap.

[0012] In one embodiment, the method includes performing an annealing process on the conductive layer and the gate layer to form an auxiliary conductive layer on the surface of the gate layer near the gate dielectric layer.

[0013] In one embodiment, forming a conductive layer on the surface of the gate layer exposed to the sacrificial gap includes: forming a conductive layer on the surface of the gate layer exposed to the sacrificial gap and on the oxide layer; and removing the conductive layer on the oxide layer.

[0014] In one embodiment, the sacrificial layer is made of silicon nitride; the semiconductor layer is made of silicon; the first conductive layer and the second conductive layer are made of metal; and the auxiliary conductive layer is made of metal silicide.

[0015] In one embodiment, the sacrificial layer is made of silicon nitride; the gate layer is made of silicon; the conductive layer is made of metal; and the auxiliary conductive layer is made of metal silicide.

[0016] Another aspect of this application provides a three-dimensional memory, comprising: a stacked structure including alternating gate layers and gate dielectric layers; and a channel structure extending through the stacked structure and including: a tunneling layer; a charge trapping layer located outside the tunneling layer and spaced into a plurality of charge trapping portions by the gate dielectric layer; and a blocking layer located outside the charge trapping layer and spaced into a plurality of blocking portions by the gate dielectric layer.

[0017] In one embodiment, the gate layer includes an alternately stacked first auxiliary conductive layer, a semiconductor layer, and a second auxiliary conductive layer, wherein the first auxiliary conductive layer and the second auxiliary conductive layer are made of metal silicide; and the semiconductor layer is made of silicon.

[0018] In one embodiment, the trench structure further includes a trench layer located inside the tunneling layer.

[0019] This application also provides a storage system. The storage system includes a controller and the aforementioned three-dimensional memory, the controller being coupled to the three-dimensional memory and used to control the storage of data in the three-dimensional memory.

[0020] Another aspect of this application provides an electronic device, including the aforementioned storage system.

[0021] According to one or more embodiments of this application, by isolating portions of the charge trapping layer corresponding to adjacent gate layers, an insulating gap can be created between the charge trapping layers corresponding to adjacent gate layers. This effectively suppresses lateral diffusion of the charge trapping layer corresponding to each gate layer, improves the storage reliability of the charge trapping layer, and thereby improves the storage retention characteristics of the fabricated three-dimensional memory.

[0022] According to one or more embodiments of this application, by forming an auxiliary conductive layer on the surface of the gate layer near the gate dielectric layer, the conductivity of the gate layer can be improved, thereby reducing the thickness of the gate layer while ensuring its conductivity.

[0023] According to one or more embodiments of this application, by replacing the sacrificial layer without replacing the gate layer, it is possible to isolate the portion of the charge trapping layer corresponding to adjacent gate layers while maintaining the conductivity of the three-dimensional memory. Compared to conventional processes that require separate replacement of the gate layer and sacrificial layer to achieve the above objective, this application, by replacing only the sacrificial layer without replacing the gate layer, helps to reduce the collapse of the overall structure. Attached Figure Description

[0024] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings.

[0025] Figure 1 This is a flowchart of a method for fabricating a three-dimensional memory according to an exemplary embodiment of this application;

[0026] Figures 2 to 10 This is a process step diagram of a method for fabricating a three-dimensional memory according to an exemplary embodiment of this application;

[0027] Figures 11 to 18This is a process step diagram of a method for fabricating a three-dimensional memory according to an exemplary embodiment of this application;

[0028] Figure 19 This is a schematic diagram of the structure of a storage system according to one embodiment of this application; and

[0029] Figure 20 This is a schematic diagram of the structure of an electronic device according to one embodiment of this application. Detailed Implementation

[0030] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely descriptions of exemplary embodiments of this application and are not intended to limit the scope of this application in any way.

[0031] It should be noted that in this specification, the terms "first," "second," "third," etc., are used only to distinguish one feature from another and do not imply any limitation on the features, especially not any order of precedence. Therefore, without departing from the teachings of this application, the first conductive layer discussed herein may also be referred to as the second conductive layer, and vice versa.

[0032] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not drawn to scale. As used herein, the terms “approximately,” “about,” and similar terms are used as expressions of approximation, not as expressions of degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art.

[0033] The terminology used herein is for the purpose of describing particular exemplary embodiments and is not intended to be limiting. When used in this specification, the terms “comprising,” “including,” “including,” and / or “comprising” indicate the presence of the stated features, integrals, elements, components, and / or combinations thereof, but do not exclude the presence of one or more other features, integrals, elements, components, and / or combinations thereof.

[0034] This document describes the embodiments with reference to schematic diagrams of exemplary implementations. The exemplary implementations disclosed herein should not be construed as limited to the specific shapes and sizes shown, but rather include various equivalent structures capable of achieving the same function, as well as shape and size variations arising, for example, during manufacturing. The positions shown in the accompanying drawings are schematic in nature and not intended to limit the positions of the components.

[0035] Unless otherwise specified, all terms used herein (including technical and scientific terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. Terms such as those defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant field and shall not be interpreted in an idealized or overly formalized sense unless expressly defined herein.

[0036] As used herein, the term "layer" refers to a portion of material comprising a region having height. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate and the top side is relatively far from the substrate. A layer can extend over the entire lower or upper layer structure, or can have a range smaller than that of the lower or upper layer structure. Furthermore, a layer can be a region of a homogeneous or non-homogeneous continuous structure whose height is less than the height of the continuous structure. For example, a layer can be located at the top and bottom surfaces of a continuous structure or between any set of horizontal planes. A layer can extend horizontally, vertically, and / or along a tapered surface. A substrate can be a layer, and can include one or more layers, and / or can have one or more layers on, above, and / or below it. A layer can contain multiple layers.

[0037] Figure 1 This is a flowchart of a method for fabricating a three-dimensional memory according to an exemplary embodiment of this application.

[0038] like Figure 1 As shown, the fabrication method 1000 of the three-dimensional memory provided in this application may include: S1, alternately stacking gate layers and sacrificial layers to form a stacked structure; S2, forming a channel structure penetrating the stacked structure, the channel structure including a barrier layer, a charge trapping layer and a tunneling layer sequentially formed on the inner wall of the channel hole; S3, sequentially removing the portions of the sacrificial layer and the barrier layer corresponding to the sacrificial layer to form a sacrificial gap; S4, isolating the portions of the charge trapping layer corresponding to adjacent gate layers through the sacrificial gap; S5, forming a gate dielectric layer within the sacrificial gap, wherein an auxiliary conductive layer is formed on the surface of the gate layer near the gate dielectric layer. Steps S1 to S5 will be described in detail below.

[0039] Example 1:

[0040] Step S1

[0041] like Figure 2 As shown, the sacrificial layer 110 and the gate layer 120 can be alternately stacked to form a stacked structure 100. Exemplarily, the sacrificial layer 110 and the gate layer 120 can be alternately stacked on the substrate 200 to form the stacked structure 100. Specifically, the sacrificial layer 110 and the gate layer 120 can be alternately stacked on the substrate 200 by, for example, a deposition process to form the stacked structure 100.

[0042] In exemplary embodiments of this application, the substrate 200 may be, for example, a polycrystalline silicon (Si) substrate, a single-crystal silicon (Si) substrate, a single-crystal germanium (Ge) substrate, a silicon-germanium (GeSi) substrate, a silicon carbide (SiC) substrate, or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, or a substrate comprising other elemental semiconductors or compound semiconductors, such as gallium arsenide (GaAs), indium phosphide (InP), or SiC. In one embodiment, the substrate 200 may also be a stacked structure, such as Si / SiGe. In another embodiment, the substrate 200 may also be other epitaxial structures, such as silicon and germanium-on-insulator (SGOI).

[0043] In an exemplary embodiment of this application, forming a stacked structure 100 on the substrate 200 can be achieved through one or more deposition processes. The deposition processes for forming the stacked structure 100 include, but are not limited to, atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), or any combination thereof. It should be understood that the number and thickness of the sacrificial layer 110 and the gate layer 120 are not limited to... Figure 2 The quantities and thicknesses shown can be varied by those skilled in the art without departing from the concept of this application, allowing for the provision of any number and thickness of sacrificial layer 110 and gate layer 120 as needed. Furthermore, the materials of sacrificial layer 110 and gate layer 120 can be selected from suitable materials known in the art. For example, sacrificial layer 110 can be a nitride layer (such as silicon nitride), and gate layer 120 can be a silicide layer (such as silicon or polysilicon).

[0044] In an exemplary embodiment of this application, vias (not shown) such as gate line slits (GLS) penetrating the stacked structure 100 can be formed using processes such as photolithography and dry etching to expose the sacrificial layer 110 and the gate layer 120. The sacrificial layer 110 can then be removed vias in subsequent processes. Exemplarily, the materials of the sacrificial layer 110 and the gate layer 120 can have different etching selectivity ratios to facilitate removal of the sacrificial layer 110 in subsequent processes. Exemplarily, the material of the sacrificial layer 110 may include silicon nitride, and the material of the gate layer 120 may include silicon.

[0045] Step S2

[0046] like Figure 2 As shown, a channel structure 300 can be formed through a multilayer structure, wherein the channel structure 300 may include a barrier layer 320, a charge trapping layer 330, and a tunneling layer 340 sequentially formed on the inner wall of a channel hole 310. Exemplarily, a channel hole 310 can be formed through the multilayer structure 100, and a barrier layer 320, a charge trapping layer 330, and a tunneling layer 340 are sequentially formed on the inner wall of the channel hole 310. Exemplarily, the channel hole 310 through the multilayer structure 100 can be formed using, for example, a dry / wet etching process, and the channel hole 310 can extend into the substrate 200. Exemplarily, a thin film deposition process such as CVD, PVD, ALD, or any combination thereof can be used to sequentially deposit the barrier layer 320, the charge trapping layer 330, the tunneling layer 340, and the channel layer 350 on the inner wall of the channel hole 310.

[0047] For example, the barrier layer 320 may be formed on the surface of the inner wall of the channel hole 310 to block the outflow of charge (electrons or holes) stored in the charge trapping layer 330 and to provide electrical insulation between the charge trapping layer 330 and the stacked structure 100. Optionally, the barrier layer 320 may be made of silicon oxide.

[0048] For example, a charge trapping layer 330 may be formed on the surface of the barrier layer 320 for enabling data writing by injecting a certain amount of charge and maintaining the storage state by retaining the amount of charge. Optionally, the charge trapping layer 330 may be made of silicon nitride (SiN).

[0049] For example, the tunneling layer 340 may be formed on the surface of the charge trapping layer 330 to maintain data storage state by suppressing charge trapping or detrapping. Optionally, the material of the tunneling layer 340 may include silicon oxide.

[0050] For example, the barrier layer 320, the charge trapping layer 330, and the tunneling layer 340 may be referred to as functional layers. It should be understood that the functional layers can serve as the storage structure of the fabricated three-dimensional memory, and the portions of the functional layers corresponding to each gate layer 120 can form independent memory cells. Each memory cell can be controlled by the gate layer 120. Charge is stored or released in the functional layer corresponding to the gate layer 120 to realize the function of a single memory cell.

[0051] A channel layer 350 may be formed on the surface of the tunneling layer 340 for transporting the required charge to form a circuit loop between multiple memory cells. Optionally, the channel layer 350 may be made of doped polysilicon.

[0052] In an exemplary embodiment of this application, deep-hole etching can be used to electrically connect the channel layer 350 to the substrate 200 to form a circuit loop between the channel structure 300 and the source region in the substrate 200. Exemplarily, thin-film deposition processes such as CVD, PVD, ALD, or any combination thereof can be used to fill one or more dielectric materials 360, such as silicon oxide, within the channel hole 310 where the functional layer and channel layer 350 are formed to form the channel structure 300. Optionally, one or more air gaps can be formed during the channel filling process by controlling the channel filling process to alleviate structural stress. It should be understood that in this step, multiple channel structures 300 extending through the stacked structure 100 and into the substrate 200 can be formed, and the number and arrangement of the channel structures 300 can be prepared according to actual storage requirements.

[0053] Step S3

[0054] like Figure 4 As shown, portions of the sacrificial layer 110 and the barrier layer 320 corresponding to the sacrificial layer 110 can be removed sequentially to form a sacrificial gap 400. For example, as... Figure 3 As shown, vias (not shown) such as gate gaps (GLS) can be used as channels for etchants. For example, a wet etching process can be used to introduce the etchant into the vias to selectively remove all of the sacrificial layer 110 in the stacked structure 100. For instance, when the sacrificial layer 110 is made of silicon nitride (SiN), a phosphoric acid solution can be used as the etchant to remove the sacrificial layer 110 formed from silicon nitride, thereby forming a portion of the plurality of sacrificial gaps 400.

[0055] In an exemplary embodiment of this application, a dry / wet etching process may be employed, and by controlling the etching time, the portion of the barrier layer 320 corresponding to the plurality of sacrificial layers 110 is removed to form a plurality of complete sacrificial gaps 400. The plurality of sacrificial gaps 400 can provide space for filling the gate dielectric layer in subsequent processes.

[0056] Step S4

[0057] Below, this application provides two exemplary methods for implementing step S4. It should be understood that this application merely exemplifies two methods for implementing step S4 and does not explicitly limit the implementation to only these two methods. In actual processes, step S4 can be implemented in any suitable manner.

[0058] Method 1

[0059] like Figure 6 As shown, a portion of the charge trapping layer 330 corresponding to the adjacent gate layers 120 can be isolated via the sacrificial gap 400. Exemplarily, as... Figure 5As shown, the portion of the charge trapping layer 330 corresponding to adjacent gate layers 120 can be removed by an etching process. Exemplarily, after the above process, the entire structure of the functional layers (barrier layer 320, charge trapping layer 330, and tunneling layer) corresponding to each gate layer 120 can be retained. In other words, the outer wall of the channel structure 300 corresponding to each gate layer 120 includes, radially from the outside to the inside, a complete functional layer consisting of the barrier layer 320, the charge trapping layer 330, and the tunneling layer. The outer wall of the channel structure 300 corresponding to each sacrificial gap 400 includes, radially from the outside to the inside, the tunneling layer 340 of the functional layer.

[0060] In an exemplary embodiment of this application, an oxide layer, such as an insulating material, may be filled in the area exposed by the removed charge trapping layer 330 to form Figure 6 The structure is shown. Exemplarily, thin-film deposition processes such as CVD, PVD, ALD, or any combination thereof can be used to fill the exposed areas of the charge trapping layer 330 with an insulating material such as oxide. Filling the exposed areas of the charge trapping layer 330 with an insulating material can electrically insulate the portions of the charge trapping layer 330 corresponding to the adjacent gate layer 120.

[0061] Method 2

[0062] like Figure 6 As shown, a portion of the charge trapping layer 330 corresponding to the adjacent gate layers 120 can be isolated via a sacrificial gap 400. Exemplarily, during the formation of... Figure 4 Following the structure shown, the portion of the charge trapping layer 330 exposed by the sacrificial gap 400 is oxidized to form an oxide layer. Figure 6 As another exemplary alternative, an oxidation process can be used to oxidize the portion of the charge trapping layer 330 exposed by the sacrificial gap 400 to form an oxide layer, thereby forming... Figure 6 The structure shown. (As illustrated) Figure 6 As shown, the oxide layer formed can be made of insulating material.

[0063] Step S5

[0064] like Figure 10 As shown, a gate dielectric layer 500 is formed within the sacrificial gap 400, wherein an auxiliary conductive layer 140 is formed on the surface of the gate layer 120 near the gate dielectric layer 500. Exemplarily, firstly, a conductive layer 130 may be formed on the surface of the gate layer 120 exposed to the sacrificial gap 400. Figure 7 Secondly, an annealing process can be performed on the conductive layer 130 and the gate layer 120 to form an auxiliary conductive layer 140 on the surface of the gate layer 120 near the gate dielectric layer 500. Figure 8Then, a gate dielectric layer 500 can be formed within the sacrificial gap 400. Figure 10 ).

[0065] Exemplarily, a conductive layer 130 may be formed on the surface of the gate layer 120 exposed to the sacrificial gap 400 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. Exemplarily, the material of the conductive layer 130 may include a material with good conductivity, such as a metal. For example, the material of the conductive layer 130 may include tungsten. In an exemplary embodiment of this application, forming the conductive layer 130 on the surface of the gate layer 120 exposed to the sacrificial gap 400 may include: firstly, forming the conductive layer 130 on the surface of the gate layer 120 exposed to the sacrificial gap 400 and on an insulating material. Figure 7 Then, the conductive layer 130 on the insulating material can be removed. Figure 9 For example, such as Figure 8 As shown, after forming a conductive layer 130 on the surface of the gate layer 120 exposed to the sacrificial gap 400 and on the insulating material, an annealing process can be performed on the conductive layer 130 and the gate layer 120 to allow the metal in the conductive layer 130 to react with the silicon in the gate layer 120 to form an auxiliary conductive layer 140, i.e., a metal silicide 140. After the annealing process is completed, the conductive layer 130 on the insulating material can be removed, leaving the metal silicide 140, to form as shown in the diagram. Figure 9 The structure shown.

[0066] The metal silicide 140 layer can serve as a high-speed conductive channel for the gate layer 120, reducing the high resistance of silicon in the gate layer 120 and further reducing the thickness of the gate layer 120. Specifically, if the gate layer 120 contains only silicon, which has high resistance, the thickness of the gate layer 120 needs to be increased to reduce its resistance, thereby achieving a larger storage capacity at the same height. This application forms a conductive layer 130 on the surface of the gate layer 120 exposed to the sacrificial gap 400, and reacts the metal in the conductive layer 130 with the silicon in the gate layer 120 to form a metal silicide 140, which reduces the thickness of the gate layer 120 while simultaneously reducing its resistance.

[0067] In an exemplary embodiment of this application, the gate dielectric layer 500 may be made of an insulating material. Exemplarily, the gate dielectric layer 500, such as an oxide, may be filled within the sacrificial gap 400 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof. Exemplarily, this process may be completed... Figure 9 Following the process steps shown, a gate dielectric layer 500, such as silicon oxide, is filled into the sacrificial gap 400. The gate dielectric layer 500 can be used to provide structural support and to electrically insulate adjacent gate layers 120.

[0068] After the above process, the gate dielectric layer 500 can form a protrusion in the direction of the axial direction of the channel structure 300 between adjacent gate layers 120. The protrusion can make the barrier layer 320 and the charge trapping layer 330 corresponding to the adjacent gate layer 120 electrically insulated.

[0069] Example 2:

[0070] Step S1

[0071] like Figure 11 As shown, the sacrificial layer 110 and the gate layer 120 can be alternately stacked to form a stacked structure 100. The gate layer 120 includes a first conductive layer 121, a semiconductor layer 122, and a second conductive layer 121' stacked sequentially. Specifically, the first conductive layer 121, the semiconductor layer 122, the second conductive layer 121', and the sacrificial layer 110 can be alternately stacked to form the stacked structure 100. Exemplarily, the first conductive layer 121, the semiconductor layer 122, the second conductive layer 121', and the sacrificial layer 110 can be alternately stacked on the substrate 200 to form the stacked structure 100. Specifically, the first conductive layer 121, the semiconductor layer 122, the second conductive layer 121', and the sacrificial layer 110 can be alternately stacked on the substrate 200 by, for example, a deposition process to form the stacked structure 100.

[0072] In exemplary embodiments of this application, the substrate 200 may be, for example, a polycrystalline silicon (Si) substrate, a single-crystal silicon (Si) substrate, a single-crystal germanium (Ge) substrate, a silicon-germanium (GeSi) substrate, a silicon carbide (SiC) substrate, or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GOI) substrate, or a substrate comprising other elemental semiconductors or compound semiconductors, such as GaAs, InP, or SiC. In one embodiment, the substrate 200 may also be a stacked structure, such as Si / SiGe. In another embodiment, the substrate 200 may also be other epitaxial structures, such as silicon-germanium-on-insulator (SGOI).

[0073] In an exemplary embodiment of this application, forming a stacked structure 100 on the substrate 200 can be achieved through one or more deposition processes. The deposition processes for forming the stacked structure 100 include, but are not limited to, atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), or any combination thereof. It should be understood that the number and thickness of the sacrificial layer 110, the first conductive layer 121, the semiconductor layer 122, and the second conductive layer 121' are not limited to... Figure 11The quantities and thicknesses shown can be varied by those skilled in the art without departing from the concept of this application. Any number and thickness of the sacrificial layer 110, the first conductive layer 121, the semiconductor layer 122, and the second conductive layer 121' can be provided as needed. Furthermore, the materials of the sacrificial layer 110, the first conductive layer 121, the semiconductor layer 122, and the second conductive layer 121' can be suitable materials known in the art. For example, the sacrificial layer 110 can be a nitride layer (such as silicon nitride), the semiconductor layer 122 can be a silicide layer (such as silicon, polycrystalline silicon), and the first conductive layer 121 and the second conductive layer 121' can be metals (such as tungsten).

[0074] In an exemplary embodiment of this application, the materials of the sacrificial layer 110, the first conductive layer 121, the semiconductor layer 122, and the second conductive layer 121' may have different etching selectivity ratios to facilitate the removal of the sacrificial layer 110 in subsequent processes. For example, the material of the sacrificial layer 110 may include silicon nitride, the material of the semiconductor layer 122 may include silicon, and the first conductive layer 121 and the second conductive layer 121' may include tungsten.

[0075] For example, an annealing process can be performed on the gate layer 120 to cause the metal in the first conductive layer 121 and the second conductive layer 121' to react with the silicon in the semiconductor layer 122 to form a first auxiliary conductive layer 123 and a second auxiliary conductive layer 123' (i.e., metal silicide layers 123 and 123'). Figure 12 In other words, the gate layer 120' formed after annealing the gate layer 120 may include alternately stacked first auxiliary conductive layer 123 (metal silicide layer 123), semiconductor layer 122, and second auxiliary conductive layer 123' (metal silicide layer 123'). These metal silicide layers 123 and 123' can serve as high-speed conduction channels for the gate layer 120', reducing the high resistance of silicon in the gate layer 120' and further reducing the thickness of the gate layer 120'. Specifically, if the gate layer 120' contains only silicon elements with high resistance, the thickness of the gate layer 120' needs to be increased to reduce its resistance, thereby achieving a larger storage capacity at the same height. This application reduces the resistance of the gate layer 120' by reacting the metal in the first conductive layer 121 and the second conductive layer 121' with the silicon in the semiconductor layer 122 to form metal silicide layers 123 and 123', thus reducing the thickness of the gate layer 120' while simultaneously reducing its resistance.

[0076] Step S2

[0077] like Figure 13As shown, a channel hole 310 can be formed through the stacked structure 100, and a barrier layer 320, a charge trapping layer 330, and a tunneling layer 340 are sequentially formed on the inner wall of the channel hole 310. Exemplarily, the channel hole 310 through the stacked structure 100 can be formed using, for example, a dry / wet etching process, and the channel hole 310 can extend into the substrate 200. Exemplarily, the barrier layer 320, the charge trapping layer 330, the tunneling layer 340, and the channel layer 350 can be sequentially deposited on the inner wall of the channel hole 310 using a thin film deposition process such as CVD, PVD, ALD, or any combination thereof.

[0078] For example, the barrier layer 320 may be formed on the surface of the inner wall of the channel hole 310 to block the outflow of charge (electrons or holes) stored in the charge trapping layer 330 and to provide electrical insulation between the charge trapping layer 330 and the stacked structure 100. Optionally, the barrier layer 320 may be made of silicon oxide.

[0079] For example, a charge trapping layer 330 may be formed on the surface of the barrier layer 320 for enabling data writing by injecting a certain amount of charge and maintaining the storage state by retaining the amount of charge. Optionally, the charge trapping layer 330 may be made of silicon nitride (SiN).

[0080] For example, the tunneling layer 340 may be formed on the surface of the charge trapping layer 330 to maintain data storage state by suppressing charge trapping or detrapping. Optionally, the material of the tunneling layer 340 may include silicon oxide.

[0081] For example, the barrier layer 320, the charge trapping layer 330, and the tunneling layer 340 may be referred to as functional layers. It should be understood that the functional layers can serve as the storage structure of the fabricated three-dimensional memory, and the portions of the functional layers corresponding to each gate layer 120 can form independent memory cells. Each memory cell can be controlled by the gate layer 120. Charge is stored or released in the functional layer corresponding to the gate layer 120 to realize the function of a single memory cell.

[0082] A channel layer 350 may be formed on the surface of the tunneling layer 340 for transporting the required charge to form a circuit loop between multiple memory cells. Optionally, the channel layer 350 may be made of doped polysilicon.

[0083] In an exemplary embodiment of this application, deep-hole etching can be used to electrically connect the channel layer 350 to the substrate 200 to form a circuit loop between the channel structure 300 and the source region in the substrate 200. Further, thin-film deposition processes such as CVD, PVD, ALD, or any combination thereof can be used to fill one or more dielectric materials 360, such as silicon oxide, within the channel holes 310 where the functional layer and channel layer 350 are formed to form the channel structure 300. Optionally, one or more air gaps can be formed during the channel filling process by controlling the channel filling process to alleviate structural stress. It should be understood that in this step, multiple channel structures 300 extending through the stacked structure 100 and into the substrate 200 can be formed, and the number and arrangement of the channel structures 300 can be prepared according to actual storage requirements.

[0084] Step S3

[0085] like Figure 15 As shown, portions of the sacrificial layer 110 and the barrier layer 320 corresponding to the sacrificial layer 110 can be removed sequentially to form a sacrificial gap 400. For example, as... Figure 14 As shown, vias (not shown), such as gate gaps (GLS), can be used as channels for etchants. For example, a wet etching process can be used to introduce the etchant into the vias to selectively remove all of the sacrificial layer 110 in the stacked structure 100. For instance, when the sacrificial layer 110 is made of silicon nitride (SiN), a phosphoric acid solution can be used as the etchant to remove the sacrificial layer 110 formed from silicon nitride, thereby forming a portion of the plurality of sacrificial gaps 400. Exemplarily, vias (not shown), such as gate gaps (GLS), that penetrate the stacked structure 100 can be formed using processes such as photolithography or dry etching to expose the sacrificial layer 110, the first conductive layer 121, the second conductive layer 121', and the semiconductor layer 122.

[0086] In an exemplary embodiment of this application, a dry / wet etching process can be used, and by controlling the etching time, portions of the barrier layer 320 corresponding to the plurality of sacrificial layers 110 are removed sequentially to form a plurality of complete sacrificial gaps 400. The plurality of sacrificial gaps 400 can provide space for filling dielectric material in subsequent processes.

[0087] Step S4

[0088] Below, this application provides two exemplary methods for implementing step S4. It should be understood that this application merely exemplifies two methods for implementing step S4 and does not explicitly limit the implementation to only these two methods. In actual processes, step S4 can be implemented in any suitable manner.

[0089] Method 1

[0090] like Figure 17 As shown, a portion of the charge trapping layer 330 corresponding to the adjacent gate layers 120' can be isolated via a sacrificial gap 400. Exemplarily, as... Figure 16 As shown, the portion of the charge trapping layer 330 corresponding to adjacent gate layers 120' can be removed by an etching process. Exemplarily, after the above process, the entire structure of the functional layers (barrier layer 320, charge trapping layer 330, and tunneling layer 340) corresponding to each gate layer 120' can be retained. In other words, the outer wall of the channel structure 300 corresponding to each gate layer 120' includes, radially from the outside to the inside, a complete functional layer consisting of the barrier layer 320, the charge trapping layer 330, and the tunneling layer 340. The outer wall of the channel structure 300 corresponding to each sacrificial gap 400 includes, radially from the outside to the inside, the tunneling layer 340 of the functional layer.

[0091] In an exemplary embodiment of this application, an oxide layer, such as an insulating material, may be filled in the area exposed by the removed charge trapping layer 330 to form Figure 17 The structure is shown. Exemplarily, thin-film deposition processes such as CVD, PVD, ALD, or any combination thereof can be used to fill the exposed areas of the charge trapping layer 330 with an insulating material such as oxide. Filling the exposed areas of the charge trapping layer 330 with an insulating material can electrically insulate the portions of the charge trapping layer 330 corresponding to the adjacent gate layer 120'.

[0092] Method 2

[0093] like Figure 17 As shown, the portion of the charge trapping layer 330 corresponding to the adjacent gate layers 120' can be isolated via the sacrificial gap 400. Exemplarily, in the formation of... Figure 15 Following the structure shown, the portion of the charge trapping layer 330 exposed by the sacrificial gap 400 is oxidized to form an oxide layer. Figure 17 Alternatively, an oxidation process can be used to oxidize the portion of the charge trapping layer 330 exposed by the sacrificial gap 400 to form an oxide layer, thereby forming... Figure 17 The structure shown. (As illustrated) Figure 17 As shown, the oxide layer formed can be made of insulating material.

[0094] Step S5

[0095] like Figure 18 As shown, a gate dielectric layer 500 is formed within the sacrificial gap 400. Exemplarily, the gate dielectric layer 500 can be filled in the region exposed by the removal of the sacrificial layer 110 to form a structure as shown... Figure 18The structure is shown. It should be understood that a first auxiliary conductive layer 123 and a second auxiliary conductive layer 123' are formed on the surface of the gate layer 120' adjacent to the gate dielectric layer 500. Exemplarily, the gate dielectric layer 500, such as oxide, can be filled within the sacrificial gap 400 using thin film deposition processes such as CVD, PVD, ALD, or any combination thereof. The gate dielectric layer 500 can be used to provide structural support and electrically insulate adjacent gate layers 120'.

[0096] After the above process, the gate dielectric layer 500 can form a protrusion in the direction of the axial direction of the channel structure 300 between adjacent gate layers 120'. This protrusion can make the barrier layer 320 and the charge trapping layer 330 corresponding to the adjacent gate layer 120' electrically insulated.

[0097] This application also provides a three-dimensional memory. Figure 18 A schematic diagram of the structure of a three-dimensional memory according to an exemplary embodiment of this application is shown.

[0098] like Figure 18 As shown, the three-dimensional memory may include a stacked structure and a channel structure 300. The stacked structure may include alternately stacked gate layers 120' and gate dielectric layers 500. The gate layer 120' includes alternately stacked first auxiliary conductive layer 123, semiconductor layer 122, and second auxiliary conductive layer 123'. The first auxiliary conductive layer 123 and the second auxiliary conductive layer 123' can serve as high-speed channels for the gate layer 120' to conduct electricity, which can reduce the high resistance of silicon in the gate layer 120' and further reduce the thickness of the gate layer 120'. The channel structure 300 may penetrate the stacked structure. The channel structure 300 may include a tunneling layer 340, a charge trapping layer 330, and a barrier layer 320.

[0099] For example, the charge trapping layer 330 may be located outside the tunneling layer 340 and spaced into a plurality of charge trapping portions by the gate dielectric layer 500. For example, the blocking layer 320 may be located outside the charge trapping layer 330 and spaced into a plurality of blocking portions by the gate dielectric layer 500.

[0100] In an exemplary embodiment of this application, the semiconductor layer 122 may be made of silicon, and the first auxiliary conductive layer 123 and the second auxiliary conductive layer 123' may be made of metal compounds.

[0101] In an exemplary embodiment of this application, the material of the barrier layer 320 may include silicon oxide; the material of the charge trapping layer 330 may include silicon nitride; and the material of the tunneling layer 340 may include silicon oxide.

[0102] In an exemplary embodiment of this application, the trench structure 300 further includes a trench layer 350. The trench layer 350 may be located inside the tunnel layer 340.

[0103] Since the contents and structures involved in the preparation methods described in any of the embodiments above can be fully or partially applied to the three-dimensional memory described herein, related or similar contents will not be repeated here.

[0104] Although exemplary fabrication methods and structures of three-dimensional memories have been described herein, it is understood that one or more features may be omitted, substituted, or added to the structure of the three-dimensional memory. Furthermore, the layers and materials described are merely exemplary.

[0105] Figure 19 This is a schematic diagram of the structure of a storage system 2000 according to one embodiment of this application.

[0106] like Figure 19 As shown, at least one embodiment of this application also provides a storage system 2000. The storage system 2000 may include a controller 2200 and at least one three-dimensional memory 2100. The three-dimensional memory 2100 may be the same as the three-dimensional memory described in any of the embodiments above, and will not be described again in this application.

[0107] The controller 2200 can be coupled to the 3D memory 2100 via channel CH to control the 3D memory 2100 to store data. The 3D memory 2100 can receive commands CMD and addresses ADDR from the controller 2200 via channel CH and access the region selected from the memory cell array in response to the address. In other words, the 3D memory 2100 can perform internal operations corresponding to commands on the region selected by the address.

[0108] In some implementations, the storage system 2000 may be implemented as a Universal Flash Storage (UFS) device, a Solid State Drive (SSD), a Multimedia Card in the form of MMC, eMMC, RS-MMC, and Micro MMC, a Secure Digital Card in the form of SD, Mini SD, and Micro SD, a PCMCIA card type storage device, a Peripheral Component Interconnect (PCI) type storage device, a High Speed ​​PCI (PCI-E) type storage device, a Compact Flash (CF) card, a Smart Media Card, or a Memory Stick, etc.

[0109] Figure 20 This is a schematic diagram of the structure of the electronic device 3000 provided in the embodiments of this application.

[0110] like Figure 20As shown, at least one embodiment of this application also provides an electronic device 3000. The electronic device 3000 includes a storage system 3100. The storage system 3100 may be the same as the storage system described in any of the embodiments above, and will not be repeated here. The electronic device 3000 may be a mobile phone, desktop computer, tablet computer, laptop computer, server, in-vehicle device, wearable device, power bank, or other device with storage functionality. Therefore, other modules of the electronic device 3000, such as a controller, can be determined according to the specific device type of the electronic device 3000. Other modules can be coupled to the storage system 3100 via channels and interact with the storage system 3100.

[0111] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method for fabricating a three-dimensional memory, characterized in that, include: Alternately stacked gate layers and sacrificial layers are used to form a stacked structure; A channel structure is formed that penetrates the stacked structure, the channel structure including a barrier layer, a charge trapping layer and a tunneling layer formed sequentially on the inner wall of the channel hole; The portions of the sacrificial layer and the barrier layer corresponding to the sacrificial layer are removed sequentially to form a sacrificial gap; The sacrificial gap isolates the portion of the charge trapping layer corresponding to the adjacent gate layers; A gate dielectric layer is formed within the sacrificial gap; The gate layer is made of silicon, and an auxiliary conductive layer is formed on the surface of the gate layer near the gate dielectric layer.

2. The preparation method according to claim 1, characterized in that, The sacrificial gap isolates the portion of the charge trapping layer corresponding to the adjacent gate layers, including: Etching removes the portion of the charge trapping layer exposed by the sacrificial gap.

3. The preparation method according to claim 1, characterized in that, The sacrificial gap isolates the portion of the charge trapping layer corresponding to the adjacent gate layers, including: The portion of the charge trapping layer exposed by the sacrificial gap is oxidized to form an oxide layer.

4. The preparation method according to any one of claims 1-3, characterized in that, The gate layer comprises a first conductive layer, a semiconductor layer, and a second conductive layer stacked sequentially. Alternatingly stacking a gate layer and a sacrificial layer to form a stacked structure includes: alternately stacking a first conductive layer, the semiconductor layer, the second conductive layer, and the sacrificial layer to form a stacked structure.

5. The preparation method according to claim 4, characterized in that, The method includes performing an annealing process on the gate layer to form an auxiliary conductive layer on the surface of the gate layer near the gate dielectric layer.

6. The preparation method according to claim 2, characterized in that, The method further includes filling an oxide layer in the area exposed by the removal of the charge trapping layer.

7. The preparation method according to claim 3 or 6, characterized in that, The method further includes forming a conductive layer on the surface of the gate layer exposed to the sacrificial gap.

8. The preparation method according to claim 7, characterized in that, The method includes performing an annealing process on the conductive layer and the gate layer to form an auxiliary conductive layer on the surface of the gate layer near the gate dielectric layer.

9. The preparation method according to claim 7, characterized in that, A conductive layer is formed on the surface of the gate layer exposed to the sacrificial gap, including: A conductive layer is formed on the surface of the gate layer exposed to the sacrificial gap and on the oxide layer; and Remove the conductive layer on the oxide layer.

10. The preparation method according to claim 5, characterized in that, The sacrificial layer is made of silicon nitride; The semiconductor layer is made of silicon; The materials of the first conductive layer and the second conductive layer include metal; and The auxiliary conductive layer is made of metal silicide.

11. The preparation method according to claim 8, characterized in that, The sacrificial layer is made of silicon nitride; The conductive layer is made of metal; and The auxiliary conductive layer is made of metal silicide.

12. A three-dimensional memory, characterized in that, include: A stacked structure, comprising alternating gate layers and gate dielectric layers; as well as A channel structure, penetrating the stacked structure and comprising: Tunneling layer; A charge trapping layer, located outside the tunneling layer and spaced into multiple charge trapping sections by the gate dielectric layer; and A barrier layer, located outside the charge trapping layer and spaced into multiple barrier portions by the gate dielectric layer, is also present. The gate layer comprises an alternately stacked first auxiliary conductive layer, a semiconductor layer, and a second auxiliary conductive layer. The first and second auxiliary conductive layers are made of metal silicide, and the semiconductor layer is made of silicon.

13. The three-dimensional memory according to claim 12, characterized in that, The trench structure further includes a trench layer located inside the tunneling layer.

14. A storage system, characterized in that, The storage system includes a controller and the three-dimensional memory as described in claim 12 or 13, wherein the controller is coupled to the three-dimensional memory and is used to control the storage of data in the three-dimensional memory.

15. An electronic device, characterized in that, include: The storage system of claim 14.

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