Storage system, and three-dimensional memory and method of making the same

Abstract

The present disclosure provides a three-dimensional memory and a method of fabricating the same. The present disclosure also provides a storage system. The method of fabricating the three-dimensional memory includes forming a stack structure including alternatingly stacked insulating layers and gate sacrificial layers and having a step region on a substrate, an upper surface of at least one insulating layer being exposed at the step region; performing a modification treatment on the exposed portion of the insulating layers to form a modified insulating portion; forming a buffer sacrificial layer covering a top surface of the modified insulating portion; replacing the gate sacrificial layers to form gate layers, and replacing the buffer sacrificial layer and at least a portion of the modified insulating portion to form a buffer portion electrically connected with the gate layers; and forming a gate contact extending through the stack structure and at least to the buffer portion.

Description

Technical Field

[0001] This application relates to the field of semiconductor devices, and more specifically, to memory systems, three-dimensional memories, and methods for fabricating the same. Background Technology

[0002] Three-dimensional storage devices, with their high storage density and capacity, have seen continuous development in recent years. For example, 3D NAND flash memory is being used more and more widely.

[0003] 3D NAND structures consist of stacked structures made up of multiple layers of insulating layers and gate layers stacked vertically and alternately. The core region of the stacked structure is used to form string memory cells, and its stepped region is located in the outer region of the core region. The gate layer serves as the gate line of each memory cell, led out through gate contacts located in the stepped region. However, during the process of forming the gate contacts, the target gate layer may be broken down or even electrically connected to the adjacent gate layer below it, leading to leakage and other problems. Furthermore, as the number of stacked layers increases, the difficulty of deep hole etching further increases, making this problem even more prominent. Summary of the Invention

[0004] One or more embodiments of this application provide a storage system that can at least partially solve the above-mentioned problems existing in the prior art, as well as a three-dimensional memory and a method for fabricating the same.

[0005] One aspect of this application provides a method for fabricating a three-dimensional memory, the method comprising: forming a stacked structure on a substrate comprising alternating insulating layers and a gate sacrificial layer and having a stepped region, wherein the upper surface of at least one of the insulating layers is exposed in the stepped region; modifying the exposed portion of the insulating layer to form a modified insulating portion; forming a buffer sacrificial layer covering the top surface of the modified insulating portion; replacing the gate sacrificial layer to form a gate layer, and replacing at least a portion of the buffer sacrificial layer and the modified insulating portion to form a buffer portion electrically connected to the gate layer; and forming a gate contact that penetrates the stacked structure and extends at least to the buffer portion.

[0006] In one embodiment of this application, modifying the exposed portion of the insulating layer to form a modified insulating portion includes: ion implanting the portion of the insulating layer exposed in the step region to form the modified insulating portion.

[0007] In one embodiment of this application, forming the gate layer and forming the buffer portion includes: replacing the gate sacrificial layer with a conductive material to form the gate layer, and replacing the buffer sacrificial layer and the peripheral portion of the modified insulating portion to form the buffer portion including the remaining portion of the modified insulating portion that has not been replaced and electrically connected to the gate layer.

[0008] In one embodiment of this application, forming the gate layer and forming the buffer portion, which includes the remaining portion of the modified insulating portion that has not been replaced and is electrically connected to the gate layer, includes: removing the gate sacrificial layer, the buffer sacrificial layer, and the peripheral portion of the modified insulating portion to form a sacrificial gap; and filling the conductive material in the sacrificial gap to form the gate layer and the buffer portion.

[0009] In one embodiment of this application, the method further includes: forming a dielectric layer covering the step region, wherein forming the sacrificial gap includes: forming a gate line slot penetrating the stacked structure and the dielectric layer; and removing the peripheral portion of the gate sacrificial layer, the buffer sacrificial layer, and the modified insulating portion through the gate line slot to form the sacrificial gap.

[0010] In one embodiment of this application, forming the gate layer and forming the buffer portion includes: replacing the gate sacrificial layer with a conductive material to form the gate layer, and replacing the buffer sacrificial layer and all of the modified insulating portions to form the buffer portion electrically connected to the gate layer.

[0011] In one embodiment of this application, replacing the gate sacrificial layer to form a gate layer, and replacing the buffer sacrificial layer and all of the modified insulating portions to form the buffer portion electrically connected to the gate layer includes: removing the gate sacrificial layer, the buffer sacrificial layer, and all of the modified insulating portions to form a sacrificial gap; and filling the sacrificial gap with the conductive material to form the gate layer and the buffer portion.

[0012] In one embodiment of this application, the method further includes: forming a dielectric layer covering the step region, wherein forming the sacrificial gap includes: forming a gate line slot penetrating the stacked structure and the dielectric layer; and removing the gate sacrificial layer, the buffer sacrificial layer, and all of the modified insulating portion through the gate line slot to form the sacrificial gap.

[0013] In one embodiment of this application, forming a buffer sacrificial layer covering the top surface of the modified insulation portion includes: forming a buffer sacrificial layer covering the step area, the buffer sacrificial layer including a horizontal portion covering the top surface of each step in the step area and a vertical portion covering the sidewall of each step; removing the vertical portion and retaining the horizontal portion to form a buffer sacrificial layer covering the top surface of the modified insulation portion.

[0014] In one embodiment of this application, the insulating layer is made of an oxide; the gate sacrificial layer and the buffer sacrificial layer are made of the same material, both comprising nitrides.

[0015] Another aspect of this application provides a three-dimensional memory comprising: a semiconductor layer; a stacked structure having a stepped region on the semiconductor layer, the stacked structure comprising alternatingly stacked plurality of insulating layers and plurality of gate layers; a buffer portion located on the top surface of the gate layer in the stepped region, the buffer portion comprising a peripheral conductor layer and a modified insulating portion, wherein the peripheral conductor layer is electrically connected to the gate layer; and a gate contact extending through the stacked structure and at least to the buffer portion.

[0016] In one embodiment of this application, the step region includes multiple steps, the modified insulating portion is located on the top surface of the gate layer electrically connected to the buffer portion, and the peripheral conductor layer includes: two vertical portions arranged adjacent to the modified insulating portion on the top surface of the gate layer, and a horizontal portion located on the top surface of the modified insulating portion and connected to the two vertical portions, wherein the two vertical portions and the modified insulating portion are arranged adjacent to each other in a direction parallel to the end face of the adjacent upper step, and the modified insulating portion is located between the two vertical portions.

[0017] In one embodiment of this application, the thickness of each buffer portion along the direction perpendicular to the gate layer is greater than the thickness of the upper insulating layer adjacent to the gate layer electrically connected to the buffer portion.

[0018] In one embodiment of this application, the insulating layer is made of silicon oxide, the modified insulating portion is made of ion-implanted silicon oxide, and the modified insulating portion and the insulating layer have different etching rates under the same etching conditions.

[0019] Another aspect of this application provides a three-dimensional memory comprising: a semiconductor layer; a stacked structure having a stepped region on the semiconductor layer, the stacked structure including a plurality of alternately stacked insulating layers and a plurality of gate layers; a buffer portion located on the top surface of the gate layer in the stepped region and electrically connected to the gate layer, the thickness of the buffer portion along a direction perpendicular to the gate layer being greater than the thickness of the upper insulating layer adjacent to the gate layer electrically connected to the buffer portion; and a gate contact penetrating the stacked structure and extending at least to the buffer portion.

[0020] Another aspect of this application provides a storage system comprising: at least one three-dimensional memory as described above; and a controller electrically connected to at least one of the three-dimensional memories for controlling at least one of the three-dimensional memories.

[0021] According to one or more embodiments of this application, a method of forming a modified insulating portion on the insulating layer of the step surface and further forming a buffer sacrificial layer on the modified insulating portion allows for a larger thickness of the buffer portion electrically connected to the gate layer formed by replacing the buffer sacrificial layer and at least part of the modified insulating portion. Specifically, the thickness of the buffer portion obtained by this method includes not only the thickness of the modified insulating portion (i.e., the thickness of the corresponding insulating layer) but also the thickness of the originally deposited buffer sacrificial layer. Therefore, during the gate contact formation process, it is less likely to cause breakdown of the underlying gate layer, which helps to avoid gate layer short circuits and leakage. On the other hand, according to the method provided in this application, due to the presence of the modified insulating portion, under the same conditions, the thickness of the buffer sacrificial layer (TS SIN) that needs to be deposited can be reduced to obtain the required thickness of the buffer portion. This makes it easier to remove the buffer sacrificial layer from the step sidewall and helps to avoid problems such as SIN residue. Furthermore, due to the presence of the modified insulating portion, the etching operation can be stopped at the modified insulating portion during the process of removing the buffer sacrificial layer from the step sidewall, thereby protecting the gate sacrificial layer below from being etched and causing material loss, and thus better ensuring that the gate layer formed subsequently has good quality. Attached Figure Description

[0022] Other features, objects, and advantages of this application will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings. Embodiments of this application are illustrated in the accompanying drawings by way of example rather than limitation, in which the same reference numerals indicate similar elements. Wherein:

[0023] Figure 1 This is a flowchart of a method for fabricating a three-dimensional memory according to an exemplary embodiment of this application;

[0024] Figure 2 This is a schematic diagram illustrating the gate breakdown that occurs during the process of forming gate contacts in related technologies;

[0025] Figure 3 This is a schematic diagram of the thickening of the tungsten layer at the gate contact landing area in related technologies;

[0026] Figure 4 This is a schematic diagram illustrating the presence of residual SIN on the side wall of a stepped structure in related technologies;

[0027] Figure 5 This is a schematic diagram showing a weak point in the gate layer due to insufficient thickness in related technologies;

[0028] Figures 6A to 6K This is a schematic diagram of the manufacturing process of a three-dimensional memory according to an exemplary embodiment of this application;

[0029] Figures 7A to 7E This is a schematic diagram of the manufacturing process of three-dimensional memory in related technologies;

[0030] Figures 8A to 8G This is a schematic diagram of the manufacturing process of a three-dimensional memory according to another exemplary embodiment of this application;

[0031] Figure 9 This is a schematic diagram of a storage system according to an exemplary embodiment of this application; and

[0032] Figure 10 This is a schematic diagram of a storage system according to another exemplary embodiment of this application. Detailed Implementation

[0033] The present application will now be described in detail with reference to the accompanying drawings. The exemplary embodiments mentioned herein are for illustrative purposes only and are not intended to limit the scope of the application. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0034] In the accompanying drawings, the thickness, dimensions, and shapes of the parts have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not strictly to scale. As used herein, the terms “approximately,” “about,” and similar terms are used to indicate approximation, not degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art. It should be understood that in this specification, the terms “first,” “second,” etc., are used only to distinguish one feature from another and do not indicate any limitation on the features, and in particular, no order of precedence.

[0035] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to an example or illustration.

[0036] Furthermore, when terms such as “connection,” “covering,” and / or “formed on” are used in this application, they may indicate that the corresponding components are in direct or indirect contact, unless there are other explicit limitations or can be inferred from the context.

[0037] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. Furthermore, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0038] As used herein, the term "substrate" refers to the material on which subsequent layers of material are added. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Additionally, the substrate may include a wide variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Optionally, the substrate may be made of a non-conductive material such as glass, plastic, or sapphire wafer. The substrate may be a single layer or comprise multiple layers.

[0039] As used herein, the term "layer" refers to a portion of material having a certain thickness. A layer can be a region of a uniform or non-uniform continuous structure, wherein the non-uniform continuous structure has a thickness that is smaller or larger than that of the continuous structure.

[0040] As used herein, the term "three-dimensional memory" refers to a semiconductor device having vertically oriented strings of memory cell transistors on a laterally oriented substrate, such that the strings of memory cell transistors extend in a direction perpendicular or substantially perpendicular to the substrate. As used herein, the term "vertical" means perpendicular or substantially perpendicular to the lateral surface of the substrate.

[0041] Many specific details of this application, such as the structure, materials, dimensions, processing techniques, and methods of the devices, are described below to provide a clearer understanding of the application. However, as those skilled in the art will understand, this application may be implemented without adhering to these specific details.

[0042] It should be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. Furthermore, unless explicitly limited or contradicted by the context, the specific steps included in the methods described in this application are not limited to the order in which they are described, but can be executed in any order or in parallel.

[0043] The three-dimensional memory structure comprises a stacked structure consisting of vertically alternating layers of insulating layers and gate layers. The core region of the stacked structure forms the string memory cell, with a stepped region located on the periphery of the core region. The gate layer, serving as the gate line for each memory cell, can be led out through gate contacts located in the stepped region. During the gate contact formation process, the target gate layer may be broken down or even electrically connected to the adjacent gate layer below it, leading to problems such as leakage. Figure 2 The circled area is shown. In related fabrication processes, a common method is to increase the thickness of the tungsten metal at the gate contact landing area in the stepped region (e.g., ...). Figure 3 (As shown in the circled area), attempts were made to reduce or eliminate the aforementioned problems. However, with the increasing integration of 3D memory and the continuous increase in the number of stacked layers, the depth that the gate contacts need to penetrate is increasing, requiring a further increase in the thickness of the tungsten metal in the gate contact landing area of ​​the step region. However, to achieve a further increase in the thickness of the tungsten metal in this area, a very thick TS SIN (silicon nitride) needs to be deposited, which poses a great challenge to the TS SIN removal process on the sidewalls of the step, easily leading to problems such as TS SIN residue, etc. Figure 4 The circled area is shown. Furthermore, the entire process in related technologies causes damage to the gate sacrificial layer (usually SIN) in the stacked structure. This results in a weaker area after the gate sacrificial layer is replaced with the gate layer, becoming a potential vulnerability and detrimental to the quality assurance of 3D memory. Figure 5 The circled part is shown.

[0044] In view of the above situation, one or more exemplary embodiments of this application provide a storage system that can at least partially solve the above problems, as well as a three-dimensional memory and a method for fabricating the same, which will be described in further detail below.

[0045] Figure 1 The diagram shows a flowchart of a method for fabricating a three-dimensional memory according to an exemplary embodiment of this application. The method 1000 for fabricating a three-dimensional memory according to an exemplary embodiment of this application may include the following steps:

[0046] S1, a stacked structure 200 is formed on a substrate 100, comprising alternating insulating layers 201 and gate sacrificial layers 202 and having a step region 210, wherein the upper surface of at least one insulating layer 201 is exposed in the step region 210.

[0047] S2, the exposed portion of the insulating layer 201 is modified to form a modified insulating portion 211;

[0048] S3, forming a buffer sacrificial layer 203-2 covering the top surface of the modified insulation part 211;

[0049] S4, replace the gate sacrificial layer 202 to form the gate layer 204, and replace at least a portion of the horizontal portion 203-2 and the modified insulating portion 211 of the buffer sacrificial layer 203 to form a buffer portion 220 electrically connected to the gate layer 204; and

[0050] S5, forming a gate contact 230 that penetrates the stacked structure 200' and extends at least to the buffer portion 220.

[0051] The aforementioned method 1000 retains the insulating layer above the gate layer in the step region and modifies this portion of the insulating layer into a modified insulating portion. A buffer sacrificial layer (TS SIN layer) is formed covering the modified insulating portion. This allows the formed buffer portion (thickened portion) of the gate layer to have a greater thickness, which is beneficial for better protecting the gate layer electrically connected to the buffer portion from breakdown during the gate contact formation process. Since the thickness of the formed buffer portion includes the thickness of the modified insulating portion, the required thickness of the deposited buffer sacrificial layer (TS SIN layer) is reduced. This facilitates better removal of the step sidewall buffer sacrificial layer (i.e., removal of the vertical portion of the buffer sacrificial layer) and reduces the likelihood of TS SIN residue. Furthermore, the presence of the modified insulating portion between the gate sacrificial layer and the buffer sacrificial layer helps control the etching operation to stop at the modified insulating portion during the removal of the buffer sacrificial layer on the step sidewall, reducing the probability of damage to the gate sacrificial layer. This, in turn, helps ensure the quality of the subsequently formed gate layer and, consequently, the electrical performance of the three-dimensional memory.

[0052] This application will now be described in detail with reference to the accompanying drawings and specific embodiments.

[0053] Figures 6A to 6J This is a schematic diagram of the manufacturing process of a three-dimensional memory according to an exemplary embodiment of this application. The following will be combined with... Figures 6A to 6J The steps described in method 1000 are explained in detail.

[0054] According to step S1 of method 1000, a substrate 100 is first formed, which can be used to support the device structure thereon. The substrate 100 may, for example, include at least one of single-crystal silicon (Si), single-crystal germanium (Ge), III-V compound semiconductor materials, II-VI compound semiconductor materials, or other semiconductor materials known in the art. In one embodiment, the substrate 100 is, for example, a doped single-crystal silicon substrate. The substrate 100 may be a P-type substrate or an N-type substrate, and may further include N-wells and / or P-wells. In some other embodiments, the substrate 100 may also be a composite substrate. It is understood that this application is not limited thereto, and the substrate 100 may be formed and selected according to actual needs.

[0055] Next, a stacked structure 200 comprising alternatingly stacked plurality of insulating layers 201 and plurality of gate sacrificial layers 202 is formed on the semiconductor substrate 100. In one embodiment, the plurality of insulating layers 201 and plurality of gate sacrificial layers 202 described above may be alternately formed on the substrate 100 using a thin film deposition process including chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), or any combination thereof, wherein the top layer of the stacked structure 200 is an insulating layer 201. The material of the insulating layer 201 may include, for example, silicon oxide. The material of the gate sacrificial layer 202 may include, for example, silicon nitride. It is understood that... Figure 6A The structure shown may only be a partial structure of the three-dimensional memory, and the number and thickness of the insulating layer 201 and the gate sacrificial layer 202 can be selected and set according to the actual situation. This application does not limit this.

[0056] like Figure 6A As shown, the stacked structure 200 also includes a step region 210 having multiple stepped steps. In one embodiment, the step region 210 may be formed at the edge of the stacked structure 200 and may be formed by performing multiple trim-etch cycles on alternatingly stacked insulating layers 201 and gate sacrificial layers 202, such that at least one insulating layer 201 has an exposed region B in the step region 210. The upper surface of the insulating layer 201 in the exposed region B of the step region 210 may serve as a region for subsequent formation of the buffer portion 220. It is understood that... Figure 6A The structure shown may only be a partial structure of the three-dimensional memory. Along the length of the substrate 100, at the other end opposite to the stepped area 210 shown in the figure, another stepped structure may be provided.

[0057] According to step S2 in method 1000, the exposed portion of the insulating layer 201 is subjected to a modification treatment to form a modified insulating portion 211. Figure 6B In one embodiment, the portion of the insulating layer 201 exposed to the step region 210 may be modified using, for example, ion implantation (IMP) to transform that portion of the insulating layer 201 into a modified insulating portion 211, such as... Figure 6B As shown. In one embodiment, the material of the insulating layer 201 is, for example, silicon oxide, and after modification treatment, the material of the modified insulating portion 211 is modified silicon oxide.

[0058] In one embodiment, the material properties of the modified insulating portion 211 can be altered by controlling factors such as the type and concentration of ion implantation. When the gate sacrificial layer 202 is subsequently removed using, for example, a wet etching method, the modified insulating portion 211 can also be partially etched under the action of the etchant. The etching rate of the modified insulating portion 211 is lower than the etching rate of the gate sacrificial layer 202; that is, after the etching operation is completed, a portion of the modified insulating portion 211 remains. In another embodiment, the material properties of the modified insulating portion 211 can be altered by controlling factors such as the type and concentration of ion implantation. When the gate sacrificial layer 202 is subsequently removed using, for example, a wet etching method, the modified insulating portion 211 can also be etched simultaneously under the action of the etchant. The etching rate of the modified insulating portion 211 is close to the etching rate of the gate sacrificial layer 202; that is, after the etching operation is completed, the modified insulating portion 211 is also completely removed. It is understood that in other embodiments, other different methods may be used to modify the portion of the insulation layer 201 exposed in the step area 210, and the degree of modification of this portion of the insulation layer 201 may also be determined according to the specific circumstances. This application is not intended to limit it.

[0059] According to step S3 in method 1000, a buffer sacrificial layer 203-2 is formed covering the top surface of the modified insulating portion 211. According to an exemplary embodiment of this application, step S3 may further include the following steps:

[0060] S3-1, forming a buffer sacrificial layer 203 covering the step area 210, such as Figure 6C As shown, the buffer sacrificial layer 203 includes a vertical portion 203-1 covering the sidewalls of each step and a horizontal portion 203-2 covering the top surface of each step. The process methods for forming the buffer sacrificial layer 203 include, but are not limited to, atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), or any combination thereof. For example, the buffer sacrificial layer 203 can be formed by a chemical vapor deposition process. As an example, the material used to form the buffer sacrificial layer 203 may be TS SIN. It should be noted that this application is not intended to limit the material or the formation process of the buffer sacrificial layer 203.

[0061] as well as

[0062] S3-2, Remove the vertical portion 203-1 of the sidewall covering each step of the buffer sacrificial layer 203. Figure 6C The buffer sacrificial layer 203 retains the horizontal portion 203-2 covering the top surface of each step, thus realizing the formation of the buffer sacrificial layer 203-2 covering the top surface of the modified insulating part 211 as described in step S3.

[0063] In one embodiment, after removing the vertical portion 203-1 of the buffer sacrificial layer 203 covering the sidewalls of each step, etching can stop at the modified insulating portion 211 located below the vertical portion 203-1. The portion of the modified insulating portion 211 located below the vertical portion 203-1 can be partially removed; that is, a portion of the modified insulating portion 211 located below the vertical portion 203-1 is retained. The retained portion of the modified insulating portion 211 is as follows: Figure 6D As shown in Figure 211-1. In this step, the vertical portion 203-1 of the buffer sacrificial layer 203 covering the sidewalls of each step is removed, so that after subsequent processes such as replacing the gate sacrificial layer 202 to form the gate layer 204, replacing the buffer sacrificial layer 203, and at least partially replacing the modified insulating portion 211 to form the buffer portion 220, adjacent buffer portions 220 or adjacent gate layers 204 will not short-circuit or leak current. In one embodiment, a corresponding mask (not shown) may be formed, and the vertical portion 203-1 of the buffer sacrificial layer 203 located on the sidewalls of the step may be removed via the mask using, for example, dry etching. In the etching process of this example, because dry etching has different etching principles for the material included in the buffer sacrificial layer 203 (e.g., TS SIN) and the material included in the modified insulating portion 211 (e.g., modified silicon oxide), the vertical portion 203-1 of the buffer sacrificial layer 203 located on the sidewalls of the step may be short-circuited or leak current. Figure 6C After the modified insulating portion 211 is removed, the portion of the modified insulating portion 211 located below the vertical portion 203-1 of the buffer sacrificial layer 203 can also be partially etched. In this step, the etching operation stops at the modified insulating portion 211 located below the vertical portion 203-1 of the buffer sacrificial layer 203, ultimately removing at least a portion of the modified insulating portion 211-1 located below the vertical portion 203-1. Figure 6D The gate sacrificial layer 202 located below the modified insulating portion 211-1 can be retained, which helps protect the gate sacrificial layer 202 from being etched and lost, thereby helping to ensure the quality of the gate layer 204 formed in subsequent processes when replacing the gate sacrificial layer 202. It is understood that the implementation method of this step is merely an example and not a limitation. In another exemplary embodiment, in step S3-2, the vertical portion 203-1 of the buffer sacrificial layer 203 covering the sidewalls of each step is removed, and the portion of the modified insulating portion 211 located below this vertical portion 203-1 can also be completely removed, that is, Figure 6DThe portion 211-1 shown may also be removed. In different embodiments, the resulting structures are not exactly the same due to different specific operations. However, it is understood that the presence of the modified insulating portion 211 located between the buffer sacrificial layer 203 and the gate sacrificial layer 202 can provide a certain degree of protection to the gate sacrificial layer 202 located below the vertical portion 203-1 during the operation of removing the vertical portion 203-1 covering the sidewall of each step, making it less susceptible to etching and loss.

[0064] According to step S4 in method 1000, the gate sacrificial layer 202 is replaced with, for example, a conductive material to form the gate layer 204, and at least a portion of the horizontal portion 203-2 and the modified insulating portion 211 of the buffer sacrificial layer 203 are replaced to form a buffer portion 220 electrically connected to the gate layer 204.

[0065] In one embodiment, the horizontal portion 203-2 of the gate sacrificial layer 202 and the buffer sacrificial layer 203 located on the top surface of each step of the step region 210, as well as the peripheral portion of the modified insulating portion 211, can be removed first to form a sacrificial gap. See [link to relevant documentation]. Figure 6E and Figure 6F Then, conductive material is filled into the formed sacrificial gap to form gate layer 204 and buffer portion 220 located in the step region of each gate layer 204, see [link to relevant documentation]. Figure 6G and Figure 6H .

[0066] According to one embodiment of this application, before forming the gate gap 240 through the stacked structure 200, step S4 may further include: forming a dielectric layer 300 covering the stepped area 210 and providing a flat upper surface for the stacked structure 200. As an example, the dielectric layer may be formed by depositing an oxide, which may be selected from, for example, a silicon oxide-based material. As an example, the dielectric layer may be planarized using processes such as chemical mechanical polishing, such that the dielectric layer provides a substantially flat upper surface for the stepped area 210 of the stacked structure 200.

[0067] Next, a gate line slot 240 can be formed through the stacked structure 200, and then the gate sacrificial layer 202, the horizontal portion 203-2 of the buffer sacrificial layer 203 located on the top surface of the step, and the peripheral portion of the modified insulating portion 211 are removed through the gate line slot 240. As an example, in this step, the gate line slot 240 can be used as an etchant channel, and isotropic etching can be used to remove the gate sacrificial layer 202, the buffer sacrificial layer 203 located on the top surface of each step of the stepped region 210, and at least a portion of the modified insulating portion 211 in the stacked structure 200. Isotropic etching can be performed using selective wet etching or vapor phase etching. In wet etching, an etching solution is used as the etchant, and the semiconductor structure is immersed in the etching solution. In vapor phase etching, an etching gas is used as the etchant, and the semiconductor structure is exposed to the etching gas. The insulating layer 201 and the gate sacrificial layer 202 in the stacked structure 200 are silicon oxide (SiO2), respectively. X ) and silicon nitride (SiN) X In the case of wet etching, phosphoric acid solution can be used as the etchant; in vapor phase etching, one or more of C4F8, C4F6, H2F2, and O2 can be used as the etchant. During the etching step, the etchant fills the gate line gap 240 and gradually etches the gate sacrificial layer 202, the buffer sacrificial layer 203, and the modified insulating portion 211 into the stacked structure. The modified insulating portion 211 is etched inwards from the outer portion exposed to the gate line gap 240 (see [reference]). Figure 6K (In the direction indicated by the middle arrow Y), because the etching rate of the etchant for the modified silicon oxide included in the modified insulating portion 211 is lower than its etching rate for the silicon nitride included in the gate sacrificial layer 202 and the buffer sacrificial layer 203, the portion of the modified insulating portion 211 located at the center is retained at the end of the etching. Due to the selectivity of the etchant, this etching operation retains the insulating layer 201.

[0068] It should be noted that the etching of the modified insulating portion 211 in this etching step depends on the degree of modification treatment performed on the exposed insulating layer 201 in the aforementioned step S2. That is, the etching results for the modified insulating portion 211 will differ depending on the material properties of the modified oxides included in the modified insulating portion 211 formed after the modification treatment. For example, in one embodiment, the modified insulating portion 211 is only partially removed. In this case, the sacrificial gap formed within the stacked structure 200 can be as follows: Figure 6E and 6F As shown. Figure 6E This is a cross-sectional view of the stacked structure 200 with the portion of the modified insulation 211 not removed. Figure 6EIt can be seen that there is still a modified insulating portion 211 between the sacrificial gap 202' formed after the gate sacrificial layer 202 is removed and the sacrificial gap 203' formed after the buffer sacrificial layer 203 is removed. Figure 6F This is a cross-sectional view of the stacked structure 200 with the outer portion removed via the modified insulation portion 211. Figure 6F It can be seen that the sacrificial gap 202' formed after the gate sacrificial layer 202 is removed and the sacrificial gap 203' formed after the buffer sacrificial layer 203 is removed are the sacrificial gap 211' formed after the outer part of the modified insulating portion 211 is removed. The sacrificial gap 203' formed after the buffer sacrificial layer 203 is removed and the sacrificial gap 211' formed after the partial modified insulating portion 211 is removed can together constitute the gap space for the subsequent formation of the buffer portion 220.

[0069] Next, conductive material can be filled into the formed sacrificial gap using one or more deposition processes to form gate layer 204 and buffer portion 220 located in the step region of each gate layer 204, see [link to relevant documentation]. Figure 6G and Figure 6H The conductive material deposited on the gate layer 204 and the buffer portion 220 includes, but is not limited to, tungsten (W) metal. The buffer portion 220 formed on the top surface of each step has a relatively thick thickness, greater than the thickness of the upper insulating layer 201 adjacent to the gate layer electrically connected thereto. Exemplarily, in one embodiment, the thickness of the buffer portion 220 is approximately equal to, for example, the sum of the thicknesses of a group of adjacent insulating layers 201 and the gate layer 204 above the gate layer. The relatively thick buffer portion 220 helps protect the gate layer from breakdown during the process of forming the gate contacts.

[0070] In one embodiment, only the peripheral portion of the modified insulating portion 211 is removed. In this case, a cross-sectional view of the stacked structure 200' formed by filling the sacrificial gap with conductive material to form the gate layer 204 and the buffer portion 220 can be found in [reference needed]. Figure 6G and Figure 6H , Figure 6G This is a cross-sectional view of the stacked structure 200' with the portion of the modified insulation 211 not removed. Figure 6G It can be seen that there is still a modified insulating portion 211 that has not been removed between the gate layer 204 formed and the conductor layer 205 formed in the sacrificial gap 203' formed after the buffer sacrificial layer 203 is removed. Figure 6H This is a cross-sectional view of the stacked structure 200' with the portion having been removed via the modified insulation section 211. Figure 6HAs can be seen, a gate layer 204 is formed within the sacrificial gap 202' formed after the gate sacrificial layer 202 is removed; a conductor layer 205 is formed within the sacrificial gap 203' formed after the buffer sacrificial layer 203 is removed; and a conductor layer 212 is formed within the sacrificial gap 211' formed after the partially modified insulating portion 211 is removed. The conductor layer 205 and conductor layer 212 together constitute the conductive portion structure of the buffer portion 220. A three-dimensional schematic diagram of the buffer portion 220 can be found in [reference needed]. Figure 6J A top view of the buffer section 220 (which shows the cross-sectional depth view of the modified insulation section 211 structure) and a ZZ-direction side view based on the top view can be seen. Figure 6K ,like Figure 6J and 6K As shown, the dark-colored structure surrounding the buffer portion 220 includes an outer conductor layer 221, and the light-colored structure surrounded by the conductor layer is the portion of the modified insulating portion 211 that has not been removed. The outer conductor layer 221 is composed of a conductor layer 205 formed after replacing the buffer sacrificial layer 203 and a conductor layer 212 formed after replacing the outer portion of the modified insulating portion 211. Figure 6J The dark portion of the structure surrounding the buffer portion 220 also includes a portion of the gate layer 204, which is located on the upper and lower sides opposite to the unremoved portion of the modified insulating portion 211, along with the conductor layer 205. Figure 6K The shape and position of the gate contact 230 shown are merely examples, intended only to facilitate understanding of the relative positional relationships between structures, and are not intended to be limiting. (Cross-section) Figure 6G The buffer section 220 shown can be understood as Figure 6J Cross-sectional view at the MM line, cross-section Figure 6H The buffer section 220 shown can be understood as Figure 6J Cross-sectional view at the NN line.

[0071] According to step S5 in method 1000, a gate contact 230 is formed that penetrates the stacked structure 200' and extends at least to the buffer portion 220, as follows: Figure 6I As shown. In one embodiment, a method for forming a gate contact 230 that penetrates the stacked structure 200' and extends at least to the buffer portion 220 may include: forming a contact hole that penetrates the dielectric layer 300 and extends at least to the buffer portion 220 using, for example, a dry etching process; and then filling the formed contact hole with a conductive material to form the gate contact 230. As an example, a conductive material such as titanium nitride or tungsten alloy may be filled into the contact hole to form the gate contact 230.

[0072] It is understood that the remaining modified insulating portion 211 included in the buffer portion 220 is surrounded in the middle by the electrically connected peripheral conductor layer 221 and gate layer. The remaining modified insulating portion 211 included in the buffer portion 220 is located on the top surface of the gate layer 204, and its top and sides are covered and surrounded by the peripheral conductor layer 221. The vertical portions of the peripheral conductor layer 221 covering the two sides of the modified insulating portion 211 are connected to the top surface of the gate layer 204. See [reference needed]. Figure 6J or Figure 6K Gate contacts 230 are formed on the top of the peripheral conductor layer 221, i.e., on one side of the conductor layer 205. Therefore, as long as the formed gate contacts 230 extend to the buffer portion 220 and are electrically connected to the peripheral conductor layer 221 of the buffer portion 220, they can be further electrically connected to the corresponding gate layer 204 via the buffer portion 220. For example, in one embodiment, a portion of the gate contacts 230 may extend to the top portion (i.e., above the modified insulating portion 211) of the peripheral conductor layer of the buffer portion 220; a portion of the gate contacts 230 may extend to the portion of the modified insulating portion 211 retained in the middle of the buffer portion 220; a portion of the gate contacts 230 may extend to the portion of the peripheral conductor layer of the buffer portion 220 below the modified insulating portion 211; and a portion of the gate contacts 230 may also extend to the gate layer 204 connected to the bottom of the buffer portion 220, such as... Figure 6I As shown in the image.

[0073] As mentioned above, in order to form a thicker tungsten metal layer, such as a metal tungsten layer, a very thick TS SIN layer needs to be deposited in the implementation process. This not only makes it difficult to remove the TS SIN located on the step sidewall, easily causing SIN residue, but also damages the gate sacrificial layer adjacent to the TS SIN layer during the process of removing the step sidewall SIN. That is, the etching operation of the step sidewall TS SIN is difficult to stop well at the TS SIN layer, and will continue to etch downwards to remove a part of the gate sacrificial layer adjacent to the step sidewall TS SIN, causing the gate sacrificial layer to be lost at that point. This, in turn, affects the gate layer formed in subsequent processes, making that area of ​​the gate layer a weak point that is prone to damage.

[0074] Figures 7A to 7E This is a schematic diagram of the manufacturing process of three-dimensional memory in related technologies. Figure 7A The three-dimensional memory shown also includes a substrate 100 and a stacked structure 200 formed on the substrate 100. The stacked structure 200 may also include a plurality of alternately stacked insulating layers 201 and a plurality of gate sacrificial layers 202 and has a stepped region 210. However, in related technologies, a portion of the insulating layer 201 on the stepped surface is removed, exposing the gate sacrificial layer 202 to the stepped region 210, such as... Figure 7BAs shown. A buffer sacrificial layer 203 (e.g., a TS SIN layer) is deposited on the surface of the exposed gate sacrificial layer 202 on the stepped region 210, i.e., the TS SIN layer is directly adjacent to the gate sacrificial layer 202, as shown. Figure 7C As shown. In contrast, according to the exemplary embodiment of this application, since the buffer sacrificial layer 203 is deposited on the top surface of the deformable insulating portion 211, that is, a deformable insulating portion 211 is spaced between the buffer sacrificial layer 203 and the gate sacrificial layer 202 below it, it is obvious that, with the same thickness of buffer sacrificial layer 203 deposited, the thickness of the buffer portion 220 in the step region of the gate layer can be obtained by the embodiment of this application. This can achieve better protection of the gate layer from breakdown, while avoiding problems such as difficulty in removing sidewall TS SIN and SIN residue caused by depositing an excessively thick TS SIN layer.

[0075] In addition, see Figure 7D In the fabrication process of related technologies, because the buffer sacrificial layer 203 (e.g., a TS SIN layer) is deposited on the surface of the exposed gate sacrificial layer 202 (material, for example, SIN) on the stepped region 210, that is, the TS SIN layer and the gate sacrificial layer 202 are directly adjacent, it is difficult to control the etching operation to stop at the gate sacrificial layer 202 during the process step of removing the TS SIN from the step sidewall. The etching operation continues to etch downwards, removing part of the adjacent gate sacrificial layer 202 below, resulting in a lack of gate sacrificial layer 202 material in this region. Figure 7D As indicated by A in the diagram. After the gate sacrificial layer 202 is subsequently replaced to form the gate layer 204, there will also be a lack of gate layer 204 material in this region, such as... Figure 7E As indicated by A', it affects the formation quality of the gate layer 204. In contrast, in the exemplary embodiment of this application, the buffer sacrificial layer 203 is not directly adjacent to the gate sacrificial layer 202 below it, but is separated by a modified insulating portion 211. Since the material of the modified insulating portion 211 is a modified oxide, such as modified silicon oxide, the etching operation on the step sidewall TS SIN can be well stopped at the modified insulating portion 211, which can effectively protect the gate sacrificial layer 202 adjacent below the modified insulating portion 211, and is less likely to cause material loss in the gate layer 204, thereby helping to ensure the formation quality of the subsequent gate layer 204.

[0076] Figures 8A to 8G This is a schematic diagram of the manufacturing process of a three-dimensional memory according to another exemplary embodiment of this application, which will be discussed in conjunction with... Figures 8A to 8G The steps described in method 1000 are explained below. For the sake of brevity, the following are not explicitly stated: [The text then abruptly shifts to a different topic:] ...and Figures 6A to 6JDescriptions of methods or technical effects repeated in the illustrated embodiments will be omitted; only the exemplary embodiments will be described in detail. Figures 6A to 6J The differences between the implementation methods shown in the examples.

[0077] See Figure 8A According to step S1 in method 1000, a stacked structure 200 is formed on substrate 100, including an alternating insulating layer 201 and a gate sacrificial layer 202 and having a step region 210, and region B on the upper surface of the insulating layer 201 is exposed in the step region 210.

[0078] See Figure 8B According to step S2 in method 1000, the exposed portion of the insulating layer 201 is modified to form a modified insulating portion 211. In this embodiment, for example, ion implantation can be used, and by controlling the type and concentration of ion implantation, the degree of modification of the region B of the insulating layer 201 exposed to the step region 210 is made more severe, so that the formed modified insulating portion 211 has an etching rate close to that of silicon nitride under the same etching conditions.

[0079] See Figure 8C and Figure 8D According to step S3 of method 1000, a buffer sacrificial layer 203 is formed covering each step of the step area 210. The buffer sacrificial layer 203 has a vertical portion 203-1 covering the sidewalls of each step and a horizontal portion 203-2 covering the top surface of each step. The vertical portion 203-1 of the buffer sacrificial layer 203 is removed, while the horizontal portion 203-2 is retained. In one embodiment, the portion of the modified insulating portion 211 located below the vertical portion 203-1 is removed, and the remaining portion of the modified insulating portion located below the original vertical portion 203-1 is shown as 211-1 in the figure.

[0080] See Figure 8E and Figure 8F According to step S4 of method 1000, the gate sacrificial layer 202 is replaced to form the gate layer 204, and the horizontal portion 203-2 and all of the modified insulating portion 211 of the buffer sacrificial layer 203 are replaced to form a buffer portion 220 electrically connected to the gate layer 204. In this embodiment, during the removal of the gate sacrificial layer 202 and the horizontal portion 203-2 of the buffer sacrificial layer 203 via the gate line gap, all of the modified insulating portion 211 is removed. In this case, the sacrificial gap formed within the stacked structure 200 can be as follows: Figure 8EAs shown, it can be understood that no modified insulating portion 211 is retained in any cross-sectional view of the stacked structure 200. In this case, a cross-sectional view of the stacked structure 200' after filling the sacrificial gap with conductive material to form the gate layer 204 and the buffer portion 220 can be found in [reference needed]. Figure 8F .

[0081] See Figure 8G According to step S5 of method 1000, a gate contact 230 is formed that penetrates the stacked structure 200' and extends at least to the buffer portion 220. In this embodiment, the buffer portion 220 is entirely made of conductive material and does not include the modified insulating portion 211. Therefore, the formed gate contact 230 can extend at least to any part of the buffer portion 220 and can be connected to the gate layer 204 electrically connected to the buffer portion 220 through the buffer portion 220. Of course, the gate contact 230 can also penetrate the buffer portion 220 and be directly connected to the gate layer 204 located below the buffer portion 220 and electrically connected to the buffer portion 220.

[0082] See you again Figures 7A to 7E The schematic diagram of the manufacturing process of a three-dimensional memory in the related art shows that, according to the manufacturing method of this exemplary embodiment of the present application, by retaining the insulating layer 201 above the gate sacrificial layer 202 in the step region and modifying this part of the insulating layer into a modified insulating portion 211, and forming a buffer sacrificial layer 203 (TS SIN layer) covering the modified insulating portion 211, the buffer portion 220 (thickened portion) of the formed gate layer 204 has a larger thickness (basically equivalent to the sum of the thicknesses of a group of insulating layers 201 and the gate layer 204 adjacent to the top surface of the gate layer 204 electrically connected to the buffer portion 220), which is beneficial to better protect the gate layer 204 electrically connected to the buffer portion 220 from being broken down during the process of forming the gate contacts. Furthermore, since the thickness of the formed buffer portion 220 includes the thickness of the modified insulating portion 211, the thickness of the required deposited buffer sacrificial layer 203 (TS SIN layer) is reduced. This facilitates better removal of the step sidewall buffer sacrificial layer 203 and reduces the likelihood of TS SIN residue. Moreover, the presence of the modified insulating portion 211 between the gate sacrificial layer 202 and the buffer sacrificial layer 203 helps control the etching operation to stop at the modified insulating portion 211 during the step sidewall TS SIN removal process, reducing the probability of damage to the gate sacrificial layer 202. This, in turn, helps ensure the quality of the subsequently formed gate layer 204 and, consequently, the electrical performance of the three-dimensional memory.

[0083] On the other hand, this application also provides a three-dimensional memory, see [link to relevant documentation]. Figure 6I and Figure 6JThe three-dimensional memory may include: a substrate 100 and a stacked structure 200' formed on the substrate 100, comprising alternating layers of insulating layers 201 and gate layers 204, and including multiple stepped sections; a buffer portion 220 located on the top surface of the gate layers 204 at the stepped section positions and electrically connected to the gate layers 204, the buffer portion 220 including a peripheral conductor layer 221 and a modified insulating portion 211 surrounded by the peripheral conductor layer 221, wherein the peripheral conductor layer 221 is electrically connected to the corresponding gate layer 204. Furthermore, the three-dimensional memory may also include: a gate contact 230 extending through the stacked structure 200' and at least to the buffer portion 220. In one embodiment, the substrate 100 may include a semiconductor layer.

[0084] In one implementation, see Figure 6J or Figure 6K The modified insulating portion 211 included in the buffer portion 220 is located on the top surface of the gate layer 204 electrically connected to the buffer portion 220. The peripheral conductor layer 221 included in the buffer portion 220 may further include two vertical portions 212 arranged adjacent to the modified insulating portion 211 on the top surface of the gate layer 204, and a horizontal portion (conductor layer 205) located on the top surface of the modified insulating portion 211 and connected to the two vertical portions 212. In the direction parallel to the end face of the adjacent upper step (i.e.... Figure 6K In the direction parallel to the Y direction shown, two vertical portions 212 and the modified insulating portion 211 are arranged adjacent to each other, and the modified insulating portion 211 is located between the two vertical portions 212.

[0085] The remaining modified insulating portion 211 included in the buffer portion 220 is surrounded by the electrically connected peripheral conductor layer 221 and gate layer. The remaining modified insulating portion 211 included in the buffer portion 220 is located on the top surface of the gate layer 204, and its top and sides are covered and surrounded by the peripheral conductor layer 221. The vertical portions of the peripheral conductor layer 221 covering the modified insulating portion 211 on both sides are connected to the top surface of the gate layer 204. See [reference needed]. Figure 6J or Figure 6KThe gate contact 230 is formed on the top of the peripheral conductor layer 221, i.e., on one side of the conductor layer 205. Therefore, as long as the gate contact 230 extends to the buffer portion 220 and is electrically connected to the peripheral conductor layer 221 of the buffer portion 220, it can be further electrically connected to the corresponding gate layer 204 via the buffer portion 220. For example, in one embodiment, a portion of the gate contact 230 may extend to the top portion (i.e., above the modified insulating portion 211) of the peripheral conductor layer of the buffer portion 220; a portion of the gate contact 230 may extend to the portion of the modified insulating portion 211 retained in the middle of the buffer portion 220; a portion of the gate contact 230 may extend to the portion of the peripheral conductor layer of the buffer portion 220 below the modified insulating portion 211; and a portion of the gate contact 230 may also extend to the gate layer 204 connected to the bottom of the buffer portion 220, such as... Figure 6I As shown in the image.

[0086] The buffer portion 220 of the three-dimensional memory has a relatively thick thickness along a direction perpendicular (or approximately perpendicular) to the substrate 100 or the gate layer 204. This thickness includes not only the thickness of the modified insulating portion 211 but also the thickness of the conductor layer 205. The thickness of the modified insulating portion 211 is equal to or approximately equal to the thickness of the corresponding insulating layer 201. Therefore, the thickness of the buffer portion 220 is at least greater than the thickness of the insulating layer 201. In one embodiment, the thickness of the buffer portion 220 along the direction perpendicular to the gate layer 204 may, for example, be substantially equal to the sum of the thicknesses of a group of insulating layers 201 and the gate layer 204 adjacent to the top surface of the gate layer 204 electrically connected to the buffer portion 220. The relatively thick buffer portion 220, as described, helps protect the gate layer from breakdown during the gate contact formation process, thus ensuring the electrical performance of the three-dimensional memory and improving yield.

[0087] In one embodiment, the material of the insulating layer 201 in the three-dimensional memory may include silicon oxide, and the material of the modified insulating portion 211 may include ion-implanted silicon oxide. The modified insulating portion 211 and the insulating layer 201 may have different etching rates under the same etching conditions.

[0088] Furthermore, this application also provides a three-dimensional memory, see [link to relevant documentation]. Figure 8GThe three-dimensional memory may include: a substrate 100 and a stacked structure 200' formed on the substrate 100, comprising alternating layers of insulating layers 201 and gate layers 204, and further comprising multiple stepped steps; it may also include a buffer portion 220 located on the top surface of the portion of the gate layer 204 at the stepped position and electrically connected to the gate layer 204, wherein the thickness of the buffer portion 220 in the direction perpendicular to the gate layer 204 is greater than the thickness of the insulating layer 201 adjacent to the top surface of the gate layer 204 electrically connected to the buffer portion 220; and may also include a gate contact 230 penetrating the stacked structure 200' and extending at least to the buffer portion 220. The buffer portion 220, as described, has a relatively thick thickness, which is beneficial for protecting the gate layer from breakdown during the process of forming the gate contact, thus ensuring the electrical performance of the three-dimensional memory and improving yield. In one embodiment, the material of the buffer portion 220 may include tungsten. In one embodiment, the substrate 100 may include a semiconductor layer.

[0089] In summary, the fabrication method for the three-dimensional memory provided in this application, and the three-dimensional memory manufactured by this method, allows for the formation of a thicker buffer portion (thickened portion) in the step region of the gate layer. This is beneficial for better protecting the gate layer electrically connected to the buffer portion from breakdown during the gate contact formation process; it also facilitates the thorough removal of TSSIN, reducing the likelihood of TSSIN residue; and it helps ensure the quality of the gate layer in the three-dimensional memory, reducing the possibility of weak points (weak regions) in the gate layer. Therefore, the fabrication method for the three-dimensional memory provided in this application is beneficial for obtaining a three-dimensional memory with superior electrical performance and for improving the product yield of the fabricated three-dimensional memory.

[0090] In another aspect, this application also provides a storage system. Figure 9 and Figure 10 These are schematic diagrams of storage systems 2000a and 2000b according to embodiments of this application. Figure 9 and Figure 10 As shown, storage system 2000a or 2000b may include at least one three-dimensional memory 2100 and controller 2200, wherein the three-dimensional memory 2100 may be a three-dimensional memory provided according to any of the embodiments described above in this application, and may accordingly include the structure described according to any of the exemplary embodiments described above in this application, which will not be repeated here.

[0091] The controller 2200 can be electrically connected to and control the three-dimensional memory 2100 via, for example, a channel (not shown), and the three-dimensional memory 2100 can perform operations based on the control of the controller 2200. Exemplarily, the three-dimensional memory 2100 can receive commands and addresses from the controller 2200 via, for example, a channel and access a region of a channel structure in response to that address. In other words, the three-dimensional memory 2100 can perform internal operations corresponding to commands on a region selected by an address.

[0092] In some examples, the controller 2200 and one or more three-dimensional memories 2100 can be integrated into various types of storage devices; in other words, storage systems 2000a and 2000b can be implemented and packaged into different types of final electronic products. Figure 9 In one example shown, the controller 2200 and a single three-dimensional memory 2100 may be integrated into a memory card-based storage system 2200a. The memory card may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a compact flash (CF) card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a universal flash memory card (UFS), etc. The memory card-based storage system 2200a may also include a memory card connector 2300a that couples it to a host (not shown).

[0093] In such Figure 10 In another example shown, the controller 2200 and multiple three-dimensional memories 2100 may be integrated into a storage system 2000b, such as a solid-state drive (SSD). The SSD may also include an SSD connector 2300b that couples it to the host.

[0094] Although exemplary fabrication methods and structures of three-dimensional memory are described in this paper, it is understood that one or more features may be omitted, substituted, or added to the structure of the three-dimensional memory. Furthermore, the layers and materials described are merely exemplary.

[0095] The above description is merely an illustration of the embodiments of this application and the technical principles employed. Those skilled in the art should understand that the scope of protection involved in this application is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the technical concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method for fabricating a three-dimensional memory, characterized in that, include: A stacked structure comprising alternating insulating layers and gate sacrificial layers and having a stepped region is formed on a substrate, wherein the upper surface of at least one of the insulating layers is exposed in the stepped region; The exposed portion of the insulating layer is subjected to a modification treatment to form a modified insulating portion; A buffer sacrificial layer is formed covering the top surface of the modified insulation portion; The gate sacrificial layer is replaced to form a gate layer, and at least a portion of the buffer sacrificial layer and the modified insulating portion is replaced to form a buffer portion electrically connected to the gate layer; as well as A gate contact is formed that runs through the stacked structure and extends at least to the buffer portion.

2. The method according to claim 1, wherein, Modifying the exposed portion of the insulation layer to form a modified insulation portion includes: Ion implantation is performed on the portion of the insulating layer exposed in the step region to form the modified insulating portion.

3. The method according to claim 1, wherein, Forming the gate layer and forming the buffer portion includes: The gate layer is formed by replacing the gate sacrificial layer with a conductive material, and the buffer sacrificial layer and the peripheral portion of the modified insulating portion are replaced to form the buffer portion, which includes the remaining portion of the modified insulating portion that has not been replaced and is electrically connected to the gate layer.

4. The method according to claim 3, wherein, Forming the gate layer and forming the buffer portion, including the remaining portion of the modified insulating portion that has not been replaced and electrically connected to the gate layer, includes: Remove the gate sacrificial layer, the buffer sacrificial layer, and the peripheral portion of the modified insulating portion to form a sacrificial gap; and The conductive material is filled into the sacrificial gap to form the gate layer and the buffer portion.

5. The method according to claim 4, wherein, The method further includes: forming a dielectric layer covering the stepped area. The formation of the sacrificial gap includes: Forming gate line gaps that penetrate the stacked structure and the dielectric layer; and The gate sacrificial layer, the buffer sacrificial layer, and the peripheral portion of the modified insulating portion are removed through the gate line gap to form the sacrificial gap.

6. The method according to claim 1, wherein, Forming the gate layer and forming the buffer portion includes: The gate layer is formed by replacing the gate sacrificial layer with a conductive material, and the buffer sacrificial layer and all of the modified insulating portions are replaced to form the buffer portion electrically connected to the gate layer.

7. The method according to claim 6, wherein, Replacing the gate sacrificial layer to form a gate layer, and replacing the buffer sacrificial layer and all of the modified insulating portions to form the buffer portion electrically connected to the gate layer includes: Remove the gate sacrificial layer, the buffer sacrificial layer, and all of the modified insulating portions to form a sacrificial gap; and The conductive material is filled into the sacrificial gap to form the gate layer and the buffer portion.

8. The method according to claim 7, wherein, The method further includes: forming a dielectric layer covering the stepped area. The formation of the sacrificial gap includes: Forming gate line gaps that penetrate the stacked structure and the dielectric layer; and The gate sacrificial layer, the buffer sacrificial layer, and all of the modified insulating portions are removed through the gate line gap to form the sacrificial gap.

9. The method according to any one of claims 1 to 8, wherein, The buffer sacrificial layer forming the top surface covering the modified insulation portion includes: A buffer sacrificial layer is formed to cover the stepped area, the buffer sacrificial layer including a horizontal portion covering the top surface of each step in the stepped area and a vertical portion covering the sidewalls of each step; Remove the vertical portion and retain the horizontal portion to form a buffer sacrificial layer covering the top surface of the modified insulation portion.

10. The method according to any one of claims 1 to 8, wherein, The insulating layer is made of oxide; the gate sacrificial layer and the buffer sacrificial layer are made of the same material, both of which are nitrides.

11. A three-dimensional memory, characterized in that, The three-dimensional memory includes: Semiconductor layer; A stacked structure with stepped regions located on the semiconductor layer, the stacked structure comprising alternating layers of insulating layers and multiple gate layers; A buffer portion, located on the top surface of the gate layer in the stepped region, includes a peripheral conductor layer and a modified insulating portion, wherein the peripheral conductor layer is electrically connected to the gate layer; and The gate contact extends through the stacked structure and at least to the buffer portion.

12. The three-dimensional memory according to claim 11, wherein, The stepped region includes multiple steps, and the modified insulating portion is located on the top surface of the gate layer electrically connected to the buffer portion. The peripheral conductor layer includes: two vertical portions arranged adjacent to the modified insulating portion on the top surface of the gate layer, and a horizontal portion located on the top surface of the modified insulating portion and connected to the two vertical portions. The two vertical portions and the modified insulating portion are arranged adjacent to each other in a direction parallel to the end face of the adjacent upper step, and the modified insulating portion is located between the two vertical portions.

13. The three-dimensional memory according to claim 11, wherein, The thickness of each buffer portion along the direction perpendicular to the gate layer is greater than the thickness of the upper insulating layer adjacent to the gate layer electrically connected to the buffer portion.

14. The three-dimensional memory according to claim 11, wherein, The insulating layer is made of silicon oxide, and the modified insulating portion is made of ion-implanted silicon oxide. The modified insulating portion and the insulating layer have different etching rates under the same etching conditions.

15. A storage system, characterized in that, include: At least one three-dimensional memory as described in any one of claims 11-14; as well as A controller, electrically connected to at least one of the three-dimensional memories, is used to control at least one of the three-dimensional memories.

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