A monolithic three-dimensional integrated device and monolithic three-dimensional integrated circuit

Abstract

The present application relates to the technical field of three-dimensional integrated circuit, and particularly relates to a monolithic three-dimensional integrated device and a monolithic three-dimensional integrated circuit. In the monolithic three-dimensional integrated device, one or more electronic elements are arranged in a configuration layer; a metal-oxide semiconductor field effect (MOSFET) device and a configuration layer electrode group are further arranged on a side of a first buried oxygen layer away from the configuration layer; the configuration layer electrode group comprises one or more electrodes; the first buried oxygen layer is provided with a conductive path corresponding to each of the one or more electrodes; and the electrode is connected to one end of an electronic element corresponding to the electrode in the configuration layer through the conductive path corresponding to the electrode in the first buried oxygen layer. The monolithic three-dimensional integrated device provided by the present application adopts a monolithic stacking mode, inherits the SOI technology, improves the integration of the circuit, and meanwhile, the monolithic three-dimensional integrated device is provided with two buried oxygen layers to realize double-layer isolation, which can effectively inhibit the influence of the substrate layer on the MOSFET device, thereby improving the reliability of the three-dimensional integrated circuit.

Description

Technical Field

[0001] This invention relates to the field of three-dimensional integrated circuit technology, specifically to a monolithic three-dimensional integrated device and a monolithic three-dimensional integrated circuit. Background Technology

[0002] To further improve the integration density of integrated circuits, thereby reducing power consumption and enhancing processing power, stacking multiple device layers into three-dimensional integrated circuits has become a potential method for further improving the processing power and power consumption of integrated circuits. However, as the integration density of integrated circuits continues to increase, the distance between electronic components is constantly decreasing, significantly impacting the reliability of three-dimensional integrated circuits.

[0003] Therefore, improving the reliability of three-dimensional integrated circuits is a technical problem that urgently needs to be solved. Summary of the Invention

[0004] The purpose of this invention is to provide a monolithic three-dimensional integrated device and a monolithic three-dimensional integrated circuit to improve the reliability of three-dimensional integrated circuits.

[0005] To achieve the above objectives, embodiments of the present invention provide the following solutions:

[0006] In a first aspect, embodiments of the present invention provide a monolithic three-dimensional integrated device, comprising: a first buried oxide layer, a configuration layer, a second buried oxide layer, and a substrate layer stacked together;

[0007] The configuration layer contains one or more electronic components;

[0008] A metal-oxide-semiconductor field-effect MOSFET device and a configuration layer electrode group are also disposed on the side of the first buried oxide layer away from the configuration layer;

[0009] The configuration layer electrode group includes one or more electrodes; the first buried oxide layer is provided with conductive paths corresponding one-to-one with the one or more electrodes;

[0010] The electrode is connected to one end of the electronic component corresponding to the electrode in the configuration layer through a conductive path in the first buried oxide layer.

[0011] In one possible embodiment, the fabrication process temperature of the electronic components in the configuration layer is not lower than a set temperature.

[0012] In one possible embodiment, the electronic components in the configuration layer include one or more of diodes, resistors, capacitors, and bipolar transistors.

[0013] In one possible embodiment, a diode is provided in the configuration layer;

[0014] The configured layer electrode includes an anode electrode and a cathode electrode;

[0015] The anode electrode is connected to the anode of the diode through a corresponding conductive path in the first buried oxide layer;

[0016] The cathode electrode is connected to the cathode of the diode through a corresponding conductive path in the first buried oxide layer;

[0017] The second buried oxide layer is further provided with an anode heat sink structure; the anode heat sink structure is in contact with the anode of the diode.

[0018] In one possible embodiment, a shallow channel isolation structure is provided between the MOSFET device and each electrode in the configuration layer electrode group; a shallow channel isolation structure is provided between each electrode in the configuration layer electrode group.

[0019] Secondly, embodiments of the present invention provide a monolithic three-dimensional integrated circuit, the three-dimensional integrated circuit comprising one or more monolithic three-dimensional integrated devices;

[0020] Each monolithic 3D integrated device includes: a first buried oxide layer, a configuration layer, a second buried oxide layer, and a substrate layer stacked together;

[0021] The configuration layer contains one or more electronic components;

[0022] A metal-oxide-semiconductor field-effect MOSFET device and a configuration layer electrode group are also disposed on the side of the first buried oxide layer away from the configuration layer;

[0023] The configuration layer electrode group includes one or more electrodes; the first buried oxide layer is provided with conductive paths corresponding one-to-one with the one or more electrodes;

[0024] The electrode is connected to one end of the electronic component corresponding to the electrode in the configuration layer through a conductive path in the first buried oxide layer.

[0025] In one possible embodiment, the fabrication process temperature of the electronic components in the configuration layer is not lower than a set temperature.

[0026] In one possible embodiment, the electronic components in the configuration layer include one or more of diodes, resistors, capacitors, and bipolar transistors.

[0027] In one possible embodiment, the one or more monolithic three-dimensional integrated devices include at least one or more heat-dissipating three-dimensional integrated devices, wherein diodes are provided in the configuration layer of the heat-dissipating three-dimensional integrated devices;

[0028] The configured layer electrode includes an anode electrode and a cathode electrode;

[0029] The anode electrode is connected to the anode of the diode through a corresponding conductive path in the first buried oxide layer;

[0030] The cathode electrode is connected to the cathode of the diode through a corresponding conductive path in the first buried oxide layer;

[0031] The second buried oxide layer is further provided with an anode heat sink structure; the anode heat sink structure is in contact with the anode of the diode.

[0032] In one possible embodiment, in each monolithic three-dimensional integrated device, a shallow channel isolation structure is provided between the MOSFET device and each electrode in the configuration layer electrode group; and a shallow channel isolation structure is provided between each electrode in the configuration layer electrode group.

[0033] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0034] The monolithic 3D integrated device provided by this invention adopts a monolithic stacking method, inherits SOI (Silicon-On-Insulator) technology, and improves the integration of the circuit. At the same time, the monolithic 3D integrated device has two buried oxide layers to achieve double-layer isolation, which can effectively suppress the influence of the substrate layer on the MOSFET device, thereby improving the reliability of the 3D integrated circuit. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of this specification or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this specification. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0036] Figure 1 This is a schematic diagram of the structure of a monolithic three-dimensional integrated device provided in an embodiment of the present invention;

[0037] Figure 2 This is a schematic diagram of the structure of a conventional three-dimensional integrated circuit implemented using TSV technology, provided by an embodiment of the present invention.

[0038] Figure 3 This is a schematic diagram of the structure of a conventional three-dimensional integrated circuit implemented using M3D technology, provided by an embodiment of the present invention;

[0039] Figure 4 This is a schematic diagram of the structure of a monolithic three-dimensional integrated device provided in an embodiment of the present invention;

[0040] Figure 5 This is a schematic diagram of the structure of a monolithic three-dimensional integrated device provided in an embodiment of the present invention;

[0041] Figure 6 This is a schematic diagram of the structure of a monolithic three-dimensional integrated device provided in an embodiment of the present invention;

[0042] Figure 7 This is a schematic diagram of the structure of a monolithic three-dimensional integrated device provided in an embodiment of the present invention;

[0043] Figure 8 This is a schematic diagram of a bandgap reference core circuit constructed using two monolithic three-dimensional integrated devices, provided by an embodiment of the present invention.

[0044] Figure 9 This is provided by the embodiments of the present invention. Figure 8 A schematic diagram of the heat dissipation design structure.

[0045] Explanation of reference numerals in the attached figures: 101 is the first buried oxide layer, 102 is the configuration layer, 103 is the second buried oxide layer, 104 is the MOSFET device, 105 is the configuration layer electrode group, 106 is the shallow channel isolation structure, and 107 is the substrate layer. Detailed Implementation

[0046] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention are within the protection scope of the embodiments of the present invention.

[0047] This embodiment provides a monolithic three-dimensional integrated device. Please refer to [link / reference]. Figure 1 , Figure 1 This is a schematic diagram of the structure of the monolithic three-dimensional integrated device, specifically including: a first buried oxide layer 101, a configuration layer 102, a second buried oxide layer 103, and a substrate layer 107 stacked together; the configuration layer 102 contains one or more electronic components; a metal-oxide-semiconductor field-effect MOSFET device 104 and a configuration layer electrode group 105 are also disposed on the side of the first buried oxide layer 101 away from the configuration layer 102; the configuration layer electrode group 105 includes one or more electrodes; the first buried oxide layer 101 has conductive paths corresponding to one or more electrodes; the electrodes are connected to one end of the electronic component corresponding to the electrode in the configuration layer 102 through the conductive paths in the first buried oxide layer 101.

[0048] Specifically, the electronic components in the configuration layer 102 are connected to form the peripheral circuit of the MOSFET device 104 to achieve performance regulation of the MOSFET device 104 (such as threshold voltage, on-state current, etc.) and / or to achieve special functions such as heat dissipation through the peripheral circuit.

[0049] Currently, three-dimensional circuit integration can be achieved using TSV (Through Silicon Via) technology, such as... Figure 2 The diagram shows a schematic of an existing 3D integrated circuit implemented using TSV technology. This technology prefabricates the integrated devices at different process platforms and then achieves vertical interconnection through processes such as TSV. Because via locations need to be pre-defined for each device layer, and the fabrication processes for each layer differ, alignment allowances must be reserved for each via. This results in excessively large contact gaps (typically greater than 100 nm) and low alignment accuracy (typically greater than 1 μm). Therefore, the integration density of this 3D integration technology is not high enough.

[0050] In this embodiment, two buried oxide layers are provided, which belong to the DSOI (double Silicon-On-Insulator) structure. This structure not only inherits SOI technology and improves the integration of the circuit, but also achieves double-layer isolation of the device through the two buried oxide layers. This effectively suppresses the influence of the substrate 107 on the MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) device, thereby improving the reliability of the three-dimensional integrated circuit.

[0051] 3D integration is a trend in integrated circuit development during the "More than Moore" era. Its typical characteristics include the use of through-silicon vias (TSVs) for 3D stacking or direct monolithic 3D integration, thereby increasing chip integration density and reducing interconnect latency. However, this high-density 3D integration also brings reliability issues related to thermal effects, posing a severe challenge to the thermal design of 3D chips. On the one hand, small-size devices have low heat dissipation capabilities and high circuit power density; the high transistor density caused by 3D integration makes circuit thermal failure more likely. On the other hand, the new materials and structures introduced by 3D integration, such as TSVs, interlayer vias, intermediate isolation layers, and transition plates, also affect heat dissipation. Therefore, research on the thermal effects of 3D integrated circuits is fundamental to their reliable applications.

[0052] In existing solutions, M3D (Monolithic 3D) technology can also be used to achieve three-dimensional circuit integration, such as... Figure 3The diagram shows a schematic of an existing 3D integrated circuit structure implemented using M3D technology, which includes NMOS (N-Metal-Oxide-Semiconductor) devices, MIV (Monolithic Inter-layer Via), ILD (inter-layer dielectrics), PMOS (P-Metal-Oxide-Semiconductor) devices, and a substrate (bottom tier). In this technology, the upper-layer devices are fabricated vertically in sequence after the lower-layer devices are fabricated. Wafer bonding is achieved between the layers through interlayer deposition, and vertical interconnection is achieved through MIV. Bonding and other processes are low-temperature processes (typically below 400 degrees Celsius, with a more complex process flow than conventional processes), which differ from the conventional process sequence in 3D integrated circuits. This requires M3D technology to develop new EDA tools adapted to low-temperature processes based on existing EDA (Electronic Design Automation) tools, increasing wafer fabrication costs. In addition, the use of upper-layer low-temperature processes greatly increases the difficulty of local interconnection between device layers in 3D integrated circuits, further increasing wafer fabrication costs.

[0053] To reduce the implementation cost of 3D integrated circuits, the fabrication process temperature of the electronic components in the configuration layer 102 in this embodiment is not lower than a set temperature. This set temperature is the boundary temperature between low-temperature and room-temperature processes in SOI technology (the set temperature can range from 500 degrees Celsius to 700 degrees Celsius, specifically 600 degrees Celsius). In other words, in this embodiment, the fabrication process of the electronic components in the configuration layer 102 is a high-temperature process, making the fabrication process of the configuration layer 102 similar to or the same as the fabrication process of other layers in the monolithic 3D integrated device of this embodiment. Therefore, in the monolithic 3D integrated device provided in this embodiment, the top silicon device (MOSFET device 104) and the configuration layer 102 device can be co-designed using the same set of EDA tools to achieve simple monolithic 3D integration of the circuit.

[0054] In addition, since the monolithic three-dimensional integrated device provided in this embodiment can be fabricated based on the same process sequence, the through-hole size in the first buried oxide layer 101 is small, the alignment accuracy is high, and the cost is relatively low.

[0055] In practical applications, the electronic components in the configuration layer 102 may include one or more of diodes, resistors, capacitors, and bipolar transistors, in conjunction with the MOSFET device 104, to achieve functions such as a bandgap reference circuit and electrostatic discharge protection for the MOSFET device 104. Since the configuration layer in this embodiment does not require the fabrication of a MOSFET device, and the fabrication processes for diodes, resistors, capacitors, and bipolar transistors do not involve complex low-temperature processes, the fabrication of the configuration layer 102 is relatively simple, reducing the implementation difficulty and cost of this embodiment.

[0056] The fabrication method in this embodiment is to achieve monolithic 3D integration on a double buried oxide SOI wafer using CMOS-compatible technology. Compared with M3D using low-temperature technology, it does not require complex low-temperature process development, while improving the integration level.

[0057] like Figure 4 The diagram shown is a structural schematic of a monolithic three-dimensional integrated device provided in this embodiment. A bipolar transistor is provided in the configuration layer 102. The collector (C), base (B) and emitter (E) of the bipolar transistor are all connected to the corresponding electrodes in the configuration layer electrode group 105 through through holes in the first buried oxide layer 101.

[0058] like Figure 5 The diagram shown is a structural schematic of a monolithic three-dimensional integrated device provided in this embodiment. A diode is provided in the configuration layer 102, and the cathode and anode of the diode are respectively connected to the corresponding electrodes in the configuration layer electrode group 105 through through holes in the first buried oxide layer 101.

[0059] like Figure 6 The diagram shown is a structural schematic of a monolithic three-dimensional integrated device provided in this embodiment. A resistor is provided in the configuration layer 102, and the two ends of the resistor are connected to the corresponding electrodes in the configuration layer electrode group 105 through through holes in the first buried oxide layer 101.

[0060] like Figure 7 The diagram shown is a structural schematic of a monolithic three-dimensional integrated device provided in this embodiment. The configuration layer 102 is provided with two conductive dielectric layers, which together form a capacitor structure. The two conductive dielectric layers are respectively connected to the corresponding electrodes in the configuration layer electrode group 105 through through holes in the first buried oxide layer 101.

[0061] Of course, the configuration layer 102 of this embodiment can be equipped with multiple electronic components. Depending on the application scenario, they can be connected to form different peripheral circuits to achieve different functions. For example, a reverse protection diode can be set in the configuration layer to limit the magnitude and direction of the current between the source and drain of the MOSFET device. Several capacitors can be set in the configuration layer to construct the gate drive circuit of the MOSFET device. The mirror current is used to charge and discharge the capacitor to drive the switching of the MOSFET device.

[0062] To improve the safety and reliability of each device and reduce the risk of short circuits, in this embodiment, a shallow trench isolation (STI) structure 106 is provided between the MOSFET device 104 and each electrode in the configuration layer electrode group 105; and a shallow trench isolation structure 106 is provided between each electrode in the configuration layer electrode group 105.

[0063] In practical applications, the monolithic 3D integrated device provided in this embodiment can also be used as a heat dissipation structure and embedded in a 3D integrated circuit to achieve efficient and uniform heat dissipation for the monolithic 3D integrated circuit.

[0064] Specifically, the electrode in the configuration layer 102 includes an anode electrode and a cathode electrode; the anode electrode is connected to the anode of the diode through a corresponding conductive path in the first buried oxide layer 101; the cathode electrode is connected to the cathode of the diode through a corresponding conductive path in the first buried oxide layer 101; the second buried oxide layer 103 is also provided with an anode heat sink structure; the anode heat sink structure is in contact with the anode of the diode.

[0065] This monolithic 3D integrated device is a heat-dissipating monolithic 3D integrated device. In this embodiment, an anode heat sink structure is set near the anode of the diode. The anode heat sink structure is made of heat sink material and has a good heat sinking effect. Through heat dissipation design, the heat of the device layer in the 3D integrated circuit can be heat-sinked through the anode heat sink structure and uniformly dissipated through the substrate layer 107, thereby achieving efficient and uniform heat dissipation of the monolithic 3D integrated circuit.

[0066] Since this embodiment does not limit the specific connection of the electronic components in the configuration layer 102 of the monolithic 3D integrated device, one or more of the monolithic 3D integrated devices described above can also be used to construct a monolithic 3D integrated circuit. Of course, other existing 3D integration technologies can also be used in combination during the construction of a monolithic 3D integrated circuit, which will not be elaborated here.

[0067] Since the assembled monolithic 3D integrated circuit can contain one or more monolithic 3D integrated devices, the monolithic 3D integrated circuit can include multiple MOSFET devices 104 and configuration layers 102. Then, the electronic components in one or more configuration layers 102 can be used to jointly build peripheral circuits, and the one or more MOSFET devices 104 can be used to build active devices such as amplifiers, and combined with peripheral circuits to realize the 3D construction of other circuits.

[0068] like Figure 8 The diagram shown is a schematic of a bandgap reference core circuit constructed using two monolithic three-dimensional integrated devices according to this embodiment. This example illustrates the construction principle of the monolithic three-dimensional integrated circuit in this embodiment. In the bandgap reference core circuit, each monolithic three-dimensional integrated device has a bipolar transistor (PNP transistor) in its configuration layer 102. S1 is the source of the MOSFET device 104 in the first monolithic three-dimensional integrated device, D1 is the drain of the MOSFET device 104 in the first monolithic three-dimensional integrated device, G1 is the gate of the MOSFET device 104 in the first monolithic three-dimensional integrated device, C1 is the configuration layer 102 electrode corresponding to the collector of the bipolar transistor in the first monolithic three-dimensional integrated device, B1 is the configuration layer 102 electrode corresponding to the base of the bipolar transistor in the first monolithic three-dimensional integrated device, and E1 is the configuration layer 102 electrode corresponding to the emitter of the bipolar transistor in the first monolithic three-dimensional integrated device. S2 is the source of MOSFET device 104 in the second monolithic three-dimensional integrated device, D2 is the drain of MOSFET device 104 in the second monolithic three-dimensional integrated device, G2 is the gate of MOSFET device 104 in the second monolithic three-dimensional integrated device, C2 is the configuration layer 102 electrode corresponding to the collector of bipolar transistor in the second monolithic three-dimensional integrated device, B2 is the configuration layer 102 electrode corresponding to the base of bipolar transistor in the second monolithic three-dimensional integrated device, and E2 is the configuration layer 102 electrode corresponding to the emitter of bipolar transistor in the second monolithic three-dimensional integrated device.

[0069] Specifically, G1 and G2 are both connected to the circuit mirror current I, C1, B1, B2 and E2 are all connected to the circuit common ground voltage VSS, S1 and D2 are both connected to the circuit operating voltage VDD, D1 is connected to E1, C2 is connected to S2, the two MOSFET devices 104 form a differential pair, forming an operational amplifier, which is then connected to two bipolar transistors in the configuration layer 102, thereby using two monolithic three-dimensional integrated devices to build a bandgap reference core circuit.

[0070] The emitter and collector of the transverse PNP tube in the configuration layer 102 pass through the first buried oxide layer 101. The particle injection is the same as that of the configuration layer 102 of the DSOI. Meanwhile, the base is close to the emitter side, and the opposite impurities can be injected. Therefore, the process is simple.

[0071] In this diagram, the dots indicate the heat-generating locations within the circuit, and the arrows indicate the direction of heat conduction. The self-heating effects of upper-layer devices, the coupling with ambient temperature, thermal coupling between the configuration layer and upper-layer devices, and heat dissipation design remain challenges for this simple 3D integration based on dual-SOI technology. On the one hand, integrated circuits are required to operate normally within a certain ambient temperature range, such as 0–70℃ for civilian use and -40℃–85℃ for industrial use; on the other hand, the self-heating effect of transistors can also lead to performance degradation. Therefore, it is essential to study the thermal effects of monolithic 3D integrated circuits based on dual-SOI technology.

[0072] Since the above provides an example of a monolithic 3D integrated device with heat dissipation function, this section will build upon that example to provide... Figure 8 The heat dissipation design is implemented for the core circuit of the bandgap reference shown.

[0073] like Figure 9 As shown Figure 8 The diagram illustrates the heat dissipation design structure. In this scheme, heat-dissipating monolithic 3D integrated devices are positioned on both sides of the bandgap reference core circuit, and heat dissipation bases are placed under both the bandgap reference core circuit and the heat-dissipating monolithic 3D integrated devices. Of course, the number and placement of the heat-dissipating monolithic 3D integrated devices can be flexibly adjusted according to actual heat dissipation design requirements.

[0074] Because three-dimensional integration leads to heat dissipation issues, reverse-biased diodes, thermal layers, and heat sinks are required for heat dissipation. The configuration layer 102 of the monolithic three-dimensional integrated device with heat dissipation function incorporates a reverse-biased diode. Utilizing its anode heat sink structure, the heat generated by the bandgap reference core circuit can be effectively and uniformly dissipated through the heat sink base, achieving efficient and uniform heat dissipation for the three-dimensional integrated circuit.

[0075] The technical solutions provided in the embodiments of the present invention have at least the following technical effects or advantages:

[0076] The monolithic three-dimensional integrated device provided in this embodiment of the invention adopts a monolithic stacking method, inherits SOI (Silicon-On-Insulator) technology, and improves the integration of the circuit. At the same time, the monolithic three-dimensional integrated device has two buried oxide layers to achieve double-layer isolation, which can effectively suppress the influence of the substrate layer on the MOSFET device, thereby improving the reliability of the three-dimensional integrated circuit.

[0077] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0078] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. A monolithic three-dimensional integrated device, characterized in that, include: A first buried oxide layer, a configuration layer, a second buried oxide layer, and a substrate layer are stacked and arranged. The configuration layer contains one or more electronic components; A metal-oxide-semiconductor field-effect MOSFET device and a configuration layer electrode group are also disposed on the side of the first buried oxide layer away from the configuration layer; The configuration layer electrode group includes one or more electrodes; the first buried oxide layer is provided with conductive paths corresponding one-to-one with the one or more electrodes; The electrode is connected to one end of the electronic component in the configuration layer corresponding to the electrode through a conductive path in the first buried oxide layer; The configuration layer includes a diode; the configuration layer electrodes include an anode electrode and a cathode electrode; the anode electrode is connected to the anode of the diode through a corresponding conductive path in the first buried oxide layer; the cathode electrode is connected to the cathode of the diode through a corresponding conductive path in the first buried oxide layer; the second buried oxide layer also includes an anode heat sink structure; the anode heat sink structure is in contact with the anode of the diode.

2. The monolithic three-dimensional integrated device according to claim 1, characterized in that, The fabrication process temperature of the electronic components in the configuration layer is not lower than a set temperature.

3. The monolithic three-dimensional integrated device according to claim 2, characterized in that, The electronic components in the configuration layer include one or more of diodes, resistors, capacitors, and bipolar transistors.

4. The monolithic three-dimensional integrated device according to claim 1, characterized in that, A shallow channel isolation structure is provided between the MOSFET device and each electrode in the configuration layer electrode group; Each electrode in the configured layer electrode group is provided with a shallow channel isolation structure.

5. A monolithic three-dimensional integrated circuit, characterized in that, The three-dimensional integrated circuit includes one or more monolithic three-dimensional integrated devices; Each monolithic 3D integrated device includes: a first buried oxide layer, a configuration layer, a second buried oxide layer, and a substrate layer stacked together; The configuration layer contains one or more electronic components; A metal-oxide-semiconductor field-effect MOSFET device and a configuration layer electrode group are also disposed on the side of the first buried oxide layer away from the configuration layer; The configuration layer electrode group includes one or more electrodes; the first buried oxide layer is provided with conductive paths corresponding one-to-one with the one or more electrodes; The electrode is connected to one end of the electronic component in the configuration layer corresponding to the electrode through a conductive path in the first buried oxide layer; The one or more monolithic three-dimensional integrated devices include at least one or more heat-dissipating three-dimensional integrated devices, wherein a diode is provided in the configuration layer of the heat-dissipating three-dimensional integrated device; the configuration layer electrodes include an anode electrode and a cathode electrode; the anode electrode is connected to the anode of the diode through a corresponding conductive path in the first buried oxide layer; the cathode electrode is connected to the cathode of the diode through a corresponding conductive path in the first buried oxide layer; the second buried oxide layer also provides an anode heat sink structure; the anode heat sink structure is in contact with the anode of the diode.

6. The monolithic three-dimensional integrated circuit according to claim 5, characterized in that, The fabrication process temperature of the electronic components in the configuration layer is not lower than a set temperature.

7. The monolithic three-dimensional integrated circuit according to claim 6, characterized in that, The electronic components in the configuration layer include one or more of diodes, resistors, capacitors, and bipolar transistors.

8. The monolithic three-dimensional integrated circuit according to claim 5, characterized in that, In each monolithic three-dimensional integrated device, a shallow channel isolation structure is provided between the MOSFET device and each electrode in the configuration layer electrode group; a shallow channel isolation structure is provided between each electrode in the configuration layer electrode group.

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