Display panel and display device

Abstract

The application provides a display panel and a display device, the display panel comprising a plurality of pixel driving circuits, a driving transistor of each pixel driving circuit comprising a source, a drain, an active layer pattern, a first gate, and a second gate, the source, the drain, the first gate, and the second gate being located on one side of the active layer pattern, the active layer pattern being electrically connected to the source and the drain through a via in a via region, in the same driving transistor, the first gate and the second gate are arranged at intervals, the second gate is located in a first region on the active layer pattern where a projection of the second gate is located, and is located between a second region on the active layer pattern where a projection of the first gate is located and the via region. According to the embodiment of the application, the second gate is arranged on both sides of the first gate, so that when the driving transistor is working, the area resistance of the active layer pattern corresponding to the second gate can be approximately 0, the resistance of the driving transistor when the driving circuit is working is reduced, and the on-state current (Ion) is improved.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] Currently, in the pixel driving circuit of display panels, the driving transistors generally use metal oxide semiconductor thin film transistors such as top-gate indium gallium zinc oxide (IGZO). During fabrication, it is necessary to conductionize the indium gallium zinc oxide in the region between the channel region (the region corresponding to the gate) and the via region (the region corresponding to the source and drain) of the active layer pattern to reduce resistance and ensure normal transmission of channel electrons. However, after conductingion, the resistance value of this region is still relatively high.

[0003] Therefore, the existing pixel driving circuit of display panels has a technical problem of high resistance value of driving transistors, which needs to be improved. Summary of the Invention

[0004] The present invention provides a display panel and a display device to alleviate the technical problem of high resistance values ​​of driving transistors in the pixel driving circuit of existing display panels.

[0005] To solve the above problems, the technical solution provided by the present invention is as follows:

[0006] This invention provides a display panel, which includes a plurality of pixel driving circuits, each of which includes a driving transistor, wherein:

[0007] The driving transistor includes a source, a drain, an active layer pattern, a first gate, and a second gate. The source and the drain are located on one side of the active layer pattern, the first gate is located on one side of the active layer pattern, and the second gate is located on one side of the active layer pattern. The active layer pattern is electrically connected to the source and the drain through vias in the via region.

[0008] In the same driving transistor, the first gate and the second gate are spaced apart, and the first region where the orthogonal projection of the second gate on the active layer pattern is located is between the second region where the orthogonal projection of the first gate on the active layer pattern is located and the via region.

[0009] In the display panel provided in the embodiments of the present invention, the first gate and the second gate are disposed on the same layer.

[0010] In the display panel provided in the embodiments of the present invention, the second gate includes a first sub-gate and a second sub-gate, and the first gate is located between the first sub-gate and the second sub-gate.

[0011] In the display panel provided in the embodiments of the present invention, the first sub-gate and the second sub-gate have the same orthographic projection on the active layer pattern.

[0012] In the display panel provided in the embodiments of the present invention, the first width of the first sub-gate is different from the second width of the second sub-gate.

[0013] In the display panel provided in the embodiments of the present invention, in the first extension direction of the active layer pattern, the width value of the first sub-gate is smaller than the width value of the first gate, and the width value of the second sub-gate is smaller than the width value of the first gate.

[0014] In the display panel provided in the embodiments of the present invention, the resistivity of the portion of the semiconductor material of the active layer pattern that is connected to the source and the drain in the via region is the same as the resistivity of the portion in the first region and the second region.

[0015] In the display panel provided in this embodiment of the invention, the first sub-gate and the second sub-gate are subjected to the same operating voltage.

[0016] In the display panel provided in this embodiment of the invention, the semiconductor material of the active layer pattern includes indium gallium zinc oxide.

[0017] Furthermore, embodiments of the present invention also provide a display device, which includes the display panel described in the above embodiments.

[0018] The beneficial effects of this invention are as follows: This invention provides a display panel and a display device. The display panel includes multiple pixel driving circuits, each of which includes a driving transistor. The driving transistor includes a source, a drain, an active layer pattern, a first gate, and a second gate. The source, the drain, the first gate, and the second gate are located on one side of the active layer pattern. The active layer pattern is electrically connected to the source and the drain through vias in a via region. In the same driving transistor, the first gate and the second gate are spaced apart. The first region where the orthographic projection of the second gate onto the active layer pattern is located is between the second region where the orthographic projection of the first gate onto the active layer pattern is located and the via region. By adding second gates on both sides of the first gate, the regional resistance of the active layer pattern corresponding to the second gate can be reduced when the driving transistor is working, thereby reducing the resistance of the driving transistor in the driving circuit and increasing the on-state current (Ion). Attached Figure Description

[0019] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0020] Figure 1 This is a cross-sectional schematic diagram of a driving transistor in the prior art;

[0021] Figure 2 A cross-sectional schematic diagram of the driving transistor provided in an embodiment of the present invention;

[0022] Figure 3 An equivalent circuit diagram of the driving transistor provided in an embodiment of the present invention;

[0023] Figure 4 This is a schematic diagram of a pixel driving circuit according to an embodiment of the present invention. Detailed Implementation

[0024] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0025] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0026] In this application, the term "exemplary" is used to mean "serving as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as being more preferred or advantageous than other embodiments. The following description is provided to enable any person skilled in the art to make and use the invention. Details are set forth in the following description for purposes of explanation. It should be understood that those skilled in the art will recognize that the invention can be made without using these specific details. In other instances, well-known structures and processes will not be described in detail to avoid obscuring the description of the invention with unnecessary detail. Therefore, the invention is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed in this application.

[0027] Figure 1 This diagram illustrates a cross-sectional view of a driving transistor provided by the prior art. The diagram uses a top-gate (gate above the active layer pattern) structure transistor as an example. Other structures such as bottom-gate (gate below the active layer pattern) have similar technical problems and will not be described in detail here.

[0028] Please see Figure 1 The driving transistor, from bottom to top, includes: a substrate m1, a buffer layer m2, a first insulating layer m3, an active layer pattern m4 (formed by patterning the entire surface of the active layer; in this application, the material of the active layer pattern is a metal oxide such as indium gallium zinc oxide), a second insulating layer m5, a gate m6, a third insulating layer m7, a source m81, and a drain m82. For ease of explanation below, the active layer pattern is spatially divided into a first via region S11 (corresponding to the connection region of the source m81), a second via region S12 (corresponding to the connection region of the drain m82), an active region S13 (corresponding to the orthographic projection region of the gate m6 on the active layer pattern m4), a first conductive region S14 located between the first via region S11 and the active region S13, and a second conductive region S15 located between the second via region S12 and the active region S13.

[0029] During fabrication, the first conductive region S14 and the second conductive region S15 need to be conductiveized to reduce the resistance of the active layer and ensure normal electron transport in the channel (the part of the active layer pattern in the active region S13). After conductiveization, the resistance values ​​of R1 in the first conductive region S14 and R2 in the second conductive region S15 are generally on the order of 10E4 (i.e., 10000) ohms, which is relatively high. This results in a very small current flowing through the driving transistor (i.e., the on-state current Ion mentioned above) at the lowest driving voltage.

[0030] The present invention addresses the technical problem of high resistance values ​​in the driving transistors of existing display panels.

[0031] Specifically, the display panel provided in this application includes multiple pixel driving circuits, each of which includes a driving transistor. The driving transistor includes a source, a drain, an active layer pattern, a first gate, and a second gate. The source and drain are located on one side of the active layer pattern, the first gate is located on one side of the active layer pattern, and the second gate is located on one side of the active layer pattern. The active layer pattern electrically connects the source and drain through vias within a via region. Within the same driving transistor, the first gate and the second gate are spaced apart. The first region where the orthographic projection of the second gate onto the active layer pattern is located is between the second region where the orthographic projection of the first gate onto the active layer pattern is located and the via region.

[0032] In one embodiment, such as Figure 2 and Figure 3 As shown, Figure 2 This is a cross-sectional schematic diagram of a driving transistor provided in an embodiment of the present invention. The diagram uses a top-gate (gate above the active layer pattern) structure transistor as an example for illustration. Other structures such as bottom-gate (gate below the active layer pattern) transistors have similar technical problems and will not be described further. Figure 2 As shown, the display panel provided in this embodiment of the invention includes multiple pixel driving circuits, each of which includes a driving transistor, wherein:

[0033] The driving transistor, from bottom to top, comprises: a substrate m1, a buffer layer m2, a first insulating layer m3, an active layer pattern m4 (formed by patterning an entire surface of the active layer; in this application, the material of the active layer pattern is a metal oxide such as indium gallium zinc oxide), a second insulating layer m5, a first gate m61, and a second gate (including...). Figure 2 The active layer pattern includes a first sub-gate m62 and a second sub-gate m63, a third insulating layer m7, a source m81, and a drain m82. For ease of explanation below, the active layer pattern is spatially divided into via regions (including a first via region S11 corresponding to the connection region of the source m81, a second via region S12 corresponding to the connection region of the drain m82, and a second region S13 (i.e., the first via region S11 corresponding to the connection region of the source m81, the second via region S12 corresponding to the connection region of the drain m82, and the second via region S13 corresponding to the connection region of the drain m82). Figure 1The active region S13 corresponds to the orthographic projection region of the first gate m61 on the active layer pattern m4, the first region (including the orthographic projection region S16 corresponding to the first sub-gate m62 on the active layer pattern m4 and the orthographic projection region S17 corresponding to the second sub-gate m63 on the active layer pattern m4), the first semiconductor region C1 between the orthographic projection region S16 and the active region S13, and the second semiconductor region C2 between the orthographic projection region S17 and the active region S13. The spatial relative positions of each region are as follows: Figure 2 As shown, no further details will be provided.

[0034] Figure 2 The equivalent circuit of the driving transistor shown is as follows Figure 3 As shown, the equivalent circuit corresponding to the driving transistor is formed by three sub-transistors and two resistors connected in series. These are: the first sub-transistor T11 formed by the first sub-gate m62 and the active layer pattern in the orthographic projection region S16; the second sub-transistor T12 formed by the first gate m61 and the active layer pattern in the second region S13; the third sub-transistor T13 formed by the second sub-gate m63 and the active layer pattern in the orthographic projection region S17; the resistor R11 formed by the active layer pattern in the first semiconductor region C1; and the resistor R12 formed by the active layer pattern in the second semiconductor region C2. In this circuit, since the lengths of the first semiconductor region C1 and the second semiconductor region C2 are very small (current technology can achieve about 1 micrometer), the resistance values ​​of resistors R11 and R12 can be much less than 10,000 ohms, or even negligible. Thus, when the driving transistor is working, and the first sub-transistor T11, the second sub-transistor T12, and the third sub-transistor T13 are all turned on, the resistance value of each sub-transistor is approximately 0, and the resistance of the entire driving transistor is approximately 0. Compared with the prior art, the resistance value of the driving transistor has been significantly reduced. According to I = U / R, U is the voltage across the source and drain, Vds. With Vds unchanged, the total resistance R decreases, so the total current I increases, that is, the on-state current (Ion) increases.

[0035] This embodiment provides a display panel including multiple pixel driving circuits. Each pixel driving circuit includes a driving transistor, which includes a source, a drain, an active layer pattern, a first gate, and a second gate. The source, drain, first gate, and second gate are located on one side of the active layer pattern. The active layer pattern is electrically connected to the source and drain through vias within a via region. Within the same driving transistor, the first gate and the second gate are spaced apart. The first region where the orthographic projection of the second gate onto the active layer pattern is located is between the second region where the orthographic projection of the first gate onto the active layer pattern is located and the via region. By adding second gates on both sides of the first gate, the region resistance of the active layer pattern corresponding to the second gate can be approximately zero when the driving transistor is operating. This reduces the resistance of the driving transistor during operation and increases the on-state current (Ion).

[0036] In one embodiment, such as Figure 2 As shown, the first gate m61 and the second gate (m62 and m63) are disposed on the same layer. Specifically, the first gate m61 and the second gate (m62 and m63) are patterned in one process by a metal layer disposed on the insulating layer m5. The co-location of the first gate and the second gate eliminates the need for a mask, simplifying the manufacturing process of the display panel.

[0037] In one embodiment, such as Figure 2 As shown, the second gate includes a first sub-gate m62 and a second sub-gate m63, with the first gate m61 located between the first sub-gate m62 and the second sub-gate m63. Specifically, the second gate is divided into two parts, respectively disposed on both sides of the first gate m61 and located above regions S16 (a part of the lightly doped region) and S17 (a part of the lightly doped region). In this embodiment, dividing the second gate into two parts increases the area of ​​the second gate, thereby increasing the corresponding area of ​​the gate and the channel region, which in turn reduces the resistance of the driving transistor in the driving circuit and increases the on-state current (Ion).

[0038] In one embodiment, such as Figure 2 As shown, the first sub-gate m62 and the second sub-gate m63 have the same orthographic projection on the active layer pattern m4. Specifically, in this embodiment, the shape and aspect ratio of the first sub-gate m62 and the second sub-gate m63 can be exactly the same to reduce the manufacturing difficulty of the mask.

[0039] In one embodiment, the first width of the first sub-gate (i.e., the length of region S16) is different from the second width of the second sub-gate (i.e., the length of region S17), which reduces the precision requirements of the fabrication process. It should be noted that in this embodiment, the first width and the second width specifically refer to the lateral lengths of the first and second sub-gates.

[0040] In one embodiment, in the first extending direction of the active layer pattern m4 (i.e. Figure 2 In the horizontal direction (as shown in the diagram), the width of the first sub-gate m62 is smaller than the width of the first gate m61, and the width of the second sub-gate m63 is smaller than the width of the first gate m61. It should be noted that the first extension direction refers to the horizontal extension direction of the cross-sectional structure diagram of the display panel provided in this embodiment of the invention. Specifically, the range of the first width and the second width is greater than or equal to 3 micrometers, with no maximum limit, but must be smaller than the width of the first gate m61.

[0041] In one embodiment, the resistivity of the portion of the semiconductor material of the active layer pattern m4 connected to the source m81 and the drain m82 within the via region is the same as the resistivity of the portion within the first region S13 and the second region (S16 and S17).

[0042] Resistivity is a physical quantity used to represent the electrical resistance of various materials. The resistance of a conductor made of a certain material that is 1 meter long and has a cross-sectional area of ​​1 square meter is numerically equal to the resistivity of that material. It reflects the property of a material to impede the flow of electric current, and it is not only related to the type of material but also affected by external factors such as temperature, pressure, and magnetic fields.

[0043] Specifically, the resistivity of the heavily doped region (i.e., region S11) below the source m81 and the heavily doped region (i.e., region S12) below the drain m82 are the same as the resistivity of the lightly doped region (i.e., region S16) and the lightly doped region (i.e., region S17).

[0044] In one embodiment, the first sub-gate m62 and the second sub-gate m63 are subjected to the same operating voltage. Based on this, the first sub-gate m62 and the second sub-gate m63 can be electrically connected, thereby reducing the number of gate control signals.

[0045] In one embodiment, the operating voltage applied to the first sub-gate m62 and the second sub-gate m63 can be the power supply voltage VDD (generally greater than 36V, etc.), which can maximize the electron migration efficiency of the active layer pattern in regions S16 and S17, reduce the electron migration difficulty of the entire transistor, and further improve the on-state current (Ion) of the entire transistor.

[0046] In one embodiment, the semiconductor material of the active layer pattern m4 includes indium gallium zinc oxide (IGNOW). Specifically, the doping degree of the IGNOW semiconductor material varies in different regions of the active layer pattern. For example, the concentration of IGNOW doped impurities is higher in heavily doped regions and regions containing heavily doped regions, and lower in lightly doped regions and regions containing lightly doped regions. Semiconductor doping is used to improve the electrical performance of the semiconductor, and the different doping degrees of IGNOW semiconductor material in different regions also reflect the different electrical performance in different regions.

[0047] In order to make this application applicable to actual products, this application uses... Figure 4 The pixel driving circuit shown is used as an example for explanation.

[0048] Figure 4 This is a circuit schematic diagram of a pixel driving circuit involved in this application. For example... Figure 4 As shown, the pixel driving circuit includes a first switching transistor T41 and a second switching transistor T42 (including...). Figure 4 The diagram shows sub-transistors T421, T422, and T423, a third switch T43, a storage capacitor C, and an organic light-emitting diode D. The second switch T42 uses the driving transistor described above, which is equivalent to three sub-transistors and two resistors (…). Figure 4 The series connection of resistors (not shown) is shown.

[0049] In this configuration, the gate of the first switch T41 is electrically connected to the first control signal line WR, the source is electrically connected to the data signal line Vdata, and the drain is electrically connected to the first node A1. The gate of the sub-transistor T422 in the second switch T42 is electrically connected to the first node A1. The gates of the sub-transistors T421 and T423 in the second switch T42 are electrically connected to the positive power supply voltage VDD (to maximize the electron migration efficiency of the semiconductor material). The source of the second switch T42 (i.e., the source of sub-transistor T421) is electrically... Connect the positive power supply voltage VDD. The drain of the second switching transistor T42 (i.e., the drain of the sub-transistor T423) is electrically connected to the second node A2. The gate of the third switching transistor T43 is electrically connected to the second control signal line RD, the source is electrically connected to the second node A2, and the drain is electrically connected to the detection signal line Monitor. One end of the storage capacitor C is electrically connected to the first node A1, and the other end is electrically connected to the second node A2. The anode of the organic light-emitting diode D is electrically connected to the second node A2, and the cathode of the organic light-emitting diode D is electrically connected to the negative power supply voltage VSS.

[0050] The first control signal line WR, the data signal line Vdata, and the second control signal line RD are electrically connected to the drive circuit, and the detection signal line Monito is electrically connected to the detection circuit.

[0051] The control circuit, detection circuit, and drive circuit are existing circuit modules in a timing controller (TCON). Those skilled in the art will understand that a timing controller mainly consists of a timing generator, display memory and management circuitry, and control circuitry. Using an existing timing controller to implement the temperature compensation function does not require additional hardware costs.

[0052] The detection circuit is used to obtain the current threshold voltage Vth of the switching transistor in the pixel circuit. Specifically, the detection circuit obtains the current threshold voltage Vth of the driving switching transistor, namely the second switching transistor T42, in each sub-pixel driving circuit in the pixel circuit in real time through the detection signal line Monito.

[0053] Specifically, when the first switch T41 and the third switch T43 are simultaneously turned on, the data voltage signal applied to the data signal line Vdata and the reference voltage signal applied to the detection signal line Monito are written to the two ends of the storage capacitor C, respectively. At this time, the second switch T42 (mainly sub-transistor T422 is turned on at this time, while sub-transistors T421 and T423 are always turned on) is turned on. Then, the reference voltage signal is turned off, and the current charges the parasitic capacitance of the detection signal line Monito through the third switch T43. When the voltage difference across the storage capacitor C reaches the current threshold voltage Vth, the second switch T42 (mainly sub-transistor T422 is turned off at this time, while sub-transistors T421 and T423 are always turned on) is turned off. At this time, the detection circuit reads the voltage on the detection signal line Monito, which is the current threshold voltage Vth driving the switch.

[0054] The control circuit is used to obtain the current voltage difference ΔVth between the current threshold voltage Vth and the initial threshold voltage Vth0. It obtains the current compensation gain G that matches the current voltage difference ΔVth from the preset correlation data between the voltage difference ΔVth and the compensation gain G. The current compensation gain G is used to control the driving circuit to drive the pixel circuit to compensate for the effect of temperature changes on the pixel circuit.

[0055] Accordingly, embodiments of the present invention also provide a display device, which includes the display panel provided by the present invention. This display device is an electronic terminal with display functionality, and can be a fixed terminal such as a desktop computer or television set, a mobile terminal such as a smartphone or tablet computer, or a wearable device such as smart glasses, a virtual display device, or an augmented reality display device.

[0056] As can be seen from the above embodiments:

[0057] This invention provides a display panel and a display device. The display panel includes multiple pixel driving circuits, each of which includes a driving transistor. Each driving transistor includes a source, a drain, an active layer pattern, a first gate, and a second gate. The source, drain, first gate, and second gate are located on one side of the active layer pattern. The active layer pattern is electrically connected to the source and drain via vias within a via region. In the same driving transistor, the first gate and the second gate are spaced apart. The first region where the orthographic projection of the second gate onto the active layer pattern is located is between the second region where the orthographic projection of the first gate onto the active layer pattern is located and the via region. By adding second gates on both sides of the first gate, the resistance of the active layer pattern corresponding to the second gate can be approximately zero when the driving transistor is operating. This reduces the resistance of the driving transistor during operation, increases the on-state current (Ion), and eliminates the need for conductor treatment of the active layer pattern region corresponding to the second gate, simplifying the manufacturing process.

[0058] In summary, although the present invention has been disclosed above with reference to preferred embodiments, the above preferred embodiments are not intended to limit the present invention. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the claims.

Claims

1. A display panel, characterized in that, The display panel includes multiple pixel driving circuits, each of which includes a driving transistor, wherein: The driving transistor includes a source, a drain, an active layer pattern, a first gate, and a second gate. The source and the drain are located on one side of the active layer pattern, and the first gate and the second gate are located on the same side of the active layer pattern. The active layer pattern is electrically connected to the source and the drain through vias in the via region. In the same driving transistor, the first gate and the second gate are disposed on the same layer and spaced apart. The first region where the orthogonal projection of the second gate on the active layer pattern is located is located between the second region where the orthogonal projection of the first gate on the active layer pattern is located and the via region. The second gate includes a first sub-gate and a second sub-gate, and the first gate is located between the first sub-gate and the second sub-gate. The operating voltage applied to the first sub-gate and the second sub-gate is the power supply voltage VDD.

2. The display panel as described in claim 1, characterized in that, The first sub-gate and the second sub-gate have the same orthographic projection on the active layer pattern.

3. The display panel as described in claim 1, characterized in that, The first width of the first sub-gate is different from the second width of the second sub-gate.

4. The display panel as described in claim 1, characterized in that, In the first extension direction of the active layer pattern, the width of the first sub-gate is smaller than the width of the first gate, and the width of the second sub-gate is smaller than the width of the first gate.

5. The display panel as described in claim 1, characterized in that, The resistivity of the portion of the semiconductor material in the active layer pattern that connects to the source and drain in the via region is the same as the resistivity of the portions in the first and second regions.

6. The display panel as described in claim 1, characterized in that, The first sub-gate and the second sub-gate are subjected to the same operating voltage.

7. The display panel as described in claim 1, characterized in that, The active layer pattern is made of indium gallium zinc oxide.

8. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 7.

Images