Semiconductor device and method of forming the same

Abstract

The application discloses a semiconductor device, comprising: a semiconductor substrate having a well region; a gate structure formed above the well region of the semiconductor substrate, wherein the gate structure has a first sidewall and a second sidewall opposite to the first sidewall; a gate spacer structure comprising two asymmetric portions covering the first sidewall and the second sidewall of the gate structure respectively; and a source region and a drain region formed in the semiconductor substrate, wherein the source region and the drain region are respectively aligned with the outer edges of the two asymmetric portions of the gate spacer structure, and the lateral distance between the drain region and the gate structure is greater than the lateral distance between the source region and the gate structure. The above-mentioned scheme of the application makes the semiconductor device have greater voltage resistance, improves the high-voltage capability of the semiconductor device, and improves the electrical performance of the semiconductor device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and more particularly to a semiconductor device and a method for forming the same. Background Technology

[0002] In recent years, with the increasing demand for high-voltage devices, research on high-voltage metal-oxide-semiconductor (MOS) transistors used in high-voltage devices has received increasing attention. High-voltage (HV) MOS devices used at high voltages can be, but are not limited to, voltages higher than the voltage supplied to I / O circuits. MOS devices such as HVMOS devices can be used as switches and are widely used in audio output drivers, CPU power supplies, power management systems, AC / DC converters, LCD or plasma TV drivers, automotive electronic components, PC peripherals, small DC motor controllers, and other consumer electronics devices.

[0003] While existing semiconductor devices, such as MOS devices, and their fabrication methods are sufficient to meet their intended purposes, they are not entirely satisfactory in all aspects. For example, the complexity of semiconductor device processing and manufacturing increases as the size of semiconductor devices shrinks. With the reduction in semiconductor device size, the lateral distance between electrodes decreases, which can have a significant impact on the electrical performance of the semiconductor device. Furthermore, with advancements in semiconductor manufacturing, the breakdown voltage of high-voltage MOS devices needs to be further increased to meet device performance requirements, as the demand for high-voltage semiconductor devices continues to grow. Therefore, there are still some problems to be overcome in semiconductor devices within semiconductor integrated circuits and technologies. Summary of the Invention

[0004] In view of this, the present invention provides a semiconductor device and a method for forming the same, in order to solve the above-mentioned problems.

[0005] According to a first aspect of the present invention, a semiconductor device is disclosed, comprising:

[0006] A semiconductor substrate having a well region;

[0007] A gate structure is formed above the well region of the semiconductor substrate, wherein the gate structure has a first sidewall and a second sidewall opposite to the first sidewall;

[0008] A gate spacing structure, comprising two asymmetrical portions respectively covering the first sidewall and the second sidewall of the gate structure; and

[0009] A source region and a drain region are formed in the semiconductor substrate, wherein the source region and the drain region are respectively aligned with the outer edges of the two asymmetrical portions of the gate spacer structure.

[0010] The lateral distance between the drain region and the gate structure is greater than the lateral distance between the source region and the gate structure.

[0011] According to a second aspect of the present invention, a method for forming a semiconductor device is disclosed, comprising:

[0012] A semiconductor substrate is provided, the semiconductor substrate having a well region and an isolation structure adjacent to the well region;

[0013] A gate structure is formed above the well region of the semiconductor substrate, wherein the gate structure has a first sidewall and a second sidewall opposite to the first sidewall.

[0014] A gate spacer structure is formed, the gate spacer structure including two asymmetric portions, the two asymmetric portions respectively covering the first sidewall and the second sidewall of the gate structure; and

[0015] A source region and a drain region are formed in the semiconductor substrate, wherein the source region and the drain region are respectively aligned with the outer edges of the two asymmetric portions of the gate spacer structure.

[0016] The lateral distance between the drain region and the gate structure is greater than the lateral distance between the source region and the gate structure.

[0017] The semiconductor device of the present invention includes: a semiconductor substrate having a well region; a gate structure formed above the well region of the semiconductor substrate, wherein the gate structure has a first sidewall and a second sidewall opposite to the first sidewall; a gate spacer structure including two asymmetrical portions respectively covering the first sidewall and the second sidewall of the gate structure; and a source region and a drain region formed in the semiconductor substrate, wherein the source region and the drain region are respectively aligned with the outer edges of the two asymmetrical portions of the gate spacer structure, and wherein the lateral distance between the drain region and the gate structure is greater than the lateral distance between the source region and the gate structure. The above-described solution of the present invention enables the semiconductor device to have a greater withstand voltage capability, improves the high-voltage capability of the semiconductor device, and enhances the electrical performance of the semiconductor device. Attached Figure Description

[0018] Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F and Figure 1G This is a cross-sectional view of an intermediate stage of a method for forming a semiconductor device according to some embodiments of the present invention.

[0019] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E , Figure 2F and Figure 2G This is a cross-sectional view of an intermediate stage of another method for forming a semiconductor device according to some embodiments of the present invention.

[0020] Figure 3 This is a cross-sectional view of an intermediate stage of a semiconductor device according to some embodiments of the present invention.

[0021] Figure 4 This is a cross-sectional view of an intermediate stage of a semiconductor device according to some embodiments of the present invention. Detailed Implementation

[0022] In the following detailed description of embodiments of the invention, reference is made to the accompanying drawings, which form part of the invention, and which illustrate specific preferred embodiments in which the invention can be practiced. These embodiments have been described in sufficient detail to enable those skilled in the art to practice them, and it should be understood that other embodiments may be utilized, and mechanical, structural, and procedural changes may be made, without departing from the spirit and scope of the invention. Therefore, the following detailed description should not be construed as limiting, and the scope of the embodiments of the invention is defined only by the appended claims.

[0023] It will be understood that although the terms “first,” “second,” “third,” “primary,” “secondary,” etc., may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, region, layer, or portion from another. Therefore, without departing from the teachings of the inventive concept, the first or primary element, component, region, layer, or portion discussed below may be referred to as a second or secondary element, component, region, layer, or portion.

[0024] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “under,” “above,” and “above” may be used herein to describe the relationship of an element or feature to it. Another element or feature is shown in the figure. In addition to the orientation described in the figure, the spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly. Additionally, it will be understood that when a “layer” is referred to as being “between” two layers, it can be the only layer between the two layers, or there may be one or more intermediate layers.

[0025] The terms “about,” “roughly,” and “about” generally mean a range of ±20%, ±10%, ±5%, ±3%, ±2%, ±1%, or ±0.5% of a specified value. The specified values ​​in this invention are approximate. Unless otherwise specified, the specified values ​​include the meanings of “about,” “roughly,” and “about.” The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used herein, the singular terms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise.

[0026] It will be understood that when an “element” or “layer” is referred to as being “on,” “connected to,” “coupled to,” or “adjacent to” another element or layer, it can be directly on, connected to, coupled to, or adjacent to the other element or layer, or there may be intermediate elements or layers. Conversely, when an element is referred to as being “directly on,” “directly connected to,” “directly coupled to,” or “immediately adjacent to” another element or layer, there are no intermediate elements or layers.

[0027] Note: (i) the same features will be represented by the same reference numerals throughout the figures and will not necessarily be described in detail in every figure in which they appear, and (ii) a series of figures may show different aspects of a single item, each of which is associated with various reference labels that may appear throughout the series or only in selected figures of the series.

[0028] According to some embodiments of the present invention, a semiconductor device and a method thereof are described below, wherein a gate spacer structure having two asymmetric (asymmetric) portions is formed to extend the distance between the drain region and the gate structure of the semiconductor device. In some embodiments, the semiconductor device includes a semiconductor substrate having a well region, a gate structure formed above the well region of the semiconductor substrate, a gate spacer structure including two asymmetric (asymmetric) portions respectively covering opposite sidewalls (e.g., the first sidewall and the second sidewall described in the embodiments below), a source region and a drain region formed in the semiconductor substrate and respectively aligned with the outer edges of the asymmetric portions of the gate spacer structure, wherein the lateral distance between the drain region and the gate is greater than the lateral distance between the source region and the gate structure. The electrical performance of the semiconductor device according to some embodiments of the present invention can be significantly improved. For example, the safe operating area (SOA) diagram defines the maximum values ​​of the drain-source voltage (VDS) and the drain current (ID) to ensure the proper operation of the semiconductor device (e.g., a metal-oxide-semiconductor field-effect transistor (MOSFET)). In some embodiments, the extended distance between the drain region and the gate structure of the semiconductor device increases the breakdown voltage and the safe operating area (SOA). Furthermore, the extended distance between the drain region and the gate structure reduces unwanted parasitic capacitance between the gate structure and the contact plug connected to the drain region. Additionally, according to some embodiments of the invention, when the lateral distance between the source region and the gate structure is smaller than the lateral distance between the drain region and the gate structure of the semiconductor device, more current is allowed to flow from the source (source region) to the drain (drain region). In this invention, by providing asymmetrical first and second spacing portions on both sides of the gate structure, wherein the second spacing portion closer to the drain region has a larger lateral width than the first spacing portion closer to the source region, the larger extended distance between the drain region and the gate structure of the semiconductor device increases the breakdown voltage and the SOA area. The above-described solution of the invention enables the semiconductor device to have a larger withstand voltage capability, improves the high-voltage capability of the semiconductor device, and enhances the electrical performance of the semiconductor device. Furthermore, the use of the first and second spacers (which are formed before the source and drain regions) enables the subsequent formation of the source and drain regions to be automatically aligned, thereby allowing the source and drain regions to automatically align with the sidewalls of the first and second spacers, saving masking and process steps, reducing manufacturing costs, and improving production efficiency.Furthermore, the larger extension distance between the drain region and the gate structure of the semiconductor device reduces the unwanted parasitic capacitance between the gate structure and the contact plug connected to the drain region.

[0029] The following provides some methods for forming a semiconductor device according to some embodiments of the present invention. It should be noted that the invention is not limited to the exemplary methods and structures described herein. The steps and structures described below are merely examples for providing examples of the fabrication and configuration of semiconductor devices.

[0030] Figure 1A , Figure 1B , Figure 1C , Figure 1D , Figure 1E , Figure 1F and Figure 1G This is a cross-sectional view of an intermediate stage of a method for forming a semiconductor device according to some embodiments of the present invention. For simplicity, only one transistor is depicted here. However, the number of transistors is not limited to this.

[0031] Reference Figure 1A A semiconductor substrate 100 is provided having a well region 104 and an isolation structure 108 adjacent to the well region 104. Furthermore, a gate structure 110 is formed above the well region 104 of the semiconductor substrate 100. In some embodiments, the semiconductor substrate 100 is a silicon substrate. The semiconductor substrate 100 may have a first conductivity type such as P-type. The well region 104 is formed in the semiconductor substrate 100 and may have a second conductivity type, such as N-type.

[0032] Although only well region 104 in semiconductor substrate 100 is depicted for simplicity, semiconductor substrate 100 may also include other features, such as other well regions. For example, semiconductor substrate 100 may also include a deep well region (not shown) having a second conductivity type opposite to the first conductivity type, such as N-type. Furthermore, semiconductor substrate 100 may also include a well region (not shown) (referred to as a P-well region) formed in the deep well region having a first conductivity type such as P-type, wherein a portion of the P-well region extends between the deep well region and well region 104. Well region 104 may be formed within the P-well region and surrounded by isolation structure 108 and the P-well region.

[0033] like Figure 1A As shown, an isolation structure 108 extending downward from the upper surface 100a of the semiconductor substrate 100 is embedded in the semiconductor substrate 100. In some embodiments, the isolation structure 108 includes a shallow trench isolation (STI) element. In some embodiments, the isolation structure 108 includes a field oxide (FOX) isolation element. The isolation structure 108 may include silicon oxide, another suitable insulating material, or a combination thereof.

[0034] In some embodiments, a gate structure 110 is formed on the upper surface 100a of the semiconductor substrate 100 and over the well region 104 of the semiconductor substrate 100. The gate structure 110 may include a gate dielectric layer 111 and a conductive layer 113 on the gate dielectric layer 111. The gate structure 110 can be formed by a photolithography process that patterns the material layers of the gate dielectric layer 111 and the conductive layer 113. Although only one gate structure 110 of the transistor is depicted in the figures, multiple gate structures 110 of the transistor can be formed in this embodiment, and these gate structures 110 may be spaced apart from each other in a first direction D1 (e.g., the X direction). Furthermore, in some embodiments, the gate structure 110 extends along a second direction D2 (e.g., the Y direction).

[0035] The gate dielectric layer 111 can be a single layer or a multilayer structure. In some embodiments, the gate dielectric layer 111 is a silicon oxide layer. In some embodiments, the gate dielectric layer 111 is formed of oxides, oxynitrides, nitrides, high-k materials, other suitable materials, and combinations thereof. In one example, the gate dielectric layer 111 may include an interfacial layer (not shown) and a high-k dielectric layer formed on the interfacial layer. The interfacial layer, the high-k dielectric layer, and the conductive layer 113 are stacked along a third direction D3 (e.g., the Z direction). For example, the interfacial layer may be formed on a semiconductor substrate 100 and may include a silicon oxide layer. The high-k dielectric layer may be formed on the interfacial layer by atomic layer deposition (ALD) or other suitable techniques. The conductive layer 113 may be formed on the high-k dielectric layer. The high-k dielectric layer may include hafnium oxide (HfO2). Alternatively, the high-k dielectric layer may optionally include other high-k dielectric materials, such as hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), and combinations thereof. It should be noted that the gate dielectric layer 111 of the present invention is not limited to including the above-mentioned materials.

[0036] The conductive layer 113 of the gate structure 110 may be referred to as the gate electrode. In some embodiments, the conductive layer 113 includes polysilicon, metal, metal silicide, metal nitride, another suitable material, and combinations thereof. Exemplary metal materials for the conductive layer 113 include TiN, TaN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, or other suitable metal materials. Furthermore, in some embodiments, the conductive layer 113 is formed of polysilicon, such as doped polysilicon. The conductive layer 113 of the gate structure 110 may be formed by deposition methods, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, electroplating, or other suitable methods.

[0037] In some embodiments, the gate structure 110 further includes a hard mask (not shown) formed over the conductive layer 113. The hard mask may be formed by a deposition process or other suitable process. The hard mask may include silicon nitride, silicon oxynitride, silicon carbide, another suitable material, or a combination thereof. For simplicity, a gate dielectric layer 111 and a conductive layer 113 are depicted herein to illustrate the gate structure 110.

[0038] Furthermore, in some embodiments, a lightly doped region (LDD) 120 is also formed in the semiconductor substrate 100. For example... Figure 1A As shown, the lightly doped region (LDD) 120 includes a first lightly doped region 121 and a second lightly doped region 122. The first lightly doped region 121 is adjacent to the first sidewall 110S1 of the gate structure 110. The second lightly doped region 122 is adjacent to the second sidewall 110S2 of the gate structure 110. In some embodiments, the lightly doped region (LDD) 120 can be formed by using the gate structure as an implant mask.

[0039] Next, a gate spacer material layer 130 comprising one or more spacer material layers is formed over the semiconductor substrate 100, and the gate spacer material layer 130 covers the gate structure 110 (e.g., Figure 1B Then, an initial gate spacer layer with symmetrical portions is formed, covering the first and second sidewalls of the gate structure, respectively (e.g., Figure 1C In this exemplary embodiment, four spacer material layers formed over the semiconductor substrate 100 are depicted for illustrative purposes. However, it should be noted that the number of spacer material layers used to form the initial gate spacer layer is not limited to the exemplary embodiments provided herein.

[0040] Reference Figure 1BA gate spacer layer 130 having four spacer material layers is formed above the semiconductor substrate 100 and covers the gate structure 110. In some embodiments, the gate spacer layer 130 includes a first spacer material layer 131, a second spacer material layer 132, a third spacer material layer 133, and a fourth spacer material layer 134. First, the first spacer material layer 131 is formed on the upper surface 100a of the semiconductor substrate 100, and the first spacer material layer 131 is conformally formed on the first sidewall 110S1 and the second sidewall 110S2 of the gate structure 110. In some embodiments, the first spacer material layer 131 also covers the isolation structure 108 and the lightly doped region (LDD) 120 (e.g., including the first lightly doped region 121 and the second lightly doped region 122). Figure 1B As shown, the first sidewall 110S1 of the gate structure 110 includes the first sidewall 111S1 of the gate dielectric layer 111 and the first sidewall 113S1 of the conductive layer 113. The second sidewall 110S2 of the gate structure 110 includes the second sidewall 111S2 of the gate dielectric layer 111 and the second sidewall 113S2 of the conductive layer 113. Then, a second spacer material layer 132 is conformally formed on the first spacer material layer 131, a third spacer material layer 133 is conformally formed on the second spacer layer 132, and a fourth spacer material layer 134 is conformally formed on the third spacer material layer 133.

[0041] The spacer material can be selected and varied based on the design requirements for forming the semiconductor device. In some embodiments, the first spacer layer 131 (as a liner spacer layer) is formed of silicon nitride, silicon oxynitride, silicon oxide, or other suitable materials. In other embodiments, the first spacer layer 131 is a silicon nitride layer having impurities of boron, carbon, fluorine, or combinations thereof. Precursors for the deposition process used to form the silicon nitride layer include silicon-containing gases, such as SiH2Cl2, Si2H6, SiH4, Si2Cl6, or BTBAS, and nitrogen-containing gases, such as NH3, N2, or N2O. Furthermore, the second spacer layer 132, the third spacer layer 133, and the fourth spacer layer 134 are, for example, dielectric layers having a low dielectric constant (low-k). The k-values ​​of the second spacer layer 132, the third spacer layer 133, and the fourth spacer layer 134 can range from about 4.2 to about 5.5. In some embodiments, the first spacer layer 131, the second spacer layer 132, the third spacer layer 133, and the fourth spacer layer 134 are low-k dielectrics containing impurities. Precursors for the deposition process of the low-k dielectric with impurities may include boron-containing gases, such as BCl3, BH3, or B2H6, or carbon-containing gases, such as C2H4 or C2H6. In some embodiments, the spacer material includes oxides, nitrides, boron-containing oxynitrides, carbon, fluorine, or combinations thereof. In some embodiments, the spacer material includes silicon carbide containing boron, nitrogen, fluorine, or combinations thereof. Furthermore, it should be noted that a suitable dielectric material for the fourth spacer layer 134 will exhibit low-k characteristics and high etch selectivity compared to the third spacer layer 133 described below.

[0042] In this embodiment, the first spacer layer 131 and the third spacer layer 133 include, but are not limited to, silicon nitride, while the second spacer layer 132 and the fourth spacer layer 134 include, but are not limited to, silicon oxide.

[0043] Furthermore, the first spacer layer 131, the second spacer layer 132, the third spacer layer 133, and the fourth spacer layer 134 can be formed using common techniques, such as plasma enhanced chemical vapor deposition (PECVD), low-pressure chemical vapor deposition (LPCVD), sub-atmospheric chemical vapor deposition (SACVD), atomic layer deposition (ALD), or other suitable deposition methods.

[0044] Reference Figure 1C The gate spacer material layer 130 is patterned to form an initial gate spacer layer 140 having symmetrical portions 141 and 142 covering the sidewalls of the gate structure 110. In this exemplary embodiment, each of the symmetrical portions 141 and 142 includes a patterned first spacer material layer (patterned first spacer material layer) 131', a patterned second spacer material layer (patterned second spacer material layer) 132', a patterned third spacer material layer (patterned third spacer material layer) 133', and a patterned fourth spacer material layer (patterned fourth spacer material layer) 134'. The patterning step can be performed by a wet etching process, a dry etching process, or a combination thereof. In some embodiments, the gate spacer material layer 130 is patterned by a dry etching process. In some embodiments, the gate spacer material layer 130 is patterned by an anisotropic dry etching process. Furthermore, the gate spacer material layer 130 is patterned without any masking provided over it. Thus, as Figure 1C As shown, symmetrical portions 141 and 142 of the initial gate spacer layer 140 are formed on the first sidewall 110S1 and the second sidewall 110S2 of the gate structure 110, respectively. Furthermore, after forming the symmetrical portions 141 and 142 of the initial gate spacer layer 140, the top surface 110a of the gate structure 110 (e.g., the top surface (upper surface) 113a of the conductive layer 113 in this exemplary embodiment) is exposed.

[0045] Please refer to Figure 1D , Figure 1E and Figure 1FAccording to some embodiments, the steps of forming a gate spacer structure GS are illustrated, the gate spacer structure GS including sidewalls of a gate structure 110 located at two opposing asymmetrical (asymmetric) portions (e.g., a first spacer portion GS-1 and a second spacer portion GS-2). In this exemplary embodiment, the asymmetrical (asymmetric) portions of the gate spacer structure GS on the opposing sidewalls of the gate structure 110 are introduced into the semiconductor device (or semiconductor apparatus) to extend the lateral distance between the gate structure and the subsequently formed drain region (this lateral distance is, for example, in a first direction D1, such as the X direction).

[0046] Reference Figure 1D A patterned masking layer 150 is provided over the semiconductor substrate 100 to expose one of the symmetrical portions 141 and 142 of the initial gate spacer layer 140. In some embodiments, a source region and a drain region are then formed adjacent to the first sidewall 110S1 and the second sidewall 110S2 of the gate structure 110, respectively. Therefore, the patterned masking layer 150 exposes the symmetrical portion 141 located above the first sidewall 110S1 of the gate structure 110, but covers the symmetrical portion 142 located above the second sidewall 110S2 of the gate structure 110. In some embodiments, the patterned masking layer 150 includes a material such as photoresist.

[0047] Please refer to Figure 1E The portion of the symmetrical portion 141 on the first sidewall 110S1 of the gate structure 110 that is not covered by the patterned masking layer 150 is removed. Therefore, the size and bottom surface of the symmetrical portion 141 can be reduced. This portion of the symmetrical portion 141 (the portion removed above) can be removed by an etching process. The etching process may include a dry etching process, a wet etching process, another suitable process, or a combination thereof. In some embodiments, the portion of the symmetrical portion 141 (the portion removed above) is removed by a selective etching process. In this embodiment, the patterned third spacer material layer 133' and the patterned fourth spacer material layer 134' of the symmetrical portion 141 are removed by selective etching. Figure 1B This forms the remaining portions of spacer material layers 131” and 132”. The remaining portions of spacer material layers 131” and 132” on the first sidewall 110S1 of the gate structure 110 can be collectively referred to as the smaller portion of the gate spacer structure GS. Furthermore, the remaining portion 142 located on the second sidewall 110S2 of the gate structure 110 and covered by the patterned masking layer 150 can be referred to as the larger portion of the gate spacer structure GS.

[0048] To briefly describe this exemplary embodiment, the remaining portions of the spacer material layers 131” and 132” on the first sidewall 110S1 of the gate structure 110 may be referred to as the first spacer portion GS-1 of the gate spacer structure GS. The remaining portion 142 on the second sidewall 110S2 of the gate structure 110 may be referred to as the second spacer portion GS-2 of the gate spacer structure GS.

[0049] After the asymmetric (non-symmetric) portion is formed and after the gate spacer structure GS is formed, for example, when forming a first spacer portion GS-1 with a smaller bottom surface and a second spacer portion GS-2 with a larger bottom surface, the patterned mask layer 150 is removed. The patterned mask layer 150 can be removed by stripping, ashing, other suitable processes, or a combination thereof.

[0050] Reference Figure 1F A heavily doped region 160, such as a source region 161 and a drain region 162, is formed in the semiconductor substrate 100. The source region 161 and the drain region 162 are located close to the first sidewall 110S1 and the second sidewall 110S2 of the gate structure 110, respectively. According to this embodiment, the source region 161 and the drain region 162 are formed using the asymmetrical portions of the gate structure 110 and the gate spacer structure GS (i.e., the first spacer portion GS-1 and the second spacer portion GS-2) as an injection mask. Therefore, according to some embodiments of the present invention, no additional mask is required during the formation of the source region 161 and the drain region 162.

[0051] Furthermore, according to some embodiments of the present invention, the inner edges of the source region 161 and the drain region 162 can be self-aligned with the outer edges of the first spacing portion GS-1 and the second spacing portion GS-2 of the gate spacing structure GS. For example... Figure 1F As shown, the inner edge of the source region 161 is aligned with the outer edge OE1 of the first spacer portion GS-1, and the inner edge of the drain region 162 is aligned with the outer edge OE2 of the second spacer portion GS-2. In other words, according to some embodiments of the invention, no spacer material covers the top surface 161a of the source region 161 and the top surface 162a of the drain region 162. Therefore, according to some embodiments, the entire top surface (top surface) 161a of the source region 161 and the entire top surface (top surface) 162a of the drain region 162 provides a large area for the formation of silicide regions (not shown) on the source region 161 and drain region 162 in subsequent processes.

[0052] Furthermore, according to some embodiments, such as Figure 1FAs shown, the lateral distance (e.g., the second width W2) between the drain region 162 and the gate structure 110 is greater than the lateral distance (e.g., the first width W1) between the source region 161 and the gate structure 110. The lateral distance between the source region 161 / drain region 162 and the gate structure 110 can be defined in a first direction D1 (e.g., the X direction). In some embodiments, the first spacing portion GS-1 covering the first sidewall 110S1 of the gate structure 110 has a first bottom surface (first bottom surface) B1, while the second spacing portion GS-2 covering the second sidewall 110S2 of the gate structure 110 has a second bottom surface (second bottom surface) B2. The second bottom surface B2 is larger than the first bottom surface B1. In some embodiments, as Figure 1F As shown, the first bottom surface B1 has a first width W1 (along the first direction D1) between the source region 161 and the gate structure 110, while the second bottom surface B2 has a second width W2 (along the first direction D1) between the drain region 162 and the gate structure 110, wherein the second width W2 is greater than the first width W1 (W2>W1). According to this embodiment, the extension distance between the drain region 162 and the gate structure 110 does indeed increase the breakdown voltage and the safe operating area (SOA) of the semiconductor device.

[0053] Furthermore, in some embodiments, after the source region 161 and drain region 162 are formed, a first lightly doped region 123 is located between the source region 161 and the gate structure 110, and a second lightly doped region 124 is located between the drain region 162 and the gate structure 110. For example... Figure 1F As shown, the first lightly doped region 123 below the first spacer portion GS-1 is adjacent to the first sidewall 110S1 of the gate structure 110, and the second lightly doped region 124 below the second spacer portion GS-2 is adjacent to the second sidewall 110S2 of the gate structure 110 (which is opposite to the first sidewall 110S1). Furthermore, the first spacer portion GS-1 of the gate spacer structure GS is formed in the first lightly doped region 123, and the second spacer portion GS-2 of the gate spacer structure GS is formed above the second lightly doped region 124.

[0054] In addition, such as Figure 1F As shown, according to some embodiments of the present invention, after forming the source region 161 and the drain region 162, the first lightly doped region 123 and the second lightly doped region 124 have different widths and extend along the upper surface 100a of the semiconductor substrate 100. In this embodiment, the width (along the first direction D1) of the second lightly doped region 124 between the gate structure 110 and the drain region 162 is greater than the width (along the first direction D1) of the first lightly doped region 123 between the gate structure 110 and the source region 161. Figure 1FAs shown, the width of the second lightly doped region 124 between the gate structure 110 and the source region 161 can be referred to as the first width W1 of the first bottom surface B1 of the first spacer portion GS-1. Similarly, the width of the second lightly doped region 124 between the gate structure 110 and the drain region 162 can be referred to as the second width W2 of the second bottom surface B2 of the second spacer portion GS-2. The first width W1 can also be described as the lateral distance from the first sidewall 110S1 of the gate structure 110 (or the inner edge IE1 of the first spacer portion GS-1) to the outer edge OE1 of the first spacer portion GS-1. The second width W2 can also be described as the lateral distance from the second sidewall 110S2 of the gate structure 110 (or the inner edge IE2 of the second spacer portion GS-2) to the outer edge OE2 of the second spacer portion GS-2.

[0055] In addition, such as Figure 1F As shown, in some embodiments, the inner edges of the first lightly doped region 123 and the second lightly doped region 124 in the semiconductor substrate 100 are aligned with the inner edges IE1 of the first spacer portion GS-1 and IE2 of the second spacer portion GS-2, respectively. Furthermore, since the source region 161 and the drain region 162 are formed using the gate structure 110 and the gate spacer structure GS as an implantation mask, after the formation of the source region 161 and the drain region 162, the outer edges of the first lightly doped region 123 and the second lightly doped region 124 that contact the source region 161 and the drain region 162 are respectively aligned with the outer edges of the two asymmetrical portions of the gate spacer structure GS. For example, the outer edge of the first lightly doped region 123 is aligned with (or aligned with) the outer edge OE1 of the first spacer portion GS-1, and the outer edge of the second lightly doped region 124 is aligned with (or aligned with) the outer edge OE2 of the second spacer portion GS-2. Therefore, this process method of the present invention can provide automatic alignment for forming the source region 161 and the drain region 162 without the need for additional masking. It not only simplifies the manufacturing process but also uses fewer components, thereby improving production efficiency and saving production costs.

[0056] Reference Figure 1G In some embodiments, an inter-layer dielectric (ILD) layer 170 is formed over the semiconductor substrate 100. A contact plug is then formed by filling contact openings (not shown) in the inter-layer dielectric layer 170 with a conductive material. Figure 1G As shown, contact plugs 181, 182 and 183 respectively contact (electrically connect) the source region 161, the gate structure 110 and the drain region 162.

[0057] In some embodiments, prior to the deposition of the interlayer dielectric layer 170, silicide regions (not shown) may be further formed on the source region 161, gate structure 110, and drain region 162 to reduce gate (e.g., polysilicon gate) contact resistance and source / drain contact resistance. In some embodiments, this can be achieved by... Figure 1F The previously formed structure is subjected to a uniform-thickness blanket depositing metal layer (not shown) followed by an annealing process to form silicide regions. During annealing, the metal layer reacts with the underlying silicon, forming silicide regions on the source region 161, gate structure 110, and drain region 162. The unreacted metal layer is then removed after the annealing process.

[0058] Furthermore, in some embodiments, after forming the silicide region, a contact etch stop layer (not shown) is further formed by uniform thickness deposition to cover it. Figure 1F The entire structure is as follows. The contact etch stop layer can act as an etch stop layer during the formation of the contact openings, thereby protecting the underlying area from over-etching. Furthermore, the contact etch stop layer provides stress to the semiconductor device, preferably tensile stress for NMOS transistors, and improves carrier mobility. Next, an interlayer dielectric layer 170 is deposited on the contact etch stop layer. Then, contact openings are formed through the interlayer dielectric layer 170, and these contact openings are filled with a conductive material layer. A planarization process, such as chemical mechanical planarization, another suitable planarization method, or a combination thereof, is then performed to planarize the conductive material layer and the interlayer dielectric material, thereby forming contact plugs 181, 182, and 183 and the interlayer dielectric material. The interlayer dielectric layer 170 has a planarized top surface, such as... Figure 1G As shown. In some embodiments, contact plugs 181, 182 and 183 contact silicide regions (not shown) on source region 161, gate structure 110 and drain region 162, respectively.

[0059] According to some embodiments, the semiconductor device includes a gate spacer structure GS having two asymmetrical portions (e.g., a first spacer portion GS-1 and a second spacer portion GS-2), respectively covering opposing sidewalls (e.g., a first sidewall 110S1 and a second sidewall 110S2) of the gate structure 110. The inner edges of the source region 161 and the drain region 162 are aligned with the outer edges (e.g., OE1 and OE2) of the asymmetrical portions of the gate spacer structure GS, respectively. Furthermore, the lateral distance between the drain region 162 and the gate structure 110 (e.g., the same as the second width W2) is greater than the lateral distance between the source region 161 and the gate structure 110 (e.g., the same as the first width W1). According to some embodiments, the extended (or extended) distance between the drain region 162 and the gate structure 110 (i.e., W2 > W1) does indeed increase the breakdown voltage and safe operating area (SOA) of the semiconductor device. Furthermore, the extended distance between the drain region 162 and the gate structure 110 of the semiconductor device reduces the undesirable parasitic capacitance between the gate structure 110 and the contact plug 183 connected to the drain region 162. Additionally, when the lateral distance between the source region 161 and the gate structure 110 (e.g., equal to the first width W1) is smaller than the lateral distance between the drain region 162 and the gate structure 110 (e.g., equal to the second width W2), more current is allowed to flow from the source to the drain terminal. Therefore, the electrical performance of the semiconductor device according to some embodiments of the present invention can be greatly improved. In this embodiment, the first spacing portion GS-1 can also be referred to as the smaller spacing portion, and the second spacing portion GS-2 can also be referred to as the larger spacing portion. In this embodiment, if necessary, the first spacing portion GS-1 can be set larger, and the second spacing portion GS-2 can be set smaller, with the positions of the source region 161 and the drain region 162 remaining unchanged; therefore, the lateral distance between the drain region and the gate structure is smaller than the lateral distance between the source region and the gate structure.

[0060] also, Figures 1A-1G A simple method is provided in some embodiments for fabricating a semiconductor device by one-step deposition of a gate spacer material layer 130 (e.g., deposition of four spacer material layers 131, 132, 133, and 134), one-step etching of the gate spacer material layer 130 to form an initial gate spacer layer 140 having symmetrical portions 141 and 142, and then removing a portion of the symmetrical portion 141 near the subsequently formed source region 161. However, it should be noted that the invention is not limited to the above. Figures 1A-1G The method shown. In some embodiments, other suitable methods are also applicable to forming semiconductor devices.

[0061] Figure 2A , Figure 2B , Figure 2C , Figure 2D , Figure 2E, Figure 2F and Figure 2G This is a cross-sectional view of an intermediate stage in a method for forming a semiconductor device according to some embodiments of the present invention. According to the method disclosed in this embodiment, two deposition steps are performed to give the gate spacer structure GS two asymmetrical portions (e.g., a first spacer portion GS-1 and a second spacer portion GS-2) located on opposite sidewalls of the gate structure. Furthermore, the same or similar reference numerals or reference references denote… Figures 1A to 1G and Figures 2A to 2G The same or similar elements (e.g., components or layers) are used. For the sake of simplicity, the materials of the same or similar components / layers and the processes for forming these components / layers will not be repeated here. The embodiments of the present invention provide different process methods, and the process steps of the embodiments of the present invention are fewer, simpler, and more efficient in manufacturing.

[0062] Reference Figure 2A According to some embodiments of the present invention, a structure having an initial gate spacer layer 240 is provided, wherein symmetrical portions 241 and 242 cover opposite sidewalls of the gate structure 110. For simplicity and clarity, Figure 2A and Figure 1C Features that are identical or similar are numbered as identical or similar.

[0063] In some embodiments, such as Figure 2A As shown, a semiconductor substrate 100 is provided having a well region 104 and an isolation structure 108 adjacent to the well region 104. The semiconductor substrate 100 may be a silicon substrate. The isolation structure 108 extends downward from the upper surface of the semiconductor substrate 100 and is embedded in the semiconductor substrate 100. The isolation structure 108 may include a shallow trench isolation (STI) element. Furthermore, a gate structure 110 is formed above the well region 104 of the semiconductor substrate 100. In some embodiments, the gate structure 110 includes a gate dielectric layer 111 and a conductive layer 113 on the gate dielectric layer 111.

[0064] Figure 2A The structure and materials of the semiconductor substrate 100, well region 104, isolation structure 108, and gate structure 110 are the same as those in the aforementioned embodiments. Figure 1A The features are the same as those in the original text, so the details of those features will not be repeated here. Additionally, Figure 2A The method for forming the structure having a semiconductor substrate 100, a well region 104, an isolation structure 108, and a gate structure 110 has been described in the foregoing embodiments and will not be repeated here.

[0065] In some embodiments, such as Figure 2AAs shown, a lightly doped region (LDD) 120, including a first lightly doped region 121 and a second lightly doped region 122, is further formed in the semiconductor substrate 100. The first lightly doped region 121 is adjacent to the first sidewall 110S1 of the gate structure 110. The second lightly doped region 122 is adjacent to the second sidewall 110S2 of the gate structure 110. In some embodiments, the lightly doped region (LDD) 120 can be created by using the gate structure 110 as an implantation mask. Figure 2A The structure and materials of the first lightly doped region 121 and the second lightly doped region 122 have been described in the foregoing embodiments, and the details of these components will not be repeated here. Furthermore, Figure 2A The methods for forming the first lightly doped region 121 and the second lightly doped region 122 are similar to those in the aforementioned embodiments, and will not be repeated here.

[0066] In some embodiments, such as Figure 2A As shown, symmetrical portions 241 and 242 of the initial gate spacer layer 240 are formed on the first sidewall 110S1 and the second sidewall 110S2 of the gate structure 110, respectively. In some embodiments, the initial gate spacer 240 can be formed by conformally depositing two spacer material layers over the semiconductor substrate 100 and covering the gate structure 110, and then patterning the spacer material layers to form the symmetrical portions 241 and 242 of the initial gate spacer layer 240. The patterning step can be performed by a wet etching process, a dry etching process, or a combination thereof. In some embodiments, the spacer material layers are patterned by a dry etching process. In some embodiments, the spacer material layers are patterned by an anisotropic dry etching process. In this embodiment, each symmetrical portion 241 and 242 includes a patterned first spacer material layer 231 and a patterned second spacer material layer 232. In one embodiment, the patterned first spacer material layer 231 includes, but is not limited to, silicon nitride, while the patterned second spacer material layer 232 includes, but is not limited to, silicon oxide. Figure 2A The suitable materials for patterning the first spacer layer 231 and the second spacer layer 232 are similar to those in the foregoing embodiments and will not be repeated here. In addition, after forming the symmetrical portions 241 and 242 of the initial gate spacer layer 240, the top surface 110a of the gate structure 110 (e.g., the top surface (upper surface) 113a of the conductive layer 113 in this exemplary embodiment) is exposed.

[0067] Reference Figure 2BIn some embodiments, a patterned mask layer 250 is provided over the semiconductor substrate 100. In some embodiments, the patterned mask layer 250 exposes one of the symmetrical portions 241 and 242 of the initial gate spacer layer 240. A source region and a drain region are then formed adjacent to the first sidewall 110S1 and the second sidewall 110S2 of the gate structure 110, respectively. Thus, the patterned mask layer 250 exposes the symmetrical portion 241 covering the first sidewall 110S1 of the gate structure 110 and the symmetrical portion 242 covering the second sidewall 110S2 of the gate structure 110. In some embodiments, the patterned mask layer 250 comprises a material such as photoresist.

[0068] Please refer to Figure 2C In some embodiments, the symmetrical portion 241 of the first sidewall 110S1 of the gate structure 110 that is not covered by the patterned masking layer 250 is removed. The symmetrical portion 241 may be partially or completely removed, provided that the remaining portion of the symmetrical portion 241 covers the bottom width (in the first direction D1) of the first sidewall 110S1 of the gate structure 110 less than the bottom width (in the first direction D1) of the second sidewall 110S2 of the gate structure 110 covered by the symmetrical portion 242. In this exemplary embodiment, the symmetrical portion 241 is completely removed, exposing the first sidewall 110S1 of the gate structure 110.

[0069] In some embodiments, the symmetrical portion 241 is removed by a selective etching process. The etching process may include a dry etching process, a wet etching process, another suitable process, or a combination thereof. After removing the symmetrical portion 241 of the initial gate spacer layer 240, the patterned mask layer 250 is removed. The patterned mask layer 250 may be removed by stripping, ashing, another suitable process, or a combination thereof.

[0070] Furthermore, since the patterned mask layer 250 completely covers the symmetrical portion 242 of the initial gate spacer layer 240, the symmetrical portion 242 is completely retained on the second sidewall 110S2 of the gate structure 110 after the patterned mask layer 250 is removed. For the sake of brevity, in the following description, the symmetrical portion 242 retained on the second sidewall 110S2 of the gate structure 110 may be referred to as the remaining initial spacer portion 242.

[0071] Next, in some embodiments, one or more spacer material layers are formed on the exposed first sidewall 110S1 of the gate structure 110 and cover the remaining initial spacer portion 242 on the second sidewall 110S2 of the gate structure 110.

[0072] Reference Figure 2DIn some embodiments, a third spacer material layer 233 is conformally formed on the gate structure 110 and the remaining initial spacer portion 242. Specifically, the third spacer material layer 233 is conformally formed on the upper surface 100a of the semiconductor substrate 100, the first sidewall 110S1 and top surface 110a of the gate structure 110, and the surface of the remaining initial spacer portion 242. Then, in some embodiments, a fourth spacer material layer 234 is conformally formed on the third spacer material layer 233.

[0073] According to some embodiments, the third spacer layer 233 and the fourth spacer layer 234 may comprise different materials. In one embodiment, the third spacer layer 233 includes, but is not limited to, silicon nitride, while the fourth spacer layer 234 includes, but is not limited to, silicon oxide. Figure 2D Suitable materials for the third spacer layer 233 and the fourth spacer layer 234 have been described in the foregoing embodiments and will not be repeated here.

[0074] Next, in some embodiments, a spacer material layer is patterned over the upper surface 100a of the semiconductor substrate 100 and covers the gate structure 110 to form a gate spacer structure GS. For example... Figure 2D As shown, according to some embodiments, the gate spacing structure GS has two asymmetrical portions on opposite sidewalls of the gate structure 110, such as a first spacing portion GS-1 and a second spacing portion GS-2.

[0075] refer to Figure 2E In some embodiments, a patterning step is performed on the spacer material layer comprising the remaining initial spacer portion 242 on the second sidewall 110S2 of the gate structure 110, and a third spacer material layer deposition 233 and a fourth spacer material layer 234 are deposited with uniform thickness to form a gate spacer structure GS. The gate spacer structure GS comprises two asymmetrical portions (i.e., a first spacer portion GS-1 and a second spacer portion GS-2) located on opposite sidewalls of the gate structure 110. It should be noted that these spacer material layers can be patterned to form the gate spacer structure GS without providing any masking above.

[0076] In some embodiments, a patterned third spacer material layer (patterned third spacer material layer) 233' and a patterned fourth spacer material layer (patterned fourth spacer material layer) 234' on the first sidewall 110S1 of the gate structure 110 together form a first spacer portion GS-1 of the gate spacer structure GS. In some embodiments, the remaining initial spacer portion 242, the patterned third spacer material layer 233', and the patterned fourth spacer material layer 234' on the second sidewall 110S2 of the gate structure 110 together form a second spacer portion GS-2 of the spacer structure GS.

[0077] It should be noted that, for the sake of simplicity and clarity, Figure 2E and Figure 1E Features with the same or similar structure are numbered the same or similarly. Figure 2E and Figure 1E The configurations of the same or similar features are similar to those in the foregoing embodiments, and will not be repeated here. Furthermore, Figure 2E The method for forming the gate spacing structure GS with two asymmetrical portions on opposite sidewalls of the gate structure 110 has been described in the foregoing embodiments and will not be repeated here.

[0078] Reference Figure 2F A heavily doped region 160, including a source region 161 and a drain region 162, is formed in a semiconductor substrate 100. The source region 161 and the drain region 162 are formed near the first sidewall 110S1 and the second sidewall 110S2 of the gate structure 110, respectively. According to this embodiment, the source region 161 and the drain region 162 are formed using the gate structure 110, the first spacer portion GS-1 of the gate spacer structure GS, and the second spacer portion GS-2 of the gate spacer structure GS as an injection mask. Therefore, according to some embodiments of the present invention, no additional mask is required to form the source region 161 and the drain region 162.

[0079] In this exemplary embodiment, the source region 161 and the drain region 162 can be self-aligned with the outer edges of the first spacing portion GS-1 and the second spacing portion GS-2 of the gate spacing structure GS. Figure 2F As shown, the inner edge of the source region 161 is aligned with the outer edge OE1 of the first spacer portion GS-1, and the inner edge of the drain region 162 is aligned with the outer edge OE2 of the second spacer portion GS-2. Furthermore, according to some embodiments of the invention, no spacer material covers the top surface 161a of the source region 161 and the top surface 162a of the drain region 162. According to some embodiments, the entire top surface 161a of the source region 161 and the entire top surface 162a of the drain region 162 provide a large area for forming silicide regions (not shown) on the source region 161 and drain region 162 in subsequent processes. The embodiments of the invention provide an automated alignment process for forming the source region 161 and drain region 162, which facilitates manufacturing and eliminates the need for additional masking, saving masking costs and steps, and improving manufacturing efficiency and yield.

[0080] Furthermore, according to some embodiments, such as Figure 2FAs shown, the lateral distance (e.g., a second width W2) between the drain region 162 and the gate structure 110 is greater than the lateral distance (e.g., a first width W1) between the source region 161 / drain region 162 and the gate structure 110. The lateral distance between the source region 161 / drain region 162 and the gate structure 110 can be defined in a first direction D1 (e.g., the X direction). In some embodiments, a first spacer portion GS-1 covering the first sidewall 110S1 of the gate structure 110 has a first bottom surface B1, while a second spacer portion GS-2 covering the second sidewall 110S2 of the gate structure 110 has a second bottom surface B2. The second bottom surface B2 is larger than the first bottom surface B1. In some embodiments, the first bottom surface B1 has a first width W1 (e.g., along the first direction D1) between the source region 161 and the gate structure 110, while the second bottom surface B2 has a second width W2 (e.g., along the first direction D1) between the drain region 162 and the gate structure 110. Figure 2F As shown, the second width W2 is greater than the first width W1 (W2>W1). According to this embodiment, the extended distance between the drain region 162 and the gate structure 110 increases the breakdown voltage and safe operating area (SOA) of the semiconductor device.

[0081] Furthermore, in some embodiments, after the source region 161 and drain region 162 are formed, a first lightly doped region 123 is located between the source region 161 and the gate structure 110, and a second lightly doped region 124 is located between the drain region 162 and the gate structure 110. For example... Figure 2F As shown, the first lightly doped region 123 is adjacent to the first sidewall 110S1 of the gate structure 110, and the second lightly doped region 124 is adjacent to the second sidewall 110S2 of the gate structure 110. Additionally, a first spacing portion GS-1 of the gate spacing structure GS is formed above the first lightly doped region 123, and a second spacing portion GS-2 of the gate spacing structure GS is formed above the second lightly doped region 124. According to some embodiments of the present invention, after the source region 161 and the drain region 162 are formed, the first lightly doped region 123 and the second lightly doped region 124 have different widths along the upper surface 100a of the semiconductor substrate 100. In this embodiment, the width (along the first direction D1) of the second lightly doped region 124 between the gate structure 110 and the drain region 162 is greater than the width (along the first direction D1) of the first lightly doped region 123 between the gate structure 110 and the source region 161. Figure 2F As shown, the width of the second lightly doped region 124 between the gate structure 110 and the source region 161 can be referred to as the first width W1 of the first bottom surface B1 of the first spacer portion GS-1. Similarly, the width of the second lightly doped region 124 between the gate structure 110 and the drain region 162 can be referred to as the second width W2 of the second bottom surface B2 of the second spacer portion GS-2.

[0082] Furthermore, in some embodiments, such as Figure 2F As shown, the inner edges of the first lightly doped region 123 and the second lightly doped region 124 in the semiconductor substrate 100 are aligned with the inner edges of the first spacer portion GS-1 (IE1) and the second spacer portion GS-2 (IE2), respectively. Furthermore, since the source region 161 and the drain region 162 are formed using the gate structure 110 and the gate spacer structure GS as implantation masks, after implantation of the source region 161 and the drain region 162, the outer edges of the first lightly doped region 123 and the second lightly doped region 124, which respectively contact the source region 161 and the drain region 162, are aligned with the outer edges of the two asymmetrical portions of the gate spacer structure GS. For example, the outer edge of the first lightly doped region 123 is aligned with the outer edge OE1 of the first spacer portion GS-1, and the outer edge of the second lightly doped region 124 is aligned with the outer edge OE2 of the second spacer portion GS-2.

[0083] Reference Figure 2G In some embodiments, an inter-layer dielectric (ILD) layer 170 is formed over a semiconductor substrate 100. Contact plugs are then formed by filling contact openings in the ILD layer 170 with a conductive material. Figure 2G As shown, contact plugs 181, 182 and 183 contact the source region 161, the gate structure 110 and the drain region 162, respectively.

[0084] It should be noted that, Figure 2G and Figure 1G For simplicity and clarity, features with the same or similar structure are numbered the same or similarly. Figure 2G and Figure 1G Configurations with the same or similar features have been described in the foregoing embodiments and will not be repeated here. Furthermore, the method for forming a structure having an interlayer dielectric (ILD) layer 170 covering a gate spacing structure GS (including two asymmetrical portions GS-1 and GS-2 on opposite sidewalls of the gate structure 110) and... Figure 2G The contact plugs 181, 182 and 183 have been described in the foregoing embodiments, and the process details will not be repeated here.

[0085] Furthermore, in some embodiments, silicide regions (not shown) may be formed on the source region 161, gate structure 110, and drain region 162 before depositing the interlayer dielectric (ILD) layer 170 to reduce gate (e.g., polysilicon gate) contact resistance and source / drain contact resistance. The formation of the silicide regions has been described in the foregoing embodiments, and therefore the process details will not be repeated here.

[0086] Furthermore, in some embodiments, after forming the silicide region, a contact etch stop layer (not shown) is further formed by uniform thickness deposition to cover it. Figure 2F The entire structure is as follows. The contact etch stop layer can act as an etch stop layer during the formation of the contact openings, thereby protecting the underlying areas from over-etching. An interlayer dielectric layer 170 is deposited on the contact etch stop layer, and contact plugs 181, 182, and 183 are formed by forming the aforementioned contact openings (not shown) and filling these contact openings with a layer of conductive material through the interlayer dielectric (ILD) layer 170. In some embodiments, contact plugs 181, 182, and 183 contact silicide regions on the source region 161, gate structure 110, and drain region 162, respectively. Contact plug 181 is used to provide a source voltage to the source region 161, contact plug 182 is used to provide a gate voltage to the gate structure 110, and contact plug 183 is used to provide a drain voltage to the drain region 162.

[0087] Furthermore, the configuration of the gate spacing structure GS in the above embodiments, for example... Figure 1F and Figure 1F The shape and arrangement 2F of the spacer material layers in the first spacer portion GS-1 and the second spacer portion GS-2 are only used to illustrate some applicable types. The present invention is not limited to the structural configuration of the gate spacer structure GS in the foregoing embodiments. According to the present invention, the first spacer portion GS-1 and the second spacer portion GS-2 of the gate spacer structure GS can have different shapes and arrangements of spacer material layers to achieve that the spacer portion near the drain region (i.e., GS-2) has a larger bottom width than the spacer portion near the source region (i.e., GS-1).

[0088] Figure 3 This is a cross-sectional view of an intermediate stage of a semiconductor device according to some embodiments of the present invention. Apart from the configuration of the gate spacing structure GS, Figure 3 The intermediate structure and Figure 1F and Figure 2F The intermediate structure is the same. For simplicity and clarity, Figure 1F , Figure 2F and Figure 3 Features that are identical or similar to those in the same structure are numbered the same or similarly.

[0089] Figure 1F , Figure 2F and Figure 3 The configurations of those identical or similar features have already been described in the previously described embodiments and will not be repeated here. Furthermore, Figure 3The method of forming the structure in the semiconductor substrate 100 includes having a well region 104 and an isolation structure 108, a gate structure 110, a gate spacing structure GS with two asymmetrical portions (e.g., the first spacing portion GS-the second spacing portion GS-2 on the opposite sidewall of the gate structure 110), a first lightly doped region 123, a second lightly doped region 124, a source region 161, and a drain region 162, etc. The structure is similar to that in the foregoing embodiment, and the details will not be repeated here.

[0090] refer to Figure 3 In some embodiments, patterned first spacer material layers (patterned first spacer material layer) 235, patterned second spacer material layers (patterned second spacer material layer) 236, patterned third spacer material layers (patterned third spacer material layer) 237, and patterned fourth spacer material layers (patterned fourth spacer material layer) 238 on the second sidewall 110S2 of the gate structure 110 collectively form the second spacer portion GS-2 of the gate spacer structure GS. In some embodiments, patterned third spacer material layers (patterned third spacer material layer) 237 and patterned fourth spacer material layers (patterned fourth spacer material layer) 238 on the first sidewall 110S1 of the gate structure 110 collectively form the first spacer portion GS-1 of the gate spacer structure GS. The embodiments of the present invention provide different process methods, and the process steps of the embodiments of the present invention are fewer and simpler, resulting in higher manufacturing efficiency.

[0091] In one example, the patterned first spacer layer 235 and the patterned third spacer layer 237 include, but are not limited to, silicon nitride, while the patterned second spacer layer 236 and the patterned fourth spacer layer 238 include, but are not limited to, silicon oxide. Figure 3 Suitable materials for the patterned first spacer layer 235, patterned second spacer layer 236, patterned third spacer layer 237, and patterned fourth spacer layer 238 have been provided and described in the foregoing embodiments and will not be repeated here.

[0092] Figure 3 The gate spacer structure GS in the image can be formed using various methods, the following are examples. Figure 3One method for fabricating the gate spacer structure GS in the example will be described below. First, a remaining spacer portion, including a patterned first spacer material layer 235 and a patterned second spacer material layer 236, is formed on the second sidewall 110S2 of the gate structure 110, while the first sidewall 110S1 of the gate structure 110 is exposed. Next, a third spacer material layer (not shown) is conformally formed on the surfaces of the upper surface 100a of the semiconductor substrate 100, the first sidewall 110S1 and the top surface 110a of the gate structure 110, and the remaining spacer portion (including the patterned first spacer material layer 235 and the patterned second spacer material layer 236) on the second sidewall 110S2 of the gate structure 110. Next, these spacer material layers are patterned to form a patterned third spacer material layer 237 on the first sidewall 110S1 of the gate structure 110 and the patterned second spacer material layer 236 adjacent to the second sidewall 110S2 of the gate structure 110. Next, a fourth spacer material layer (not shown) is conformally formed on the upper surface 100a of the semiconductor substrate 100, the patterned third spacer material layer 237, and the exposed upper surface 110a of the gate structure 110. Then, a patterning step is performed on the fourth spacer material layer to form a patterned fourth spacer material layer 238 on the patterned third spacer material layer 237. It should be noted that these patterning steps do not require additional masking. Furthermore, the top surface 110a of the gate structure 110 (e.g., the upper surface 113a of the conductive layer 113 in this embodiment) is exposed after the asymmetrical portion of the gate sidewall structure GS (i.e., the first spacer portion GS-1 and the second spacer portion GS-2) is formed.

[0093] Furthermore, according to some embodiments, such as Figure 3 As shown, the lateral distance (e.g., the second width W2) between the drain region 162 and the gate structure 110 is greater than the lateral distance (e.g., the first width W1) between the source region 161 and the gate structure 110. In some embodiments, the first spacing portion GS-1 covering the first sidewall 110S1 of the gate structure 110 has a first bottom surface, and the second spacing portion GS-2 covering the second sidewall 110S2 of the gate structure 110 has a second bottom surface. In some embodiments, the first bottom surface has a first width W1 (e.g., along the first direction D1) between the source region 161 and the gate structure 110, and the second bottom surface has a second width W2 (e.g., along the first direction D1) between the drain region 162 and the gate structure 110. Figure 3 As shown, the second width W2 is greater than the first width W1 (W2>W1).

[0094] although Figure 3 The configuration of the gate spacing structure GS in the middle is different from that in the middle. Figure 1F and Figure 2FThe configuration of the gate spacing structure GS in the [structure], according to some embodiments, [is as follows]. Figure 3 The extended distance between the middle drain region 162 and the gate structure 110 does indeed increase the breakdown voltage and safe operating area (SOA) of the semiconductor device.

[0095] According to the above embodiments, the gate spacer structure GS of the semiconductor device is formed by multiple spacer material layers, wherein the two asymmetrical portions (i.e., GS-1 and GS-2) of the gate sidewall structure GS, which respectively cover the first and second sidewalls of the gate structure, each have a different number of sidewall material layers. However, the present invention is not limited to the configuration of the gate spacer structure GS described above. It should be noted that the multilayer spacing of the first spacer portion GS-1 and the second spacer portion GS-2 in the foregoing embodiments is only used to provide some examples of the gate spacer structure GS.

[0096] Figure 4 This is a cross-sectional view of an intermediate stage of a semiconductor device according to some embodiments of the present invention. Apart from the configuration of the gate spacing structure GS, Figure 4 The intermediate structure and Figure 1F , Figure 2F and Figure 3 The intermediate structure is the same. For simplicity and clarity, Figure 1F , Figure 2F , Figure 3 and Figure 4 The same or similar features of the structure are numbered the same or similarly.

[0097] Figure 1F , Figure 2F , Figure 3 and Figure 4 The configurations of the same or similar features are similar to those in the foregoing embodiments, and will not be repeated here. Furthermore, Figure 4 The method for forming the structure in the semiconductor substrate 100, including a well region 104 and an isolation structure 108, a gate structure 110, two asymmetric gate spacing structures GS located in the gate structure 110, a first lightly doped region 123, a second lightly doped region 124, a source region 161 and a drain region 162, etc., has been provided in the foregoing embodiments, so the process details will not be repeated here.

[0098] refer to Figure 4In some embodiments, the gate spacer structure GS is made of a single spacer material layer (monolayer spacer material layer). That is, each of the first spacer portion GS-1 and the second spacer portion GS-2 of the gate spacer structure GS includes a spacer material layer. The spacer material layers of the first spacer portion GS-1 and the second spacer portion GS-2 may include silicon nitride, silicon oxide, or other suitable materials. The monolayer spacer material layer is located on both sides of the first sidewall 110S1 and the second sidewall 110S2, respectively, and is indicated by dotted areas in the figures without additional labels. The embodiments of the present invention provide different manufacturing processes; the monolayer spacer material layer has fewer and simpler manufacturing steps, resulting in higher manufacturing efficiency.

[0099] In some embodiments, the first spacer portion GS-1 and the second spacer portion GS-2 of the gate spacer structure GS, which respectively cover the first sidewall 110S1 and the second sidewall 110S2 of the gate structure 110, have different bottom widths of the spacer material layers. Figure 4 As shown, the lateral distance (e.g., the second width W2) between the drain region 162 and the gate structure 110 is greater than the lateral distance (e.g., the first width W1) between the source region 161 and the gate structure 110. In some embodiments, the first spacing portion GS-1 covering the first sidewall 110S1 of the gate structure 110 has a first bottom surface, while the second spacing portion GS-2 covering the second sidewall 110S2 of the gate structure 110 has a second bottom surface. In some embodiments, the first bottom surface has a first width W1 (e.g., the bottom width in the first direction D1) between the source region 161 and the gate structure 110, and the second bottom surface has a second width W2 (e.g., the bottom width in the first direction D1) between the drain region 162 and the gate structure 110. Figure 4 As shown, the second width W2 is greater than the first width W1 (W2>W1).

[0100] Although Figure 4 The configuration of the gate spacing structure GS in the middle is different from that in the middle. Figure 1F , Figure 2F and Figure 3 The configuration of the gate spacing structure GS in the middle, Figure 4 The increased distance (extension) between the drain region 162 and the gate structure 110 increases the breakdown voltage and safe operating area (SOA) of the semiconductor device.

[0101] According to the embodiments described above, the semiconductor device and its formation method achieve several advantages. In some embodiments, the gate spacer structure GS has two asymmetrical portions (e.g., a first spacer portion GS-1 and a second spacer portion GS-2) that respectively cover opposite sidewalls (e.g., a first sidewall 110S1 and a second sidewall 110S2) of the gate structure 110 in the semiconductor device. The lateral distance (e.g., a second width W2) between the drain region 162 and the gate structure 110 is greater than the lateral distance (e.g., a first width W1) between the source region 161 and the gate structure 110 (W2>W1). The extended distance between the drain region 162 and the gate structure 110 increases the breakdown voltage and safe operating area (SOA) region of the semiconductor device. Moreover, the extended distance between the drain region 162 and the gate structure 110 of the semiconductor device reduces undesirable parasitic capacitance between the gate structure 110 and the contact plug 183 connected to the drain region 162. Furthermore, when the lateral distance (e.g., a first width W1) between the source region 161 and the gate structure 110 is smaller than the lateral distance (e.g., a second width W2) between the drain region 162 and the gate structure 110 of the semiconductor device, more current is allowed to flow from the source to the drain terminal. Additionally, according to some embodiments, the method for forming the semiconductor device is simple and compatible with current processes. The structural configuration of the features in the semiconductor device formed according to the method of some embodiments also brings several advantages. For example, the source region 161 and drain region 162 formed in the semiconductor substrate are self-aligned with the outer edges (e.g., OE1 and OE2) of the asymmetric portion of the gate spacing structure GS, thereby providing a larger contact area for contact plugs disposed on the source region 161 and drain region 162 in subsequent processes, significantly increasing the production line window, improving production efficiency, and, as described above, significantly improving the electrical performance of the semiconductor device (device).

[0102] In one exemplary aspect, the present invention relates to a semiconductor device. The semiconductor device includes a semiconductor substrate having a well region and a gate structure formed over the well region of the semiconductor substrate. In some embodiments, the gate structure has a first sidewall and a second sidewall. The second sidewall is opposite to the first sidewall. The semiconductor device also includes a gate spacer structure (gate spacer structure) having two asymmetrical portions. In some embodiments, the asymmetrical portions of the gate spacer structure are formed on the first sidewall and the second sidewall of the gate structure, respectively. The semiconductor device also includes a source region and a drain region located in the semiconductor substrate, the inner edges of the source region and the drain region being aligned with the outer edges of the asymmetrical portions of the gate spacer structure, respectively. Furthermore, the lateral distance between the drain region and the gate structure is greater than the lateral distance between the source region and the gate structure.

[0103] In some embodiments, an asymmetric portion formed adjacent to the drain region has a larger bottom surface than another asymmetric portion adjacent to the source region. In some embodiments, the source and drain regions are located near the first and second sidewalls of the gate structure, respectively. In some embodiments, the gate spacer structure is composed of a single spacer material layer, and the spacer material layers covering the first and second sidewalls of the gate structure have different bottom widths. In some embodiments, the gate spacer structure is composed of multiple spacer material layers, and the two asymmetric portions of the gate spacer structure covering the first and second sidewalls of the gate structure each have different numbers of spacer material layers. In some embodiments, the semiconductor device further includes a lightly doped region located in the semiconductor substrate and below the two asymmetric portions (asymmetric portions) of the gate spacer structure, wherein the lightly doped region has different widths extending along the upper surface of the semiconductor substrate. In some embodiments, the outer edge of the lightly doped region is aligned with the outer edge of the two asymmetric portions of the gate spacer structure. In some embodiments, the gate spacing structure includes a first spacing portion covering a first sidewall of the gate structure and a second spacing portion covering a second sidewall of the gate structure, wherein the bottom surface of the first spacing portion has a first width between the source region and the gate structure, and the bottom surface of the second spacing portion has a second width between the drain region and the gate structure, and the second width is greater than the first width.

[0104] In another exemplary aspect, the present invention relates to a method of forming a semiconductor device. The method includes providing a semiconductor substrate having a well region and an isolation structure adjacent to the well region. A gate structure is formed over the well region of the semiconductor substrate. The gate structure has a first sidewall and a second sidewall. The second sidewall is opposite to the first sidewall. A gate spacer structure is formed, including two asymmetrical portions covering the first and second sidewalls of the gate structure. A source region and a drain region are formed in the semiconductor substrate. The source and drain regions are aligned with the outer edges of the asymmetrical portions of the gate spacer structure. Furthermore, the lateral distance between the drain region and the gate structure is greater than the lateral distance between the source region and the gate structure.

[0105] In some embodiments, forming a gate spacer structure includes forming an initial gate spacer layer having symmetrical portions covering a first sidewall and a second sidewall of a gate structure, respectively; partially removing one of the symmetrical portions on the first sidewall of the gate structure, wherein the other symmetrical portion remains on the second sidewall of the gate structure. In other embodiments, forming a gate spacer structure includes forming an initial gate spacer layer having symmetrical portions covering the first and second sidewalls of the gate structure; removing the symmetrical portion on the first sidewall of the gate structure to expose the first sidewall of the gate structure, while the other symmetrical portion remains on the second sidewall of the gate structure, which may be referred to as the remaining initial spacer portion. Spacer material is formed covering the exposed first sidewall of the gate structure and covering the remaining initial spacer portion on the second sidewall of the gate structure.

[0106] It should be noted that the structural and manufacturing details of the embodiments are for illustrative purposes only, and the detailed descriptions of the embodiments are not intended to limit the invention. It should be observed that not all embodiments of the invention are shown. Various modifications and variations can be made without departing from the spirit of the invention to meet the needs of practical applications. Therefore, there may be other embodiments of the invention not specifically described. Furthermore, the drawings have been simplified for clear illustration of the embodiments. The dimensions and scales in the drawings may not be proportional to the actual product. Therefore, the specification and drawings should be considered illustrative rather than restrictive.

[0107] Those skilled in the art will readily observe that numerous modifications and alterations can be made to the apparatus and method while maintaining the teachings of this invention. Therefore, the foregoing disclosure should be interpreted as being limited only by the scope and limits of the appended claims.

Claims

1. A semiconductor device, characterized in that, include: A semiconductor substrate having a well region; A gate structure is formed above the well region of the semiconductor substrate, wherein the gate structure has a first sidewall and a second sidewall opposite to the first sidewall; A gate spacing structure includes two asymmetrical portions that respectively cover the first sidewall and the second sidewall of the gate structure; as well as A source region and a drain region are formed in the semiconductor substrate, wherein the source region and the drain region are respectively aligned with the outer edges of the two asymmetrical portions of the gate spacer structure. Wherein, the lateral distance between the drain region and the gate structure is greater than the lateral distance between the source region and the gate structure; The two asymmetric portions of the gate spacing structure include: The first spacing portion is located between the source region and the first sidewall of the gate structure; and The second spacing portion is located between the drain region and the second sidewall of the gate structure; The second spacer portion includes a symmetrical portion of the initial gate spacer layer, while the first spacer portion does not have the symmetrical portion of the initial gate spacer layer. Both the first spacer portion and the second spacer portion include a spacer material layer with a low dielectric constant.

2. The semiconductor device as claimed in claim 1, characterized in that, The bottom surfaces of the two asymmetric portions of the gate spacing structure are formed above the well region, and the bottom surface of one of the two asymmetric portions adjacent to the drain region is larger than the bottom surface of the other asymmetric portion adjacent to the source region.

3. The semiconductor device as claimed in claim 1, characterized in that, The source region and the drain region are located near the first sidewall and the second sidewall of the gate structure, respectively.

4. The semiconductor device as claimed in claim 1, characterized in that, The gate spacer structure is composed of multiple spacer material layers, and the two asymmetrical portions of the gate spacer structure located on the first and second sidewalls of the gate structure have different numbers of spacer material layers.

5. The semiconductor device as claimed in claim 1, characterized in that, Also includes: A lightly doped region is formed in the semiconductor substrate, and below the two asymmetric portions of the gate spacer structure. The lightly doped region has different widths extending along the upper surface of the semiconductor substrate.

6. The semiconductor device as claimed in claim 5, characterized in that, The outer edges of the lightly doped region that contact the source region and the drain region are aligned with the outer edges of the two asymmetric portions of the gate spacer structure, respectively.

7. The semiconductor device as claimed in claim 1, characterized in that, The first spacer portion covers the first sidewall of the gate structure, wherein the bottom surface of the first spacer portion has a first width between the source region and the gate structure; and The second spacer portion covers the second sidewall of the gate structure, wherein the bottom surface of the second spacer portion has a second width between the drain region and the gate structure. The second width is greater than the first width.

8. The semiconductor device as claimed in claim 7, characterized in that, Also includes: A first lightly doped region is formed in the semiconductor substrate and located below the first spacer portion of the gate spacer structure; as well as A second lightly doped region is formed in the semiconductor substrate and located below the second spacer portion of the gate spacer structure. The width of the second lightly doped region between the gate structure and the drain region is greater than the width of the first lightly doped region between the gate structure and the source region.

9. A method for forming a semiconductor device, characterized in that, include: A semiconductor substrate is provided, the semiconductor substrate having a well region and an isolation structure adjacent to the well region; A gate structure is formed above the well region of the semiconductor substrate, wherein the gate structure has a first sidewall and a second sidewall opposite to the first sidewall; A gate spacer structure is formed, the gate spacer structure including two asymmetric portions, the two asymmetric portions respectively covering the first sidewall and the second sidewall of the gate structure; as well as A source region and a drain region are formed in the semiconductor substrate, wherein the source region and the drain region are respectively aligned with the outer edges of the two asymmetrical portions of the gate spacer structure. Wherein, the lateral distance between the drain region and the gate structure is greater than the lateral distance between the source region and the gate structure; The step of forming the gate spacer structure includes: Symmetrical portions of the initial gate spacer layer are formed on the first sidewall and the second sidewall, respectively. Remove the symmetrical portion of the first sidewall of the gate structure; A spacer material layer with a low dielectric constant is formed on the symmetrical portions of the first sidewall and the second sidewall of the gate structure; The spacer material layer is patterned to form the gate spacer structure.

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